ATA6809 [ATMEL]
Fail-safe IC with Relay Driver and Lamp Driver; 故障保险IC带有继电器驱动器和灯驱动
| 型号： | ATA6809 |
| 厂家： | 
ATMEL |
| 描述： | Fail-safe IC with Relay Driver and Lamp Driver |
| 文件： | 总16页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
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Digital Self-supervising Watchdog with Hysteresis
Three 250-mA Output Drivers
One Relay Driver, Two Lamp Drivers
Lamp Drivers With Auxiliary Ground
Short-circuit-protected Lamp Drivers
Lamp Drivers With Status Feedback
Fail-safe IC with
Relay Driver
and Lamp
Enable Output
Overvoltage/Undervoltage Detection and Reset
All Power Outputs Protected Against Standard Transients
All Power Outputs Protected Against 40V Load Dump
Lamp Drivers Automatically Activated if VS is Disconnected
Lamp Drivers Automatically Activated Via AUX GND if Standard
Ground is Disconnected
Driver
1. Description
ATA6809
The ATA6809 is designed to support the fail-safe function of safety-critical systems
such as ABS. It includes a relay driver, two independent short-circuit-protected lamp
drivers which are supplied by redundant ground lines, two monitoring circuits for the
lamp driver output voltage and output current, a watchdog controlled by an external
RC network, and a reset circuit initiated by an overvoltage or undervoltage condition
of the 5V supply providing a positive and a negative reset signal.
Rev. 4902A–AUTO–11/05
Figure 1-1. Block Diagram
VS
LA1I
LA2I
RELI
WDI
Open-collector
250 mA
lamp driver 1
Digital input lamp 1
Digital input lamp 2
Digital input relay
Digital input wd
Logic
LA1O
LA2O
Short-circuit
detection and
temperature
monitor
Temperature
Open-collector
250 mA
Micro-
controller
lamp driver 2
Watchdog
Loads
FBLA1
FBLA2
Feedback lamp 1
Feedback lamp 2
Open-collector
250 mA
relay driver
Debouncing of
over- and under-
voltage detection
RELO
ENO
PRES
NRES
p reset
n reset
Oscillator
monitoring
RC-oscillator
Open-collector
25 mA
enable driver
OSC
GND
AUX GND
2. Pin Configuration
Figure 2-1. Pinning SO20
20
19
18
17
16
15
14
13
1
2
WDI
REL1
VS
LA1I
3
LA1O
LA2I
4
RELO
GND
GND
FBLA1
GND
GND
GND
LA2O
5
ATA6809
6
7
AUX
GND
8
NRES
PRES
FBLA2
9
12 ENO
11
10
OSC
2
ATA6809
4902A–AUTO–11/05
ATA6809
Table 2-1.
Pin
Pin Description
Name
Type
Function
Logic
Driver on: L
Driver off: H
1
2
3
RELI
Digital input
Digital input
Digital input
Activation of relay driver
Driver off: L
Driver on: H
LA1I
LA2I
Activation of lamp driver 1
Activation of lamp driver 2
Driver off: L
Driver on: H
Driver off:---
Driver on: L
4
5, 6
7
RELO
GND
Open-collector driver output
Supply
Fail-safe relay driver
Standard ground
Feedback lamp 1
See Table 3-1 on page 5 and
Table 3-2 on page 5
FBLA1
Digital output
Reset: L
No reset: H
8
9
NRES
PRES
Digital output
Digital output
Negative reset signal
Positive reset signal
Reset: H
No reset: L
See Table 3-1 on page 5 and
Table 3-2 on page 5
10
FBLA2
OSC
Digital output
Feedback lamp 2
11
Analog input
External RC for watchdog timer
Watchdog disable output
Auxiliary ground of lamp drivers
Warning lamp driver
Watchdog ok: ---
Watchdog not ok: L
12
13
ENO
Open-collector output
AUX, GND Supply
Driver off: ---
Driver on: L
14
LA2O
GND
LA1O
Open-collector driver output
15, 16, 17
18
Supply
Standard ground
Driver off: ---
Driver on: L
Open-collector driver output
Warning lamp driver
19
20
VS
Supply
5V supply
WDI
Digital input
Watchdog trigger signal
Pulse sequence
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3. Detailed Block Diagram with External Components
Figure 3-1. Detailed Block Diagram
Push pull
Reset
debouncing
19
R+
VS
9
8
VRef 4
+ PRES
+
-
Push pull
R-
Reset
delay
- NRES
VBatt
+
-
4
7
A
VRef 5
Temperature
shut down
RELO
1
Push pull
L1
RELI
LA1I
LA2I
WDI
+
-
FBLA1
VBatt
VS
VRef2
Failure
detection
lamp 1
2
+
-
+
-
18
VS
LA1O
VBatt
C
VRef3
3
+
-
+
-
Failure
detection
lamp 2
VRef2
20
+
-
E
14
+
-
LA2O
VRef 1
D
A
C
B
D
VRef3
Watchdog
Oscillator
VS
+
-
Ground backup
E
GND
AUX GND
11
OSC
C
D
Push pull
L2
E
10
12
Integrated
oscillator
Internal
timing
FBLA2
ENO
Short-circuit
protection
B
5 6 15 16 17
GND
13
AUX GND
4
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Table 3-1.
Truth Table for Lamp Drivers and Lamp Feedback
Inputs
Outputs
Lamp
Driver
Current
Lamp
Voltage
Lamp
Current
Lamp
Current
Feedback
Lamp
Lamp (I)
Comment
Output ok or open (internal pull-up) or shorted to
VBatt
0
1
0
Off
Off
1
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
On
On
Off
On
On
Off
On
On
On
Off
1
0
0
0
1
Output shorted to VBatt and faulty input level
Internal driver activated due to internal failure
Output shorted to GND
Output ok
Output shorted to VBatt
Internal driver deactivated due to internal failure or
thermal shutdown
1
1
1
0
Off
Off
1
0
0
Off
On/off
1
Output shorted to GND or open
Note:
Lamp voltage is logic 1 if output voltage > threshold voltage detection
Lamp voltage is logic 0 if output voltage < threshold voltage detection
Lamp current is logic 1 if output current > threshold current detection
Lamp current is logic 0 if output current < threshold current detection
Table 3-2.
Condition
Table of Fault Detection
Feedback Lamp
Lamp Input is 1 (Lamp On)
0
Lamp Input is 0 (Lamp Off)
1
Normal operation
Lamp output shorted to GND
Lamp output shorted to VBatt
Lamp output open
0 (= detection)
1 (= detection)
1 (= detection)
1 (= detection)
0 (= no detection)
1 (= detection)
1 (= detection)
0 (= no detection)
1 (= no detection)
1 (= no detection)
0 (= detection)
Feedback shorted to GND
Feedback shorted to VS
Lamp input shorted to GND
Lamp input shorted to VS
1 (= no detection)
1 (= no detection)
0 (= detection)
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4902A–AUTO–11/05
4. Fail-safe Functions
A fail-safe IC has to maintain its monitoring function even if there is a fault condition at one of the
pins (for example, a short circuit). This ensures that a microcontroller system is not brought into
a critical status. A critical status is reached if the system is not able to actuate a warning lamp
and switch off the relay. The following table shows fault conditions for different pins during which
the IC still works as a fail-safe device.
Table 4-1.
Pin Function
LA2O Short-circuit proof driver for warning lamp
LA2I Digital input to activate warning lamp
Table of Fault Condition
Short to VS
LA2O partly on LA2O off
LA2O on LA2O on
Short to VBatt
Short to GND
LA2O on
Open Circuit
LA2O off
LA2O off
LA2O on
FBLA2 Digital feedback of warning lamp
Faulty feedback Faulty feedback Faulty feedback Faulty feedback
LA1O Short-circuit proof driver for warning lamp
LA1O partly on LA1O off
LA1O on LA1O on
LA1O on
LA1O off
LA1O off
LA1O on
LA1I
Digital input to activate warning lamp
FBLA1 Digital feedback of warning lamp
Faulty feedback Faulty feedback Faulty feedback Faulty feedback
Relay off Relay off Relay on Relay off
RELI
WDI
OSC
Digital input to activate the fail safe relay
Watchdog trigger input
Watchdog reset Watchdog reset Watchdog reset Watchdog reset
Watchdog reset Watchdog reset Watchdog reset Watchdog reset
Capacitor and resistor of watchdog
5. Description of the Watchdog
5.1
Abstract
The microcontroller is monitored by a digital window watchdog which accepts an incoming trig-
ger signal of a constant frequency for correct operation. The frequency of the trigger signal can
be varied in a broad range as the watchdog's time window is determined by external RC
components.
The following description refers to Figure 1-1 on page 2.
Figure 5-1. Watchdog Block Diagram
Binary counter
RCOSC
Dual MUX
Slope
detector
Up/down
counter
WD-OK
RS-FF
WDI
RESET
OSCERR
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4902A–AUTO–11/05
ATA6809
5.2
WDI Input (Pin 20)
The microcontroller has to provide a trigger signal with the frequency fWDI, which is fed to the
WDI input. A positive edge of fWDI detected by a slope detector resets the binary counter and
also clocks the up/down counter. The up/down counter only counts from 0 to 3 or reverse. Each
correct trigger increments the up/down counter by 1, each wrong trigger decrements it by 1. As
soon as the counter reaches the count of 3 the RS flip-flop is set (see Figure 5-2). A missing
incoming trigger signal is detected after 250 clocks of the internal watchdog frequency fRC (see
“WD-OK Output” ) and resets the up/down counter directly.
5.3
RCOSC Input
The IC generates a time base (frequency fRC) independent from the microcontroller via external
RC circuitry. The watchdog's time window refers to a frequency of
RC = 100 × fWDI
5.4
5.5
Reset Input
During power-on and undervoltage/overvoltage detection, a reset signal is fed to this pin. It
resets the watchdog timer and sets the initial state.
WD-OK Output
After the up/down counter has reached 3 (see the WD state diagram, Figure 5-2 on page 7), the
RS flip-flop is set and the WD-OK output becomes logic 1. This information is available for the
microcontroller at the open-collector output ENO. If, on the other hand, the up/down counter is
decremented to 0, the RS flip-flop is reset, and the WD-OK output and the ENO output are dis-
abled. The WD-OK output also controls a dual MUX stage which shifts the time window by one
clock after a successful trigger, thus forming a hysteresis to provide stable conditions for the
evaluation of the trigger signal "good” or “bad". The WD-OK signal is also reset if the watchdog
counter is not reset after 250 clocks (missing trigger signal).
5.6
Watchdog State Diagram
Figure 5-2. Watchdog State Diagram
good
bad
Initial status
2/NF
1/NF
good
bad
good
bad
O/F
bad
3/NF
bad
good
bad
good
1/F
2/F
good
In each block, the number represents the state of the counter. “F” or “NF” indicates the fault sta-
tus of the counter. Fault status is indicated by "F" and no-fault status is indicated by "NF". When
the watchdog is powered up initially, the counter starts at the 0/F block (initial state). "Good" indi-
cates that a pulse has been received whose width resides within the timing window. "Bad"
indicates that a pulse has been received whose width is either too short or too long.
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4902A–AUTO–11/05
5.7
Watchdog Window Calculation
Example with recommended values
C
R
osc = 3.3 nF (should preferably be 10%, NPO)
osc = 39 kΩ (may be 5%, Rosc < 100 kΩ due to leakage current and humidity)
5.8
5.9
RC Oscillator
tWDC (s) = 10–3 × [Cosc (nF) × [(0.00078 × Rosc (kΩ)) + 0.0005]]
WDC (Hz) = 1 / (tWDC
f
)
Watchdog WDI
fWDI (Hz) = 0.01 × fWDC
tWDC = 100 µs -> fWDC = 10 kHz
WDI = 100Hz -> tWDI = 10 ms
f
5.9.1
WDI Pulse Width for Fault Detection After 3 Pulses
Upper watchdog window
Minimum: 169 / fWDC = 16.9 ms -> fWDC / 169 = 59.1Hz
Maximum: 170 / fWDC = 17.0 ms -> fWDC / 170 = 58.8Hz
Lower watchdog window
Minimum: 79 / fWDC = 7.9 ms -> fWDC / 79 = 126.6Hz
Maximum: 80 / fWDC = 8.0 ms -> fWDC / 80 = 125.0Hz
5.9.2
WDI Dropouts for Immediate Fault Detection
Minimum: 250 / fWDC = 25 ms
Maximum: 251 / fWDC = 25.1 ms
Figure 5-3. Watchdog Timing Diagram with Tolerances
Time/s
79
/
fWDC
80
/
fWDC
169
/
fWDC
170
/
fWDC
250
/
fWDC
251 / fWDC
Watchdog
window update
rate is good
Update rate is
either too slow
or pulse has
dropped out
Update rate is
either too fast or
good
Update rate is
either too slow
or good
Update rate is
too fast
Update rate is
too slow
Pulse has
dropped out
5.9.3
Remark to Reset Delay
The duration of the overvoltage or undervoltage pulse determines the enable and reset output. A
pulse duration shorter than the debounce time has no effect on the outputs. A pulse longer than
the debounce time results in the first reset delay. If a pulse appears during this delay, a 2nd
delay time is triggered. Therefore, the total reset delay time can be longer than specified in the
datasheet.
8
ATA6809
4902A–AUTO–11/05
ATA6809
6. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
VS
Value
–0.2 to +16
±1.5
Unit
V
Supply voltage range
AUX GND offset voltage to GND
AUX GND offset current to GND
VAUX
IAUX
V
–600
mA
Power dissipation VS = 5V;
Tamb = 125°C
Ptot
700
mW
Thermal resistance
Rthjc
Tj
25
K/W
° C
Junction temperature
150
Ambient temperature range
Storage temperature range
Tamb
Tstg
–40 to +125
–55 to +155
° C
° C
7. Electrical Characteristics
VS = 5V, Tamb = –40 to +125°C; reference pin is GND; fintern = 100 kHz + 50% – 45%, fWDC = 10 kHz ±10%; fWDI = 100Hz
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Supply Voltage
Operation range general
Operation range reset
Supply Current
VS
VS
4.5
1.5
5.5
V
V
16.0
Tamb = –40°C
Tamb = 125°C
40
35
mA
mA
Lamp driver on, relay off
Lamp driver off, relay on
Tamb = –40°C
Tamb = 125°C
25
20
mA
mA
Tamb = –40°C
Tamb = 125°C
15
10
mA
mA
Lamp driver off, relay off
Auxiliary Ground (AUX GND)
Tamb = –40°C
Tamb = 90° C
Tamb = 125°C
–1.2
–0.65
–0.5
1.2
1.0
0.8
V
V
V
AUX GND offset voltage operation
range
AUX GND offset voltage to GND
IAUX = –600 mA
–1.7
3.0
V
Digital Inputs (LA1I, LA2I, REL1 and WDI)
Detection low
–0.2
0.2 × VS
V
V
VS +
0.5V
Detection high
0.7 × VS
Resistance to VS
10
100
–5
40
550
5
kΩ
µA
µA
Input current low
Input current high
Input voltage = 0V
Input voltage = VS
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4902A–AUTO–11/05
7. Electrical Characteristics (Continued)
VS = 5V, Tamb = –40 to +125°C; reference pin is GND; fintern = 100 kHz + 50% – 45%, fWDC = 10 kHz ±10%; fWDI = 100Hz
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Digital Outputs; Lamp Driver Feedbacks (FBLA1, FBLA2)
Voltage low
Voltage high
I ≤1.6 mA
I ≤10A
0
0.5
VS
V
V
0.8 × VS
0.7 ×
10A ≤I ≤1.6 mA
VS + 0.1
Threshold voltage detection
Threshold current detection
0.4 × VS
0.5 × VS
V
10
50
mA
Digital Outputs (PRES and NRES)
0.7 ×
VS + 0.1
Voltage high
Voltage low
I ≤100A
I ≤1 mA
VS
V
V
0
0.3
Digital Output (ENO) with Open Collector
Saturation voltage low
Clamping voltage
Current limit low
I ≤25 mA
0
0.3
30
V
V
26
25
mA
VENO = 5V
VENO = 16V
VENO = 26V
20
100
200
µA
µA
µA
Leakage current
Lamp Drivers (LA1O and LA2O) with Integrated Pull-up Resistor
I ≤125 mA; VS = 5V
Saturation voltage
0.5
1.5
V
V
I ≤125 mA; VS = 0V
I ≤250 mA; VS = 5V
Saturation voltage
1.0
2.0
3.0
V
V
V
I ≤250 mA; VS = 0V
250 mA requires enhanced heat sink
I ≤250 mA; no GND
T
amb = 90°C
250
180
mA
mA
Maximum load current
Clamping voltage
Leakage current
Tamb = 125°C
26
30
V
VLA1O, LA2O = 16V
VLA1O, LA2O = 26V
1
3
mA
mA
Threshold current limitation
Pull-up resistor
0.5
2
1.0
17
A
kΩ
Relay Driver (RELO)
Saturation voltage
I ≤250 mA
0.5
V
Tamb = 90° C
Tamb = 125°C
250
200
mA
mA
Maximum load current
Clamping voltage
Leakage current
26
30
V
V
Batt = 16V
20
200
µA
µA
VBatt = 26V
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ATA6809
4902A–AUTO–11/05
ATA6809
7. Electrical Characteristics (Continued)
VS = 5V, Tamb = –40 to +125°C; reference pin is GND; fintern = 100 kHz + 50% – 45%, fWDC = 10 kHz ±10%; fWDI = 100Hz
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Reset and VS Control
Lower reset level
Upper reset level
Hysteresis
VS
VS
4.5
5.2
25
4.8
5.5
V
V
mV
µs
ms
Reset debounce time
Reset delay
120
20
500
80
Watchdog Timing
Feedback reaction time
(FBLA1, FBLA2)
No fault, edge at LA1I, LA2I
No fault, pulse at LA1I, LA2I
tFB
2.56
12.8
ms
ms
Minimum lamp input toggle time for a
secure feedback reaction
tP, F B
10.24
Power-on-reset prolongation time
Detection time for RC-oscillator fault
tPOR
34.3
81.9
103.1
246
ms
ms
VRC = constant
tRCerror
Time interval for overvoltage/
undervoltage detection
tD,OUV
tR,OUV
tP, B G N D
tR,BGND
0.16
0.187
13.3
0.64
0.72
ms
ms
µs
Reaction time of NRES output on
overvoltage/undervoltage
Minimum toggle time for a secure
broken ground detection
Maximum reaction time for broken
ground detection
100
µs
Nominal frequency for WDI
Nominal frequency for RC
fRC = 100 × fWDI
fWDI
fRC
10
1
130
13
Hz
fWDI = 1
/
100 × fRC
kHz
Minimum pulse duration for a secure
WDI input pulse detection
tP, W D I
fWDI
182
µs
Frequency range for a correct
WDI signal
64.7
112.5
25.5
Hz
Number of incorrect WDI trigger
counts for locking the outputs
nlock
3
3
Number of correct WDI trigger counts
for releasing the outputs
nrelease
tWDIerror
Detection time for a stuck
WDI signal
VWDI = constant
24.5
ms
Watchdog Timing Relative to fRC
Minimum pulse duration for a securely
WDI input pulse detection
2
1
cycles
cycles
cycle
Frequency range for a correct
WDI signal
80
170
251
Hysteresis range at the
WDI ok margins
Detection time for a stuck
WDI signal
VWDI = constant
250
cycles
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4902A–AUTO–11/05
Table 7-1.
Pulse
Protection Against Transient Voltages According to ISO TR 7637-3 Level 4 (Except Pulse 5)
Voltage
–110V
+110V
–160V
+150V
40V
Source Resistance(1)
Rise Time
100V/s
Duration
2 ms
Amount
15.000
15.000
1h
1
2
10Ω
10Ω
50Ω
50Ω
2Ω
100V/s
0.05 ms
0.1s
3a
3b
5
30V/ns
20V/ns
0.1s
1h
10V/ms
250 ms
20
Note:
1. Lamp drivers: 1.2Ωlamps need to be added to the source resistance.
Relay driver: relay coil with Rmin = 70Ω need to be added to the source resistance.
7.1
Application Hints
a.)
b.)
The lamp output pins LA1O and LA2O may need to be protected by external
protection diodes (for example, BAV 202) against reversed battery, in order
to avoid a reset during negative pulses.
If pilot lamps with a wattage of P > 1.2W are connected, external Zener diodes
are mandatory.
8. Timing Diagrams
Figure 8-1. Watchdog in Too Fast Condition
Normal operation
WDI too fast
Normal operation
5 V
WDI
0 V
VBatt
RELO
0 V
5 V
ENO
0 V
VBatt
LAXO
0 V
Don't care
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ATA6809
Figure 8-2. Watchdog in Too Slow Condition
Normal operation
WDI too low
Normal operation
5 V
WDI
0 V
VBatt
RELO
0 V
5 V
ENO
0 V
VBatt
LAXO
0 V
Don't care
Figure 8-3. Overvoltage Condition
Overvoltage condition
> 120 µs
< 120 µs
≥ 5.5 V
5 V
VS
≥ 5.5 V
0 V
VBatt
RELO
0 V
5 V
ENO
0 V
5 V
NRES
0 V
VBatt
LAXO
0 V
3 good WDI pulses
2nd Reset delay
Reset debounce time
Don't care
1st Reset delay
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4902A–AUTO–11/05
Figure 8-4. Undervoltage Condition
Undervoltage condition
> 120 µs
< 120 µs
5 V
0 V
≤ 4.5 V
≤ 4.5 V
VS
VBatt
RELO
ENO
0 V
5 V
0 V
5 V
NRES
LAXO
0 V
VBatt
0 V
3 good WDI pulses
2nd Reset delay
Reset debounce time
Don't care
1st Reset delay
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9. Ordering Information
Extended Type Number
Package
Remarks
ATA6809-TGQY
SO20 special lead frame
Taped and reeled, Pb-free
10. Package Information
9.15
8.65
Package SO20
Dimensions in mm
12.95
12.70
7.5
7.3
2.35
0.25
0.25
0.10
0.4
10.50
10.20
1.27
11.43
20
11
technical drawings
according to DIN
specifications
1
10
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4902A–AUTO–11/05
Atmel Corporation
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Microcontrollers
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CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
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La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
BP 123
38521 Saint-Egreve Cedex, France
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Fax: (33) 4-76-58-34-80
Asia
Room 1219
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77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
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ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
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