AT93C86-10SJ-2.7 [ATMEL]
EEPROM, 1KX16, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, MS-012, SOIC-8;
| 型号： | AT93C86-10SJ-2.7 |
| 厂家： | 
ATMEL |
| 描述： | EEPROM, 1KX16, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, MS-012, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总15页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
• User Selectable Internal Organization
– 16K: 2048 x 8 or 1024 x 16
• 3-wire Serial Interface
• Sequential Read Operation
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• 2 MHz Clock Rate (5V) Compatibility
• Self-timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade, Extended Temperature and Lead-Free Devices Available
• 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
3-wire Serial
EEPROM
16K (2048 x 8 or 1024 x 16)
Description
The AT93C86 provides 16384 bits of serial electrically erasable programmable read
only memory (EEPROM) organized as 1024 words of 16 bits each when the ORG Pin
is connected to VCC and 2048 words of 8 bits each when it is tied to ground. The
device is optimized for use in many industrial and commercial applications where low
power and low voltage operations are essential. The AT93C86 is available in space
saving 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages.
AT93C86
The AT93C86 is enabled through the Chip Select pin (CS), and accessed via a 3-wire
serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK).
Pin Configurations
8-lead PDIP
Pin Name
Function
CS
Chip Select
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
DC
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
ORG
GND
DI
DO
DO
GND
VCC
ORG
DC
Power Supply
Internal Organization
Don’t Connect
8-lead SOIC
CS
1
8
7
6
5
VCC
SK
DI
2
3
4
DC
ORG
GND
DO
8-lead TSSOP
CS
1
2
3
4
8
7
6
5
VCC
DC
SK
DI
ORG
GND
DO
Rev. 1237F–SEEPR–9/03
Upon receiving a READ instruction at DI, the address is decoded and the data is clocked out serially on the data output pin
DO. The WRITE cycle is completely self-timed and no separate ERASE cycle is required before WRITE. The WRITE cycle
is only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is brought “high” following the initiation of
a WRITE cycle, the DO pin outputs the READY/BUSY status of the part. The AT93C86 is available in a 2.7V to 5.5V
version.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
Vcc
GND
MEMORY ARRAY
ADDRESS
DECODER
2048 x 8
OR
ORG
1024 x 16
DATA
REGISTER
OUTPUT
BUFFER
DI
MODE
DECODE
LOGIC
CS
CLOCK
GENERATOR
DO
SK
Note:
1. When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organiza-
tion is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the
internal 1 Meg ohm pullup, then the x 16 organization is selected. This feature is not available on the 1.8V devices.
2
AT93C86
1237F–SEEPR–9/03
AT93C86
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max
5
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
5
pF
Note:
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.7V to +5.5V,
TAE = -40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise noted).
Symbol
VCC1
Parameter
Test Condition
Min
2.7
4.5
Typ
Max
5.5
Unit
V
Supply Voltage
Supply Voltage
VCC2
5.5
V
READ at 1.0 MHz
WRITE at 1.0 MHz
CS = 0V
0.5
0.5
6.0
17
2.0
mA
mA
µA
µA
µA
µA
ICC
Supply Current
VCC = 5.0V
2.0
ISB1
ISB2
IIL
Standby Current
Standby Current
Input Leakage
VCC = 2.7V
10.0
30
VCC = 5.0V
CS = 0V
VIN = 0V to VCC
VIN = 0V to VCC
0.1
0.1
1.0
IOL
Output Leakage
1.0
(1)
VIL1
VIH1
Input Low Voltage
Input High Voltage
-0.6
CC x 0.7
VCC x 0.3
4.5V ≤ VCC ≤ 5.5V
V
V
(1)
V
V
V
CC + 1
(1)
VIL2
VIH2
Input Low Voltage
Input High Voltage
-0.6
CC x 0.7
VCC x 0.3
V
CC ≤ 2.7V
(1)
V
CC + 1
0.4
IOL = 2.1 mA
V
V
V
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
4.5V ≤ VCC ≤ 5.5V
I
I
I
OH = -0.4 mA
OL = 0.15 mA
OH = -100 µA
2.4
0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
V
CC ≤ 2.7V
VCC - 0.2
Note:
1. VIL min and VIH max are reference only and are not tested.
3
1237F–SEEPR–9/03
AC Characteristics
Applicable over recommended operating range from TAI = -40°C to + 85°C, TAE = -40°C to + 125°C,VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
SK Clock
Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0
0
2
1
fSK
MHz
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
tSKH
tSKL
tCS
SK High Time
SK Low Time
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
Minimum CS
Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
50
50
tCSS
CS Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
tDIS
tCSH
tDIH
DI Setup Time
CS Hold Time
DI Hold Time
Relative to SK
Relative to SK
Relative to SK
ns
ns
ns
0
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
tPD1
tPD0
tSV
Output Delay to ‘1’
Output Delay to ‘0’
CS to Status Valid
AC Test
AC Test
AC Test
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
CS to DO in High
Impedance
AC Test
CS = VIL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
tDF
10
ms
ms
tWP
Write Cycle Time
4.5V ≤ VCC ≤ 5.5V
4
Endurance(1)
5.0V, 25°C, Page Mode
1M
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
4
AT93C86
1237F–SEEPR–9/03
AT93C86
Instruction Set for the AT93C86
Address
Data
Instruction
SB
Op Code
x 8
x 16
x 8
x 16
Comments
READ
1
10
A
10 - A0
A9 - A0
Reads data stored in memory,
at specified address.
EWEN
1
00
11XXXXXXXX
11XXXXXXXX
Write enable must precede all
programming modes.
ERASE
WRITE
ERAL
1
1
1
11
01
00
A
10 - A0
A9 - A0
A9 - A0
Erases memory location An - A0.
A
10 - A0
D7 - D0
D7 - D0
D15 - D0 Writes memory location An - A0.
10XXXXXXXX
10XXXXXXXX
Erases all memory locations.
Valid only at VCC = 4.5V to 5.5V.
WRAL
EWDS
1
1
00
00
01XXXXXXXX
01XXXXXXXX
00XXXXXXXX
D15 - D0 Writes all memory locations.
Valid when VCC = 4.5V to 5.5V and
Disable Register cleared.
00XXXXXXXX
Disables all programming instructions.
Functional
Description
The AT93C86 is accessed via a simple and versatile 3-wire serial communication inter-
face. Device operation is controlled by seven instructions issued by the host processor.
A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic
“1”) followed by the appropriate Op Code and the desired memory Address location.
READ (READ): The Read (READ) instruction contains the Address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C86 sup-
ports sequential read operations. The device will automatically increment the internal
address pointer and clock out the next memory location as long as Chip Select (CS) is
held high. In this case, the dummy bit (logic “0”) will not be clocked out between memory
locations, thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the Erase/Write Enable state, programming
remains enabled until an Erase/Write Disable (EWDS) instruction is executed or VCC
power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
A logic “1” at pin DO indicates that the selected memory location has been erased, and
the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle, tWP, starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
READY/BUSY status of the part if CS is brought high after being kept low for a minimum
of 250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic
5
1237F–SEEPR–9/03
“1” indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
READY/BUSY status cannot be obtained if the CS is brought high after the end of
the self-timed programming cycle, tWP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the READY/BUSY status of the part if CS is brought high after being kept low for
a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
6
AT93C86
1237F–SEEPR–9/03
AT93C86
Timing Diagrams
Synchronous Data Timing
Note:
1. This is the minimum SK period.
Organization Key for Timing Diagrams
AT93C86 (16K)
I/O
AN
DN
x 8
A10
D7
x 16
A9
D15
7
1237F–SEEPR–9/03
READ Timing
tCS
High Impedance
EWEN Timing
tCS
CS
SK
DI
...
1
0
0
1
1
EWDS Timing
tCS
CS
SK
DI
...
0
0
0
1
0
8
AT93C86
1237F–SEEPR–9/03
AT93C86
WRITE Timing
tCS
CS
SK
DI
...
...
AN
DN
1
0
1
A0
D0
HIGH IMPEDANCE
BUSY
READY
DO
tWP
WRAL Timing(1)
tCS
CS
SK
DI
1
0
0
0
1
...
DN ... D0
BUSY
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
9
1237F–SEEPR–9/03
ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
A0
1
1
1
AN
...
AN-1 AN-2
tDF
tSV
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
DO
READY
tWP
ERAL Timing(1)
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
1
0
0
1
0
tDF
tSV
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
10
AT93C86
1237F–SEEPR–9/03
AT93C86
AT93C86 Ordering Information
Ordering Code
Package
Operation Range
AT93C86-10PI-2.7
AT93C86-10SI-2.7
AT93C86-10TI-2.7
8P3
8S1
8A2
Industrial
(-40°C to 85°C)
AT93C86-10SJ-2.7
8S1
Lead-Free/Industrial Temperature
(-40°C to 85°C)
AT93C86-10SE-2.7
8S1
High Grade/Extended Temperature
(-40°C to 125°C)
Note:
For 2.7V devices used in a 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
8P3
8S1
8A2
-2.7
Low Voltage (2.7V to 5.5V)
11
1237F–SEEPR–9/03
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
12
AT93C86
1237F–SEEPR–9/03
AT93C86
8S1 – JEDEC SOIC
1
3
2
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
–
MAX
1.75
0.51
0.25
5.00
4.00
NOM
NOTE
SYMBOL
A
B
C
D
E
e
–
A2
L
–
–
–
–
–
–
–
–
1.27 BSC
E
H
L
–
–
–
–
6.20
1.27
End View
Note:
This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
A
R
Small Outline (JEDEC SOIC)
13
1237F–SEEPR–9/03
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
14
AT93C86
1237F–SEEPR–9/03
Atmel Corporation
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others.
Printed on recycled paper.
1237F–SEEPR–9/03
xM
相关型号：
AT93C86A-10PQ-2.7
EEPROM, 1KX16, Serial, CMOS, PDIP8, 0.300 INCH, LEAD AND HALOGEN FREE, PLASTIC, MS-001BA, DIP-8
ATMEL
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