AT93C86A-10PU-1.8 [ATMEL]
Three-wire Serial EEPROM; 三线制串行EEPROM
| 型号： | AT93C86A-10PU-1.8 |
| 厂家： | 
ATMEL |
| 描述： | Three-wire Serial EEPROM |
| 文件： | 总18页 (文件大小：722K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• User Selectable Internal Organization
– 16K: 2048 x 8 or 1024 x 16
• Three-wire Serial Interface
• Sequential Read Operation
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• 2 MHz Clock Rate (5V) Compatibility
• Self-timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Devices Available
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), and 8-
lead TSSOP Packages
Three-wire
Serial
EEPROM
16K (2048 x 8 or 1024 x 16)
• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Description
AT93C86A
The AT93C86A provides 16384 bits of serial electrically erasable programmable read
only memory (EEPROM), organized as 1024 words of 16 bits each when the ORG pin
is connected to VCC and 2048 words of eight bits each when it is tied to ground. The
device is optimized for use in many industrial and commercial applications where low-
power and low-voltage operations are essential. The AT93C86A is available in space
saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), and 8-
lead TSSOP packages.
Table 1. Pin Configurations
8-lead PDIP
Pin Name
CS
Function
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
NC
Chip Select
ORG
GND
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
DO
DI
DO
8-lead SOIC
GND
VCC
ORG
NC
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
NC
Power Supply
Internal Organization
No Connect
ORG
GND
DO
8-lead
Ultra Thin Mini-MAP (MLP
2x3)
8-lead TSSOP
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
8
7
6
5
1
2
3
4
VCC
NC
CS
SK
DI
DO
ORG
GND
DO
Bottom View
Rev. 3408H–SEEPR–1/07
The AT93C86A is enabled through the Chip Select pin (CS), and accessed via a three-
wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a Read instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The Write cycle is completely self-timed
and no separate Erase cycle is required before Write. The Write cycle is only enabled
when the part is in the Erase/Write Enable state. When CS is brought “high” following
the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part. The
AT93C86A is available in a 2.7V to 5.5V version.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
Vcc
GND
MEMORY ARRAY
ADDRESS
DECODER
2048 x 8
OR
ORG
1024 x 16
DATA
REGISTER
OUTPUT
BUFFER
DI
MODE
DECODE
LOGIC
CS
CLOCK
GENERATOR
DO
SK
Note:
When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organization
is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1
Meg ohm pullup, then the x 16 organization is selected.
2
AT93C86A
3408H–SEEPR–1/07
AT93C86A
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol
COUT
CIN
Test Conditions
Max
5
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
5
pF
Note:
1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V,
AE = −40°C to +125°C, VCC = +1.8V to +5.5V (unless otherwise noted)
T
Symbol
VCC1
Parameter
Test Condition
Min
1.8
2.7
4.5
Typ
Max
5.5
5.5
5.5
2.0
2.0
0.1
10.0
30
Unit
V
Supply Voltage
Supply Voltage
Supply Voltage
VCC2
V
VCC3
V
READ at 1.0 MHz
WRITE at 1.0 MHz
CS = 0V
0.5
0.5
0
mA
mA
µA
µA
µA
µA
µA
ICC
Supply Current
VCC = 5.0V
ISB1
ISB2
ISB3
IIL
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 1.8V
VCC = 2.7V
CS = 0V
6.0
17
VCC = 5.0V
CS = 0V
VIN = 0V to VCC
VIN = 0V to VCC
0.1
0.1
3.0
3.0
IOL
Output Leakage
(1)
--−0.6
2.0
VIL1
Input Low Voltage
Input High Voltage
0.8
VCC + 1
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 2.7V
V
V
(1)
VIH1
(1)
VIL2
Input Low Voltage
Input High Voltage
−0.6
CC x 0.7
V
CC x 0.3
VCC + 1
(1)
VIH2
V
I
I
I
OL = 2.1 mA
OH = –0.4 mA
OL = 0.15 mA
0.4
0.2
V
V
V
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 2.7V
2.4
VOL2
VOH2
Output Low Voltage
Output High Voltage
IOH = –100 µA
VCC – 0.2
Note:
1. VIL min and VIH max are reference only and are not tested.
3
3408H–SEEPR–1/07
Table 4. AC Characteristics
Applicable over recommended operating range from TAI = −40°C to + 85°C, TAE = −40°C to +125°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
0
0
0
2
1
0.25
SK Clock
Frequency
fSK
MHz
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
tSKH
tSKL
tCS
SK High Time
SK Low Time
ns
ns
ns
ns
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
Minimum CS
Low Time
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
50
200
tCSS
CS Setup Time
Relative to SK
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
400
tDIS
tCSH
tDIH
DI Setup Time
CS Hold Time
DI Hold Time
Relative to SK
Relative to SK
Relative to SK
ns
ns
ns
0
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
400
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
tPD1
tPD0
tSV
Output Delay to “1”
Output Delay to “0”
CS to Status Valid
AC Test
AC Test
AC Test
ns
ns
ns
ns
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
CS to DO in High
Impedance
AC Test
CS = VIL
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
150
400
tDF
1.8V ≤ VCC ≤ 5.5V
0.1
1M
3
10
ms
ms
tWP
Write Cycle Time
5.0V, 25°C
Endurance(1)
Write Cycles
Note:
1. This parameter is ensured by characterization.
4
AT93C86A
3408H–SEEPR–1/07
AT93C86A
Table 5. Instruction Set for the AT93C86A
Address
Data
Instruction
SB
Op Code
x 8
x 16
x 8
x 16
Comments
READ
1
10
A
10 – A0
A9 – A0
Reads data stored in memory,
at specified address.
EWEN
1
00
11XXXXXXXXX
11XXXXXXXX
Write enable must precede all
programming modes.
ERASE
WRITE
ERAL
1
1
1
11
01
00
A
10 – A0
A9 – A0
A9 – A0
Erases memory location An – A0.
A
10 – A0
D7 – D0
D7 – D0
D15 – D0 Writes memory location An – A0.
10XXXXXXXXX
10XXXXXXXX
Erases all memory locations.
Valid only at VCC = 4.5V to 5.5V.
WRAL
EWDS
1
1
00
00
01XXXXXXXXX
01XXXXXXXX
00XXXXXXXX
D15 – D0 Writes all memory locations.
Valid when VCC = 4.5V to 5.5V and
Disable Register cleared.
00XXXXXXXXX
Disables all programming
instructions.
Functional
Description
The AT93C86A is accessed via a simple and versatile three-wire serial communication
interface. Device operation is controlled by seven instructions issued by the host pro-
cessor. A valid instruction starts with a rising edge of CS and consists of a Start Bit
(logic “1”) followed by the appropriate Op Code and the desired memory address
location.
READ (READ): The Read (READ) instruction contains the address code for the mem-
ory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C86A sup-
ports sequential read operations. The device will automatically increment the internal
address pointer and clock out the next memory location as long as CS is held high. In
this case, the dummy bit (logic “0”) will not be clocked out between memory locations,
thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the EWEN state, programming remains enabled
until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the Ready/Busy sta-
tus of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A
logic “1” at pin DO indicates that the selected memory location has been erased, and the
part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle tWP starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of
5
3408H–SEEPR–1/07
250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1”
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
Ready/Busy status cannot be obtained if the CS is brought high after the end of the self-
timed programming cycle tWP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturbance, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
6
AT93C86A
3408H–SEEPR–1/07
AT93C86A
Timing Diagrams
Figure 2. Synchronous Data Timing
Note:
1. This is the minimum SK period.
Organization Key for Timing Diagrams
AT93C86A (16K)
I/O
AN
DN
x 8
A10
D7
x 16
A9
D15
Figure 3. READ Timing
7
3408H–SEEPR–1/07
Figure 4. EWEN Timing
tCS
CS
SK
DI
...
1
0
0
1
1
Figure 5. EWDS Timing
tCS
CS
SK
DI
...
0
0
0
1
0
Figure 6. WRITE Timing
tCS
CS
SK
DI
...
...
AN
DN
1
0
1
A0
D0
HIGH IMPEDANCE
BUSY
READY
DO
tWP
8
AT93C86A
3408H–SEEPR–1/07
AT93C86A
Figure 7. WRAL Timing(1)
tCS
CS
SK
DI
1
0
0
0
1
...
DN ... D0
BUSY
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
Figure 8. ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
A0
1
1
1
AN
...
AN-1 AN-2
tDF
tSV
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
DO
READY
tWP
9
3408H–SEEPR–1/07
Figure 9. ERAL Timing(1)
Note:
1. Valid only at VCC = 4.5V to 5.5V.
10
AT93C86A
3408H–SEEPR–1/07
AT93C86A
AT93C86A Ordering Information(1)
Ordering Code
Package
Operation Range
AT93C86A-10PU-2.7(2)
AT93C86A-10PU-1.8(2)
AT93C86A-10SU-2.7(2)
AT93C86A-10SU-1.8(2)
AT93C86A-10TU-2.7(2)
AT93C86A-10TU-1.8(2)
AT93C86AY1-10YU-1.8(2)(Not recommended for new
design)
AT93C86AY6-10YH-1.8(3)
8P3
8P3
8S1
8S1
8A2
8A2
8Y1
8Y6
Lead-Free/Halogen-Free/
Industrial Temperature
(−40°C to 85°C)
Industrial Temperature
AT93C86A-W1.8-11(4)
Die Sale
(−40°C to 85°C)
Notes: 1. For 2.7V devices used in a 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.
2. “U” designates Green package + RoHS compliant.
3. “H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish.
4. Available in Waffle pack and Wafer form; order as SL788 for inkless Wafer form. Bumped die available upon request. Please
contact Serial EEPROM marketing.
Package Type
8P3
8S1
8A2
8Y1
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3
mm)
8Y6
Options
Low Voltage (2.7V to 5.5V)
−2.7
−1.8
Low Voltage (1.8V to 5.5V)
11
3408H–SEEPR–1/07
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
12
AT93C86A
3408H–SEEPR–1/07
AT93C86A
8Y6 - MLP 2x3 mm
A
D2
b
(8X)
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
e (6X)
A2
A1
1.50 REF.
A3
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
2.00 BSC
3.00 BSC
1.50
NOTE
SYMBOL
D
E
D2
E2
A
1.40
1.60
1.40
0.60
0.05
0.55
-
-
-
-
A1
A2
A3
L
0.0
-
0.02
-
0.20 REF
0.30
0.20
0.20
0.40
0.30
e
0.50 BSC
0.25
b
2
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
8/26/05
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
Dual No Lead Package (DFN) ,(MLP 2x3)
8Y6
C
R
13
3408H–SEEPR–1/07
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
B
C
D
E1
E
e
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.00
3.99
6.20
–
–
D
–
–
Side View
1.27 BSC
L
0.40
0°
–
–
1.27
8°
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
REV.
TITLE
DRAWING NO.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
B
R
Small Outline (JEDEC SOIC)
14
AT93C86A
3408H–SEEPR–1/07
AT93C86A
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
15
3408H–SEEPR–1/07
8Y1 - MAP
PIN 1 INDEX AREA
A
1
3
4
2
PIN 1 INDEX AREA
E1
D1
D
L
8
6
5
7
b
e
A1
E
Bottom View
End View
Top View
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
MIN
–
MAX
0.90
0.05
5.10
3.20
1.15
1.15
0.35
NOM
–
NOTE
A
A1
D
0.00
4.70
2.80
0.85
0.85
0.25
–
4.90
3.00
1.00
1.00
0.30
0.65 TYP
0.60
Side View
E
D1
E1
b
e
L
0.50
0.70
2/28/03
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1
8Y1
C
R
16
AT93C86A
3408H–SEEPR–1/07
AT93C86A
Revision History
Doc. Rev.
Date
Comments
3408H
1/2007
Add “Bottom View” to pg 1 Ultra Thin MiniMap package drawing
pg 4 revise Note 1 added “ensured by characterization”
3408G
7/2006
Revision history implemented.
Deleted ‘Preliminary’ status from datasheet; Added ‘Ultra Thin’
description to MLP 2x3 package; Deleted ‘1.8V not available’ on
Figure 1 Note; Added 1.8V range on Table 4 under Write Cycle
Time.
17
3408H–SEEPR–1/07
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
Fax: (33) 4-76-58-34-80
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.
© 2007 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are® and others, are registered trade-
marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
Printed on recycled paper.
3408H–SEEPR–1/07
相关型号：
©2020 ICPDF网 联系我们和版权申明