AT93C86A-10SQ-2.7 [ATMEL]
Three-wire Automotive Temperature Serial EEPROM 16K (2048 x 8 or 1024 x 16); 三线汽车温度串行EEPROM 16K （ 2048 ×8或1024 ×16 ）
| 型号： | AT93C86A-10SQ-2.7 |
| 厂家： | 
ATMEL |
| 描述： | Three-wire Automotive Temperature Serial EEPROM 16K (2048 x 8 or 1024 x 16) |
| 文件： | 总14页 (文件大小：452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1. Features
• Medium-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
• Automotive Temperature Range –40°C to +125°C
• User Selectable Internal Organization
– 16K: 2048 x 8 or 1024 x 16
• 3-wire Serial Interface
• Sequential Read Operation
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• 2 MHz Clock Rate (5V) Compatibility
• Self-timed Write Cycle (10 ms max)
• High Reliability
Three-wire
Automotive
Temperature
Serial
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Lead-Free/Halogen-Free Devices Available
• 8-lead JEDEC SOIC and 8-lead TSSOP Packages
EEPROM
2. Description
16K (2048 x 8 or 1024 x 16)
The AT93C86A provides 16384 bits of serial electrically erasable programmable read
only memory (EEPROM), organized as 1024 words of 16 bits each when the ORG pin
is connected to VCC and 2048 words of 8 bits each when it is tied to ground. The
device is optimized for use in many automotive applications where low-power and
low-voltage operations are essential. The AT93C86A is available in space saving 8-
lead JEDEC SOIC and 8-lead TSSOP packages.
AT93C86A
Table 2-1.
Pin Name
CS
Pin Configuration
Function
8-lead SOIC
Chip Select
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
DC
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
ORG
GND
DI
DO
DO
GND
VCC
ORG
DC
Power Supply
Internal Organization
Don’t Connect
8-lead TSSOP
CS
1
2
3
4
8
7
6
5
VCC
DC
SK
DI
ORG
GND
DO
The AT93C86A is enabled through the Chip Select pin (CS), and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the
data is clocked out serially on the data output pin DO. The write cycle is completely
self-timed and no separate erase cycle is required before Write. The write cycle is only
enabled when the part is in the Erase/Write Enable state. When CS is brought “high”
following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of
the part. The AT93C86A is available in a 2.7V to 5.5V version.
Rev. 5096E–SEEPR–1/08
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature..................................–55°C to +125°C
Storage Temperature.....................................–65°C to +150°C
Voltage on any Pin
with Respect to Ground....................................–1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 2-1. Block Diagram
Vcc
GND
MEMORY ARRAY
ADDRESS
DECODER
2048 x 8
OR
ORG
1024 x 16
DATA
REGISTER
OUTPUT
BUFFER
DI
MODE
DECODE
LOGIC
CS
CLOCK
GENERATOR
DO
SK
Note:
When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organization
is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1
Meg ohm pullup, then the x 16 organization is selected.
Table 2-2.
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Pin Capacitance(1)
Symbol
COUT
CIN
Test Conditions
Max
5
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
5
pF
Note:
1. This parameter is characterized and is not 100% tested.
2
AT93C86A
5096E–SEEPR–1/08
AT93C86A
Table 2-3.
DC Characteristics
Applicable over recommended operating range from: TA = –40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise
noted)
Symbol
VCC1
Parameter
Test Condition
Min
2.7
4.5
Typ
Max
5.5
Unit
V
Supply Voltage
Supply Voltage
VCC2
5.5
V
READ at 1.0 MHz
WRITE at 1.0 MHz
CS = 0V
0.5
0.5
2.0
mA
mA
µA
µA
µA
µA
V
ICC
Supply Current
VCC = 5.0V
2.0
ISB1
ISB2
IIL
Standby Current
Standby Current
Input Leakage
Output Leakage
VCC = 2.7V
6.0
10.0
15.0
3.0
VCC = 5.0V
CS = 0V
10.0
0.1
0.1
VIN = 0V to VCC
VIN = 0V to VCC
IOL
3.0
(1)
−−−−0.6
0.8
VIL1
Input Low Voltage
Input High Voltage
2.7V ≤ VCC ≤ 5.5V
(1)
VIH1
2.0
VCC + 1
0.4
V
I
I
OL = 2.1 mA
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
2.7V ≤ VCC ≤ 5.5V
OH = –0.4 mA
2.4
V
Note:
1. VIL min and VIH max are reference only and are not tested.
Table 2-4.
AC Characteristics
Applicable over recommended operating range from TA = –40°C to +125°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
SK Clock
Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0
0
2
1
fSK
MHz
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
tSKH
tSKL
tCS
SK High Time
SK Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
ns
Minimum CS
Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
50
50
tCSS
CS Setup Time
Relative to SK
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
tDIS
tCSH
tDIH
DI Setup Time
CS Hold Time
DI Hold Time
Relative to SK
Relative to SK
Relative to SK
ns
ns
ns
0
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
500
tPD1
Output Delay to ‘1’
Output Delay to ‘0’
AC Test
AC Test
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
500
tPD0
3
5096E–SEEPR–1/08
Table 2-4.
AC Characteristics (Continued)
Applicable over recommended operating range from TA = –40°C to +125°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
tSV
CS to Status Valid
AC Test
ns
CS to DO in High
Impedance
AC Test
CS = VIL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
150
tDF
ns
tWP
Write Cycle Time
5.0V, 25°C
2.7V ≤ VCC ≤ 5.5V
0.1
1M
4
10
ms
(1)
Endurance
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
Table 2-5.
Instruction Set for the AT93C86A
Address
Data
Instruction
SB
Op Code
x 8
x 16
x 8
x 16
Comments
READ
1
10
A
10 – A0
A9 – A0
Reads data stored in memory,
at specified address.
EWEN
1
00
11XXXXXXXXX
11XXXXXXXX
Write enable must precede all
programming modes.
ERASE
WRITE
ERAL
1
1
1
11
01
00
A10 – A0
A10 – A0
A9 – A0
A9 – A0
Erases memory location An – A0.
D7 – D0
D7 – D0
D15 – D0 Writes memory location An – A0.
10XXXXXXXXX
10XXXXXXXX
Erases all memory locations.
Valid only at VCC = 4.5V to 5.5V.
WRAL
EWDS
1
1
00
00
01XXXXXXXXX
00XXXXXXXXX
01XXXXXXXX
00XXXXXXXX
D15 – D0 Writes all memory locations.
Valid when VCC = 4.5V to 5.5V and
Disable Register cleared.
Disables all programming
instructions.
4
AT93C86A
5096E–SEEPR–1/08
AT93C86A
3. Functional Description
The AT93C86A is accessed via a simple and versatile 3-wire serial communication interface.
Device operation is controlled by seven instructions issued by the host processor. A valid
instruction starts with a rising edge of CS and consists of a Start Bit (logic “1”) followed by the
appropriate Op Code and the desired memory address location.
READ (READ): The Read (READ) instruction contains the address code for the memory loca-
tion to be read. After the instruction and address are decoded, data from the selected memory
location is available at the serial output pin DO. Output data changes are synchronized with the
rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or
16-bit data output string. The AT93C86A supports sequential read operations. The device will
automatically increment the internal address pointer and clock out the next memory location as
long as CS is held high. In this case, the dummy bit (logic “0”) will not be clocked out between
memory locations, thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN)
instruction must be executed first before any programming instructions can be carried out.
Please note that once in the EWEN state, programming remains enabled until an EWDS instruc-
tion is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory
location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and
address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought
high after being kept low for a minimum of 250 ns (tCS). A logic “1” at pin DO indicates that the
selected memory location has been erased, and the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written
into the specified memory location. The self-timed programming cycle tWP starts after the last bit
of data is received at serial data input pin DI. The DO pin outputs the Ready/Busy status of the
part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO
indicates that programming is still in progress. A logic “1” indicates that the memory location at
the specified address has been written with the data pattern contained in the instruction and the
part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is
brought high after the end of the self-timed programming cycle tWP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array
to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns
(tCS). The Eral instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the
data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if
CS is brought high after being kept low for a minimum of 250 ns (tCS). The Wral instruction is
valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturbance, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be exe-
cuted after all programming operations. The operation of the Read instruction is independent of
both the Ewen and Ewds instructions and can be executed at any time.
5
5096E–SEEPR–1/08
4. Timing Diagrams
Figure 4-1. Synchronous Data Timing
Note:
1. This is the minimum SK period.
Table 4-1.
Organization Key for Timing Diagrams
AT93C86A (16K)
I/O
AN
DN
x 8
A10
D7
x 16
A9
D15
Figure 4-2. READ Timing
6
AT93C86A
5096E–SEEPR–1/08
AT93C86A
Figure 4-3. EWEN Timing
tCS
CS
SK
DI
...
1
0
0
1
1
Figure 4-4. EWDS Timing
tCS
CS
SK
...
0
0
0
DI
1
0
Figure 4-5. WRITE Timing
tCS
CS
SK
...
...
DI
AN
DN
1
0
1
A0
D0
HIGH IMPEDANCE
BUSY
READY
DO
tWP
7
5096E–SEEPR–1/08
Figure 4-6. WRAL Timing(1)
tCS
CS
SK
DI
1
0
0
0
1
...
DN ... D0
BUSY
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
Figure 4-7. ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
A0
DI
1
1
1
AN
...
AN-1 AN-2
tDF
tSV
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
DO
READY
tWP
8
AT93C86A
5096E–SEEPR–1/08
AT93C86A
Figure 4-8. ERAL Timing(1)
D
Note:
1. Valid only at VCC = 4.5V to 5.5V.
9
5096E–SEEPR–1/08
5. AT93C86A Ordering Information
Ordering Code
Package
Operation Range
Lead-free/Halogen-free
Automotive Temperature
AT93C86A-10SQ-2.7
AT93C86A-10TQ-2.7
8S1
8A2
(−40°C to 125°C)
Package Type
8S1
8A2
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
−2.7
Low Voltage (2.7V to 5.5V)
10
AT93C86A
5096E–SEEPR–1/08
AT93C86A
6. Packaging Information
6.1
8S1 – JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.35
0.10
MAX
1.75
0.25
NOM
NOTE
SYMBOL
A1
A
–
–
A1
b
C
D
E1
E
0.31
0.17
4.80
3.81
5.79
–
0.51
0.25
5.05
3.99
6.20
–
–
D
–
–
SIDE VIEW
e
1.27 BSC
L
0.40
0°
–
–
1.27
8°
θ
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
3/17/05
TITLE
DRAWING NO.
REV.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
C
Small Outline (JEDEC SOIC)
R
11
5096E–SEEPR–1/08
6.2
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
D
2.90
3.10
2, 5
A
b
E
6.40 BSC
4.40
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
e
A2
–
D
e
0.65 BSC
0.60
L
0.45
0.75
Side View
L1
1.00 REF
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
DRAWING NO.
TITLE
REV.
2325 Orchard Parkway
San Jose, CA 95131
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
B
8A2
R
12
AT93C86A
5096E–SEEPR–1/08
AT93C86A
7. Revision History
Doc. Rev.
Date
Comments
Moved to new template
5096E
5096D
5096C
1/2008
Replaced Table 5 with correct version
Removed PDIP package offering
Removed Pb’d part numbers
2/2007
9/2006
Revision history implemented; Removed ‘Preliminary’ status
from datasheet.
13
5096E–SEEPR–1/08
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5096E–SEEPR–1/08
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