AT89C51RD2_08_技术文档

Features

80C52 Compatible

•

– 8051 Instruction Compatible

– Six 8-bit I/O Ports (64 Pins or 68 Pins Versions)

– Four 8-bit I/O Ports (44 Pins Version)

– Three 16-bit Timer/Counters

– 256 Bytes Scratch Pad RAM

– 9 Interrupt Sources with 4 Priority Levels

Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply

ISP (In-System Programming) Using Standard V_CCPower Supply

2048 Bytes Boot ROM Contains Low Level Flash Programming Routines and a Default

Serial Loader

•

8-bit Flash

Microcontroller

•

High-speed Architecture

– In Standard Mode:

• 40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)

• 60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

– In X2 mode (6 Clocks/machine cycle)

AT89C51RD2

AT89C51ED2

• 20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)

• 30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

64K Bytes On-chip Flash Program/Data Memory

– Byte and Page (128 Bytes) Erase and Write

– 100k Write Cycles

•

On-chip 1792 bytes Expanded RAM (XRAM)

– Software Selectable Size (0, 256, 512, 768, 1024, 1792 Bytes)

– 768 Bytes Selected at Reset for T89C51RD2 Compatibility

On-chip 2048 Bytes EEPROM Block for Data Storage (AT89C51ED2 Only)

100K Write Cycles

•

Dual Data Pointer

Variable Length MOVX for Slow RAM/Peripherals

Improved X2 Mode with Independent Selection for CPU and Each Peripheral

Keyboard Interrupt Interface on Port 1

SPI Interface (Master/Slave Mode)

8-bit Clock Prescaler

16-bit Programmable Counter Array

– High Speed Output

– Compare/Capture

– Pulse Width Modulator

– Watchdog Timer Capabilities

•

Asynchronous Port Reset

Full-duplex Enhanced UART with Dedicated Internal Baud Rate Generator

Low EMI (Inhibit ALE)

Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-off Flag

Power Control Modes: Idle Mode, Power-down Mode

Single Range Power Supply: 2.7V to 5.5V

Industrial Temperature Range (-40 to +85°C)

Packages: PLCC44, VQFP44, PLCC68, VQFP64

1. Description

AT89C51RD2/ED2 is high performance CMOS Flash version of the 80C51 CMOS single chip 8-

bit microcontroller. It contains a 64-Kbyte Flash memory block for code and for data.

The 64-Kbytes Flash memory can be programmed either in parallel mode or in serial mode with

the ISP capability or with software. The programming voltage is internally generated from the

standard V_CCpin.

The AT89C51RD2/ED2 retains all of the features of the Atmel 80C52 with 256 bytes of internal

RAM, a 9-source 4-level interrupt controller and three timer/counters. The AT89C51ED2 pro-

vides 2048 bytes of EEPROM for nonvolatile data storage.

In addition, the AT89C51RD2/ED2 has a Programmable Counter Array, an XRAM of 1792

bytes, a Hardware Watchdog Timer, SPI interface, Keyboard, a more versatile serial channel

that facilitates multiprocessor communication (EUART) and a speed improvement mechanism

(X2 Mode).

The fully static design of the AT89C51RD2/ED2 allows to reduce system power consumption by

bringing the clock frequency down to any value, including DC, without loss of data.

The AT89C51RD2/ED2 has 2 software-selectable modes of reduced activity and an 8-bit clock

prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while

the peripherals and the interrupt system are still operating. In the Power-down mode the RAM is

saved and all other functions are inoperative.

The added features of the AT89C51RD2/ED2 make it more powerful for applications that need

pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control,

corded phones, and smart card readers.

Table 1-1.

Memory Size and I/O Pins

Package

PLCC44/VQFP44

PLCC68/VQFP64

Flash (Bytes)

64K

XRAM (Bytes)

1792

Total RAM (Bytes)

I/O

34

50

2048

64K

1792

2

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

2. Block Diagram

Figure 2-1. Block Diagram

(2) (2)

(1)

(1) (1)

(1)

Flash

64K x 8

XRAM

1792 x 8

EEPROM*

Watch

-dog

RAM

256x8

PCA

XTALA1

XTALA2

EUART

Timer2

Keyboard

2K x 8

(AT89C51ED2)

C51

CORE

IB-bus

CPU

ALE/PROG

PSEN

EA

Parallel I/O Ports &

External Bus

BOOT Regulator

2K x 8

ROM

(2)

Timer 0

Timer 1

INT

Ctrl

RD

SPI

POR / PFD

(2)

Port 2

Port 0 Port 1

Port 3 Port4 Port 5

WR

(2) (2)

(1)

(1)(1)

(1): Alternate function of Port 1

(2): Alternate function of Port 3

3

4235K–8051–05/08

3. SFR Mapping

The Special Function Registers (SFRs) of the AT89C51RD2/ED2 fall into the following

categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP

• I/O port registers: P0, P1, P2, P3, PI2

• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L,

RCAP2H

• Serial I/O port registers: SADDR, SADEN, SBUF, SCON

• PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL

(x: 0 to 4)

• Power and clock control registers: PCON

• Hardware Watchdog Timer registers: WDTRST, WDTPRG

• Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1

• Keyboard Interface registers: KBE, KBF, KBLS

• SPI registers: SPCON, SPSTR, SPDAT

• BRG (Baud Rate Generator) registers: BRL, BDRCON

• Clock Prescaler register: CKRL

• Others: AUXR, AUXR1, CKCON0, CKCON1

Table 3-1.

C51 Core SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

ACC

B

E0h Accumulator

F0h B Register

PSW

SP

D0h Program Status Word

81h Stack Pointer

CY

AC

F0

RS1

RS0

OV

F1

P

DPL

DPH

82h Data Pointer Low Byte

83h Data Pointer High Byte

Table 3-2.

System Management SFRs

Mnemonic

Add Name

7

6

5

4

3

GF1

XRS1

GF3

-

2

1

0

IDL

AO

PCON

87h Power Control

SMOD1

SMOD0

-

POF

GF0

PD

AUXR

8Eh Auxiliary Register 0

A2h Auxiliary Register 1

97h Clock Reload Register

8Fh Clock Control Register 0

AFh Clock Control Register 1

DPU

-

M0

XRS2

XRS0

EXTRAM

AUXR1

CKRL

-

ENBOOT

-

0

-

DPS

-

SIX2

-

T1X2

-

T0X2

-

CKCKON0

CKCKON1

WDTX2

-

PCAX2

-

T2X2

-

X2

SPIX2

4

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Table 3-3.

Interrupt SFRs

Mnemonic

Add Name

7

6

5

4

ES

-

3

2

1

0

IEN0

IEN1

IPH0

IPL0

IPH1

IPL1

A8h Interrupt Enable Control 0

EA

EC

ET2

ET1

EX1

ET0

EX0

B1h Interrupt Enable Control 1

-

ESPI

PX1H

PX1L

SPIH

SPIL

KBD

B7h Interrupt Priority Control High 0

B8h Interrupt Priority Control Low 0

B3h Interrupt Priority Control High 1

B2h Interrupt Priority Control Low 1

PPCH

PT2H

PHS

PLS

-

PT1H

PT0H

PT0L

PX0H

PX0L

KBDH

KBDL

PPCL

PT2L

PT1L

-

Table 3-4.

Port SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

P0

P1

P2

P3

P4

P5

80h 8-bit Port 0

90h 8-bit Port 1

A0h 8-bit Port 2

B0h 8-bit Port 3

C0h 8-bit Port 4

E8h 8-bit Port 5

C7h 8-bit Port 5 (byte addressable)

Table 3-5.

Timer SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

TCON

TMOD

TL0

88h Timer/Counter 0 and 1 Control

89h Timer/Counter 0 and 1 Modes

8Ah Timer/Counter 0 Low Byte

8Ch Timer/Counter 0 High Byte

8Bh Timer/Counter 1 Low Byte

8Dh Timer/Counter 1 High Byte

A6h WatchDog Timer Reset

A7h WatchDog Timer Program

C8h Timer/Counter 2 control

C9h Timer/Counter 2 Mode

TF1

TR1

TF0

M11

TR0

M01

IE1

IT1

IE0

M10

IT0

M00

GATE1

C/T1#

GATE0

C/T0#

TH0

TL1

TH1

WDTRST

WDTPRG

T2CON

T2MOD

-

TF2

-

EXF2

-

RCLK

-

TCLK

-

WTO2

TR2

-

WTO1

C/T2#

T2OE

WTO0

CP/RL2#

DCEN

EXEN2

-

Timer/Counter 2 Reload/Capture

High Byte

RCAP2H

CBh

Timer/Counter 2 Reload/Capture

RCAP2L

TH2

CAh

Low Byte

CDh Timer/Counter 2 High Byte

5

4235K–8051–05/08

Table 3-5.

Timer SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

TL2

CCh Timer/Counter 2 Low Byte

Table 3-6.

PCA SFRs

Mnemo

-nic

Add Name

7

6

5

4

3

2

1

0

CCON

CMOD

CL

D8h PCA Timer/Counter Control

D9h PCA Timer/Counter Mode

E9h PCA Timer/Counter Low Byte

F9h PCA Timer/Counter High Byte

CF

CR

CCF4

CCF3

CCF2

CPS1

CCF1

CPS0

CCF0

ECF

CIDL

WDTE

CH

CCAPM0 DAh PCA Timer/Counter Mode 0

CCAPM1 DBh PCA Timer/Counter Mode 1

CCAPM2 DCh PCA Timer/Counter Mode 2

CCAPM3 DDh PCA Timer/Counter Mode 3

CCAPM4 DEh PCA Timer/Counter Mode 4

ECOM0

ECOM1

ECOM2

ECOM3

ECOM4

CAPP0

CAPP1

CAPP2

CAPP3

CAPP4

CAPN0

CAPN1

CAPN2

CAPN3

CAPN4

MAT0

MAT1

MAT2

MAT3

MAT4

TOG0

TOG1

TOG2

TOG3

TOG4

PWM0

PWM1

PWM2

PWM3

PWM4

ECCF0

ECCF1

ECCF2

ECCF3

ECCF4

CCAP0H FAh PCA Compare Capture Module 0 H CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0

CCAP1H FBh PCA Compare Capture Module 1 H CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H3 CCAP1H2 CCAP1H1 CCAP1H0

CCAP2H FCh PCA Compare Capture Module 2 H CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP2H3 CCAP2H2 CCAP2H1 CCAP2H0

CCAP3H FDh PCA Compare Capture Module 3 H CCAP3H7 CCAP3H6 CCAP3H5 CCAP3H4 CCAP3H3 CCAP3H2 CCAP3H1 CCAP3H0

CCAP4H FEh PCA Compare Capture Module 4 H CCAP4H7 CCAP4H6 CCAP4H5 CCAP4H4 CCAP4H3 CCAP4H2 CCAP4H1 CCAP4H0

CCAP0L EAh PCA Compare Capture Module 0 L CCAP0L7 CCAP0L6 CCAP0L5 CCAP0L4 CCAP0L3 CCAP0L2 CCAP0L1 CCAP0L0

CCAP1L EBh PCA Compare Capture Module 1 L CCAP1L7 CCAP1L6 CCAP1L5 CCAP1L4 CCAP1L3 CCAP1L2 CCAP1L1 CCAP1L0

CCAP2L ECh PCA Compare Capture Module 2 L CCAP2L7 CCAP2L6 CCAP2L5 CCAP2L4 CCAP2L3 CCAP2L2 CCAP2L1 CCAP2L0

CCAP3L EDh PCA Compare Capture Module 3 L CCAP3L7 CCAP3L6 CCAP3L5 CCAP3L4 CCAP3L3 CCAP3L2 CCAP3L1 CCAP3L0

CCAP4L EEh PCA Compare Capture Module 4 L CCAP4L7 CCAP4L6 CCAP4L5 CCAP4L4 CCAP4L3 CCAP4L2 CCAP4L1 CCAP4L0

Table 3-7.

Serial I/O Port SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

SCON

SBUF

98h Serial Control

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

99h Serial Data Buffer

B9h Slave Address Mask

A9h Slave Address

SADEN

SADDR

BDRCON

BRL

9Bh Baud Rate Control

9Ah Baud Rate Reload

BRR

TBCK

RBCK

SPD

SRC

Table 3-8.

SPI Controller SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

SPCON

SPSTA

SPDAT

C3h SPI Control

C4h SPI Status

C5h SPI Data

SPR2

SPIF

SPD7

SPEN

WCOL

SPD6

SSDIS

SSERR

SPD5

MSTR

MODF

SPD4

CPOL

CPHA

SPR1

SPR0

SPD3

SPD2

SPD1

SPD0

6

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Table 3-9.

Keyboard Interface SFRs

Mnemonic

Add Name

7

6

5

4

3

2

1

0

KBLS

KBE

KBF

9Ch Keyboard Level Selector

9Dh Keyboard Input Enable

9Eh Keyboard Flag Register

KBLS7

KBE7

KBF7

KBLS6

KBE6

KBF6

KBLS5

KBE5

KBF5

KBLS4

KBE4

KBF4

KBLS3

KBE3

KBF3

KBLS2

KBE2

KBF2

KBLS1

KBE1

KBF1

KBLS0

KBE0

KBF0

Table 3-10. EEPROM data Memory SFR (AT89C51ED2 only)

Mnemonic

Add Name

7

6

5

4

3

2

1

0

EECON

D2h EEPROM Data Control

EEE

EEBUSY

shows all SFRs with their address and their reset value.

Table 3-11. SFR Mapping

Bit

Addressable

Non Bit Addressable

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

CH

CCAP0H

CCAP1H

CCAP2H

CCAP3H

CCAP4H

F8h

F0h

FFh

F7h

0000 0000

XXXX XXXX

B

0000 0000

P5 bit

addressable

CL

CCAP0L

CCAP1L

CCAP2L

CCAP3L

CCAP4L

E8h

EFh

0000 0000

XXXX XXXX

1111 1111

ACC

E0h

D8h

D0h

C8h

E7h

DFh

D7h

CFh

0000 0000

CCON

CMOD

CCAPM0

CCAPM1

CCAPM2

CCAPM3

CCAPM4

00X0 0000

00XX X000

X000 0000

FCON

PSW

EECON

0000 0000

xxxx xx00

XXXX 0000

T2CON

0000 0000

T2MOD

XXXX XX00

RCAP2L

0000 0000

RCAP2H

0000 0000

TL2

0000 0000

TH2

0000 0000

P5 byte

P4

SPCON

SPSTA

SPDAT

Addressable

C0h

C7h

1111 1111

0001 0100

0000 0000

XXXX XXXX

1111 1111

IPL0

SADEN

B8h

B0h

A8h

BFh

B7h

AFh

X000 000

0000 0000

P3

IEN1

IPL1

IPH1

IPH0

1111 1111

XXXX X000

X000 0000

IEN0

SADDR

CKCON1

0000 0000

XXXX XXX0

7

4235K–8051–05/08

Table 3-11. SFR Mapping

P2

A0h

AUXR1

WDTRST

WDTPRG

A7h

9Fh

97h

8Fh

87h

1111 1111

0XXX X0X0

XXXX XXXX

XXXX X000

SCON

SBUF

BRL

BDRCON

KBLS

KBE

KBF

98h

90h

88h

80h

0000 0000

XXXX XXXX

0000 0000

XXX0 0000

0000 0000

P1

CKRL

1111 1111

TCON

TMOD

TL0

TL1

TH0

TH1

CKCON0

AUXR

0X00 1000

0000 0000

P0

PCON

SP

0000 0111

DPL

0000 0000

DPH

0000 0000

1111 1111

00X1 0000

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

reserved

8

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

4. Pin Configurations

Figure 4-1. Pin Configurations

6

5 4 3 2 1

44 43 42 41 40

P1.5/CEX2/MISO

39

38

7

8

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA

P1.6/CEX3/SCK

P1.7/CEx4/MOSI

RST

37

9

10

11

12

13

36

35

34

33

P3.0/RxD

AT89C51RD2/ED2

PLCC44

NIC*

P3.1/TxD

ALE/PROG

PSEN

P3.2/INT0

P3.3/INT1

P3.4/T0

14

15

16

17

32

31

30

29

P2.7/A15

P2.6/A14

P2.5/A13

P3.5/T1

18 19 20 21 22 23 24 25 26 27 28

44 43 42 41 40 39 38 37 36 35 34

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA

P1.5/CEX2/MISO

P1.6/CEX3/SCK

P1.7/CEX4/MOSI

RST

33

32

1

2

31

3

4

30

29

28

27

P3.0/RxD

5

NIC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

6

7

8

AT89C51RD2/ED2

VQFP44 1.4

ALE/PROG

PSEN

26

25

24

P2.7/A15

P2.6/A14

P2.5/A13

9

10

11

23

P3.5/T1

1213141516171819202122

9

4235K–8051–05/08

60 P5.0

P5.5 10

P0.3/AD3 11

P0.2/AD2 12

P5.6 13

59 P2.4/A12

58 P2.3/A11

57 P4.7

56 P2.2/A10

55 P2.1/A9

54 P2.0/A8

53 P4.6

52 NIC

51 VSS

50 P4.5

P0.1/AD1 14

P0.0/AD0 15

P5.7 16

VCC 17

NIC 18

P1.0/T2 19

P4.0 20

AT89C51ED2

PLCC68

49 XTAL1

48 XTAL2

47 P3.7/RD

46 P4.4

P1.1/T2EX/SS 21

P1.2/ECI 22

P1.3/CEX0 23

P4.1 24

45 P3.6/WR

44 P4.3

P1.4/CEX1 25

P4.2 26

P5.5

P0.3/AD3

P0.2/AD2

P5.6

P0.1/AD1

P0.0/AD0

P5.7

VCC

NIC

P1.0/T2 10

P4.0 11

1

2

3

4

5

6

7

8

9

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P2.4/A12

P2.3/A11

P4.7

P2.2/A10

P2.1/A9

P2.0/A8

P4.6

NIC

VSS

P4.5

XTAL1

XTAL2

P3.7/RD

P4.4

AT89C51ED2

VQFP64

P1.1/T2EX/SS 12

P1.2/ECI 13

P1.3/CEX0 14

P4.1 15

P1.4/CEX1 16

P3.6/WR

P4.3

NIC: Not Internaly Connected

10

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Table 4-1.

Pin Description

Pin Number

Mnemonic PLCC44 VQFP44 PLCC68 VQFP64

Type

Name and Function

V_SS

V_CC

22

44

16

38

51

17

40

8

I

Ground: 0V reference

Power Supply: This is the power supply voltage for normal, idle and

power-down operation

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that

have 1s written to them float and can be used as high impedance inputs.

Port 0 must be polarized to V_CCor V_SSin order to prevent any parasitic

current consumption. Port 0 is also the multiplexed low-order address

15, 14,

12, 11,

6, 5, 3, 2,

64,

P0.0 - P0.7 43 - 36

37 - 30

I/O and data bus during access to external program and data memory. In this

application, it uses strong internal pull-up when emitting 1s. Port 0 also

inputs the code bytes during EPROM programming. External pull-ups are

required during program verification during which P0 outputs the code

bytes.

9,6, 5, 3 61,60,59

19, 21,

22, 23,

25, 27,

28, 29

10, 12,

13, 14,

16, 18,

19, 20

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1

I/O pins that have 1s written to them are pulled high by the internal pull-ups

and can be used as inputs. As inputs, Port 1 pins that are externally

pulled low will source current because of the internal pull-ups. Port 1 also

receives the low-order address byte during memory programming and

verification.

P1.0 - P1.7

2 - 9

40 - 44

1 - 3

Alternate functions for AT89C51RD2/ED2 Port 1 include:

2

3

40

41

19

21

10

12

I/O

P1.0: Input/Output

I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout

I/O

P1.1: Input/Output

I

T2EX: Timer/Counter 2 Reload/Capture/Direction Control

SS: SPI Slave Select

4

5

6

7

42

43

44

1

22

23

25

27

13

14

16

18

I/O

I

P1.2: Input/Output

ECI: External Clock for the PCA

P1.3: Input/Output

I/O

I/O CEX0: Capture/Compare External I/O for PCA module 0

I/O P1.4: Input/Output

I/O CEX1: Capture/Compare External I/O for PCA module 1

I/O P1.5: Input/Output

I/O CEX2: Capture/Compare External I/O for PCA module 2

I/O MISO: SPI Master Input Slave Output line

When SPI is in master mode, MISO receives data from the slave

peripheral. When SPI is in slave mode, MISO outputs data to the master

controller.

8

2

28

19

I/O

P1.6: Input/Output

I/O CEX3: Capture/Compare External I/O for PCA module 3

I/O SCK: SPI Serial Clock

11

4235K–8051–05/08

Table 4-1.

Pin Description (Continued)

Pin Number

Type

I/O

Mnemonic PLCC44 VQFP44 PLCC68 VQFP64

Name and Function

9

3

29

20

P1.7: Input/Output:

I/O CEX4: Capture/Compare External I/O for PCA module 4

I/O MOSI: SPI Master Output Slave Input line

When SPI is in master mode, MOSI outputs data to the slave peripheral.

When SPI is in slave mode, MOSI receives data from the master

controller.

XTALA 1: Input to the inverting oscillator amplifier and input to the

internal clock generator circuits.

XTALA1

XTALA2

21

20

15

14

49

48

38

37

I

O

XTALA 2: Output from the inverting oscillator amplifier

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2

pins that have 1s written to them are pulled high by the internal pull-ups

and can be used as inputs. As inputs, Port 2 pins that are externally

pulled low will source current because of the internal pull-ups. Port 2

54, 55,

56, 58,

59, 61,

64, 65

43, 44,

45, 47,

48, 50,

53, 54

P2.0 - P2.7 24 - 31

18 - 25

I/O emits the high-order address byte during fetches from external program

memory and during accesses to external data memory that use 16-bit

addresses (MOVX @DPTR).In this application, it uses strong internal

pull-ups emitting 1s. During accesses to external data memory that use

8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.

34, 39,

40, 41,

42, 43,

45, 47

25, 28,

29, 30,

31, 32,

34, 36

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3

P3.0 - P3.7

11,

5,

I/O

pins that have 1s written to them are pulled high by the internal pull-ups

13 - 19

7 - 13

and can be used as inputs. As inputs, Port 3 pins that are externally

pulled low will source current because of the internal pull-ups. Port 3 also

serves the special features of the 80C51 family, as listed below.

11

13

14

15

16

17

18

19

5

7

34

39

40

41

42

43

45

47

25

28

29

30

31

32

34

36

I

O

I

RXD (P3.0): Serial input port

TXD (P3.1): Serial output port

8

INT0 (P3.2): External interrupt 0

INT1 (P3.3): External interrupt 1

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

9

I

10

11

12

13

I

O

20, 24,

26, 44,

46, 50,

53, 57

11, 15,

17,33,

35,39,

42, 46

Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3

pins that have 1s written to them are pulled high by the internal pull-ups

and can be used as inputs. As inputs, Port 3 pins that are externally

pulled low will source current because of the internal pull-ups.

P4.0 - P4.7

P5.0 - P5.7

-

I/O

I

Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3

pins that have 1s written to them are pulled high by the internal pull-ups

and can be used as inputs. As inputs, Port 3 pins that are externally

pulled low will source current because of the internal pull-ups.

60, 62,

63, 7, 8,

49, 51,

52, 62,

10, 13, 16 63, 1, 4, 7

Reset: A high on this pin for two machine cycles while the oscillator is

running, resets the device. An internal diffused resistor to V_SSpermits a

power-on reset using only an external capacitor to V_CC. This pin is an

output when the hardware watchdog forces a system reset.

RST

10

4

30

21

12

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Table 4-1.

Pin Description (Continued)

Pin Number

Mnemonic PLCC44 VQFP44 PLCC68 VQFP64

ALE/PRO

Type

O (I)

Name and Function

Address Latch Enable/Program Pulse: Output pulse for latching the

low byte of the address during an access to external memory. In normal

operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the

oscillator frequency, and can be used for external timing or clocking. Note

that one ALE pulse is skipped during each access to external data

memory. This pin is also the program pulse input (PROG) during Flash

programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With

this bit set, ALE will be inactive during internal fetches.

33

27

68

56

G

PSEN

32

35

26

29

67

55

58

O

Program Strobe ENable: The read strobe to external program memory.

When executing code from the external program memory, PSEN is

activated twice each machine cycle, except that two PSEN activations

are skipped during each access to external data memory. PSEN is not

activated during fetches from internal program memory.

EA

2

I

External Access Enable: EA must be externally held low to enable the

device to fetch code from external program memory locations 0000H to

FFFFH. If security level 1 is programmed, EA will be internally latched on

Reset.

13

4235K–8051–05/08

5. Port Types

AT89C51RD2/ED2 I/O ports (P1, P2, P3, P4, P5) implement the quasi-bidirectional output that

is common on the 80C51 and most of its derivatives. This output type can be used as both an

input and output without the need to reconfigure the port. This is possible because when the port

outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the

pin is pulled low, it is driven strongly and able to sink a fairly large current. These features are

somewhat similar to an open drain output except that there are three pull-up transistors in the

quasi-bidirectional output that serve different purposes. One of these pull-ups, called the "weak"

pull-up, is turned on whenever the port latch for the pin contains a logic 1. The weak pull-up

sources a very small current that will pull the pin high if it is left floating. A second pull-up, called

the "medium" pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin

itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidi-

rectional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an external

device, the medium pull-up turns off, and only the weak pull-up remains on. In order to pull the

pin low under these conditions, the external device has to sink enough current to overpower the

medium pull-up and take the voltage on the port pin below its input threshold.

The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up low-to-

high transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a

logic 1. When this occurs, the strong pull-up turns on for a brief time, two CPU clocks, in order to

pull the port pin high quickly. Then it turns off again.

The DPU bit (bit 7 in AUXR register) allows to disable the permanent weak pull up of all ports

when latch data is logical 0.

The quasi-bidirectional port configuration is shown in Figure 5-1.

Figure 5-1. Quasi-Bidirectional Output

P

2 CPU

Clock Delay

Strong

Weak

Medium

Port Latch

Data

N

DPU

AUXR.7

Input

Data

14

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

6. Oscillator

To optimize the power consumption and execution time needed for a specific task, an internal

prescaler feature has been implemented between the oscillator and the CPU and peripherals.

6.1

Registers

Table 6-1.

CKRL Register

CKRL – Clock Reload Register (97h)

7

6

5

4

3

2

1

0

CKRL7

CKRL6

CKRL5

CKRL4

CKRL3

CKRL2

CKRL1

CKRL0

Bit Number

Mnemonic

Description

Clock Reload Register

Prescaler value

7:0

CKRL

Reset Value = 1111 1111b

Not bit addressable

Table 6-2.

PCON Register

PCON – Power Control Register (87h)

7

6

5

4

3

2

1

0

SMOD1

SMOD0

-

POF

GF1

GF0

PD

IDL

Bit Number

Bit Mnemonic

Description

Serial Port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

7

SMOD1

Serial Port Mode bit 0

6

5

SMOD0

-

Cleared to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-off Flag

Cleared by software to recognize the next reset type.

Set by hardware when V_CCrises from 0 to its nominal voltage. Can also be

set by software.

4

POF

General-purpose Flag

3

2

1

0

GF1

GF0

PD

Cleared by software for general-purpose usage.

Set by software for general-purpose usage.

General-purpose Flag

Cleared by software for general-purpose usage.

Set by software for general-purpose usage.

Power-down Mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle Mode bit

Cleared by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset Value = 00X1 0000b Not bit addressable

15

4235K–8051–05/08

6.2

Functional Block Diagram

Figure 6-1. Functional Oscillator Block Diagram

Reload

Reset

CKRL

F_OSC

Xtal1

Xtal2

Osc

1

0

8-bit

Prescaler-Divider

:2

1

0

CLK

Periph

X2

Peripheral Clock

CPU Clock

CKCON0

CLK

CPU

Idle

CKRL = 0xFF?

6.2.1

Prescaler Divider

• A hardware RESET puts the prescaler divider in the following state:

CKRL = FFh: F_{CLK CPU}= F_{CLK PERIPH}= F_OSC/2 (Standard C51 feature)

•

• Any value between FFh down to 00h can be written by software into CKRL register in order to

divide frequency of the selected oscillator:

•

CKRL = 00h: minimum frequency

_{CLK CPU}= F_{CLK PERIPH}= F_OSC/1020 (Standard Mode)

F_{CLK CPU}= F_{CLK PERIPH}= F_OSC/510 (X2 Mode)

F

•

CKRL = FFh: maximum frequency

F_{CLK CPU}= F_{CLK PERIPH}= F_OSC/2 (Standard Mode)

F_{CLK CPU}= F_{CLK PERIPH}= F_OSC(X2 Mode)

F_{CLK CPU}and F_{CLK PERIPH}

In X2 Mode, for CKRL<>0xFF:

F_OSC

F_CLKPERIPH= ----------------------------------------------

2 × (255 – CKRL)

F_CPU

=

In X1 Mode, for CKRL<>0xFF then:

F_OSC

F_CPU

= F_CLKPERIPH= ----------------------------------------------

4 × (255 – CKRL)

16

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

7. Enhanced Features

In comparison to the original 80C52, the AT89C51RD2/ED2 implements some new features,

which are

:

• X2 option

• Dual Data Pointer

• Extended RAM

• Programmable Counter Array (PCA)

• Hardware Watchdog

• SPI interface

• 4-level interrupt priority system

• Power-off flag

• ONCE mode

• ALE disabling

• Some enhanced features are also located in the UART and the Timer 2

7.1

X2 Feature

The AT89C51RD2/ED2 core needs only 6 clock periods per machine cycle. This feature called

‘X2’ provides the following advantages:

• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

• Save power consumption while keeping same CPU power (oscillator power saving).

• Save power consumption by dividing dynamically the operating frequency by 2 in operating

and idle modes.

• Increase CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig-

nal and the main clock input of the core (phase generator). This divider may be disabled by

software.

7.1.1

Description

The clock for the whole circuit and peripherals is first divided by two before being used by the

CPU core and the peripherals.

This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is

bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.

Figure 7-1 shows the clock generation block diagram. X2 bit is validated on the rising edge of

the XTAL1 ÷ 2 to avoid glitches when switching from X2 to STD mode. Figure 7-2 shows the

switching mode waveforms.

17

4235K–8051–05/08

Figure 7-1. Clock Generation Diagram

CKRL

F_OSC

XTAL1:2

2

XTAL1

F_{CLK CPU}

F_{CLK PERIPH}

0

1

8-bit Prescaler

FXTAL

X2

CKCON0

Figure 7-2. Mode Switching Waveforms

XTAL1

XTAL1:2

X2 Bit

F_OSC

CPU Clock

STD Mode

X2 Mode

STD Mode

The X2 bit in the CKCON0 register (see Table 7-1) allows a switch from 12 clock periods per

instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of

Hardware Security Byte (HSB). By default, Standard mode is active. Setting the X2 bit activates

the X2 feature (X2 mode).

The T0X2, T1X2, T2X2, UartX2, PcaX2, and WdX2 bits in the CKCON0 register (Table 7-1) and

SPIX2 bit in the CKCON1 register (see Table 7-2) allows a switch from standard peripheral

speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods per

peripheral clock cycle). These bits are active only in X2 mode.

Table 7-1.

CKCON0 Register

CKCON0 - Clock Control Register (8Fh)

7

-

6

5

4

3

2

1

0

WDX2

PCAX2

SIX2

T2X2

T1X2

T0X2

X2

Bit

Number

Mnemonic Description

7

6

Reserved

WDX2

The values for this bit are indeterminite. Do not set this bit.

Watchdog Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no

effect).

Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

18

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Bit

Number

Mnemonic Description

Programmable Counter Array Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no

effect).

5

4

3

2

1

0

PCAX2

SIX2

T2X2

T1X2

T0X2

X2

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

Enhanced UART Clock (Mode 0 and 2)

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no

effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

Timer2 Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no

effect).

Cleared to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer1 Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no

effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

Timer0 Clock

(This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no

effect).

Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock

periods per peripheral clock cycle.

CPU Clock

Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and all the

peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the

individual peripherals’X2’ bits. Programmed by hardware after Power-up regarding

Hardware Security Byte (HSB), Default setting, X2 is cleared.

Reset Value = 0000 000’HSB. X2’b (See “Hardware Security Byte”)

Not bit addressable

Table 7-2.

CKCON1 Register

CKCON1 - Clock Control Register (AFh)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

SPIX2

Bit

Number

Mnemonic Description

7

6

5

4

3

-

Reserved

19

4235K–8051–05/08

Bit

Number

Mnemonic Description

2

1

-

Reserved

SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit

has no effect).

Clear to select 6 clock periods per peripheral clock cycle.

0

SPIX2

Set to select 12 clock periods per peripheral clock cycle.

Reset Value = XXXX XXX0b

Not bit addressable

20

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

8. Dual Data Pointer Register (DPTR)

The additional data pointer can be used to speed up code execution and reduce code size.

The dual DPTR structure is a way by which the chip will specify the address of an external data

memory location. There are two 16-bit DPTR registers that address the external memory, and a

single bit called DPS = AUXR1.0 (see Table 8-1) that allows the program code to switch

between them (Refer to Figure 8-1).

Figure 8-1. Use of Dual Pointer

External Data Memory

7

0

DPS

DPTR1

DPTR0

AUXR1(A2H)

DPH(83H) DPL(82H)

Table 8-1.

AUXR1 Register

AUXR1- Auxiliary Register 1(0A2h)

7

6

5

4

3

2

1

0

-

ENBOOT

-

GF3

0

-

DPS

Bit

Number

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

7

6

-

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Enable Boot Flash

Cleared to disable boot ROM.

5

4

ENBOOT

Set to map the boot ROM between F800h - 0FFFFh.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

-

3

2

GF3

0

This bit is a general-purpose user flag.⁽¹⁾

Always cleared

Reserved

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Data Pointer Selection

Cleared to select DPTR0.

Set to select DPTR1.

DPS

21

4235K–8051–05/08

Reset Value = XXXX XX0X0b

Not bit addressable

Note:

1. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.

ASSEMBLY LANGUAGE

; Block move using dual data pointers

; Modifies DPTR0, DPTR1, A and PSW

; note: DPS exits opposite of entry state

; unless an extra INC AUXR1 is added

;

00A2 AUXR1 EQU 0A2H

;

0000 909000MOV DPTR,#SOURCE ; address of SOURCE

0003 05A2 INC AUXR1 ; switch data pointers

0005 90A000 MOV DPTR,#DEST ; address of DEST

0008 LOOP:

0008 05A2 INC AUXR1 ; switch data pointers

000A E0 MOVX A,@DPTR ; get a byte from SOURCE

000B A3 INC DPTR ; increment SOURCE address

000C 05A2 INC AUXR1 ; switch data pointers

000E F0 MOVX @DPTR,A ; write the byte to DEST

000F A3 INC DPTR ; increment DEST address

0010 70F6JNZ LOOP ; check for 0 terminator

0012 05A2 INC AUXR1 ; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR.

However, note that the INC instruction does not directly force the DPS bit to a particular state,

but simply toggles it. In simple routines, such as the block move example, only the fact that DPS

is toggled in the proper sequence matters, not its actual value. In other words, the block move

routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc-

tion (INC AUXR1), the routine will exit with DPS in the opposite state.

22

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

9. Expanded RAM (XRAM)

The AT89C51RD2/ED2 provides additional on-chip random access memory (RAM) space for

increased data parameter handling and high level language usage.

AT89C51RD2/ED2 device haS expanded RAM in external data space configurable up to 1792

bytes (see Table 9-1).

The AT89C51RD2/ED2 internal data memory is mapped into four separate segments.

The four segments are:

1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly

addressable.

2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly address-

able only.

4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the

EXTRAM bit cleared in the AUXR register (see Table 9-1).

The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128

bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same

address space as the SFR. That means they have the same address, but are physically sepa-

rate from SFR space.

Figure 9-1. Internal and External Data Memory Address

0FFh or 6FFh

0FFh

0FFFFh

Upper

128 Bytes

Internal

Special

Function

Register

External

Data

Memory

RAM

Indirect Accesses

Direct Accesses

80h

7Fh

80h

XRAM

Lower

128 Bytes

Internal

RAM

Direct or Indirect

Accesses

00FFh up to 06FFh

0000

00

When an instruction accesses an internal location above address 7Fh, the CPU knows whether

the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used

in the instruction.

• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data,

accesses the SFR at location 0A0h (which is P2).

• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For

example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address

0A0h, rather than P2 (whose address is 0A0h).

• The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and

MOVX instructions. This part of memory which is physically located on-chip, logically

occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a

23

4235K–8051–05/08

part of the available XRAM as explained in Table 9-1. This can be useful if external

peripherals are mapped at addresses already used by the internal XRAM.

• With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in

combination with any of the registers R0, R1 of the selected bank or DPTR. An access to

XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM =

0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H

rather than external memory. An access to external data memory locations higher than the

accessible size of the XRAM will be performed with the MOVX DPTR instructions in the same

way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7

as write and read timing signals. Accesses to XRAM above 0FFH can only be done by the

use of DPTR.

• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard

80C51.MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any

output port pins can be used to output higher order address bits. This is to provide the

external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs

the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order

eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read

or write signals on P3.6 (WR) and P3.7 (RD).

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM)

internal data memory. The stack may not be located in the XRAM.

The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are

extended from 6 to 30 clock periods. This is useful to access external slow peripherals.

9.1

Registers

Table 9-1.

AUXR Register

AUXR - Auxiliary Register (8Eh)

7

6

-

5

4

3

2

1

0

DPU

M0

XRS2

XRS1

XRS0

EXTRAM

AO

Bit

Number

Mnemonic Description

Disable Weak Pull-up

7

6

DPU

-

Cleared by software to activate the permanent weak pull-up (default)

Set by software to disable the weak pull-up (reduce power consumption)

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Pulse length

Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods

(default).

5

M0

Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.

4

3

XRS2

XRS1

XRAM Size

XRS2XRS1XRS0XRAM size

0

1

0

1

0

0256bytes

1

512 bytes

0768 bytes(default)

11024 bytes

01792 bytes

2

XRS0

24

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Bit

Number

Mnemonic Description

EXTRAM bit

Cleared to access internal XRAM using movx @ Ri/ @ DPTR.

Set to access external memory.

1

EXTRAM

Programmed by hardware after Power-up regarding Hardware Security Byte (HSB),

default setting, XRAM selected.

ALE Output bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2

mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is

used.

0

AO

Reset Value = 0X00 1000

Not bit addressable

25

4235K–8051–05/08

10. Reset

10.1 Introduction

The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and Reset

input.

Figure 10-1. Reset schematic

Power

Monitor

Hardware

Watchdog

Internal Reset

PCA

Watchdog

RST

10.2 Reset Input

The Reset input can be used to force a reset pulse longer than the internal reset controlled by

the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply con-

necting an external capacitor to V_CCas shown in Figure 10-2. Resistor value and input

characteristics are discussed in the Section “DC Characteristics” of the AT89C51RD2/ED2

datasheet.

Figure 10-2. Reset Circuitry and Power-On Reset

VDD

To internal reset

RST

+

RST

VSS

a. RST input circuitry

b. Power-on Reset

10.3 Reset Output

Reset output can be generated by two sources:

• Internal POR/PFD

• Hardware watchdog timer

As detailed in Section “Hardware Watchdog Timer”, page 84, the WDT generates a 96-clock

period pulse on the RST pin.

In order to properly propagate this pulse to the rest of the application in case of external capaci-

tor or power-supply supervisor circuit, a 1 kΩ resistor must be added as shown Figure 10-3.

26

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Figure 10-3. Recommended Reset Output Schematic

VDD

+

RST

VDD

1K

AT89C51XD2

RST

To other

on-board

circuitry

VSS

27

4235K–8051–05/08

11. Power Monitor

The POR/PFD function monitors the internal power-supply of the CPU core memories and the

peripherals, and if needed, suspends their activity when the internal power supply falls below a

safety threshold. This is achieved by applying an internal reset to them.

By generating the Reset the Power Monitor insures a correct start up when AT89C51RD2/ED2

is powered up.

11.1 Description

In order to startup and maintain the microcontroller in correct operating mode, V_CChas to be sta-

bilized in the V_CCoperating range and the oscillator has to be stabilized with a nominal amplitude

compatible with logic level VIH/VIL.

These parameters are controlled during the three phases: power-up, normal operation and

power going down. See Figure 11-1.

Figure 11-1. Power Monitor Block Diagram

VCC

CPU core

Regulated

Supply

Power On Reset

Power Fail Detect

Voltage Regulator

Memories

Peripherals

XTAL1

(1)

Internal Reset

RST pin

PCA

Watchdog

Hardware

Watchdog

Note:

1. Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock period delay

will extend the reset coming from the Power Fail Detect. If the power falls below the Power Fail

Detect threshold level, the Reset will be applied immediately.

The Voltage regulator generates a regulated internal supply for the CPU core the memories and

the peripherals. Spikes on the external Vcc are smoothed by the voltage regulator.

The Power fail detect monitor the supply generated by the voltage regulator and generate a

reset if this supply falls below a safety threshold as illustrated in the Figure 11-2 below.

28

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Figure 11-2. Power Fail Detect

Vcc

VPFDP

VPFDM

t

Reset

Vcc

When the power is applied, the Power Monitor immediately asserts a reset. Once the internal

supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL

clock input. The internal reset will remain asserted until the Xtal1 levels are above and below

VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is

de-asserted.

If the internal power supply falls below a safety level, a reset is immediately asserted.

.

29

4235K–8051–05/08

12. Timer 2

The Timer 2 in the AT89C51RD2/ED2 is the standard C52 Timer 2. It is a 16-bit timer/counter:

the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded. It is con-

trolled by T2CON (Table 12-1) and T2MOD (Table 12-2) registers. Timer 2 operation is similar to

Timer 0 and Timer 1. C/T2 selects F_OSC/12 (timer operation) or external pin T2 (counter opera-

tion) as the timer clock input. Setting TR2 allows TL2 to increment by the selected input.

Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes

are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON).

Refer to the Atmel 8-bit Microcontroller Hardware Manual for the description of Capture and

Baud Rate Generator Modes.

Timer 2 includes the following enhancements:

• Auto-reload mode with up or down counter

• Programmable clock-output

12.1 Auto-reload Mode

The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with automatic

reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to the Atmel C51

Microcontroller Hardware Manual). If DCEN bit is set, Timer 2 acts as an Up/down timer/counter

as shown in Figure 12-1. In this mode the T2EX pin controls the direction of count.

When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag

and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and

RCAP2L registers to be loaded into the timer registers TH2 and TL2.

When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the timer

registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The under-

flow sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of the

count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.

30

AT89C51RD2/ED2

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AT89C51RD2/ED2

Figure 12-1. Auto-reload Mode Up/Down Counter (DCEN = 1)

F_{CLK PERIPH}

0

:6

1

T2

TR2

C/T2

T2CON

T2EX:

(DOWN COUNTING RELOAD VALUE)

If DCEN = 1, 1 = UP

If DCEN = 1, 0 = DOWN

If DCEN = 0, up counting

FFh

(8-bit)

FFh

(8-bit)

T2CON

EXF2

TOGGLE

TIMER 2

INTERRUPT

TL2

(8-bit)

TH2

(8-bit)

TF2

T2CON

RCAP2L

(8-bit)

RCAP2H

(8-bit)

(UP COUNTING RELOAD VALUE)

12.2 Programmable

Clock-output

In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock generator

(See Figure 12-2). The input clock increments TL2 at frequency F_{CLK PERIPH}/2. The timer repeat-

edly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L

registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do not generate inter-

rupts. The formula gives the clock-out frequency as a function of the system oscillator frequency

and the value in the RCAP2H and RCAP2L registers:

F_CLKPERIPH

Clock–OutFrequency = --------------------------------------------------------------------------------------------

4 × (65536 – RCAP2H ⁄ RCAP2L)

For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz

(F_{CLK PERIPH}/2¹⁶

) to 4 MHz (F_{CLK PERIPH}/4). The generated clock signal is brought out to T2 pin

(P1.0).

Timer 2 is programmed for the clock-out mode as follows:

• Set T2OE bit in T2MOD register.

• Clear C/T2 bit in T2CON register.

• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L

registers.

• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value

or a different one depending on the application.

• To start the timer, set TR2 run control bit in T2CON register.

31

4235K–8051–05/08

It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For

this configuration, the baud rates and clock frequencies are not independent since both func-

tions use the values in the RCAP2H and RCAP2L registers.

Figure 12-2. Clock-out Mode C/T2 = 0

:6

FCLK PERIPH

TR2

T2CON

TL2

(8-bit)

TH2

(8-bit)

OVER-

FLOW

RCAP2H

RCAP2L

(8-bit) (8-bit)

Toggle

T2

Q

D

T2OE

T2MOD

TIMER 2

INTERRUPT

T2EX

EXF2

T2CON

EXEN2

T2CON

12.3 Registers

Table 12-1. T2CON Register

T2CON - Timer 2 Control Register (C8h)

7

6

5

4

3

2

1

0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

32

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Bit

Number

Mnemonic Description

Timer 2 overflow Flag

Must be cleared by software.

Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.

7

6

TF2

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2

= 1.

When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt

is enabled.

EXF2

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode

(DCEN = 1).

Receive Clock bit

Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.

5

4

RCLK

TCLK

Transmit Clock bit

Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Cleared to ignore events on T2EX pin for Timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is detected, if

Timer 2 is not used to clock the serial port.

3

2

1

EXEN2

TR2

Timer 2 Run control bit

Cleared to turn off Timer 2.

Set to turn on Timer 2.

Timer/Counter 2 select bit

Cleared for timer operation (input from internal clock system: F_{CLK PERIPH}).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for

clock out mode.

C/T2#

Timer 2 Capture/Reload bit

If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload on Timer

2 overflow.

Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if

EXEN2=1.

0

CP/RL2#

Set to capture on negative transitions on T2EX pin if EXEN2 = 1.

Reset Value = 0000 0000b

Bit addressable

33

4235K–8051–05/08

Table 12-2. T2MOD Register

T2MOD - Timer 2 Mode Control Register (C9h)

7

-

6

-

5

-

4

-

3

-

2

-

1

0

T2OE

DCEN

Bit

Number

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

7

6

5

4

3

2

-

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 Output Enable bit

Cleared to program P1.0/T2 as clock input or I/O port.

Set to program P1.0/T2 as clock output.

1

0

T2OE

DCEN

Down Counter Enable bit

Cleared to disable Timer 2 as up/down counter.

Set to enable Timer 2 as up/down counter.

Reset Value = XXXX XX00b

Not bit addressable

34

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

13. Programmable Counter Array (PCA)

The PCA provides more timing capabilities with less CPU intervention than the standard

timer/counters. Its advantages include reduced software overhead and improved accuracy. The

PCA consists of a dedicated timer/counter which serves as the time base for an array of five

compare/capture modules. Its clock input can be programmed to count any one of the following

signals:

• Peripheral clock frequency (F_{CLK PERIPH}

• Timer 0 overflow

)

÷

6

2

• External input on ECI (P1.2)

Each compare/capture module can be programmed in any one of the following modes:

• Rising and/or falling edge capture

• Software timer

• High-speed output

• Pulse width modulator

Module 4 can also be programmed as a watchdog timer (see Section "PCA Watchdog Timer",

page 46).

When the compare/capture modules are programmed in the capture mode, software timer, or

high speed output mode, an interrupt can be generated when the module executes its function.

All five modules plus the PCA timer overflow share one interrupt vector.

The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins

are listed below. If one or several bits in the port are not used for the PCA, they can still be used

for standard I/O.

PCA Component

16-bit Counter

External I/O Pin

P1.2/ECI

16-bit Module 0

16-bit Module 1

16-bit Module 2

16-bit Module 3

P1.3/CEX0

P1.4/CEX1

P1.5/CEX2

P1.6/CEX3

The PCA timer is a common time base for all five modules (see Figure 13-1). The timer count

source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 13-1) and can

be programmed to run at:

• 1/6 the peripheral clock frequency (F_{CLK PERIPH}

• 1/2 the peripheral clock frequency (F_{CLK PERIPH}

• The Timer 0 overflow

)

• The input on the ECI pin (P1.2)

The CMOD register includes three additional bits associated with the PCA (See Figure 13-1 and

Table 13-1).

• The CIDL bit which allows the PCA to stop during idle mode.

• The WDTE bit which enables or disables the watchdog function on module 4.

35

4235K–8051–05/08

• The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON

SFR) to be set when the PCA timer overflows.

Figure 13-1. PCA Timer/Counter

To PCA

Modules

F_{CLK PERIPH}/6

F_{CLK PERIPH}/2

T0 OVF

Overflow

IT

CH

CL

16 Bit Up Counter

P1.2

CMOD

0xD9

CIDL WDTE

CPS1 CPS0 ECF

Idle

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

36

AT89C51RD2/ED2

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AT89C51RD2/ED2

Table 13-1. CMOD Register

CMOD - PCA Counter Mode Register (D9h)

7

6

5

-

4

-

3

-

2

1

0

CIDL

WDTE

CPS1

CPS0

ECF

Bit

Number

Mnemonic Description

Counter Idle Control

7

6

CIDL

Cleared to program the PCA Counter to continue functioning during idle Mode.

Set to program PCA to be gated off during idle.

Watchdog Timer Enable

WDTE

Cleared to disable Watchdog Timer function on PCA Module 4.

Set to enable Watchdog Timer function on PCA Module 4.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

5

4

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3

2

-

CPS1

PCA Count Pulse Select

CPS1CPS0

Selected PCA input

Internal clock F_{CLK PERIPH}/6

0

1

0

1

0

1

Internal clock F_{CLK PERIPH}/2

1

0

CPS0

ECF

Timer 0 Overflow

External clock at ECI/P1.2 pin (max rate = F_{CLK PERIPH}/4)

PCA Enable Counter Overflow Interrupt

Cleared to disable CF bit in CCON to inhibit an interrupt.

Set to enable CF bit in CCON to generate an interrupt.

Reset Value = 00XX X000b

Not bit addressable

The CCON register contains the run control bit for the PCA and the flags for the PCA timer (CF)

and each module (Refer to Table 13-2).

• Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this

bit.

• Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be

generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by

software.

• Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and

are set by hardware when either a match or a capture occurs. These flags also can only be

cleared by software.

37

4235K–8051–05/08

Table 13-2. CCON Register

CCON - PCA Counter Control Register (D8h)

7

6

5

-

4

3

2

1

0

CF

CR

CCF4

CCF3

CCF2

CCF1

CCF0

Bit

Number

Mnemonic Description

PCA Counter Overflow flag

Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is

set. CF

7

CF

may be set by either hardware or software but can only be cleared by software.

PCA Counter Run control bit

6

5

4

CR

-

Must be cleared by software to turn the PCA counter off.

Set by software to turn the PCA counter on.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

PCA Module 4 interrupt flag

CCF4

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 3 interrupt flag

3

2

1

0

CCF3

CCF2

CCF1

CCF0

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 2 interrupt flag

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 1 interrupt flag

Must be cleared by software.

Set by hardware when a match or capture occurs.

PCA Module 0 interrupt flag

Must be cleared by software.

Set by hardware when a match or capture occurs.

Reset Value = 00X0 0000b

Bit addressable

The watchdog timer function is implemented in Module 4 (See Figure 13-4).

The PCA interrupt system is shown in Figure 13-2.

38

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Figure 13-2. PCA Interrupt System

CCON

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

0xD8

PCA Timer/Counter

Module 0

Module 1

Module 2

Module 3

Module 4

To Interrupt

Priority Decoder

IEN0.6

EC

IEN0.7

EA

CMOD.0

CCAPMn.0

ECCFn

ECF

PCA Modules: each one of the five compare/capture modules has six possible functions. It can

perform:

• 16-bit Capture, positive-edge triggered

• 16-bit Capture, negative-edge triggered

• 16-bit Capture, both positive and negative-edge triggered

• 16-bit Software Timer

• 16-bit High Speed Output

• 8-bit Pulse Width Modulator

In addition, Module 4 can be used as a Watchdog Timer.

Each module in the PCA has a special function register associated with it. These registers are:

CCAPM0 for Module 0, CCAPM1 for Module 1, etc. (See Table 13-3). The registers contain the

bits that control the mode that each module will operate in.

• The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the

CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the

associated module.

• PWM (CCAPMn.1) enables the pulse width modulation mode.

• The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to

toggle when there is a match between the PCA counter and the modules capture/compare

register.

• The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be

set when there is a match between the PCA counter and the modules capture/compare

register.

• The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a

capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit

enables the positive edge. If both bits are set both edges will be enabled and a capture will

occur for either transition.

• The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.

39

4235K–8051–05/08

Table 13-3 shows the CCAPMn settings for the various PCA functions.

Table 13-3. CCAPMn Registers (n = 0-4)

CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh)

CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh)

CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh)

CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh)

CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)

7

-

6

5

4

3

2

1

0

ECOMn

CAPPn

CAPNn

MATn

TOGn

PWMn

ECCFn

Bit

Number

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

7

6

-

Enable Comparator

ECOMn

CAPPn

CAPNn

MATn

Cleared to disable the comparator function.

Set to enable the comparator function.

Capture Positive

5

4

3

2

1

Cleared to disable positive edge capture.

Set to enable positive edge capture.

Capture Negative

Cleared to disable negative edge capture.

Set to enable negative edge capture.

Match

When MATn = 1, a match of the PCA counter with this module's compare/capture

register causes the CCFn bit in CCON to be set, flagging an interrupt.

Toggle

TOGn

When TOGn = 1, a match of the PCA counter with this module's compare/capture

register causes the CEXn pin to toggle.

Pulse Width Modulation Mode

PWMn

Cleared to disable the CEXn pin to be used as a pulse width modulated output.

Set to enable the CEXn pin to be used as a pulse width modulated output.

Enable CCF interrupt

Cleared to disable compare/capture flag CCFn in the CCON register to generate an

interrupt.

0

CCF0

Set to enable compare/capture flag CCFn in the CCON register to generate an interrupt.

Reset Value = X000 0000b

Not bit addressable

40

AT89C51RD2/ED2

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AT89C51RD2/ED2

Table 13-4. PCA Module Modes (CCAPMn Registers)

ECOMn CAPPn

CAPNn

MATn

TOGn

PWMm

ECCFn Module Function

0

1

0

No Operation

16-bit capture by a positive-edge

trigger on CEXn

X

0

1

0

X

16-bit capture by a negative trigger on

CEXn

X

0

X

1

0

1

0

1

0

1

0

1

0

X

0

1

0

X

0

16-bit capture by a transition on CEXn

16-bit Software Timer/Compare mode.

16-bit High Speed Output

8-bit PWM

X

Watchdog Timer (module 4 only)

There are two additional registers associated with each of the PCA modules. They are CCAPnH

and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a

compare should occur. When a module is used in the PWM mode these registers are used to

control the duty cycle of the output (See Table 13-5 & Table 13-6).

Table 13-5. CCAPnH Registers (n = 0 - 4)

CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh)

CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh)

CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh)

CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh)

CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)

7

6

5

4

3

2

1

0

-

Bit

Number

Mnemonic Description

PCA Module n Compare/Capture Control

CCAPnH Value

7 - 0

-

Reset Value = 0000 0000b

Not bit addressable

41

4235K–8051–05/08

Table 13-6. CCAPnL Registers (n = 0 - 4)

CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh)

CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh)

CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh)

CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh)

CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

PCA Module n Compare/Capture Control

7 - 0

-

CCAPnL Value

Reset Value = 0000 0000b

Not bit addressable

Table 13-7. CH Register

CH - PCA Counter Register High (0F9h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

PCA counter

7 - 0

-

CH Value

Reset Value = 0000 0000b

Not bit addressable

Table 13-8. CL Register

CL - PCA Counter Register Low (0E9h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

PCA Counter

CL Value

7 - 0

-

Reset Value = 0000 0000b

Not bit addressable

42

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

13.1 PCA Capture Mode

To use one of the PCA modules in the capture mode either one or both of the CCAPM bits

CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1)

is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of

the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and

CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn

SFR are set then an interrupt will be generated (Refer to Figure 13-3).

Figure 13-3. PCA Capture Mode

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

PCA IT

PCA Counter/Timer

Cex.n

CH

CL

Capture

CCAPnH

CCAPnL

CCAPMn, n= 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

13.2 16-bit Software Timer/ Compare Mode

The PCA modules can be used as software timers by setting both the ECOM and MAT bits in

the modules CCAPMn register. The PCA timer will be compared to the module's capture regis-

ters and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn

(CCAPMn SFR) bits for the module are both set (See Figure 13-4).

43

4235K–8051–05/08

Figure 13-4. PCA Compare Mode and PCA Watchdog Timer

CCON

0xD8

CF

CCF4 CCF3 CCF2 CCF1 CCF0

CR

Write to

CCAPnL Reset

PCA IT

Write to

CCAPnH

CCAPnL

Enable

1

0

Match

16 bit comparator

RESET *

CH

CL

PCA counter/timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

CMOD

0xD9

CIDL WDTE

CPS1 CPS0 ECF

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other-

wise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.

Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur

while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user

software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be

controlled by accessing to CCAPMn register.

13.3 High Speed Output Mode

In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a

match occurs between the PCA counter and the modules capture registers. To activate this

mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See

Figure 13-5).

A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.

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Figure 13-5. PCA High Speed Output Mode

CCON

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

0xD8

Write to

CCAPnL

Reset

PCA IT

Write to

CCAPnH

CCAPnL

0

1

Enable

Match

16 bit comparator

CEXn

CH

CL

PCA counter/timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other-

wise an unwanted match could happen.

Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur

while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user

software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be

controlled by accessing to CCAPMn register.

13.4 Pulse Width Modulator Mode

All of the PCA modules can be used as PWM outputs. Figure 13-6 shows the PWM function.

The frequency of the output depends on the source for the PCA timer. All of the modules will

have the same frequency of output because they all share the PCA timer. The duty cycle of each

module is independently variable using the modules capture register CCAPLn. When the value

of the PCA CL SFR is less than the value in the modules CCAPLn SFR the output will be low,

when it is equal to or greater than the output will be high. When CL overflows from FF to 00,

CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches.

The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM

mode.

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4235K–8051–05/08

Figure 13-6. PCA PWM Mode

CCAPnH

Overflow

CCAPnL

“0”

“1”

CEXn

Enable

8-bit Comparator

CL

PCA Counter/Timer

CCAPMn, n= 0 to 4

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

13.5 PCA Watchdog Timer

An on-board watchdog timer is available with the PCA to improve the reliability of the system

without increasing chip count. Watchdog timers are useful for systems that are susceptible to

noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be

programmed as a watchdog. However, this module can still be used for other modes if the

watchdog is not needed. Figure 13-4 shows a diagram of how the watchdog works. The user

pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit

value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be

generated. This will not cause the RST pin to be driven high.

In order to hold off the reset, the user has three options:

1. Periodically change the compare value so it will never match the PCA timer.

2. Periodically change the PCA timer value so it will never match the compare values.

3. Disable the watchdog by clearing the WDTE bit before a match occurs and then re-

enable it.

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The first two options are more reliable because the watchdog timer is never disabled as in option

#3. If the program counter ever goes astray, a match will eventually occur and cause an internal

reset. The second option is also not recommended if other PCA modules are being used.

Remember, the PCA timer is the time base for all modules; changing the time base for other

modules would not be a good idea. Thus, in most applications the first solution is the best option.

This watchdog timer won’t generate a reset out on the reset pin.

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14. Serial I/O Port

The serial I/O port in the AT89C51RD2/ED2 is compatible with the serial I/O port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as a Univer-

sal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and

3). Asynchronous transmission and reception can occur simultaneously and at different baud

rates

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

14.1 Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To

enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 14-

1).

Figure 14-1. Framing Error Block Diagram

SM0/FE SM1

SM2

REN

TB8

RB8

TI

RI

SCON (98h)

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)

SM0 to UART mode control (SMOD0 = 0)

PCON (87h)

SMOD1SMOD0

-

POF GF1

GF0

PD

IDL

To UART framing error control

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.

An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by

two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table

14-4.) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set, only soft-

ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear

FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure

14-2. and Figure 14-3.).

Figure 14-2. UART Timings in Mode 1

RXD

D0

D1

D2

D3

D4

D5

D6

D7

Start

bit

Data byte

Stop

bit

RI

SMOD0=X

FE

SMOD0=1

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Figure 14-3. UART Timings in Modes 2 and 3

RXD

D0

D1

D2

D3

D4

D5

D6

D7

D8

Start

bit

Data byte

Ninth Stop

bit

RI

SMOD0=0

RI

SMOD0=1

FE

SMOD0=1

14.2 Automatic Address Recognition

The automatic address recognition feature is enabled when the multiprocessor communication

feature is enabled (SM2 bit in SCON register is set).

Implemented in hardware, automatic address recognition enhances the multiprocessor commu-

nication feature by allowing the serial port to examine the address of each incoming command

frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON

register to generate an interrupt. This ensures that the CPU is not interrupted by command

frames addressed to other devices.

If desired, the user may enable the automatic address recognition feature in mode 1.In this con-

figuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received

command frame address matches the device’s address and is terminated by a valid stop bit.

To support automatic address recognition, a device is identified by a given address and a broad-

cast address.

Note:

The multiprocessor communication and automatic address recognition features cannot be

enabled in mode 0 (i. e. setting SM2 bit in SCON register in mode 0 has no effect).

14.2.1

Given Address

Each device has an individual address that is specified in SADDR register; the SADEN register

is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given

address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The

following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111 1111b.

For example:

SADDR0101 0110b

SADEN1111 1100b

Given0101 01XXb

The following is an example of how to use given addresses to address different slaves:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 0X0Xb

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 0XX1b

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Slave C:SADDR1111 0010b

SADEN1111 1101b

Given1111 00X1b

The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1.To communicate

with slave A only, the master must send an address where bit 0 is clear (e. g. 1111 0000b).

For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves

B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e. g. 1111

0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1

clear, and bit 2 clear (e. g. 1111 0001b).

14.2.2

Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers with

zeros defined as don’t-care bits, e. g. :

SADDR0101 0110b

SADEN1111 1100b

Broadcast =SADDR OR SADEN1111 111Xb

The use of don’t-care bits provides flexibility in defining the broadcast address, however in most

applications, a broadcast address is FFh. The following is an example of using broadcast

addresses:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Broadcast1111 1X11b,

Slave B:SADDR1111 0011b

SADEN1111 1001b

Broadcast1111 1X11B,

Slave C:SADDR=1111 0011b

SADEN1111 1101b

Broadcast1111 1111b

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of

the slaves, the master must send an address FFh. To communicate with slaves A and B, but not

slave C, the master can send and address FBh.

14.2.3

Reset Addresses

On reset, the SADDR and SADEN registers are initialized to 00h, i. e. the given and broadcast

addresses are XXXX XXXXb(all don’t-care bits). This ensures that the serial port will reply to any

address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not

support automatic address recognition.

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14.3 Registers

Table 14-1. SADEN Register

SADEN - Slave Address Mask Register (B9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Not bit addressable

Table 14-2. SADDR Register

SADDR - Slave Address Register (A9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Not bit addressable

14.4 Baud Rate Selection for UART for Mode 1 and 3

The Baud Rate Generator for transmit and receive clocks can be selected separately via the

T2CON and BDRCON registers.

Figure 14-4. Baud Rate Selection

TIMER1

TIMER_BRG_RX

0

1

0

1

TIMER2

/ 16

Rx Clock

RCLK

RBCK

INT_BRG

TIMER1

TIMER2

TIMER_BRG_TX

0

1

0

1

/ 16

Tx Clock

TCLK

TBCK

INT_BRG

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Table 14-3. Baud Rate Selection Table UART

TCLK

RCLK

TBCK

RBCK

Clock Source

UART Tx

Clock Source

UART Rx

(T2CON)

(BDRCON)

0

1

0

1

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

Timer 1

Timer 2

Timer 1

Timer 2

INT_BRG

Timer 1

Timer 2

INT_BRG

Timer 2

INT_BRG

14.4.1

Internal Baud Rate Generator (BRG)

When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG

overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON

register and the value of the SMOD1 bit in PCON register.

Figure 14-5. Internal Baud Rate

F_{Clk Periph}

÷ 6

0

1

Overflow

BRG

(8 bits)

÷ 2

0

1

INT_BRG

SPD

BDRCON.1

BRR

BDRCON.4

SMOD1

PCON.7

BRL

(8 bits)

• The baud rate for UART is token by formula:

2^SMOD1⋅ F_PER

6^(1-SPD)⋅ 32 ⋅ (256 -BRL)

Baud_Rate =

2^SMOD1⋅ F_PER

6^(1-SPD)⋅ 32 ⋅ Baud_Rate

BRL = 256 -

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Table 14-4. SCON Register

SCON - Serial Control Register (98h)

7

6

5

4

3

2

1

0

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

Bit

Number

Mnemonic

Description

Framing Error bit (SMOD0=1)

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

FE

SMOD0 must be set to enable access to the FE bit.

7

Serial port Mode bit 0

Refer to SM1 for serial port mode selection.

SM0

SM1

SMOD0 must be cleared to enable access to the SM0 bit.

Serial port Mode bit 1

SM0SM1Mode

Baud Rate

F_XTAL/12 (or F_XTAL/6 in mode X2)

Variable

0

1

0

1

0

1

Shift Register

8-bit UART

6

5

9-bit UARTF_XTAL/64 or F_XTAL/32

9-bit UARTVariable

Serial port Mode 2 bit / Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.

SM2

Set to enable multiprocessor communication feature in mode 2 and 3, and

eventually mode 1.This bit should be cleared in mode 0.

Reception Enable bit

Clear to disable serial reception.

Set to enable serial reception.

4

3

REN

TB8

Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

Receiver Bit 8 / Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

2

1

0

RB8

In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.

Transmit Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the

stop bit in the other modes.

TI

Receive Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 14-2. and

Figure 14-3. in the other modes.

RI

Reset Value = 0000 0000b

Bit addressable

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Table 14-5. Example of Computed Value When X2=1, SMOD1=1, SPD=1

Baud Rates

F_OSC= 16. 384 MHz

F_OSC= 24MHz

BRL

Error (%)

1.23

BRL

243

230

217

204

178

100

-

Error (%)

0.16

-

115200

57600

38400

28800

19200

9600

247

238

229

220

203

149

43

1.23

0.63

0.31

4800

1.23

Table 14-6. Example of Computed Value When X2=0, SMOD1=0, SPD=0

Baud Rates

F_OSC= 16. 384 MHz

F_OSC= 24MHz

BRL

Error (%)

1.23

BRL

243

230

202

152

Error (%)

0.16

4800

2400

1200

600

247

238

220

185

1.23

0.16

1.23

3.55

0.16

The baud rate generator can be used for mode 1 or 3 (refer to Figure 14-4.), but also for mode 0

for UART, thanks to the bit SRC located in BDRCON register (Table 14-13.)

14.5 UART Registers

Table 14-7. SADEN Register

SADEN - Slave Address Mask Register for UART (B9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Table 14-8. SADDR Register

SADDR - Slave Address Register for UART (A9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

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Table 14-9. SBUF Register

SBUF - Serial Buffer Register for UART (99h)

7

6

5

4

3

2

1

0

Reset Value = XXXX XXXXb

Table 14-10. BRL Register

BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

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Table 14-11. T2CON Register

T2CON - Timer 2 Control Register (C8h)

7

6

5

4

3

2

1

0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Bit

Number

Mnemonic

Description

Timer 2 overflow Flag

Must be cleared by software.

7

6

TF2

Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if

EXEN2=1.

EXF2

When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is

enabled.

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter

mode (DCEN = 1)

Receive Clock bit for UART

Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.

5

4

RCLK

TCLK

Transmit Clock bit for UART

Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Cleared to ignore events on T2EX pin for timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is detected, if

timer 2 is not used to clock the serial port.

3

2

1

EXEN2

TR2

Timer 2 Run control bit

Cleared to turn off timer 2.

Set to turn on timer 2.

Timer/Counter 2 select bit

Cleared for timer operation (input from internal clock system: F_{CLK PERIPH}).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for

clock out mode.

C/T2#

Timer 2 Capture/Reload bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2

overflow.

0

CP/RL2#

Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin if

EXEN2=1.

Set to capture on negative transitions on T2EX pin if EXEN2=1.

Reset Value = 0000 0000b

Bit addressable

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Table 14-12. PCON Register

PCON - Power Control Register (87h)

7

6

5

-

4

3

2

1

0

SMOD1

SMOD0

POF

GF1

GF0

PD

IDL

Bit

Number

Mnemonic

Description

Serial port Mode bit 1 for UART

Set to select double baud rate in mode 1, 2 or 3.

7

6

5

SMOD1

SMOD0

-

Serial port Mode bit 0 for UART

Cleared to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Cleared to recognize next reset type.

4

POF

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by

software.

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

3

2

1

0

GF1

GF0

PD

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

Power-Down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle mode bit

Cleared by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset Value = 00X1 0000b

Not bit addressable

Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect

the value of this bit.

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Table 14-13. BDRCON Register

BDRCON - Baud Rate Control Register (9Bh)

7

-

6

-

5

-

4

3

2

1

0

BRR

TBCK

RBCK

SPD

SRC

Bit

Number

Bit

Mnemonic Description

Reserved

7

6

5

-

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Baud Rate Run Control bit

4

3

2

1

0

BRR

TBCK

RBCK

SPD

Cleared to stop the internal Baud Rate Generator.

Set to start the internal Baud Rate Generator.

Transmission Baud rate Generator Selection bit for UART

Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

Reception Baud Rate Generator Selection bit for UART

Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

Baud Rate Speed Control bit for UART

Cleared to select the SLOW Baud Rate Generator.

Set to select the FAST Baud Rate Generator.

Baud Rate Source select bit in Mode 0 for UART

SRC

Cleared to select F_OSC/12 as the Baud Rate Generator (F_{CLK PERIPH}/6 in X2 mode).

Set to select the internal Baud Rate Generator for UARTs in mode 0.

Reset Value = XXX0 0000b

Not bit addressable

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15. Keyboard Interface

The AT89C51RD2/ED2 implements a keyboard interface allowing the connection of a

8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both

high or low level. These inputs are available as alternate function of P1 and allow to exit from

idle and power-down modes.

The keyboard interfaces with the C51 core through 3 special function registers: KBLS, the Key-

board Level Selection register (Table 15-3), KBE, the Keyboard interrupt Enable register

(Table 15-2), and KBF, the Keyboard Flag register (Table 15-1).

15.0.1

Interrupt

The keyboard inputs are considered as 8 independent interrupt sources sharing the same inter-

rupt vector. An interrupt enable bit (KBD in IE1) allows global enable or disable of the keyboard

interrupt (see Figure 15-1). As detailed in Figure 15-2 each keyboard input has the capability to

detect a programmable level according to KBLS. x bit value. Level detection is then reported in

interrupt flags KBF.x that can be masked by software using KBE. x bits.

This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allows usage of P1

inputs for other purpose.

Figure 15-1. Keyboard Interface Block Diagram

Vcc

0

P1:x

KBF.x

1

KBE.x

Internal Pullup

KBLS.x

Figure 15-2. Keyboard Input Circuitry

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

Input Circuitry

KBDIT

Keyboard Interface

Interrupt Request

KBD

IE1

15.0.2

Power Reduction Mode

P1 inputs allow exit from idle and power-down modes as detailed in Section “Power Manage-

ment”, page 80.

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4235K–8051–05/08

15.1 Registers

Table 15-1. KBF Register

KBF-Keyboard Flag Register (9Eh)

7

6

5

4

3

2

1

0

KBF7

KBF6

KBF5

KBF4

KBF3

KBF2

KBF1

KBF0

Bit

Bit Number Mnemonic Description

Keyboard line 7 flag

Set by hardware when the Port line 7 detects a programmed level. It generates a

Keyboard interrupt request if the KBKBIE.7 bit in KBIE register is set.

Must be cleared by software.

7

6

5

4

3

2

1

0

KBF7

KBF6

KBF5

KBF4

KBF3

KBF2

KBF1

KBF0

Keyboard line 6 flag

Set by hardware when the Port line 6 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE.6 bit in KBIE register is set.

Must be cleared by software.

Keyboard line 5 flag

Set by hardware when the Port line 5 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE.5 bit in KBIE register is set.

Must be cleared by software.

Keyboard line 4 flag

Set by hardware when the Port line 4 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE.4 bit in KBIE register is set.

Must be cleared by software.

Keyboard line 3 flag

Set by hardware when the Port line 3 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE.3 bit in KBIE register is set.

Must be cleared by software.

Keyboard line 2 flag

Set by hardware when the Port line 2 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE.2 bit in KBIE register is set.

Must be cleared by software.

Keyboard line 1 flag

Set by hardware when the Port line 1 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE.1 bit in KBIE register is set.

Must be cleared by software.

Keyboard line 0 flag

Set by hardware when the Port line 0 detects a programmed level. It generates a

Keyboard interrupt request if the KBIE.0 bit in KBIE register is set.

Must be cleared by software.

Reset Value = 0000 0000b

This register is read only access, all flags are automatically cleared by reading the register.

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Table 15-2. KBE Register

KBE-Keyboard Input Enable Register (9Dh)

7

6

5

4

3

2

1

0

KBE7

KBE6

KBE5

KBE4

KBE3

KBE2

KBE1

KBE0

Bit

Number

Bit

Mnemonic Description

Keyboard line 7 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.7 bit in KBF register to generate an interrupt request.

7

6

5

4

3

2

1

0

KBE7

KBE6

KBE5

KBE4

KBE3

KBE2

KBE1

KBE0

Keyboard line 6 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.6 bit in KBF register to generate an interrupt request.

Keyboard line 5 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.5 bit in KBF register to generate an interrupt request.

Keyboard line 4 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.4 bit in KBF register to generate an interrupt request.

Keyboard line 3 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.3 bit in KBF register to generate an interrupt request.

Keyboard line 2 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.2 bit in KBF register to generate an interrupt request.

Keyboard line 1 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.1 bit in KBF register to generate an interrupt request.

Keyboard line 0 Enable bit

Cleared to enable standard I/O pin.

Set to enable KBF.0 bit in KBF register to generate an interrupt request.

Reset Value = 0000 0000b

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Table 15-3. KBLS Register

KBLS-Keyboard Level Selector Register (9Ch)

7

6

5

4

3

2

1

0

KBLS7

KBLS6

KBLS5

KBLS4

KBLS3

KBLS2

KBLS1

KBLS0

Bit

Bit Number Mnemonic Description

Keyboard line 7 Level Selection bit

7

6

5

4

3

2

1

0

KBLS7

KBLS6

KBLS5

KBLS4

KBLS3

KBLS2

KBLS1

KBLS0

Cleared to enable a low level detection on Port line 7.

Set to enable a high level detection on Port line 7.

Keyboard line 6 Level Selection bit

Cleared to enable a low level detection on Port line 6.

Set to enable a high level detection on Port line 6.

Keyboard line 5 Level Selection bit

Cleared to enable a low level detection on Port line 5.

Set to enable a high level detection on Port line 5.

Keyboard line 4 Level Selection bit

Cleared to enable a low level detection on Port line 4.

Set to enable a high level detection on Port line 4.

Keyboard line 3 Level Selection bit

Cleared to enable a low level detection on Port line 3.

Set to enable a high level detection on Port line 3.

Keyboard line 2 Level Selection bit

Cleared to enable a low level detection on Port line 2.

Set to enable a high level detection on Port line 2.

Keyboard line 1 Level Selection bit

Cleared to enable a low level detection on Port line 1.

Set to enable a high level detection on Port line 1.

Keyboard line 0 Level Selection bit

Cleared to enable a low level detection on Port line 0.

Set to enable a high level detection on Port line 0.

Reset Value = 0000 0000b

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16. Serial Port Interface (SPI)

The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communica-

tion between the MCU and peripheral devices, including other MCUs.

16.1 Features

Features of the SPI Module include the following:

• Full-duplex, three-wire synchronous transfers

• Master or Slave operation

• Eight programmable Master clock rates

• Serial clock with programmable polarity and phase

• Master Mode fault error flag with MCU interrupt capability

• Write collision flag protection

16.2 Signal Description

Figure 16-1 shows a typical SPI bus configuration using one Master controller and many Slave

peripherals. The bus is made of three wires connecting all the devices.

Figure 16-1. SPI Master/Slaves Interconnection

Slave 1

MISO

MOSI

SCK

SS

VDD

Master

0

1

2

3

Slave 4

Slave 3

Slave 2

The Master device selects the individual Slave devices by using four pins of a parallel port to

control the four SS pins of the Slave devices.

16.2.1

16.2.2

Master Output Slave Input (MOSI)

This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI

line is used to transfer data in series from the Master to the Slave. Therefore, it is an output sig-

nal from the Master, and an input signal to a Slave. A Byte (8-bit word) is transmitted most

significant bit (MSB) first, least significant bit (LSB) last.

Master Input Slave Output (MISO)

This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO

line is used to transfer data in series from the Slave to the Master. Therefore, it is an output sig-

nal from the Slave, and an input signal to the Master. A Byte (8-bit word) is transmitted most

significant bit (MSB) first, least significant bit (LSB) last.

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16.2.3

16.2.4

SPI Serial Clock (SCK)

This signal is used to synchronize the data movement both in and out of the devices through

their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to

exchange one Byte on the serial lines.

Slave Select (SS)

Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any

message for a Slave. It is obvious that only one Master (SS high level) can drive the network.

The Master may select each Slave device by software through port pins (Figure 16-2). To pre-

vent bus conflicts on the MISO line, only one slave should be selected at a time by the Master

for a transmission.

In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI

Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Error

conditions).

A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.

The SS pin could be used as a general-purpose if the following conditions are met:

• The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of

configuration can be found when only one Master is driving the network and there is no way

that the SS pin could be pulled low. Therefore, the MODF flag in the SPSTA will never be

set⁽¹⁾.

• The Device is configured as a Slave with CPHA and SSDIS control bits set⁽²⁾. This kind of

configuration can happen when the system comprises one Master and one Slave only.

Therefore, the device should always be selected and there is no reason that the Master uses

the SS pin to select the communicating Slave device.

Note:

1. Clearing SSDIS control bit does not clear MODF.

2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because in this

mode, the SS is used to start the transmission.

16.2.5

Baud Rate

In Master mode, the baud rate can be selected from a baud rate generator which is controlled by

three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is selected from one

of seven clock rates resulting from the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128.

Table 16-1 gives the different clock rates selected by SPR2:SPR1:SPR0.

Table 16-1. SPI Master Baud Rate Selection

SPR2

SPR1

SPR0

Clock Rate

F_{CLK PERIPH}/2

F_{CLK PERIPH}/4

F_{CLK PERIPH}/8

F_{CLK PERIPH}/16

F_{CLK PERIPH}/32

F_{CLK PERIPH}/64

F_{CLK PERIPH}/128

Don’t Use

Baud Rate Divisor (BD)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

No BRG

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16.3 Functional Description

Figure 16-2 shows a detailed structure of the SPI Module.

Figure 16-2. SPI Module Block Diagram

Internal Bus

SPDAT

Shift Register

4

FCLK PERIPH

7

6

5

3

2

1

0

/4

Clock

Divider

/8

/16

/32

/64

Receive Data Register

Control

Logic

MOSI

MISO

/128

Clock

Logic

M

S

SCK

SS

Clock

Select

SPR2

SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

SPCON

8-bit bus

SPI

Control

1-bit signal

SPI Interrupt Request

SPSTA

-

SPIF WCOL

MODF

16.3.1

Operating Modes

The Serial Peripheral Interface can be configured in one of the two modes: Master mode or

Slave mode. The configuration and initialization of the SPI Module is made through one register:

• The Serial Peripheral Control register (SPCON)

Once the SPI is configured, the data exchange is made using:

• SPCON

• The Serial Peripheral STAtus register (SPSTA)

• The Serial Peripheral DATa register (SPDAT)

During an SPI transmission, data is simultaneously transmitted (shifted out serially) and

received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the

two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a

Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities.

When the Master device transmits data to the Slave device via the MOSI line, the Slave device

responds by sending data to the Master device via the MISO line. This implies full-duplex trans-

mission with both data out and data in synchronized with the same clock (Figure 16-3).

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Figure 16-3. Full-Duplex Master-Slave Interconnection

MISO

MOSI

MISO

MOSI

8-bit Shift register

SPI

Clock Generator

SCK

SS

SCK

SS

VDD

Master MCU

Slave MCU

VSS

16.3.1.1

Master Mode

The SPI operates in Master mode when the Master bit, MSTR ⁽¹⁾, in the SPCON register is set.

Only one Master SPI device can initiate transmissions. Software begins the transmission from a

Master SPI Module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register

is empty, the Byte is immediately transferred to the shift register. The Byte begins shifting out on

MOSI pin under the control of the serial clock, SCK. Simultaneously, another Byte shifts in from

the Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral transfer

data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received

Byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF

by reading the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading

the SPDAT.

16.3.1.2

Slave Mode

The SPI operates in Slave mode when the Master bit, MSTR ⁽²⁾, in the SPCON register is

cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave device must

be set to ’0’. SS must remain low until the transmission is complete.

In a Slave SPI Module, data enters the shift register under the control of the SCK from the Mas-

ter SPI Module. After a Byte enters the shift register, it is immediately transferred to the receive

data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software

must then read the SPDAT before another Byte enters the shift register ⁽³⁾. A Slave SPI must

complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI

starts a transmission. If the write to the data register is late, the SPI transmits the data already in

the shift register from the previous transmission. The maximum SCK frequency allowed in slave

mode is F_{CLK PERIPH}/4.

16.3.2

Transmission Formats

Software can select any of four combinations of serial clock (SCK) phase and polarity using two

bits in the SPCON: the Clock Polarity (CPOL ⁽⁴⁾) and the Clock Phase (CPHA⁴). CPOL defines

the default SCK line level in idle state. It has no significant effect on the transmission format.

CPHA defines the edges on which the input data are sampled and the edges on which the out-

put data are shifted (Figure 16-4 and Figure 16-5). The clock phase and polarity should be

identical for the Master SPI device and the communicating Slave device.

1.

The SPI Module should be configured as a Master before it is enabled (SPEN set). Also, the Mas-

ter SPI should be configured before the Slave SPI.

2.

3.

4.

The SPI Module should be configured as a Slave before it is enabled (SPEN set).

The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed.

Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).

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Figure 16-4. Data Transmission Format (CPHA = 0)

1

2

3

4

5

6

7

8

SCK Cycle Number

SPEN (Internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI (from Master)

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

MISO (from Slave)

MSB

SS (to Slave)

Capture Point

Figure 16-5. Data Transmission Format (CPHA = 1)

1

2

3

4

5

6

7

8

SCK Cycle Number

SPEN (Internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

MOSI (from Master)

MISO (from Slave)

SS (to Slave)

Capture Point

Figure 16-6. CPHA/SS Timing

Byte 3

MISO/MOSI

Byte 1

Byte 2

Master SS

Slave SS

(CPHA = 0)

Slave SS

(CPHA = 1)

As shown in Figure 16-4, the first SCK edge is the MSB capture strobe. Therefore, the Slave

must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to

start the transmission. The SS pin must be toggled high and then low between each Byte trans-

mitted (Figure 16-6).

Figure 16-5 shows an SPI transmission in which CPHA is ’1’. In this case, the Master begins

driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first SCK edge as a

start transmission signal. The SS pin can remain low between transmissions (Figure 16-6). This

format may be preferred in systems having only one Master and only one Slave driving the

MISO data line.

16.3.3

Error Conditions

The following flags in the SPSTA signal SPI error conditions:

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16.3.3.1

Mode Fault (MODF)

Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is

inconsistent with the actual mode of the device. MODF is set to warn that there may be a multi-

master conflict for system control. In this case, the SPI system is affected in the following ways:

• An SPI receiver/error CPU interrupt request is generated

• The SPEN bit in SPCON is cleared. This disables the SPI

• The MSTR bit in SPCON is cleared

When SS Disable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the

SS signal becomes ’0’.

However, as stated before, for a system with one Master, if the SS pin of the Master device is

pulled low, there is no way that another Master attempts to drive the network. In this case, to

prevent the MODF flag from being set, software can set the SSDIS bit in the SPCON register

and therefore making the SS pin as a general-purpose I/O pin.

Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed

by a write to the SPCON register. SPEN Control bit may be restored to its original set state after

the MODF bit has been cleared.

16.3.3.2

Write Collision (WCOL)

A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done

during a transmit sequence.

WCOL does not cause an interruption, and the transfer continues uninterrupted.

Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an

access to SPDAT.

16.3.3.3

Overrun Condition

An overrun condition occurs when the Master device tries to send several data Bytes and the

Slave devise has not cleared the SPIF bit issuing from the previous data Byte transmitted. In this

case, the receiver buffer contains the Byte sent after the SPIF bit was last cleared. A read of the

SPDAT returns this Byte. All others Bytes are lost.

This condition is not detected by the SPI peripheral.

16.3.3.4

SS Error Flag (SSERR)

A Synchronous Serial Slave Error occurs when SS goes high before the end of a received data

in slave mode. SSERR does not cause in interruption, this bit is cleared by writing 0 to SPEN bit

(reset of the SPI state machine).

16.3.4

Interrupts

Two SPI status flags can generate a CPU interrupt requests:

Table 16-2. SPI Interrupts

Flag

Request

SPIF (SP data transfer)

MODF (Mode Fault)

SPI Transmitter Interrupt request

SPI Receiver/Error Interrupt Request (if SSDIS = ’0’)

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Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been

completed. SPIF bit generates transmitter CPU interrupt requests.

Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent

with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt

requests. When SSDIS is set, no MODF interrupt request is generated.

Figure 16-7 gives a logical view of the above statements.

Figure 16-7. SPI Interrupt Requests Generation

SPIF

SPI Transmitter

CPU Interrupt Request

SPI

CPU Interrupt Request

MODF

SSDIS

SPI Receiver/error

CPU Interrupt Request

16.3.5

Registers

There are three registers in the Module that provide control, status and data storage functions. These registers are

describes in the following paragraphs.

16.3.5.1

Serial Peripheral Control Register (SPCON)

• The Serial Peripheral Control Register does the following:

• Selects one of the Master clock rates

• Configure the SPI Module as Master or Slave

• Selects serial clock polarity and phase

• Enables the SPI Module

• Frees the SS pin for a general-purpose

Table 16-3 describes this register and explains the use of each bit

Table 16-3. SPCON Register

SPCON - Serial Peripheral Control Register (0C3H)

7

6

5

4

3

2

1

0

SPR2

SPEN

SSDIS

MSTR

CPOL

CPHA

SPR1

SPR0

Bit Number

Bit Mnemonic

Description

Serial Peripheral Rate 2

7

SPR2

SPEN

Bit with SPR1 and SPR0 define the clock rate.

Serial Peripheral Enable

6

5

Cleared to disable the SPI interface.

Set to enable the SPI interface.

SS Disable

Cleared to enable SS in both Master and Slave modes.

SSDIS

Set to disable SS in both Master and Slave modes. In Slave mode, this bit

has no effect if CPHA =’0’. When SSDIS is set, no MODF interrupt request

is generated

.

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Bit Number

Bit Mnemonic

Description

Serial Peripheral Master

4

MSTR

Cleared to configure the SPI as a Slave.

Set to configure the SPI as a Master.

Clock Polarity

3

2

CPOL

CPHA

SPR1

Cleared to have the SCK set to ’0’ in idle state.

Set to have the SCK set to ’1’ in idle low.

Clock Phase

Cleared to have the data sampled when the SCK leaves the idle state (see

CPOL).

Set to have the data sampled when the SCK returns to idle state (see

CPOL).

SPR2 SPR1 SPR0 Serial Peripheral Rate

0

1

0

1

0

1

1F_{CLK PERIPH}/2

1F_{CLK PERIPH}/4

0F_{CLK PERIPH}/8

1F_{CLK PERIPH}/16

0F_{CLK PERIPH}/32

1F_{CLK PERIPH}/64

0F_{CLK PERIPH}/128

1Invalid

1

SPR0

Reset Value = 0001 0100b

Not bit addressable

16.3.5.2

Serial Peripheral Status Register (SPSTA)

The Serial Peripheral Status Register contains flags to signal the following conditions:

• Data transfer complete

• Write collision

• Inconsistent logic level on SS pin (mode fault error)

Table 16-4 describes the SPSTA register and explains the use of every bit in the register.

Table 16-4. SPSTA Register

SPSTA - Serial Peripheral Status and Control register (0C4H)

7

6

5

4

3

-

2

-

1

-

0

-

SPIF

WCOL

SSERR

MODF

Bit

Bit Number Mnemonic Description

Serial Peripheral Data Transfer Flag

Cleared by hardware to indicate data transfer is in progress or has been approved by a

clearing sequence.

7

6

SPIF

Set by hardware to indicate that the data transfer has been completed.

Write Collision Flag

Cleared by hardware to indicate that no collision has occurred or has been approved by a

clearing sequence.

WCOL

Set by hardware to indicate that a collision has been detected.

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Bit

Bit Number Mnemonic Description

Synchronous Serial Slave Error Flag

5

4

SSERR

MODF

Set by hardware when SS is de-asserted before the end of a received data.

Cleared by disabling the SPI (clearing SPEN bit in SPCON).

Mode Fault

Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been

approved by a clearing sequence.

Set by hardware to indicate that the SS pin is at inappropriate logic level.

Reserved

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reset Value = 00X0 XXXXb

Not Bit addressable

16.3.5.3

Serial Peripheral DATa Register (SPDAT)

The Serial Peripheral Data Register (Table 16-5) is a read/write buffer for the receive data regis-

ter. A write to SPDAT places data directly into the shift register. No transmit buffer is available in

this model.

A Read of the SPDAT returns the value located in the receive buffer and not the content of the

shift register.

Table 16-5. SPDAT Register

SPDAT - Serial Peripheral Data Register (0C5H)

7

6

5

4

3

2

1

0

R7

R6

R5

R4

R3

R2

R1

R0

Reset Value = Indeterminate

R7:R0: Receive data bits

SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-

going exchange. However, special care should be taken when writing to them while a transmis-

sion is on-going:

• Do not change SPR2, SPR1 and SPR0

• Do not change CPHA and CPOL

• Do not change MSTR

• Clearing SPEN would immediately disable the peripheral

• Writing to the SPDAT will cause an overflow.

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17. Interrupt System

The AT89C51RD2/ED2 has a total of 9 interrupt vectors: two external interrupts (INT0 and

INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard

interrupt and the PCA global interrupt. These interrupts are shown in Figure 17-1.

Figure 17-1. Interrupt Control System

High Priority

Interrupt

IPH, IPL

3

0

INT0

IE0

3

0

3

0

3

TF0

Interrupt

Polling

INT1

IE1

Sequence, Decreasing from

High to Low Priority

TF1

0

3

PCA IT

0

3

0

RI

TI

3

TF2

EXF2

0

3

KBD IT

SPI IT

0

3

0

Low Priority

Interrupt

Individual Enable

Global Disable

Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit

in the Interrupt Enable register (Table 17-4 and Table 17-6). This register also contains a global

disable bit, which must be cleared to disable all interrupts at once.

Each interrupt source can also be individually programmed to one out of four priority levels by

setting or clearing a bit in the Interrupt Priority register (Table 17-7) and in the Interrupt Priority

High register (Table 17-5 and Table 17-6) shows the bit values and priority levels associated

with each combination.

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17.1 Registers

The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at

address 004BH and Keyboard interrupt vector is located at address 003BH. All other vectors

addresses are the same as standard C52 devices.

Table 17-1. Priority Level Bit Values

IPH.x

IPL.x

Interrupt Level Priority

0

1

0

1

0

1

0 (Lowest)

1

2

3 (Highest)

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-

ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.

If two interrupt requests of different priority levels are received simultaneously, the request of

higher priority level is serviced. If interrupt requests of the same priority level are received simul-

taneously, an internal polling sequence determines which request is serviced. Thus within each

priority level there is a second priority structure determined by the polling sequence.

17.2 Interrupt Sources and Vector Addresses

Table 17-2. Interrupt Sources and Vector Addresses

Vector

Interrupt

Request

Number

Polling Priority

Interrupt Source

Reset

Address

0

1

0

1

0000h

0003h

000Bh

0013h

001Bh

0023h

002Bh

0033h

003Bh

0043h

004Bh

INT0

IE0

2

Timer 0

INT1

TF0

3

IE1

4

Timer 1

UART

IF1

5

6

RI+TI

6

7

Timer 2

PCA

TF2+EXF2

7

5

CF + CCFn (n = 0 - 4)

8

Keyboard

-

KBDIT

-

9

10

SPI

SPIIT

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Table 17-3. IENO Register

IEN0 - Interrupt Enable Register (A8h)

7

6

5

4

3

2

1

0

EA

EC

ET2

ES

ET1

EX1

ET0

EX0

Bit

Number

Mnemonic Description

Enable All interrupt bit

7

6

EA

EC

Cleared to disable all interrupts.

Set to enable all interrupts.

PCA interrupt enable bit

Cleared to disable.

Set to enable.

Timer 2 overflow interrupt Enable bit

Cleared to disable timer 2 overflow interrupt.

Set to enable timer 2 overflow interrupt.

5

4

3

2

1

0

ET2

ES

Serial port Enable bit

Cleared to disable serial port interrupt.

Set to enable serial port interrupt.

Timer 1 overflow interrupt Enable bit

Cleared to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

ET1

EX1

ET0

EX0

External interrupt 1 Enable bit

Cleared to disable external interrupt 1.

Set to enable external interrupt 1.

Timer 0 overflow interrupt Enable bit

Cleared to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

External interrupt 0 Enable bit

Cleared to disable external interrupt 0.

Set to enable external interrupt 0.

Reset Value = 0000 0000b

Bit addressable

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Table 17-4. IPL0 Register

IPL0 - Interrupt Priority Register (B8h)

7

-

6

5

4

3

2

1

0

PPCL

PT2L

PSL

PT1L

PX1L

PT0L

PX0L

Bit

Number

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

7

6

5

4

3

2

1

0

-

PCA interrupt Priority bit

PPCL

PT2L

PSL

Refer to PPCH for priority level.

Timer 2 overflow interrupt Priority bit

Refer to PT2H for priority level.

Serial port Priority bit

Refer to PSH for priority level.

Timer 1 overflow interrupt Priority bit

PT1L

PX1L

PT0L

PX0L

Refer to PT1H for priority level.

External interrupt 1 Priority bit

Refer to PX1H for priority level.

Timer 0 overflow interrupt Priority bit

Refer to PT0H for priority level.

External interrupt 0 Priority bit

Refer to PX0H for priority level.

Reset Value = X000 0000b

Bit addressable

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Table 17-5. IPH0 Register

IPH0 - Interrupt Priority High Register (B7h)

7

6

5

4

3

2

1

0

-

PPCH

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

Bit

Number

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

7

6

-

PCA interrupt Priority high bit.

PPCHPPCLPriority Level

0

1

0Lowest

1

PPCH

PT2H

PSH

0

1Highest

Timer 2 overflow interrupt Priority High bit

PT2HPT2L Priority Level

0Lowest

0

1

5

4

3

2

1

0

1

0

1Highest

Serial port Priority High bit

PSH PSLPriority Level

0

1

0Lowest

1

0

1Highest

Timer 1 overflow interrupt Priority High bit

PT1HPT1L Priority Level

0

1

0 Lowest

1

PT1H

PX1H

PT0H

PX0H

0

1Highest

External interrupt 1 Priority High bit

PX1HPX1LPriority Level

0

1

0Lowest

1

0

1Highest

Timer 0 overflow interrupt Priority High bit

PT0HPT0LPriority Level

0

1

0Lowest

1

0

1Highest

External interrupt 0 Priority High bit

PX0H PX0LPriority Level

0

1

0Lowest

1

0

1Highest

Reset Value = X000 0000b

Not bit addressable

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Table 17-6. IEN1 Register

IEN1 - Interrupt Enable Register (B1h)

7

6

5

4

3

2

1

0

-

ESPI

-

KBD

Bit

Number

Mnemonic Description

7

6

5

4

3

-

Reserved

SPI interrupt Enable bit

Cleared to disable SPI interrupt.

2

1

0

ESPI

Set to enable SPI interrupt.

Reserved

Keyboard interrupt Enable bit

KBD

Cleared to disable keyboard interrupt.

Set to enable keyboard interrupt.

Reset Value = XXXX X000b

Bit addressable

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Table 17-7. IPL1 Register

IPL1 - Interrupt Priority Register (B2h)

7

-

6

-

5

-

4

-

3

-

2

1

0

SPIL

TWIL

KBDL

Bit

Number

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

7

6

5

4

3

2

1

0

-

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

-

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

SPI interrupt Priority bit

Refer to SPIH for priority level.

SPIL

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Keyboard interrupt Priority bit

KBDL

Refer to KBDH for priority level.

Reset Value = XXXX X000b

Bit addressable

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Table 17-8. IPH1 Register

IPH1 - Interrupt Priority High Register (B3h)

7

-

6

-

5

-

4

-

3

-

2

1

-

0

SPIH

KBDH

Bit

Number

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

7

6

5

4

3

-

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

SPI interrupt Priority High bit

SPIHSPILPriority Level

0

1

0Lowest

2

1

0

SPIH

1

0

1Highest

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Keyboard interrupt Priority High bit

KB DHKBDLPriority Level

0

1

0 Lowest

KBDH

1

0

1Highest

Reset Value = XXXX X000b

Not bit addressable

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18. Power Management

18.1 Introduction

Two power reduction modes are implemented in the AT89C51RD2/ED2. The Idle mode and the

Power-Down mode. These modes are detailed in the following sections. In addition to these

power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2

using the X2 mode detailed in Section “Enhanced Features”, page 17.

18.2 Idle Mode

Idle mode is a power reduction mode that reduces the power consumption. In this mode, pro-

gram execution halts. Idle mode freezes the clock to the CPU at known states while the

peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e.,

the program counter and program status word register retain their data for the duration of Idle

mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during

Idle mode is detailed in Table 18-1.

18.2.1

Entering Idle Mode

To enter Idle mode, set the IDL bit in PCON register (see Table 18-2). The AT89C51RD2/ED2

enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL

bit is the last instruction executed.

Note:

If IDL bit and PD bit are set simultaneously, the AT89C51RD2/ED2 enters Power-Down mode.

Then it does not go in Idle mode when exiting Power-Down mode.

18.2.2

Exiting Idle Mode

There are two ways to exit Idle mode:

1. Generate an enabled interrupt.

– Hardware clears IDL bit in PCON register which restores the clock to the CPU.

Execution resumes with the interrupt service routine. Upon completion of the

interrupt service routine, program execution resumes with the instruction

immediately following the instruction that activated Idle mode. The general purpose

flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt

occurred during normal operation or during Idle mode. When Idle mode is exited by

an interrupt, the interrupt service routine may examine GF1 and GF0.

2. Generate a reset.

– A logic high on the RST pin clears IDL bit in PCON register directly and

asynchronously. This restores the clock to the CPU. Program execution momentarily

resumes with the instruction immediately following the instruction that activated the

Idle mode and may continue for a number of clock cycles before the internal reset

algorithm takes control. Reset initializes the AT89C51RD2/ED2 and vectors the CPU

to address C:0000h.

Note:

During the time that execution resumes, the internal RAM cannot be accessed; however, it is pos-

sible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction

immediately following the instruction that activated Idle mode should not write to a Port pin or to

the external RAM.

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18.3 Power-Down Mode

The Power-Down mode places the AT89C51RD2/ED2 in a very low power state. Power-Down

mode stops the oscillator, freezes all clock at known states. The CPU status prior to entering

Power-Down mode is preserved, i.e., the program counter, program status word register retain

their data for the duration of Power-Down mode. In addition, the SFR and RAM contents are pre-

served. The status of the Port pins during Power-Down mode is detailed in Table 18-1.

Note:

VCC may be reduced to as low as V_RETduring Power-Down mode to further reduce power dissi-

pation. Take care, however, that VDD is not reduced until Power-Down mode is invoked.

18.3.1

18.3.2

Entering Power-Down Mode

To enter Power-Down mode, set PD bit in PCON register. The AT89C51RD2/ED2 enters the

Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets

PD bit is the last instruction executed.

Exiting Power-Down Mode

Note:

If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until VCC is

restored to the normal operating level.

There are three ways to exit the Power-Down mode:

1. Generate an enabled external interrupt.

– The AT89C51RD2/ED2 provides capability to exit from Power-Down using INT0#,

INT1#.

Hardware clears PD bit in PCON register which starts the oscillator and restores the

clocks to the CPU and peripherals. Using INTx# input, execution resumes when the

input is released (see Figure 18-1). Execution resumes with the interrupt service

routine. Upon completion of the interrupt service routine, program execution

resumes with the instruction immediately following the instruction that activated

Power-Down mode.

Note:

The external interrupt used to exit Power-Down mode must be configured as level sensitive

(INT0# and INT1#) and must be assigned the highest priority. In addition, the duration of the inter-

rupt must be long enough to allow the oscillator to stabilize. The execution will only resume when

the interrupt is deasserted.

Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM content.

Figure 18-1. Power-Down Exit Waveform Using INT1:0#

INT1:0#

OSC

Active phase

Power-down phase

Oscillator restart phase

Active phase

2. Generate a reset.

– A logic high on the RST pin clears PD bit in PCON register directly and

asynchronously. This starts the oscillator and restores the clock to the CPU and

peripherals. Program execution momentarily resumes with the instruction

immediately following the instruction that activated Power-Down mode and may

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continue for a number of clock cycles before the internal reset algorithm takes

control. Reset initializes the AT89C51RD2/ED2 and vectors the CPU to address

0000h.

3. Generate an enabled external Keyboard interrupt (same behavior as external interrupt).

Note:

During the time that execution resumes, the internal RAM cannot be accessed; however, it is pos-

sible for the Port pins to be accessed. To avoid unexpected outputs at the Port pins, the instruction

immediately following the instruction that activated the Power-Down mode should not write to a

Port pin or to the external RAM.

Note:

Exit from power-down by reset redefines all the SFRs, but does not affect the internal RAM

content.

Table 18-1. Pin Conditions in Special Operating Modes

Mode

Reset

Port 0

Port 1

Port 2

Port 3

Port 4

ALE

PSEN#

Floating

High

Idle (internal

code)

Data

High

Idle (external

code)

Floating

Power-Down

(internal

code)

Data

Low

Power-Down

(external

code)

Floating

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18.4 Registers

Table 18-2. PCON Register

PCON (S87:h) Power configuration Register

7

-

6

-

5

-

4

-

3

2

1

0

GF1

GF0

PD

IDL

Bit

Bit Number Mnemonic Description

Reserved

The value read from these bits is indeterminate. Do not set these bits.

7-4

3

-

General Purpose flag 1

GF1

One use is to indicate whether an interrupt occurred during normal operation or during

Idle mode.

General Purpose flag 0

One use is to indicate whether an interrupt occurred during normal operation or during

Idle mode.

2

1

GF0

PD

Power-Down Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Power-Down mode.

If IDL and PD are both set, PD takes precedence.

Idle Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Idle mode.

0

IDL

If IDL and PD are both set, PD takes precedence.

Reset Value= XXXX 0000b

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19. Hardware Watchdog Timer

The WDT is intended as a recovery method in situations where the CPU may be subjected to

software upset. The WDT consists of a 14-bit counter and the Watchdog Timer ReSeT

(WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user

must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is

enabled, it will increment every machine cycle while the oscillator is running and there is no way

to disable the WDT except through reset (either hardware reset or WDT overflow reset). When

WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.

19.1 Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR loca-

tion 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to

WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH)

and this will reset the device. When WDT is enabled, it will increment every machine cycle while

the oscillator is running. This means the user must reset the WDT at least every 16383 machine

cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write

only register. The WDT counter cannot be read or written. When WDT overflows, it will generate

an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x T_{CLK PERIPH}, where

T_{CLK PERIPH}= 1/F_{CLK PERIPH}. To make the best use of the WDT, it should be serviced in those sec-

tions of code that will periodically be executed within the time required to prevent a WDT reset.

To have a more powerful WDT, a 2⁷counter has been added to extend the Time-out capability,

ranking from 16 ms to 2s @ F_OSCA= 12 MHz. To manage this feature, refer to WDTPRG register

description, Table 19-1. The WDTPRG register should be configured before the WDT activation

sequence, and can not be modified until next reset.

Table 19-1. WDTRST Register

WDTRST - Watchdog Reset Register (0A6h)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Reset Value = XXXX XXXXb

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.

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Table 19-2. WDTPRG Register

WDTPRG - Watchdog Timer Out Register (0A7h)

7

-

6

-

5

-

4

-

3

-

2

1

0

S2

S1

S0

Bit

Number

Mnemonic Description

7

6

5

4

3

2

1

0

-

Reserved

-

The value read from this bit is undetermined. Do not try to set this bit.

-

S2

S1

S0

WDT Time-out select bit 2

WDT Time-out select bit 1

WDT Time-out select bit 0

S2 S1 S0Selected Time-out

0

1

00

(2¹⁴- 1) machine cycles, 16. 3 ms @ F_OSCA=12 MHz

(2¹⁵- 1) machine cycles, 32.7 ms @ F_OSCA=12 MHz

01

10 (2¹⁶- 1) machine cycles, 65. 5 ms @ F_OSCA=12 MHz

11

(2¹⁷- 1) machine cycles, 131 ms @ F_OSCA=12 MHz

(2¹⁸- 1) machine cycles, 262 ms @ F_OSCA=12 MHz

00

01 (2¹⁹- 1) machine cycles, 542 ms @ F_OSCA=12 MHz

10

11

(2²⁰- 1) machine cycles, 1.05 ms @ F_OSCA=12 MHz

(2²¹- 1) machine cycles, 2.09 ms @ F_OSCA=12 MHz

Reset Value = XXXX X000

19.2 WDT during Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-

down mode the user does not need to service the WDT. There are 2 methods of exiting Power-

down mode: by a hardware reset or via a level activated external interrupt which is enabled prior

to entering Power-down mode. When Power-down is exited with hardware reset, servicing the

WDT should occur as it normally should whenever the AT89C51RD2/ED2 is reset. Exiting

Power-down with an interrupt is significantly different. The interrupt is held low long enough for

the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent

the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until

the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service

routine.

To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is bet-

ter to reset the WDT just before entering powerdown.

In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the

AT89C51RD2/ED2 while in Idle mode, the user should always set up a timer that will periodically

exit Idle, service the WDT, and re-enter Idle mode.

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20. ONCE^®Mode (ON- Chip Emulation)

The ONCE mode facilitates testing and debugging of systems using AT89C51RD2/ED2 without

removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the

AT89C51RD2/ED2; the following sequence must be exercised:

• Pull ALE low while the device is in reset (RST high) and PSEN is high.

• Hold ALE low as RST is deactivated.

While the AT89C51RD2/ED2 is in ONCE mode, an emulator or test CPU can be used to drive

the circuit. Table 20-1 shows the status of the port pins during ONCE mode.

Normal operation is restored when normal reset is applied.

Table 20-1. External Pin Status During ONCE Mode

ALE

PSEN

Port 0

Port 1

Port 2

Port 3

Port I2

XTALA1/2

XTALB1/2

Weak pull- Weak pull-

up up

Weak pull- Weak pull- Weak pull-

up up up

Float

Active

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21. Power-off Flag

The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start”

reset.

A cold start reset is the one induced by V_CCswitch-on. A warm start reset occurs while V_CCis still

applied to the device and could be generated for example by an exit from power-down.

The power-off flag (POF) is located in PCON register (Table 21-1). POF is set by hardware

when V_CCrises from 0 to its nominal voltage. The POF can be set or cleared by software allow-

ing the user to determine the type of reset.

Table 21-1. PCON Register

PCON - Power Control Register (87h)

7

6

5

-

4

3

2

1

0

SMOD1

SMOD0

POF

GF1

GF0

PD

IDL

Bit

Number

Mnemonic Description

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

7

6

5

SMOD1

SMOD0

-

Serial port Mode bit 0

Cleared to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Cleared by software to recognize the next reset type.

Set by hardware when V_CCrises from 0 to its nominal voltage. Can also be set by

software.

4

POF

General-purpose Flag

3

2

1

0

GF1

GF0

PD

Cleared by user for general-purpose usage.

Set by user for general-purpose usage.

General-purpose Flag

Cleared by user for general-purpose usage.

Set by user for general-purpose usage.

Power-down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle mode bit

IDL

Cleared by hardware when interrupt or reset occurs.

Set to enter idle mode.

Reset Value = 00X1 0000b

Not bit addressable

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22. Reduced EMI Mode

The ALE signal is used to demultiplex address and data buses on port 0 when used with exter-

nal program or data memory. Nevertheless, during internal code execution, ALE signal is still

generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit.

The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer

output but remains active during MOVX and MOVC instructions and external fetches. During

ALE disabling, ALE pin is weakly pulled high.

Table 22-1. AUXR Register

AUXR - Auxiliary Register (8Eh)

7

6

-

5

4

3

2

1

0

DPU

M0

XRS2

XRS1

XRS0

EXTRAM

AO

Bit

Number

Mnemonic Description

Disable Weak Pull-up

7

6

DPU

Cleared by software to activate the permanent weak pull-up (default)

Set by software to disable the weak pull-up (reduce power consumption)

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Pulse length

Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods

(default).

5

M0

Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.

4

3

XRS2

XRS1

XRAM Size

XRS2 XRS1XRS0XRAM size

0

1

0

1

0

0256bytes

1512 bytes

0768 bytes(default)

11024 bytes

01792 bytes

2

XRS0

EXTRAM bit

Cleared to access internal XRAM using MOVX @ Ri/ @ DPTR.

Set to access external memory.

1

0

EXTRAM

Programmed by hardware after Power-up regarding Hardware Security Byte (HSB),

default setting, XRAM selected.

ALE Output bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2

mode is used) (default). Set, ALE is active only during a MOVX or MOVC instruction is

used.

AO

Reset Value = XX00 10’HSB. XRAM’0b

Not bit addressable

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23. EEPROM Data Memory

This feature is available only for the AT89C51ED2 device.

The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the

XRAM/ERAM memory space and is selected by setting control bits in the EECON register.

A read or write access to the EEPROM memory is done with a MOVX instruction.

23.1 Write Data

Data is written by byte to the EEPROM memory block as for an external RAM memory.

The following procedure is used to write to the EEPROM memory:

• Check EEBUSY flag

• If the user application interrupts routines use XRAM memory space: Save and disable

interrupts.

• Load DPTR with the address to write

• Store A register with the data to be written

• Set bit EEE of EECON register

• Execute a MOVX @DPTR, A

• Clear bit EEE of EECON register

• Restore interrupts.

• EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress

and that the EEPROM segment is not available for reading or writing.

• The end of programming is indicated by a hardware clear of the EEBUSY flag.

Figure 23-1 represents the optimal write sequence to the on-chip EEPROM data memory.

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Figure 23-1. Recommended EEPROM Data Write Sequence

EEPROM Data Write

Sequence

EEBusy

Cleared?

Save & Disable IT

EA= 0

EEPROM Data Mapping

EECON = 02h (EEE=1)

Data Write

DPTR= Address

ACC= Data

Exec: MOVX @DPTR, A

EEPROM Mapping

EECON = 00h (EEE=0)

Restore IT

Last Byte

to Load?

23.2 Read Data

The following procedure is used to read the data stored in the EEPROM memory:

• Check EEBUSY flag

• If the user application interrupts routines use XRAM memory space: Save and disable

interrupts.

• Load DPTR with the address to read

• Set bit EEE of EECON register

• Execute a MOVX A, @DPTR

• Clear bit EEE of EECON register

• Restore interrupts.

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Figure 23-2. Recommended EEPROM Data Read Sequence

EEPROM Data Read

Sequence

EEBusy

Cleared?

Save & Disable IT

EA= 0

EEPROM Data Mapping

EECON = 02h (EEE=1)

Data Read

DPTR= Address

ACC= Data

Exec: MOVX A, @DPTR

Last Byte

to Read?

EEPROM Data Mapping

EECON = 00h (EEE = 0

Restore IT

23.3 Registers

Table 23-1. EECON Register

EECON (0D2h)

EEPROM Control Register

7

-

6

-

5

-

4

-

3

-

2

-

1

0

EEE

EEBUSY

Bit

Bit Number

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

7 - 2

-

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Bit

Bit Number

Mnemonic Description

Enable EEPROM Space bit

Set to map the EEPROM space during MOVX instructions (Write or Read to the

EEPROM.

1

EEE

Clear to map the XRAM space during MOVX.

Programming Busy flag

Set by hardware when programming is in progress.

Cleared by hardware when programming is done.

Can not be set or cleared by software.

0

EEBUSY

Reset Value = XXXX XX00b

Not bit addressable

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24. Flash/EEPROM Memory

The Flash memory increases EEPROM and ROM functionality with in-circuit electrical erasure

and programming. It contains 64K bytes of program memory organized respectively in 512

pages of 128 bytes. This memory is both parallel and serial In-System Programmable (ISP). ISP

allows devices to alter their own program memory in the actual end product under software con-

trol. A default serial loader (bootloader) program allows ISP of the Flash.

The programming does not require external dedicated programming voltage. The necessary

high programming voltage is generated on-chip using the standard V_CCpins of the

microcontroller.

24.1 Features

• Flash EEPROM Internal Program Memory

• Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory

space. This configuration provides flexibility to the user.

• Default loader in Boot ROM allows programming via the serial port without the need of a user

provided loader.

• Up to 64K bytes external program memory if the internal program memory is disabled (EA =

0).

• Programming and erasing voltage with standard power supply

• Read/Programming/Erase:

– Byte-wise read without wait state

– Byte or page erase and programming (10 ms)

• Typical programming time (64K bytes) is 22s with on chip serial bootloader

• Parallel programming with 87C51 compatible hardware interface to programmer

• Programmable security for the code in the Flash

• 100K write cycles

• 10 years data retention

24.2 Flash Programming and Erasure

The 64-K byte Flash is programmed by bytes or by pages of 128 bytes. It is not necessary to

erase a byte or a page before programming. The programming of a byte or a page includes a

self erase before programming.

There are three methods of programming the Flash memory:

1. The on-chip ISP bootloader may be invoked which will use low level routines to pro-

gram the pages. The interface used for serial downloading of Flash is the UART.

2. The Flash may be programmed or erased in the end-user application by calling low-

level routines through a common entry point in the Boot ROM.

3. The Flash may be programmed using the parallel method by using a conventional

EPROM programmer. The parallel programming method used by these devices is simi-

lar to that used by EPROM 87C51 but it is not identical and the commercially available

programmers need to have support for the AT89C51RD2/ED2. The bootloader and the

Application Programming Interface (API) routines are located in the BOOT ROM.

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24.3 Flash Registers and Memory Map

The AT89C51RD2/ED2 Flash memory uses several registers for its management:

• Hardware register can only be accessed through the parallel programming modes which are

handled by the parallel programmer.

• Software registers are in a special page of the Flash memory which can be accessed through

the API or with the parallel programming modes. This page, called "Extra Flash Memory", is

not in the internal Flash program memory addressing space.

24.3.1

Hardware Register

The only hardware register of the AT89C51RD2/ED2 is called Hardware Byte or Hardware

Security Byte (HSB).

Table 24-1. Hardware Security Byte (HSB)

7

6

5

-

4

-

3

2

1

0

X2

BLJB

XRAM

LB2

LB1

LB0

Bit

Number

Bit

Mnemonic Description

X2 Mode

Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset.

7

X2

Unprogrammed (‘1’ Value) to force X1 mode, Standard Mode, after reset (Default).

Boot Loader Jump Bit

6

BLJB

Unprogrammed (‘1’ value) to start the user’s application on next reset at address 0000h.

Programmed (‘0’ value) to start the boot loader at address F800h on next reset (Default).

5

4

-

Reserved

XRAM config bit (only programmable by programmer tools)

Programmed to inhibit XRAM.

3

XRAM

Unprogrammed, this bit to valid XRAM (Default).

User Memory Lock Bits (only programmable by programmer tools)

2-0

LB2-0

See Table 24-2

Boot Loader Jump Bit (BLJB)

One bit of the HSB, the BLJB bit, is used to force the boot address:

• When this bit is programmed (‘0’ value) the boot address is F800h.

• When this bit is unprogrammed (‘1’ value) the boot address is 0000h.

By default, this bit is programmed and the ISP is enabled.

24.3.2

Flash Memory Lock Bits

The three lock bits provide different levels of protection for the on-chip code and data when pro-

grammed as shown in Table 24-2.

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Table 24-2. Program Lock Bits

Program Lock Bits

Security

Level

LB0

LB1

LB2 Protection Description

1

U

No program lock features enabled.

MOVC instruction executed from external program memory is disabled from

fetching code bytes from internal memory, EA is sampled and latched on reset,

and further parallel programming of the on chip code memory is disabled.

2

P

U

ISP and software programming with API are still allowed.

Same as 2, also verify code memory through parallel programming interface is

disabled.

3

4

X

P

X

U

P

Same as 3, also external execution is disabled (Default).

Note:

U: Unprogrammed or "one" level.

P: Programmed or "zero" level.

X: Do not care

WARNING: Security level 2 and 3 should only be programmed after Flash and code verification.

These security bits protect the code access through the parallel programming interface. They

are set by default to level 4. The code access through the ISP is still possible and is controlled

by the "software security bits" which are stored in the extra Flash memory accessed by the ISP

firmware.

To load a new application with the parallel programmer, a chip erase must first be done. This will

set the HSB in its inactive state and will erase the Flash memory. The part reference can always

be read using Flash parallel programming modes.

24.3.3

Default Values

The default value of the HSB provides parts ready to be programmed with ISP:

• BLJB: Programmed force ISP operation.

• X2: Unprogrammed to force X1 mode (Standard Mode).

• XRAM: Unprogrammed to valid XRAM

• LB2-0: Security level four to protect the code from a parallel access with maximum security.

24.3.4

Software Registers

Several registers are used in factory and by parallel programmers. These values are used by

Atmel ISP.

These registers are in the "Extra Flash Memory" part of the Flash memory. This block is also

called "XAF" or eXtra Array Flash. They are accessed in the following ways:

• Commands issued by the parallel memory programmer.

• Commands issued by the ISP software.

• Calls of API issued by the application software.

Several software registers are described in Table 24-3.

Table 24-3.

Default Values

Mnemonic Definition

SBV Software Boot Vector

Default value

Description

FCh

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Mnemonic Definition

Default value

0FFh

Description

BSB

SSB

Boot Status Byte

Software Security Byte

FFh

Copy of the Manufacturer Code

Copy of the Device ID #1: Family Code

58h

Atmel

D7h

C51 X2, Electrically Erasable

AT89C51RD2/ED2 64KB

Copy of the Device ID #2: Memories Size and

Type

ECh

EFh

AT89C51RD2/ED2 64KB,

Revision 0

Copy of the Device ID #3: Name and Revision

After programming the part by ISP, the BSB must be cleared (00h) in order to allow the applica-

tion to boot at 0000h.

The content of the Software Security Byte (SSB) is described in Table 24-4 and Table 24-5.

To assure code protection from a parallel access, the HSB must also be at the required level.

Table 24-4. Software Security Byte

7

-

6

-

5

-

4

-

3

-

2

-

1

0

LB1

LB0

Bit

Number

Mnemonic Description

Reserved

Do not clear this bit.

7

6

-

Reserved

-

Do not clear this bit.

Reserved

Do not clear this bit.

5

-

Reserved

Do not clear this bit.

4

-

Reserved

3

-

Do not clear this bit.

Reserved

Do not clear this bit.

2

User Memory Lock Bits

See Table 24-5

1-0

LB1-0

The two lock bits provide different levels of protection for the on-chip code and data, when pro-

grammed as shown in Table 24-5.

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Table 24-5.

User Memory Lock Bits of the SSB

Program Lock Bits

Security

Level

LB0

1

LB1

Protection Description

1

2

3

1

0

No program lock features enabled.

ISP programming of the Flash is disabled.

0

X

Same as 2, also verify through ISP programming interface is disabled.

Note:

X: Do not care

WARNING: Security level 2 and 3 should only be programmed after Flash verification.

24.4 Flash Memory Status

AT89C51RD2/ED2 parts are delivered in standard with the ISP ROM bootloader.

After ISP or parallel programming, the possible contents of the Flash memory are summarized in

Figure 24-1:

Figure 24-1. Flash Memory Possible Contents

FFFFh

Virgin

or

Application

Virgin

or

Application

Virgin

Application

Virgin

or

Application

Dedicated

ISP

Dedicated

ISP

0000h

After Parallel After Parallel

Programming Programming

After Parallel

Programming

After ISP

Default

After ISP

24.5 Memory Organization

When the EA pin is high, the processor fetches instructions from internal program Flash. If the

EA pin is tied low, all program memory fetches are from external memory.

24.6 Bootloader Architecture

24.6.1

Introduction

The bootloader manages communication according to a specifically defined protocol to provide

the whole access and service on Flash memory. Furthermore, all accesses and routines can be

called from the user application.

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Figure 24-2. Diagram Context Description

Access Via

Specific

Protocol

Flash Memory

Bootloader

Access From

User

Application

24.6.2

Acronyms

ISP: In-System Programming

SBV: Software Boot Vector

BSB: Boot Status Byte

SSB: Software Security Byte

HW: Hardware Byte

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24.6.3

Functional Description

Figure 24-3. Bootloader Functional Description

External Host with

Specific Protocol

Communication

User

Application

User Call

Management (API)

ISP Communication

Management

Flash Memory

Management

Flash

Memory

On the above diagram, the on-chip bootloader processes are:

• ISP Communication Management

The purpose of this process is to manage the communication and its protocol between the on-

chip bootloader and a external device. The on-chip ROM implements a serial protocol (see sec-

tion “Bootloader Protocol”). This process translate serial communication frame (UART) into

Flash memory access (read, write, erase, etc.).

• User Call Management

Several Application Program Interface (API) calls are available for use by an application pro-

gram to permit selective erasing and programming of Flash pages. All calls are made through a

common interface (API calls), included in the ROM bootloader. The programming functions are

selected by setting up the microcontroller’s registers before making a call to a common entry

point (0xFFF0). Results are returned in the registers. The purpose on this process is to translate

the registers values into internal Flash Memory Management.

• Flash Memory Management

This process manages low level access to Flash memory (performs read and write access).

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24.6.4

Bootloader Functionality

The bootloader can be activated by two means: Hardware conditions or regular boot process.

The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the on-chip

bootloader execution. This allows an application to be built that will normally execute the end

user’s code but can be manually forced into default ISP operation.

As PSEN is a an output port in normal operating mode after reset, user application should take

care to release PSEN after falling edge of reset signal. The hardware conditions are sampled at

reset signal falling edge, thus they can be released at any time when reset input is low.

To ensure correct microcontroller startup, the PSEN pin should not be tied to ground during

power-on (See Figure 24-4).

Figure 24-4. Hardware conditions typical sequence during power-on.

VCC

PSEN

RST

The on-chip bootloader boot process is shown Figure 24-5.

Table 24-6. Bootloader Process Description

Purpose

The Hardware Conditions force the bootloader execution whatever BLJB,

Hardware Conditions

BSB and SBV values.

The Boot Loader Jump Bit forces the application execution.

BLJB = 0 => Bootloader execution

BLJB = 1 => Application execution

The BLJB is a fuse bit in the Hardware Byte.

BLJB

It can be modified by hardware (programmer) or by software (API).

Note: The BLJB test is performed by hardware to prevent any program

execution.

The Software Boot Vector contains the high address of customer bootloader

stored in the application.

SBV

SBV = FCh (default value) if no customer bootloader in user Flash.

Note: The customer bootloader is called by JMP [SBV]00h instruction.

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24.6.5

Boot Process

Figure 24-5. Bootloader Process

RESET

If BLJB = 0 then ENBOOT Bit (AUXR1) is Set

else ENBOOT Bit (AUXR1) is Cleared

Yes (PSEN = 0, EA = 1, and ALE =1 or Not Connected)

Hardware

Condition?

BLJB = 1

ENBOOT = 0

BLJB!= 0

?

BLJB = 0

ENBOOT = 1

BSB = 00h

?

PC = 0000h

User Application

SBV = FCh

?

USER BOOT LOADER

Atmel BOOT LOADER

PC= [SBV]00h

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24.7 ISP Protocol Description

24.7.1

Physical Layer

The UART used to transmit information has the following configuration:

• Character: 8-bit data

• Parity: none

• Stop: 2 bits

• Flow control: none

• Baudrate: autobaud is performed by the bootloader to compute the baudrate chosen by the

host.

24.7.2

Frame Description

The Serial Protocol is based on the Intel Hex-type records.

Intel Hex records consist of ASCII characters used to represent hexadecimal values and are

summarized below.

Figure 24-6. Intel Hex Type Frame

Data

or

Info

Record

Mark

’:’

Load

Offset

Record

Type

Checksum

1-byte

Reclen

1-byte

2-bytes

n-bytes

1-byte

• Record Mark:

Record Mark is the start of frame. This field must contain ’:’.

• Reclen:

Reclen specifies the number of bytes of information or data which follows the Record Type field

of the record.

• Load Offset:

Load Offset specifies the 16-bit starting load offset of the data bytes, therefore this field is used

only for Data Program Record (see Section “ISP Commands Summary”).

• Record Type:

Record Type specifies the command type. This field is used to interpret the remaining informa-

tion within the frame. The encoding for all the current record types is described in Section “ISP

Commands Summary”.

• Data/Info:

Data/Info is a variable length field. It consists of zero or more bytes encoded as pairs of hexa-

decimal digits. The meaning of data depends on the Record Type.

• Checksum:

The two’s complement of the 8-bit bytes that result from converting each pair of ASCII hexadec-

imal digits to one byte of binary, and including the Reclen field to and including the last byte of

the Data/Info field. Therefore, the sum of all the ASCII pairs in a record after converting to

binary, from the Reclen field to and including the Checksum field, is zero.

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24.8 Functional Description

24.8.1

Software Security Bits (SSB)

The SSB protects any Flash access from ISP command.

The command "Program Software Security Bit" can only write a higher priority level.

There are three levels of security:

• level 0: NO_SECURITY (FFh)

This is the default level.

From level 0, one can write level 1 or level 2.

• level 1: WRITE_SECURITY (FEh)

For this level it is impossible to write in the Flash memory, BSB and SBV.

The Bootloader returns ’P’ on write access.

From level 1, one can write only level 2.

• level 2: RD_WR_SECURITY (FCh

The level 2 forbids all read and write accesses to/from the Flash/EEPROM memory.

The Bootloader returns ’L’ on read or write access.

Only a full chip erase in parallel mode (using a programmer) or ISP command can reset the soft-

ware security bits.

From level 2, one cannot read and write anything.

Table 24-7. Software Security Byte Behavior

Level 0

Any access allowed

Read-only access allowed

Allowed

Level 1

Level 2

Flash/EEPROM

Fuse Bit

Read-only access allowed

Write level 2 allowed

Read-only access allowed

Not allowed

Any access not allowed

Read-only access allowed

Not allowed

BSB & SBV

SSB

Manufacturer Info

Bootloader Info

Erase Block

Full Chip Erase

Blank Check

Allowed

24.8.2

Full Chip Erase

The ISP command "Full Chip Erase" erases all user Flash memory (fills with FFh) and sets

some bytes used by the bootloader at their default values:

• BSB = FFh

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• SBV = FCh

• SSB = FFh

The Full Chip Erase does not affect the bootloader.

24.8.3

Checksum Error

When a checksum error is detected, send ‘X’ followed with CR&LF.

24.9 Flow Description

24.9.1

Overview

An initialization step must be performed after each Reset. After microcontroller reset, the boot-

loader waits for an autobaud sequence (see section ‘Autobaud Performances’).

When the communication is initialized, the protocol depends on the record type requested by the

host.

FLIP, a software utility to implement ISP programming with a PC, is available from the Atmel

web site.

24.9.2

Communication Initialization

The host initializes the communication by sending a ’U’ character to help the bootloader to com-

pute the baudrate (autobaud).

Figure 24-7. Initialization

Bootloader

Host

Init Communication

"U"

Performs Autobaud

Sends Back “U” Characte

If (Not Received "U")

Else

Communication Opened

24.9.3

Autobaud Performances

The ISP feature allows a wide range of baud rates in the user application. It is also adaptable to

a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single

bit in a received character. This information is then used to program the baud rate in terms of

timer counts based on the oscillator frequency. The ISP feature requires that an initial character

(an uppercase U) be sent to the AT89C51RD2/ED2 to establish the baud rate. Table show the

autobaud capability.

Table 24-8. Autobaud Performances

Frequency

(MHz)

Baudrate (kHz)

1.8432

2

2.4576

3

3.6864

4

5

6

7.3728

2400

OK

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Table 24-8. Autobaud Performances (Continued)

Frequency

(MHz)

Baudrate (kHz)

1.8432

2

-

2.4576

OK

-

3

3.6864

OK

-

4

5

OK

-

6

OK

-

7.3728

OK

4800

OK

-

OK

9600

OK

19200

-

OK

38400

OK

-

OK

57600

-

OK

115200

-

OK

Frequency

(MHz)

Baudrate (kHz)

8

OK

-

10

OK

-

11.0592

OK

12

OK

-

14.746

OK

16

OK

-

20

OK

-

24

OK

-

26.6

OK

-

2400

4800

OK

9600

OK

19200

OK

38400

OK

57600

-

OK

115200

-

OK

-

OK

24.9.4

Command Data Stream Protocol

All commands are sent using the same flow. Each frame sent by the host is echoed by the

bootloader.

Figure 24-8. Command Flow

Host

Bootloader

":"

If (not received ":")

Sends First Character of the

Frame

Else

Sends Echo and Start

Reception

Sends Frame (made of 2 ASCII

Characters Per Byte)

Echo Analysis

Gets Frame, and Sends Back Echo

for Each Received Byte

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24.9.5

Write/Program Commands Description

This flow is common to the following frames:

• Flash/EEPROM Programming Data Frame

• EOF or Atmel Frame (only Programming Atmel Frame)

• Config Byte Programming Data Frame

• Baud Rate Frame

Figure 24-9. Write/Program Flow

Bootloader

Host

Write Command

’X’ & CR & LF

Send Write Command

Wait Write Command

OR

Checksum Error

Wait Checksum Error

Send Checksum Error

COMMAND ABORTED

NO_SECURITY

OR

’P’ & CR & LF

’.’ & CR & LF

Wait Security Error

Send Security Error

COMMAND ABORTED

Wait Programming

Wait COMMAND_OK

COMMAND FINISHED

Send COMMAND_OK

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24.9.5.1

Example

Programming Data (write 55h at address 0010h in the Flash)

HOST

BOOTLOADER

: 01 0010 00 55 9A

: 01 0010 00 55 9A . CR LF

Programming Atmel function (write SSB to level 2)

HOST

: 02 0000 03 05 01 F5

BOOTLOADER

: 02 0000 03 05 01 F5. CR LF

Writing Frame (write BSB to 55h)

HOST

: 03 0000 03 06 00 55 9F

: 03 0000 03 06 00 55 9F . CR LF

BOOTLOADER

24.9.6

Blank Check Command Description

Figure 24-10. Blank Check Flow

Bootloader

Host

Blank Check Command

Send Blank Check Command

Wait Blank Check Command

OR

Checksum Error

’X’ & CR & LF

Wait Checksum Error

Send Checksum Error

COMMAND ABORTED

Flash Blank

’.’ & CR & LF

Wait COMMAND_OK

COMMAND FINISHED

OR

Send COMMAND_OK

address & CR & LF

Send First Address

not Erased

Wait Address not

Erased

COMMAND FINISHED

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24.9.6.1

Example

Blank Check ok

HOST

: 05 0000 04 0000 7FFF 01 78

BOOTLOADER

: 05 0000 04 0000 7FFF 01 78 . CR LF

Blank Check ok at address xxxx

HOST

: 05 0000 04 0000 7FFF 01 78

: 05 0000 04 0000 7FFF 01 78 xxxx CR LF

BOOTLOADER

Blank Check with checksum error

HOST

: 05 0000 04 0000 7FFF 01 70

: 05 0000 04 0000 7FFF 01 70 X CR LF CR LF

BOOTLOADER

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24.9.7

Display Data Description

Figure 24-11. Display Flow

Bootloader

Host

Display Command

’X’ & CR & LF

Send Display Command

Wait Display Command

OR

Checksum error

Wait Checksum Error

Send Checksum Error

COMMAND ABORTED

RD_WR_SECURITY

OR

’L’ & CR & LF

Wait Security Error

Send Security Error

COMMAND ABORTED

Read Data

All Data Read

Complet Frame

"Address = "

"Reading Value"

CR & LF

Wait Display Data

Send Display Data

All Data Read

COMMAND FINISHED

24.9.7.1

Example

Display data from address 0000h to 0020h

HOST

: 05 0000 04 0000 0020 00 D7

BOOTLOADER : 05 0000 04 0000 0020 00 D7

BOOTLOADER 0000=-----data------ CR LF (16 data)

BOOTLOADER 0010=-----data------ CR LF (16 data)

BOOTLOADER 0020=data CR LF

( 1 data)

24.9.8

Read Function Description

This flow is similar for the following frames:

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• Reading Frame

• EOF Frame/ Atmel Frame (only reading Atmel Frame)

Figure 24-12. Read Flow

Bootloader

Host

Read Command

Send Read Command

Wait Read Command

OR

Checksum error

’X’ & CR & LF

Wait Checksum Error

Send Checksum error

COMMAND ABORTED

RD_WR_SECURITY

OR

’L’ & CR & LF

Wait Security Error

Send Security error

COMMAND ABORTED

Read Value

’value’ & ’.’ & CR & LF

Wait Value of Data

Send Data Read

COMMAND FINISHED

24.9.8.1

Example

Read function (read SBV)

HOST : 02 0000 05 07 02 F0

BOOTLOADER : 02 0000 05 07 02 F0 Value . CR LF

Atmel Read function (read Bootloader version)

HOST

: 02 0000 01 02 00 FB

BOOTLOADER : 02 0000 01 02 00 FB Value . CR LF

24.9.9

ISP Commands Summary

Table 24-9. ISP Commands Summary

Command

Command Name

Data[0]

Data[1]

Command Effect

Program Nb Code Byte.

00h

Program Code

Bootloader will accept up to 128 (80h) data bytes. The data

bytes should be 128 byte page flash boundary.

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Table 24-9. ISP Commands Summary (Continued)

Command

Command Name

Data[0]

Data[1]

00h

20h

40h

80h

C0h

00h

01h

00h

01h

Command Effect

Erase block0 (0000h-1FFFh)

Erase block1 (2000h-3FFFh)

Erase block2 (4000h-7FFFh)

Erase block3 (8000h- BFFFh)

Erase block4 (C000h- FFFFh)

Hardware Reset

01h

03h

04h

Erase SBV & BSB

Program SSB level 1

03h

Write Function

05h

Program SSB level 2

Program BSB (value to write in data[2])

Program SBV (value to write in data[2])

06h

07h

Full Chip Erase (This command needs about 6 sec to be

executed)

-

0Ah

04h

08h

Program BLJB fuse (value to write in data[2])

Program X2 fuse (value to write in data[2])

Display Code

Data[0:1] = start address

Data [2:3] = end address

Data[4] = 00h:Display Code

Data[4] = 01h: Blank check

Data[4] = 02h: Display EEPROM

Blank Check

04h

Display Function

Display EEPROM data

00h

Manufacturer Id

Device Id #1

01h

00h

02h

Device Id #2

03h

00h

Device Id #3

Read SSB

01h

Read BSB

05h

Read Function

07h

02h

Read SBV

06h

Read Extra Byte

Read Hardware Byte

Read Device Boot ID1

Read Device Boot ID2

Read Bootloader Version

0Bh

0Eh

0Fh

00h

01h

00h

Program Nn EEprom Data Byte.

07h

Program EEPROM data

Bootloader will accept up to 128 (80h) data bytes.

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24.10 API Call Description

The IAP allows to reprogram a microcontroller on-chip Flash memory without removing it from

the system and while the embedded application is running.

The user application can call some Application Programming Interface (API) routines allowing

IAP. These API are executed by the bootloader.

To call the corresponding API, the user must use a set of Flash_api routines which can be linked

with the application.

Example of Flash_api routines are available on the Atmel web site on the software application

note:

C Flash Drivers for the AT89C51RD2/ED2

The API calls description and arguments are shown in Table 24-10.

24.10.1 Process

The application selects an API by setting R1, ACC, DPTR0 and DPTR1 registers.

All calls are made through a common interface “USER_CALL” at the address FFF0h.

The jump at the USER_CALL must be done by LCALL instruction to be able to comeback in the

application.

Before jump at the USER_CALL, the bit ENBOOT in AUXR1 register must be set.

24.10.2 Constraints

The interrupts are not disabled by the bootloader.

Interrupts must be disabled by user prior to jump to the USER_CALL, then re-enabled when

returning.

Interrupts must also be disabled before accessing EEPROM Data then re-enabled after.

The user must take care of hardware watchdog before launching a Flash operation.

Table 24-10. API Call Summary

Command

R1

A

DPTR0

0000h

DPTR1

XXh

Returned Value

ACC = Manufacturer Id

ACC = Device Id 1

ACC = Device Id 2

ACC = Device Id 3

Command Effect

Read Manufacturer identifier

Read Device identifier 1

Read Device identifier 2

Read Device identifier 3

Erase block 0

READ MANUF ID

READ DEVICE ID1

READ DEVICE ID2

READ DEVICE ID3

00h

XXh

0001h

XXh

0002h

XXh

0003h

XXh

DPH = 00h

DPH = 20h

DPH = 40h

DPH = 80h

DPH = C0h

Erase block 1

ERASE BLOCK

01h

XXh

00h

ACC = DPH

Erase block 2

Erase block 3

Erase block 4

Address of

byte to

program

Program up one data byte in the on-chip

flash memory.

PROGRAM DATA BYTE 02h Vaue to write

XXh

ACC = 0: DONE

112

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Table 24-10. API Call Summary (Continued)

Command

R1

A

DPTR0

DPTR1

Returned Value

Command Effect

DPH = 00h

DPL = 00h

Set SSB level 1

DPH = 00h

DPL = 01h

Set SSB level 2

Set SSB level 0

PROGRAM SSB

05h

XXh

00h

ACC = SSB value

DPH = 00h

DPL = 10h

DPH = 00h

DPL = 11h

Set SSB level 1

New BSB

value

PROGRAM BSB

PROGRAM SBV

06h

0000h

0001h

XXh

none

Program boot status byte

Program software boot vector

New SBV

value

READ SSB

READ BSB

READ SBV

07h

XXh

0000h

0001h

0002h

XXh

ACC = SSB

ACC = BSB

ACC = SBV

Read Software Security Byte

Read Boot Status Byte

Read Software Boot Vector

Program up to 128 bytes in user Flash.

Address of

the first byte

to program in

the Flash

Address in

XRAM of the

first data to

program

Number of

byte to

program

Remark: number of bytes to program is

limited such as the Flash write remains in a

single 128 bytes page. Hence, when ACC is

128, valid values of DPL are 00h, or, 80h.

ACC = 0: DONE

PROGRAM DATA PAGE 09h

memory

Fuse value

00h or 01h

PROGRAM X2 FUSE

0Ah

0008h

0004h

XXh

none

Program X2 fuse bit with ACC

Program BLJB fuse bit with ACC

Fuse value

00h or 01h

PROGRAM BLJB FUSE 0Ah

READ HSB

0Bh

0Eh

XXh

XXXXh

DPL = 00h

DPL = 01h

XXXXh

XXh

ACC = HSB

ACC = ID1

Read Hardware Byte

Read boot ID1

READ BOOT ID1

READ BOOT ID2

ACC = ID2

Read boot ID2

READ BOOT VERSION 0Fh

ACC = Boot_Version

Read bootloader version

113

4235K–8051–05/08

25.

Electrical Characteristics

25.1 Absolute Maximum Ratings

Note:

Stresses at or above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other condi-

tions above those indicated in the operational

sections of this specification is not implied. Exposure

to absolute maximum rating conditions may affect

device reliability.

I = industrial ........................................................-40

Storage Temperature.................................... -65

°

C to 85

°C to + 150

°

C

Voltage on V_CCto V_SS......................................-0.5V to + 6.5V

VVoltage on Any Pin to V_SS.......................-0.5V to V_CC+ 0.5V

Power Dissipation........................................................... 1 W⁽²⁾

Power dissipation is based on the maximum allow-

able die temperature and the thermal resistance of

the package.

25.2 DC Parameters for Standard Voltage

T_A= -40°C to +85°C; V_SS= 0V;

V_CC=2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)

V_CC=4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only)

Symbol

V_IL

Parameter

Min

-0.5

Typ

Max

Unit Test Conditions

Input Low Voltage

0.2 V_CC- 0.1

V_CC+ 0.5

V

V_IH

Input High Voltage except RST, XTAL1

Input High Voltage RST, XTAL1

0.2 V_CC+ 0.9

0.7 V_CC

V

V_IH1

V

V_CC= 4.5V to 5.5V

0.3

0.45

1.0

V

I_OL= 100 µ

A⁽⁴⁾

I_OL= 1.6 mA⁽⁴⁾

I_OL= 3.5 mA⁽⁴⁾

V_OL

Output Low Voltage, ports 1, 2, 3, 4 ⁽⁶⁾

V_CC= 2.7V to 5.5V

I_OL= 0.8 mA⁽⁴⁾

0.45

V

V_CC= 4.5V to 5.5V

0.3

0.45

1.0

V

I_OL= 200 µ

A⁽⁴⁾

I_OL= 3.2 mA⁽⁴⁾

I_OL= 7.0 mA⁽⁴⁾

V_OL1

Output Low Voltage, port 0, ALE, PSEN ⁽⁶⁾

V_CC= 2.7V to 5.5V

I_OL= 1.6 mA⁽⁴⁾

0.45

V

V_CC= 5V 10%

V_CC- 0.3

V_CC- 0.7

V_CC- 1.5

V

I_OH= -10

I_OH= -30

I_OH= -60

µ

A

V_OH

Output High Voltage, ports 1, 2, 3, 4

V_CC= 2.7V to 5.5V

I_OH= -10

0.9 V_CC

V

µA

114

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

T_A= -40°C to +85°C; V_SS= 0V;

V_CC=2.7V to 5.5V and F = 0 to 40 MHz (both internal and external code execution)

V_CC=4.5V to 5.5V and F = 0 to 60 MHz (internal code execution only) (Continued)

Symbol

Parameter

Min

Typ

Max

Unit Test Conditions

V_CC= 5V 10%

V_CC- 0.3

V_CC- 0.7

V_CC- 1.5

V

I_OH= -200 µA

I_OH= -3.2 mA

I_OH= -7.0 mA

V_OH1

Output High Voltage, port 0, ALE, PSEN

V_CC= 2.7V to 5.5V

0.9 V_CC

50

V

I_OH= -10 µA

R_RST

I_IL

RST Pull-down Resistor

200⁽⁵⁾

250

-50

kΩ

Logical 0 Input Current ports 1, 2, 3, 4 and 5

Input Leakage Current

µ

A

V_IN= 0.45V

I_LI

10

0.45V < V_IN< V_CC

V_IN= 2.0V

I_TL

Logical 1 to 0 Transition Current, ports 1, 2, 3, 4

-650

F_C= 3 MHz

T_A= 25°C

C_IO

Capacitance of I/O Buffer

10

pF

I_PD

Power-down Current

75

150

µ

A

2.7 < V_{CC <}5.5V⁽³⁾

V_CC= 5.5V⁽¹⁾

V_CC= 5.5V⁽²⁾

V_CC= 5.5V

I_CCOP

Power Supply Current on normal mode

Power Supply Current on idle mode

Power Supply Current on flash or EEdata write

Flash or EEdata programming time

Internal POR/PFD VPFDP threshold

Internal POR/PFD VPFDM threshold

Internal POR/PFD Hysteresys

0.4 x Frequency (MHz) + 5

mA

ms

V

I_CCIDLE

I_CCWRITE

t_WRITE

0.3 x Frequency (MHz) + 5

0.8 x Frequency (MHz) + 15

7

17

2.7 < V_{CC <}5.5V

VPFDP

VPFDM

Vhyst

2.25

2.15

70

2.5

2.35

140

2.69

2.62

250

V

mV

Vcc

Maximum Vcc Power supply slew rate⁽⁷⁾

0.1

V/µs

dV/dt

Notes: 1. Operating I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns (see Figure 25-4), V_IL=

V_SS+ 0.5V, V_IH= V_CC- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V_CC. I_CCwould be slightly higher if a crystal oscillator used

(see Figure 25-1).

2. Idle I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns, V_IL= V_SS+ 0.5V, V_IH= V_CC

0.5V; XTAL2 N.C; Port 0 = V_CC; EA = RST = V_SS(see Figure 25-2).

-

3. Power-down I_CCis measured with all output pins disconnected; EA = V_SS, PORT 0 = V_CC; XTAL2 NC.; RST = V_SS(see Fig-

ure 25-3).

4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_OLSof ALE and Ports 1

and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0

transitions during bus operation. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed

0.45V with maxi V_OLpeak 0.6V. A Schmitt Trigger use is not necessary.

5. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature

and 5V.

6. Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

Maximum I_OLper port pin: 10 mA

Maximum I_OLper 8-bit port:

115

4235K–8051–05/08

Port 0: 26 mA

Ports 1, 2 and 3: 15 mA

Maximum total I_OLfor all output pins: 71 mA

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

7. The maximum dV/dt value specifies the maximum Vcc drop to issure no internal POR/PFD reset.

Figure 25-1. I_CCTest Condition, Active Mode

V_CC

I_CC

V_CC

P0

V_CC

RST

EA

XTAL2

XTAL1

(NC)

CLOCK

SIGNAL

V_SS

All other pins are disconnected.

Figure 25-2. I_CCTest Condition, Idle Mode

V_CC

I_CC

V_CC

P0

RST

EA

(NC)

CLOCK

SIGNAL

XTAL2

XTAL1

V_SS

Figure 25-3. I_CCTest Condition, Power-down Mode

V_CC

I_CC

V_CC

P0

RST

EA

(NC)

XTAL2

XTAL1

V_SS

116

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Figure 25-4. Clock Signal Waveform for I_CCTests in Active and Idle Modes

V_CC-0.5V

0.7V_CC

0.2V_CC-0.1

0.45V

T_CHCL

T_CLCH

T_CLCH= T_CHCL= 5ns.

25.3 AC Parameters

25.3.1

Explanation of the AC Symbols

Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The

other characters, depending on their positions, stand for the name of a signal or the logical sta-

tus of that signal. The following is a list of all the characters and what they stand for.

Example:T_AVLL= Time for Address Valid to ALE Low.

T_LLPL= Time for ALE Low to PSEN Low.

(Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other outputs =

80 pF.)

Table 25-1 Table 25-4, and Table 25-7 give the description of each AC symbols.

Table 25-2, Table 25-3, Table 25-5 and Table 25-8 gives the range for each AC parameter.

Table 25-2, Table 25-3 and Table 25-9 give the frequency derating formula of the AC parameter

for each speed range description. To calculate each AC symbols. take the x value in the corre-

ponding column (-M) and use this value in the formula.

Example: T_LLIUfor -M and 20 MHz, Standard clock.

x = 35 ns

T 50 ns

T

_CCIV= 4T - x = 165 ns

117

4235K–8051–05/08

25.3.2

External Program Memory Characteristics

Table 25-1. Symbol Description

Symbol

T

Parameter

Oscillator clock period

T_LHLL

T_AVLL

T_LLAX

T_LLIV

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_AVIV

T_PLAZ

ALE pulse width

Address Valid to ALE

Address Hold After ALE

ALE to Valid Instruction In

ALE to PSEN

PSEN Pulse Width

PSEN to Valid Instruction In

Input Instruction Hold After PSEN

Input Instruction Float After PSEN

Address to Valid Instruction In

PSEN Low to Address Float

Table 25-2. AC Parameters for a Fix Clock

Symbol

-M

Units

Min

25

35

5

Max

T

ns

T_LHLL

T_AVLL

T_LLAX

T_LLIV

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_AVIV

T_PLAZ

5

n 65

5

50

30

0

10

80

10

118

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Table 25-3. AC Parameters for a Variable Clock

X parameter for

Symbol

T_LHLL

T_AVLL

T_LLAX

T_LLIV

Type

Min

Standard Clock

X2 Clock

T - x

-M range

Units

ns

2 T - x

T - x

4 T - x

T - x

3 T - x

x

15

20

35

15

25

45

0

Min

0.5 T - x

2 T - x

0.5 T - x

1.5 T - x

x

ns

Min

ns

Max

Min

ns

T_LLPL

T_PLPH

T_PLIV

ns

Min

ns

Max

Min

ns

T_PXIX

T_PXIZ

T_AVIV

ns

Max

T - x

5 T - x

x

0.5 T - x

2.5 T - x

x

15

45

10

ns

T_PLAZ

ns

25.3.3

External Program Memory Read Cycle

12 T_CLCL

T_LHLL

T_LLIV

ALE

PSEN

T_LLPL

T_PLPH

T_PXAV

T_PXIZ

T_LLAX

T_AVLL

T_PLIV

TPLAZ

T_PXIX

PORT 0

PORT 2

INSTR IN

A0-A7

INSTR IN

A0-A7

INSTR IN

T_AVIV

ADDRESS A8-A15

ADDRESS

OR SFR-P2

ADDRESS A8-A15

25.3.4

External Data Memory Characteristics

119

4235K–8051–05/08

Table 25-4. Symbol Description

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Parameter

RD Pulse Width

WR Pulse Width

RD to Valid Data In

Data Hold After RD

Data Float After RD

ALE to Valid Data In

Address to Valid Data In

ALE to WR or RD

T_AVDV

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

Address to WR or RD

Data Valid to WR Transition

Data Set-up to WR High

Data Hold After WR

RD Low to Address Float

RD or WR High to ALE high

T_WHLH

Table 25-5. AC Parameters for a Fix Clock

-M

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Min

Max

Units

ns

125

95

0

25

155

160

105

T_AVDV

T_LLWL

45

70

5

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

155

10

0

T_WHLH

5

45

120

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Table 25-6. AC Parameters for a Variable Clock

Standard

X parameter for

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Type

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Clock

6 T - x

5 T - x

x

X2 Clock

3 T - x

2.5 T - x

x

-M range

Units

ns

25

30

0

2 T - x

8 T - x

9 T - x

3 T - x

3 T + x

4 T - x

T - x

25

4T -x

45

T_AVDV

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

T_WHLH

4.5 T - x

1.5 T - x

1.5 T + x

2 T - x

0.5 T - x

3.5 T - x

0.5 T - x

x

65

30

20

7 T - x

T - x

20

15

x

0

T - x

0.5 T - x

0.5 T + x

20

T + x

20

25.3.5

External Data Memory Write Cycle

T_WHLH

ALE

PSEN

WR

T_LLWL

T_WLWH

T_QVWX

T_WHQX

T_LLAX

A0-A7

T_QVWH

DATA OUT

PORT 0

PORT 2

T_AVWL

ADDRESS

OR SFR-P2

ADDRESS A8-A15 OR SFR P2

121

4235K–8051–05/08

25.3.6

External Data Memory Read Cycle

T_WHLH

T_LLDV

ALE

PSEN

RD

T_LLWL

T_RLRH

T_RHDZ

T_AVDV

T_LLAX

T_RHDX

DATA IN

PORT 0

PORT 2

A0-A7

T_RLAZ

T_AVWL

ADDRESS

OR SFR-P2

ADDRESS A8-A15 OR SFR P2

25.3.7

Serial Port Timing - Shift Register Mode

Table 25-7. Symbol Description

Symbol

T_XLXL

Parameter

Serial port clock cycle time

T_QVHX

T_XHQX

T_XHDX

T_XHDV

Output data set-up to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

Table 25-8. AC Parameters for a Fix Clock

-M

Symbol

T_XLXL

Min

300

200

30

Max

Units

ns

T_QVHX

T_XHQX

T_XHDX

T_XHDV

ns

0

ns

117

ns

122

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Table 25-9. AC Parameters for a Variable Clock

Standard

X Parameter For

Symbol

T_XLXL

Type

Min

Max

Clock

X2 Clock

6 T

-M Range

Units

ns

12 T

T_QVHX

T_XHQX

T_XHDX

T_XHDV

10 T - x

2 T - x

x

5 T - x

T - x

50

20

0

ns

x

ns

10 T - x

5 T- x

133

ns

25.3.8

Shift Register Timing Waveforms

0

1

2

3

4

5

6

7

8

INSTRUCTION

ALE

T_XLXL

CLOCK

T_XHQX

1

T_QVXH

0

2

3

4

5

6

7

OUTPUT DATA

T_XHDX

SET TI

T_XHDV

WRITE to SBUF

INPUT DATA

VALID

SET RI

CLEAR RI

25.3.9

External Clock Drive Waveforms

V_CC-0.5V

0.45V

0.7V_CC

0.2V_CC-0.1

T_CHCX

T_CLCH

T_CLCX

T_CHCL

T_CLCL

25.3.10 AC Testing Input/Output Waveforms

V_CC-0.5V

0.45V

0.2 V_CC+ 0.9

0.2 V_CC- 0.1

INPUT/OUTPUT

AC inputs during testing are driven at V_CC- 0.5 for a logic “1” and 0.45V for a logic “0”. Timing

measurement are made at V_IHmin for a logic “1” and V_ILmax for a logic “0”.

123

4235K–8051–05/08

25.3.11 Float Waveforms

FLOAT

V_LOAD

V_OH- 0.1V

V_OL+ 0.1V

V_LOAD+ 0.1V

_LOAD- 0.1V

V

For timing purposes as port pin is no longer floating when a 100 mV change from load voltage

occurs and begins to float when a 100 mV change from the loaded V_OH/V_OLlevel occurs. I_OL/I_OH

≥

20 mA.

25.3.12 Clock Waveforms

Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.

124

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

Figure 25-5. Internal Clock Signals

STATE4

STATE5

STATE6

P1 P2

STATE1

STATE2

P1 P2

STATE3

P1 P2

STATE4

P1 P2

STATE5

P1 P2

INTERNAL

CLOCK

P1 P2

P1

P2

XTAL2

ALE

THESE SIGNALS ARE NOT ACTIVATED DURING THE

EXECUTION OF A MOVX INSTRUCTION

EXTERNAL PROGRAM MEMORY FETCH

PSEN

P0

DATA

SAMPLED

PCL OUT

DATA

SAMPLED

PCL OUT

DATA

SAMPLED

PCL OUT

FLOAT

P2 (EXT)

INDICATES ADDRESS TRANSITIONS

READ CYCLE

RD

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

DPL OR Rt OUT

DATA

SAMPLED

P0

FLOAT

P2

INDICATES DPH OR P2 SFR TO PCH TRANSITION

WRITE CYCLE

WR

PCL OUT (EVEN IF PROGRAM

MEMORY IS INTERNAL)

DPL OR Rt OUT

P0

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

DATA OUT

P2

INDICATES DPH OR P2 SFR TO PCH TRANSITION

PORT OPERATION

MOV PORT SRC

OLD DATA

NEW DATA

P0 PINS SAMPLED

MOV DEST P0

MOV DEST PORT (P1. P2. P3)

(INCLUDES INTO. INT1. TO T1)

P1, P2, P3 PINS SAMPLED

RXD SAMPLED

P1, P2, P3 PINS SAMPLED

SERIAL PORT SHIFT CLOCK

RXD SAMPLED

TXD (MODE 0)

This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however,

ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propa-

gation also varies from output to output and component. Typically though (T_A= 25°C fully loaded) RD and WR propagation

delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC

specifications.

125

4235K–8051–05/08

26. Ordering Information

Table 26-1. Possible Order Entries

Temperature

Range

Part Number

Data EEPROM

Supply Voltage

Package

PLCC44

VQFP44

VQFP64

PLCC68

PLCC44

VQFP44

PLCC68

VQFP64

Packing

Stick

Tray

Product Marking

AT89C51RD2-UM

AT89C51ED2-UM

AT89C51RD2-SLSUM

AT89C51RD2-RLTUM

AT89C51RD2-RDTUM⁽¹⁾

AT89C51RD2-SMSUM⁽¹⁾

AT89C51ED2-SLSUM

AT89C51ED2-RLTUM

AT89C51ED2- SMSUM

AT89C51ED2-RDTUM

No

Tray

Stick

Tray

Industrial &

Green

2.7V - 5.5V

Yes

Stick

Tray

Note:

1. For PLCC68 and VQFP64 packages, please contact Atmel sales office for availability.

126

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

27. Packaging Information

27.1 PLCC44

127

4235K–8051–05/08

STANDARD NOTES FOR PLCC

1/ CONTROLLING DIMENSIONS : INCHES

2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982.

3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS.

MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER

SIDE.

128

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

27.2 VQFP44

129

4235K–8051–05/08

STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP

1/ CONTROLLING DIMENSIONS : INCHES

2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M -

1982.

3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS.

MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH).

THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM

PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm.

4/ DATUM PLANE "H" LOCATED AT MOLD PARTING LINE AND

COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT

BOTTOM OF PARTING LINE.

5/ DATUM "A" AND "D" TO BE DETERMINED AT DATUM PLANE H.

6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE

DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE

" f " DIMENSION AT MAXIMUM MATERIAL CONDITION .

DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.

130

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

27.3 PLCC68

131

4235K–8051–05/08

27.4 VQFP64

132

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

28. Document Revision History

28.1 Changes from 4235A -04/03 to 4135B - 06/03

1. V_IHmin changed from 0.2 V_CC+ 1.1 to 0.2 V_CC+ 0.9.

2. Added POR/PFD and reset specific sections.

3. Added DIL40 package.

4. Added Flash write programming time specification.

28.2 Changes from 4235B -06/03 to 4235C - 08/03

1. Changed maximum frequency to 60 MHz in X1 mode and 30 MHz in X2 mode for Vcc =

4.5V to 5.5V and internal code execution.

2. Added PDIL40 Packaging for AT89C51ED2.

28.3 Changes from 4235C - 08/03 to 4235D - 12/03

1. Improved explanations throughout the document.

28.4 Changes from 4235D - 12/03 to 4235E - 04/04

1. Improved explanations throughout the document.

28.5 Changes from 4235E - 04/04 to 4235F - 09/04

1. Improved explanations in Flash and EEPROM sections.

28.6 Changes from 4235F - 09/04 to 4235G 08/05

1. Added ‘Industrial & Green” product versions.

28.7 Changes from 4235G 08/05 to 4235H - 10/06

1. Correction to PDIL figure on page 9.

28.8 Changes from 4235H - 10/06 to 4235I - 04/07

1. Removal of PDIL40 package offering.

28.9 Changes from 4235I - 04/07 to 4235J - 01/08

1. Minor corrections throughout the document.

2. Updated Package drawings.

28.10 Changes from 4235J - 01/08 to 4235K - 05/08

1. Removed non-green packages from product ordering information.

133

4235K–8051–05/08

AT89C51RD2/ED2

Features .................................................................................................... 1

Description ............................................................................................... 2

Block Diagram .......................................................................................... 3

SFR Mapping ............................................................................................ 4

Pin Configurations ................................................................................... 9

Port Types .............................................................................................. 14

Oscillator ................................................................................................ 15

1

2

3

4

5

6

6.1

6.2

Registers .........................................................................................................15

Functional Block Diagram ................................................................................16

7

Enhanced Features ................................................................................ 17

7.1

X2 Feature .......................................................................................................17

8

9

Dual Data Pointer Register (DPTR) ...................................................... 21

Expanded RAM (XRAM) ......................................................................... 23

9.1

Registers .........................................................................................................24

10 Reset ....................................................................................................... 26

10.1

10.2

10.3

Introduction ......................................................................................................26

Reset Input ......................................................................................................26

Reset Output ...................................................................................................26

11 Power Monitor ........................................................................................ 28

11.1

Description .......................................................................................................28

12 Timer 2 .................................................................................................... 30

12.1

12.2

12.3

Auto-reload Mode ............................................................................................30

Programmable Clock-output ............................................................................31

Registers .........................................................................................................32

13 Programmable Counter Array (PCA) .................................................... 35

13.1

13.2

13.3

13.4

13.5

PCA Capture Mode .........................................................................................43

16-bit Software Timer/ Compare Mode ...........................................................43

High Speed Output Mode ................................................................................44

Pulse Width Modulator Mode ..........................................................................45

PCA Watchdog Timer ......................................................................................46

135

4235K–8051–05/08

14 Serial I/O Port ......................................................................................... 48

14.1

14.2

14.3

14.4

14.5

Framing Error Detection ..................................................................................48

Automatic Address Recognition ......................................................................49

Registers .........................................................................................................51

Baud Rate Selection for UART for Mode 1 and 3 ............................................51

UART Registers ...............................................................................................54

15 Keyboard Interface ................................................................................ 59

15.1

Registers .........................................................................................................60

16 Serial Port Interface (SPI) ...................................................................... 63

16.1

16.2

16.3

Features ..........................................................................................................63

Signal Description ............................................................................................63

Functional Description .....................................................................................65

17 Interrupt System .................................................................................... 72

17.1

17.2

Registers .........................................................................................................73

Interrupt Sources and Vector Addresses .........................................................73

18 Power Management ............................................................................... 80

18.1

18.2

18.3

18.4

Introduction ......................................................................................................80

Idle Mode .........................................................................................................80

Power-Down Mode ..........................................................................................81

Registers .........................................................................................................83

19 Hardware Watchdog Timer ................................................................... 84

19.1

19.2

Using the WDT ................................................................................................84

WDT during Power-down and Idle ...................................................................85

20 ONCE^®Mode (ON- Chip Emulation) ..................................................... 86

21 Power-off Flag ........................................................................................ 87

22 Reduced EMI Mode ................................................................................ 88

23 EEPROM Data Memory .......................................................................... 89

23.1

23.2

23.3

Write Data ........................................................................................................89

Read Data .......................................................................................................90

Registers .........................................................................................................91

24 Flash/EEPROM Memory ........................................................................ 93

24.1

24.2

Features ..........................................................................................................93

Flash Programming and Erasure .....................................................................93

136

AT89C51RD2/ED2

4235K–8051–05/08

AT89C51RD2/ED2

24.3

24.4

24.5

24.6

24.7

24.8

24.9

Flash Registers and Memory Map ...................................................................94

Flash Memory Status....................................................................................... 97

Memory Organization ......................................................................................97

Bootloader Architecture ...................................................................................97

ISP Protocol Description ................................................................................102

Functional Description ...................................................................................103

Flow Description ............................................................................................104

24.10 API Call Description .......................................................................................112

25 Electrical Characteristics .................................................................... 114

25.1

25.2

25.3

Absolute Maximum Ratings ...........................................................................114

DC Parameters for Standard Voltage ............................................................114

AC Parameters ..............................................................................................117

26 Ordering Information ........................................................................... 126

27 Packaging Information ........................................................................ 127

27.1

27.2

27.3

27.4

PLCC44 .........................................................................................................127

VQFP44 .........................................................................................................129

PLCC68 .........................................................................................................131

VQFP64 .........................................................................................................132

28 Document Revision History ................................................................ 133

28.1

28.2

28.3

28.4

28.5

28.6

28.7

28.8

28.9

Changes from 4235A -04/03 to 4135B - 06/03 ..............................................133

Changes from 4235B -06/03 to 4235C - 08/03 ..............................................133

Changes from 4235C - 08/03 to 4235D - 12/03 ............................................133

Changes from 4235D - 12/03 to 4235E - 04/04 .............................................133

Changes from 4235E - 04/04 to 4235F - 09/04 .............................................133

Changes from 4235F - 09/04 to 4235G 08/05 ...............................................133

Changes from 4235G 08/05 to 4235H - 10/06 ..............................................133

Changes from 4235H - 10/06 to 4235I - 04/07 ..............................................133

Changes from 4235I - 04/07 to 4235J - 01/08 ...............................................133

28.10 Changes from 4235J - 01/08 to 4235K - 05/08 .............................................133

137

4235K–8051–05/08

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4235K–8051–05/08


型号：	AT89C51RD2_08
厂家：	ATMEL
描述：	8-bit Flash Microcontroller 8位闪存微控制器闪存微控制器
文件：	总137页 (文件大小：1412K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT89C51RD2_08 [ATMEL]

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