AT89C51SND1C-7HTUL_技术文档

1. Features

• MPEG I/II-Layer 3 Hardwired Decoder

– Stand-alone MP3 Decoder

– 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency

– Separated Digital Volume Control on Left and Right Channels (Software Control

using 31 Steps)

– Bass, Medium, and Treble Control (31 Steps)

– Bass Boost Sound Effect

– Ancillary Data Extraction

– CRC Error and MPEG Frame Synchronization Indicators

• Programmable Audio Output for Interfacing with Common Audio DAC

– PCM Format Compatible

Single-Chip

Flash

Microcontroller

with MP3

– I²S Format Compatible

• 8-bit MCU C51 Core Based (F_MAX= 20 MHz)

• 2304 Bytes of Internal RAM

• 64K Bytes of Code Memory

– AT89C51SND1C: Flash (100K Erase/Write Cycles)

– AT83SND1C: ROM

• 4K Bytes of Boot Flash Memory (AT89C51SND1C)

– ISP: Download from USB (standard) or UART (option)

• External Code Memory

Decoder and

Human Interface

– AT80C51SND1C: ROMless

• USB Rev 1.1 Controller

– Full Speed Data Transmission

• Built-in PLL

AT83SND1C

– MP3 Audio Clocks

– USB Clock

AT89C51SND1C

AT80C51SND1C

• MultiMedia Card^®Interface Compatibility

• Atmel DataFlash^®SPI Interface Compatibility

• IDE/ATAPI Interface

• 2 Channels 10-bit ADC, 8 kHz (8-true bit)

– Battery Voltage Monitoring

– Voice Recording Controlled by Software

• Up to 44 Bits of General-purpose I/Os

– 4-bit Interrupt Keyboard Port for a 4 x n Matrix

– SmartMedia^®Software Interface

• 2 Standard 16-bit Timers/Counters

• Hardware Watchdog Timer

• Standard Full Duplex UART with Baud Rate Generator

• Two Wire Master and Slave Modes Controller

• SPI Master and Slave Modes Controller

• Power Management

– Power-on Reset

– Software Programmable MCU Clock

– Idle Mode, Power-down Mode

• Operating Conditions:

– 3V, 10%, 25 mA Typical Operating at 25°C

– Temperature Range: -40°C to +85°C

• Packages

– TQFP80, BGA81, PLCC84 (Development Board)

– Dice

Rev. 4109H–8051–01/05

2. Description

The AT8xC51SND1C are fully integrated stand-alone hardwired MPEG I/II-Layer 3

decoder with a C51 microcontroller core handling data flow and MP3-player control.

The AT89C51SND1C includes 64K Bytes of Flash memory and allows In-System Pro-

gramming through an embedded 4K Bytes of Boot Flash memory.

The AT83SND1C includes 64K Bytes of ROM memory.

The AT80C51SND1C does not include any code memory.

The AT8xC51SND1C include 2304 Bytes of RAM memory.

The AT8xC51SND1C provides the necessary features for human interface like timers,

keyboard port, serial or parallel interface (USB, TWI, SPI, IDE), ADC input, I²S output,

and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia,

DataFlash cards).

3. Typical

Applications

•

MP3-Player

PDA, Camera, Mobile Phone MP3

Car Audio/Multimedia MP3

Home Audio/Multimedia MP3

4. Block Diagram

Figure 1. AT8xC51SND1C Block Diagram

INT0

INT1

VDD VSS UVDD UVSS AVDD AVSS AREF AIN1:0 TXD RXD

T0

T1

SS MISO MOSI SCK SCL SDA

3

4

1

Interrupt

Handler Unit

Flash

ROM

UART

and

BRG

RAM

2304 Bytes

10-bit A to D

Converter

Timers 0/1

Watchdog

SPI/DataFlash

Controller

TWI

Controller

64 KBytes

Flash Boot

4 KBytes

8-Bit Internal Bus

C51 (X2 Core)

I/O

Ports

MP3 Decoder

Unit

I²S/PCM

Audio Interface

USB

Controller

Keyboard

Interface

MMC

Interface

IDE

Clock and PLL

Unit

Interface

1

FILT

X1 X2

RST

ISP

ALE

DOUT DCLK DSEL SCLK D+ D-

MCLK

KIN3:0

P0-P5

MDAT MCMD

1 Alternate function of Port 1

3 Alternate function of Port 3

4 Alternate function of Port 4

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AT8xC51SND1C

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AT8xC51SND1C

5. Pin Description

5.1 Pinouts

Figure 1. AT8xC51SND1C 80-pin QFP Package

ALE

ISP¹/PSEN²/NC

P1.0/KIN0

P1.1/KIN1

P1.2/KIN2

P1.3/KIN3

P1.4

1

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

P4.5

2

P4.4

3

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

VSS

4

5

6

7

P1.5

8

P1.6/SCL

P1.7/SDA

VDD

9

AT89C51SND1C-RO (FLASH)

AT83SND1C-RO (ROM)

AT80C51SND1C-RO (ROMLESS)

10

11

12

13

14

15

16

17

18

19

20

VDD

MCLK

MDAT

MCMD

RST

PVDD

FILT

PVSS

VSS

SCLK

X2

DSEL

X1

DCLK

DOUT

VSS

TST

UVDD

UVSS

VDD

Notes: 1. ISP pin is only available in AT89C51SND1C product.

Do not connect this pin on AT83SND1C product.

2. PSEN pin is only available in AT80C51SND1C product.

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4109H–8051–01/05

Figure 2. AT8xC51SND1C 81-pin BGA Package

9

8

7

6

5

4

3

2

1

P2.0/

A8

P4.0/

MISO

P4.2/

SCK

P0.2/

AD2

P0.3/

AD3

P4.6

VDD

P5.0

ALE

A

ISP¹/

PSEN²

NC

P4.1/

MOSI

P4.3/

SS

P0.1/

AD1

P0.4/

AD4

P0.0/

AD0

P4.4

P4.7

P1.1

B

C

P2.5/

A13

P2.2/

A10

P2.1/

A9

P1.0/

KIN0

P1.3/

KIN3

P1.2/

KIN2

P0.6

VSS

P5.1

P2.4/

A12

P2.6/

A14

P0.7/

AD7

P0.5/

AD5

P1.6/

SCL

P1.7/

SDA

P4.5

VSS

P1.5

X1

P1.4

VDD

X2

D

E

F

P2.3/

A11

P2.7/

A15

VDD

RST

FILT

PVDD

UVSS

VDD

P3.4/

T0

MCMD

SCLK

VSS

MCLK

DOUT

AIN1

MDAT

P5.3

AVDD

PVSS

TST

D-

P3.7/

RD

P3.5/

T1

DSEL

DCLK

VSS

UVDD

G

H

J

P3.3/

INT1

P3.1/

TXD

AVSS

AIN0

P3.6/

WR

P3.2/

INT0

P3.0/

RXD

VDD

P5.2

AREFP

AREFN

VSS

D+

Notes: 1. ISP pin is only available in AT89C51SND1C product.

Do not connect this pin on AT83SND1C and AT80C51SND1C product.

2. PSEN pin is only available in AT80C51SND1C product.

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4109H–8051–01/05

AT8xC51SND1C

Figure 3. AT8xC51SND1C 84-pin PLCC Package

ALE 12

ISP 13

74 NC

73 P4.5

P1.0/KIN0 14

P1.1/KIN1 15

P1.2/KIN2 16

P1.3/KIN3 17

P1.4 18

72 P4.4

71 P2.2/A10

70 P2.3/A11

69 P2.4/A12

68 P2.5/A13

67 P2.6/A14

66 P2.7/A15

65 VSS

P1.5 19

P1.6/SCL 20

P1.7/SDA 21

AT89C51SND1C-SR (FLASH)

VDD 22

PAVDD 23

FILT 24

PAVSS 25

VSS 26

X2 27

64 VDD

63 MCLK

62 MDAT

61 MCMD

60 RST

59 SCLK

58 DSEL

57 DCLK

56 DOUT

55 VSS

NC 28

X1 29

TST 30

UVDD 31

UVSS 32

54 VDD

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4109H–8051–01/05

5.2 Signals

All the AT8xC51SND1C signals are detailed by functionality in Table 3 to Table 16.

Table 3. Ports Signal Description

Signal

Name

Alternate

Function

Type

Description

Port 0

P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s

written to them float and can be used as high impedance inputs. To

avoid any parasitic current consumption, floating P0 inputs must be

P0.7:0

I/O

AD7:0

polarized to V_DDor V_SS

.

KIN3:0

SCL

SDA

Port 1

P1.7:0

P2.7:0

I/O

P1 is an 8-bit bidirectional I/O port with internal pull-ups.

Port 2

A15:8

P2 is an 8-bit bidirectional I/O port with internal pull-ups.

RXD

TXD

INT0

INT1

T0

Port 3

P3.7:0

I/O

P3 is an 8-bit bidirectional I/O port with internal pull-ups.

T1

WR

RD

MISO

MOSI

SCK

SS

Port 4

P4.7:0

P5.3:0

I/O

P4 is an 8-bit bidirectional I/O port with internal pull-ups.

Port 5

-

P5 is a 4-bit bidirectional I/O port with internal pull-ups.

Table 4. Clock Signal Description

Signal

Name

Alternate

Function

Type

Description

Input to the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected to

this pin. If an external oscillator is used, its output is connected to this

pin. X1 is the clock source for internal timing.

X1

I

-

Output of the on-chip inverting oscillator amplifier

X2

O

I

To use the internal oscillator, a crystal/resonator circuit is connected to

this pin. If an external oscillator is used, leave X2 unconnected.

-

PLL Low Pass Filter input

FILT receives the RC network of the PLL low pass filter.

FILT

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Table 5. Timer 0 and Timer 1 Signal Description

Signal

Name

Alternate

Function

Type

Description

Timer 0 Gate Input

INT0 serves as external run control for timer 0, when selected by

GATE0 bit in TCON register.

INT0

I

P3.2

External Interrupt 0

INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set,

bit IE0 is set by a falling edge on INT0. If bit IT0 is cleared, bit IE0 is set

by a low level on INT0.

Timer 1 Gate Input

INT1 serves as external run control for timer 1, when selected by

GATE1 bit in TCON register.

INT1

I

P3.3

External Interrupt 1

INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set,

bit IE1 is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set

by a low level on INT1.

Timer 0 External Clock Input

T0

T1

I

When timer 0 operates as a counter, a falling edge on the T0 pin

increments the count.

P3.4

P3.5

Timer 1 External Clock Input

When timer 1 operates as a counter, a falling edge on the T1 pin

increments the count.

Table 6. Audio Interface Signal Description

Signal

Alternate

Function

Name

DCLK

DOUT

Type

O

Description

DAC Data Bit Clock

DAC Audio Data

-

O

DAC Channel Select Signal

DSEL is the sample rate clock output.

DSEL

SCLK

O

-

DAC System Clock

SCLK is the oversampling clock synchronized to the digital audio data

(DOUT) and the channel selection signal (DSEL).

Table 7. USB Controller Signal Description

Signal

Name

Alternate

Function

Type

I/O

Description

USB Positive Data Upstream Port

This pin requires an external 1.5 KΩ pull-up to V_DDfor full speed

operation.

D+

-

D-

I/O

USB Negative Data Upstream Port

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4109H–8051–01/05

Table 8. MutiMediaCard Interface Signal Description

Signal

Name

Alternate

Function

Type

Description

MMC Clock output

Data or command clock transfer.

MCLK

O

-

MMC Command line

Bidirectional command channel used for card initialization and data

transfer commands. To avoid any parasitic current consumption,

MCMD

MDAT

I/O

-

unused MCMD input must be polarized to V_DDor V_SS

.

MMC Data line

Bidirectional data channel. To avoid any parasitic current consumption,

unused MDAT input must be polarized to V_DDor V_SS

-

.

Table 9. UART Signal Description

Signal

Name

Alternate

Function

Type

Description

Receive Serial Data

RXD

I/O

RXD sends and receives data in serial I/O mode 0 and receives data in

serial I/O modes 1, 2 and 3.

P3.0

P3.1

Transmit Serial Data

TXD outputs the shift clock in serial I/O mode 0 and transmits data in

serial I/O modes 1, 2 and 3.

TXD

O

Table 10. SPI Controller Signal Description

Signal

Name

Alternate

Function

Type

Description

SPI Master Input Slave Output Data Line

MISO

I/O

When in master mode, MISO receives data from the slave peripheral.

When in slave mode, MISO outputs data to the master controller.

P4.0

P4.1

SPI Master Output Slave Input Data Line

When in master mode, MOSI outputs data to the slave peripheral.

When in slave mode, MOSI receives data from the master controller.

MOSI

I/O

SPI Clock Line

SCK

SS

I/O

I

When in master mode, SCK outputs clock to the slave peripheral. When

in slave mode, SCK receives clock from the master controller.

P4.2

P4.3

SPI Slave Select Line

When in controlled slave mode, SS enables the slave mode.

Table 11. TWI Controller Signal Description

Signal

Name

Alternate

Function

Type

Description

TWI Serial Clock

When TWI controller is in master mode, SCL outputs the serial clock to

the slave peripherals. When TWI controller is in slave mode, SCL

receives clock from the master controller.

SCL

I/O

P1.6

P1.7

TWI Serial Data

SDA is the bidirectional Two Wire data line.

SDA

I/O

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AT8xC51SND1C

Table 12. A/D Converter Signal Description

Signal

Alternate

Function

Name

AIN1:0

AREFP

Type

Description

I

A/D Converter Analog Inputs

Analog Positive Voltage Reference Input

-

Analog Negative Voltage Reference Input

This pin is internally connected to AVSS.

AREFN

I

-

Table 13. Keypad Interface Signal Description

Signal

Name

Alternate

Function

Type

Description

Keypad Input Lines

KIN3:0

I

Holding one of these pins high or low for 24 oscillator periods triggers a

keypad interrupt.

P1.3:0

Table 14. External Access Signal Description

Signal

Name

Alternate

Function

Type

Description

Address Lines

A15:8

I/O

Upper address lines for the external bus.

Multiplexed higher address and data lines for the IDE interface.

P2.7:0

P0.7:0

Address/Data Lines

Multiplexed lower address and data lines for the external memory or the

IDE interface.

AD7:0

ALE

I/O

O

Address Latch Enable Output

ALE signals the start of an external bus cycle and indicates that valid

address information is available on lines A7:0. An external latch is used

to demultiplex the address from address/data bus.

-

Program Store Enable Output (AT80C51SND1C Only)

This signal is active low during external code fetch or external code

read (MOVC instruction).

PSEN

ISP

I/O

-

ISP Enable Input (AT89C51SND1C Only)

This signal must be held to GND through a pull-down resistor at the

falling reset to force execution of the internal bootloader.

Read Signal

RD

O

P3.7

P3.6

Read signal asserted during external data memory read operation.

Write Signal

WR

Write signal asserted during external data memory write operation.

External Access Enable (Dice Only)

EA must be externally held low to enable the device to fetch code from

external program memory locations 0000h to FFFFh.

EA⁽¹⁾⁽²⁾

I

-

Notes: 1. For ROM/Flash Dice product versions: pad EA must be connected to VCC.

2. For ROMless Dice product versions: pad EA must be connected to VSS.

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4109H–8051–01/05

Table 15. System Signal Description

Signal

Name

Alternate

Function

Type

Description

Reset Input

Holding this pin high for 64 oscillator periods while the oscillator is

running resets the device. The Port pins are driven to their reset

conditions when a voltage lower than V_ILis applied, whether or not the

oscillator is running.

RST

I

-

This pin has an internal pull-down resistor which allows the device to be

reset by connecting a capacitor between this pin and V_DD

.

Asserting RST when the chip is in Idle mode or Power-Down mode

returns the chip to normal operation.

Test Input

TST

I

-

Test mode entry signal. This pin must be set to V_DD

.

Table 16. Power Signal Description

Signal

Name

Alternate

Function

Type

Description

Digital Supply Voltage

Connect these pins to +3V supply voltage.

VDD

PWR

-

Circuit Ground

Connect these pins to ground.

VSS

GND

PWR

GND

PWR

GND

PWR

GND

Analog Supply Voltage

Connect this pin to +3V supply voltage.

AVDD

AVSS

PVDD

PVSS

UVDD

UVSS

Analog Ground

Connect this pin to ground.

PLL Supply voltage

Connect this pin to +3V supply voltage.

PLL Circuit Ground

Connect this pin to ground.

USB Supply Voltage

Connect this pin to +3V supply voltage.

USB Ground

Connect this pin to ground.

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4109H–8051–01/05

AT8xC51SND1C

5.17 Internal Pin

Structure

Table 18. Detailed Internal Pin Structure

Circuit⁽¹⁾

Type

Pins

VDD

Input

TST

VDD

Watchdog Output

P

Input/Output

RST

VSS

VDD

2 osc

periods

P1⁽²⁾

P2⁽³⁾

P3

Latch Output

P₁

P₂

P₃

Input/Output

P4

N

P53:0

VSS

VDD

P0

P

MCMD

MDAT

Input/Output

ISP

N

PSEN

VSS

VDD

ALE

SCLK

DCLK

P

Output

DOUT

DSEL

MCLK

N

VSS

D+

D-

Input/Output

D+

D-

Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to

the Section “DC Characteristics”, page 184.

2. When the Two Wire controller is enabled, P₁, P₂, and P₃transistors are disabled

allowing pseudo open-drain structure.

3. In Port 2, P₁transistor is continuously driven when outputting a high level bit address

(A15:8).

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4109H–8051–01/05

6. Clock Controller

The AT8xC51SND1C clock controller is based on an on-chip oscillator feeding an on-

chip Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are

generated by this controller.

6.1 Oscillator

The AT8xC51SND1C X1 and X2 pins are the input and the output of a single-stage on-

chip inverter (see Figure 4) that can be configured with off-chip components such as a

Pierce oscillator (see Figure 5). Value of capacitors and crystal characteristics are

detailed in the Section “DC Characteristics”, page 163.

The oscillator outputs three different clocks: a clock for the PLL, a clock for the CPU

core, and a clock for the peripherals as shown in Figure 4. These clocks are either

enabled or disabled, depending on the power reduction mode as detailed in the section

“Power Management” on page 48. The peripheral clock is used to generate the Timer 0,

Timer 1, MMC, ADC, SPI, and Port sampling clocks.

Figure 4. Oscillator Block Diagram and Symbol

0

X1

X2

÷ 2

Peripheral

Clock

1

CPU Core

Clock

X2

CKCON.0

IDL

PCON.0

PD

PCON.1

Oscillator

Clock

PER

CPU

OSC

CLOCK

Peripheral Clock Symbol

CPU Core Clock Symbol

Oscillator Clock Symbol

Figure 5. Crystal Connection

X1

C1

C2

Q

VSS

X2

6.2 X2 Feature

Unlike standard C51 products that require 12 oscillator clock periods per machine cycle,

the AT8xC51SND1C need only 6 oscillator clock periods per machine cycle. This fea-

ture called the “X2 feature” can be enabled using the X2 bit⁽¹⁾in CKCON (see Table 5)

and allows the AT8xC51SND1C to operate in 6 or 12 oscillator clock periods per

machine cycle. As shown in Figure 4, both CPU and peripheral clocks are affected by

this feature. Figure 6 shows the X2 mode switching waveforms. After reset the standard

mode is activated. In standard mode the CPU and peripheral clock frequency is the

oscillator frequency divided by 2 while in X2 mode, it is the oscillator frequency.

Note:

1. The X2 bit reset value depends on the X2B bit in the Hardware Security Byte (see

Table 12 on page 24). Using the AT89C51SND1C (Flash Version) the system can

boot either in standard or X2 mode depending on the X2B value. Using AT83SND1C

(ROM Version) the system always boots in standard mode. X2B bit can be changed

to X2 mode later by software.

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4109H–8051–01/05

AT8xC51SND1C

Figure 6. Mode Switching Waveforms

X1

X1 ÷ 2

X2 Bit

Clock

X2 Mode⁽¹⁾

STD Mode

Note:

1. In order to prevent any incorrect operation while operating in X2 mode, user must be

aware that all peripherals using clock frequency as time reference (timers, etc.) will

have their time reference divided by 2. For example, a free running timer generating

an interrupt every 20 ms will then generate an interrupt every 10 ms.

6.3 PLL

6.3.1 PLL Description

The AT8xC51SND1C PLL is used to generate internal high frequency clock (the PLL

Clock) synchronized with an external low-frequency (the Oscillator Clock). The PLL

clock provides the MP3 decoder, the audio interface, and the USB interface clocks.

Figure 7 shows the internal structure of the PLL.

The PFLD block is the Phase Frequency Comparator and Lock Detector. This block

makes the comparison between the reference clock coming from the N divider and the

reverse clock coming from the R divider and generates some pulses on the Up or Down

signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON

register is used to enable the clock generation. When the PLL is locked, the bit PLOCK

in PLLCON register (see Table 6) is set.

The CHP block is the Charge Pump that generates the voltage reference for the VCO by

injecting or extracting charges from the external filter connected on PFILT pin (see

Figure 8). Value of the filter components are detailed in the Section “DC

Characteristics”.

The VCO block is the Voltage Controlled Oscillator controlled by the voltage V_refpro-

duced by the charge pump. It generates a square wave signal: the PLL clock.

Figure 7. PLL Block Diagram and Symbol

PFILT

CHP

PLLCON.1

PLLEN

N divider

N6:0

Up

OSC

CLOCK

Vref

PLL

Clock

PFLD

VCO

Down

PLOCK

PLLCON.0

R divider

R9:0

PLL

CLOCK

OSCclk × (R + 1)

PLLclk = ----------------------------------------------

N + 1

PLL Clock Symbol

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4109H–8051–01/05

Figure 8. PLL Filter Connection

FILT

R

C2

C1

VSS

6.3.2 PLL Programming

The PLL is programmed using the flow shown in Figure 9. As soon as clock generation

is enabled, the user must wait until the lock indicator is set to ensure the clock output is

stable. The PLL clock frequency will depend on MP3 decoder clock and audio interface

clock frequencies.

Figure 9. PLL Programming Flow

PLL

Programming

Configure Dividers

N6:0 = xxxxxxb

R9:0 = xxxxxxxxxxb

Enable PLL

PLLRES = 0

PLLEN = 1

PLL Locked?

PLOCK = 1?

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AT8xC51SND1C

6.4 Registers

Table 5. CKCON Register

CKCON (S:8Fh) – Clock Control Register

7

6

5

-

4

3

-

2

1

0

TWIX2

WDX2

SIX2

T1X2

T0X2

X2

Bit

Number

Mnemonic Description

Two-Wire Clock Control Bit

Set to select the oscillator clock divided by 2 as TWI clock input (X2

independent).

7

TWIX2

Clear to select the peripheral clock as TWI clock input (X2 dependent).

Watchdog Clock Control Bit

Set to select the oscillator clock divided by 2 as watchdog clock input (X2

independent).

Clear to select the peripheral clock as watchdog clock input (X2 dependent).

6

5

4

3

2

WDX2

Reserved

-

The values read from this bit is indeterminate. Do not set this bit.

Enhanced UART Clock (Mode 0 and 2) Control Bit

Set to select the oscillator clock divided by 2 as UART clock input (X2

independent).

SIX2

-

Clear to select the peripheral clock as UART clock input (X2 dependent)..

Reserved

The values read from this bit is indeterminate. Do not set this bit.

Timer 1 Clock Control Bit

Set to select the oscillator clock divided by 2 as timer 1 clock input (X2

independent).

T1X2

Clear to select the peripheral clock as timer 1 clock input (X2 dependent).

Timer 0 Clock Control Bit

Set to select the oscillator clock divided by 2 as timer 0 clock input (X2

independent).

Clear to select the peripheral clock as timer 0 clock input (X2 dependent).

1

0

T0X2

X2

System Clock Control Bit

Clear to select 12 clock periods per machine cycle (STD mode, F_CPU= F_PER

F_OSC/2).

=

Set to select 6 clock periods per machine cycle (X2 mode, F_CPU= F_PER= F_OSC).

Reset Value = 0000 000Xb (AT89C51SND1C) or 0000 0000b (AT83SND1C)

Table 6. PLLCON Register

PLLCON (S:E9h) – PLL Control Register

7

6

5

-

4

-

3

2

-

1

0

R1

R0

PLLRES

PLLEN

PLOCK

Bit

Number

Mnemonic Description

PLL Least Significant Bits R Divider

2 LSB of the 10-bit R divider.

7 - 6

5 - 4

R1:0

-

Reserved

The values read from these bits are always 0. Do not set these bits.

PLL Reset Bit

3

PLLRES Set this bit to reset the PLL.

Clear this bit to free the PLL and allow enabling.

15

4109H–8051–01/05

Bit

Number

Mnemonic Description

Reserved

2

1

-

The value read from this bit is always 0. Do not set this bit.

PLL Enable Bit

Set to enable the PLL.

Clear to disable the PLL.

PLLEN

PLOCK

PLL Lock Indicator

Set by hardware when PLL is locked.

Clear by hardware when PLL is unlocked.

0

Reset Value = 0000 1000b

Table 7. PLLNDIV Register

PLLNDIV (S:EEh) – PLL N Divider Register

7

-

6

5

4

3

2

1

0

N6

N5

N4

N3

N2

N1

N0

Bit

Number

Mnemonic Description

Reserved

7

-

The value read from this bit is always 0. Do not set this bit.

PLL N Divider

7 - bit N divider.

6 - 0

N6:0

Reset Value = 0000 0000b

Table 8. PLLRDIV Register

PLLRDIV (S:EFh) – PLL R Divider Register

7

6

5

4

3

2

1

0

R9

R8

R7

R6

R5

R4

R3

R2

Bit

Number

Mnemonic Description

PLL Most Significant Bits R Divider

8 MSB of the 10-bit R divider.

7 - 0

R9:2

Reset Value = 0000 0000b

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AT8xC51SND1C

7. Program/Code

Memory

The AT8xC51SND1C execute up to 64K Bytes of program/code memory. Figure 10

shows the split of internal and external program/code memory spaces depending on the

product.

The AT83SND1C product provides the internal program/code memory in ROM memory

while the AT89C51SND1C product provides it in Flash memory. These 2 products do

not allow external code memory execution. External code memory execution is

achieved using the AT80C51SND1C product which does not provide any internal pro-

gram/code memory.

The Flash memory increases EPROM and ROM functionality by in-circuit electrical era-

sure and programming. The high voltage needed for programming or erasing Flash cells

is generated on-chip using the standard V_DDvoltage, made possible by the internal

charge pump. Thus, the AT89C51SND1C can be programmed using only one voltage

and allows In-application software programming. Hardware programming mode is also

available using common programming tools. See the application note ‘Programming

T89C51x and AT89C51x with Device Programmers’.

The AT89C51SND1C implements an additional 4K Bytes of on-chip boot Flash memory

provided in Flash memory. This boot memory is delivered programmed with a standard

boot loader software allowing In-System Programming (ISP). It also contains some

Application Programming Interface routines named API routines allowing In Application

Programming (IAP) by using user’s own boot loader.

Figure 10. Program/Code Memory Organization

FFFFh

F000h

FFFFh

F000h

4K Bytes

Boot Flash

64K Bytes

External Code

64K Bytes

Code ROM

64K Bytes

Code Flash

0000h

AT80C51SND1C

AT83SND1C

AT89C51SND1C

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4109H–8051–01/05

7.1 ROMLESS Memory

Architecture

As shown in Figure 11 the AT80C51SND1C external memory is composed of one

space detailed in the following paragraph.

Figure 11. AT80C51SND1C Memory Architecture

FFFFh

64K Bytes

User

External Memory

0000h

7.1.1 User Space

This space is composed of a 64K Bytes code (Flash, EEPROM, EPROM…) memory. It

contains the user’s application code.

7.1.2 Memory Interface

The external memory interface comprises the external bus (port 0 and port 2) as well as

the bus control signals (PSEN, and ALE).

Figure 12 shows the structure of the external address bus. P0 carries address A7:0

while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 12

describes the external memory interface signals.

Figure 12. External Code Memory Interface Structure

Flash

EPROM

AT80C51SND1C

A15:8

P2

ALE

P0

A15:8

A7:0

AD7:0

Latch A7:0

D7:0

OE

PSEN

Table 2. External Code Memory Interface Signals

Signal

Name

Alternate

Function

Type Description

Address Lines

Upper address lines for the external bus.

A15:8

O

P2.7:0

P0.7:0

Address/Data Lines

Multiplexed lower address lines and data for the external memory.

AD7:0

ALE

I/O

O

Address Latch Enable

ALE signals indicates that valid address information are available on lines

AD7:0.

-

Program Store Enable Output (AT80C51SND1C Only)

This signal is active low during external code fetch or external code read

(MOVC instruction).

PSEN

O

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AT8xC51SND1C

7.2.1 External Bus Cycles

This section describes the bus cycles the AT80C51SND1C executes to fetch code (see

Figure 13) in the external program/code memory.

External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator

clock periods in standard mode or 6 oscillator clock periods in X2 mode. For further

information on X2 mode see section “Clock “.

For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized

form and does not provide precise timing information.

For bus cycling parameters refer to the ‘AC-DC parameters’ section.

Figure 13. External Code Fetch Waveforms

CPU Clock

ALE

PSEN

D7:0

PCH

PCL

D7:0

PCL

D7:0

P0

P2

PCH

7.3 ROM Memory

Architecture

As shown in Figure 14 the AT83SND1C ROM memory is composed of one space

detailed in the following paragraph.

Figure 14. AT83SND1C Memory Architecture

FFFFh

64K Bytes

User

ROM Memory

0000h

7.3.1 User Space

This space is composed of a 64K Bytes ROM memory programmed during the manu-

facturing process. It contains the user’s application code.

7.4 Flash Memory

Architecture

As shown in Figure 15 the AT89C51SND1C Flash memory is composed of four spaces

detailed in the following paragraphs.

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4109H–8051–01/05

Figure 15. AT89C51SND1C Memory Architecture

Hardware Security

Extra Row

FFFFh

4K Bytes

Flash Memory

Boot

F000h

64K Bytes

User

Flash Memory

0000h

7.4.1 User Space

7.4.2 Boot Space

This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128

Bytes. It contains the user’s application code.

This space can be read or written by both software and hardware modes.

This space is composed of a 4K Bytes Flash memory. It contains the boot loader for In-

System Programming and the routines for In Application Programming.

This space can only be read or written by hardware mode using a parallel programming

tool.

7.4.3 Hardware Security Space This space is composed of one Byte: the Hardware Security Byte (HSB see Table 12)

divided in 2 separate nibbles. The MSN contains the X2 mode configuration bit and the

Boot Loader Jump Bit as detailed in Section “Boot Memory Execution”, page 21 and can

be written by software while the LSN contains the lock system level to protect the mem-

ory content against piracy as detailed in Section “Hardware Security System”, page 21

and can only be written by hardware.

7.4.4 Extra Row Space

This space is composed of 2 Bytes:

•

The Software Boot Vector (SBV, see Table 13).

This Byte is used by the software boot loader to build the boot address.

•

The Software Security Byte (SSB, see Table 14).

This Byte is used to lock the execution of some boot loader commands.

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AT8xC51SND1C

7.5 Hardware Security

System

The AT89C51SND1C implements three lock bits LB2:0 in the LSN of HSB (see

Table 12) providing three levels of security for user’s program as described in Table 12

while the AT83SND1C is always set in read disabled mode.

Level 0 is the level of an erased part and does not enable any security feature.

Level 1 locks the hardware programming of both user and boot memories.

Level 2 locks also hardware verifying of both user and boot memories

Level 3 locks also the external execution.

Table 6. Lock Bit Features⁽¹⁾

Internal

External

Execution

Hardware

Verifying

Hardware

Programming Programming

Software

Level LB2⁽²⁾LB1 LB0 Execution

0

1

U

P

U

P

X

U

P

X

Enable

Disable

Enable

Disable

Enable

Disable

Enable

2

3⁽³⁾

Notes: 1. U means unprogrammed, P means programmed and X means don’t care (pro-

grammed or unprogrammed).

2. LB2 is not implemented in the AT8xC51SND1C products.

3. AT89C51SND1C products are delivered with third level programmed to ensure that

the code programmed by software using ISP or user’s boot loader is secured from

any hardware piracy.

7.7 Boot Memory

Execution

As internal C51 code space is limited to 64K Bytes, some mechanisms are implemented

to allow boot memory to be mapped in the code space for execution at addresses from

F000h to FFFFh. The boot memory is enabled by setting the ENBOOT bit in AUXR1

(see Figure 10). The three ways to set this bit are detailed in the following sections.

7.7.1 Software Boot Mapping

The software way to set ENBOOT consists in writing to AUXR1 from the user’s soft-

ware. This enables boot loader or API routines execution.

7.7.2 Hardware Condition

Boot Mapping

The hardware condition is based on the ISP pin. When driving this pin to low level, the

chip reset sets ENBOOT and forces the reset vector to F000h instead of 0000h in order

to execute the boot loader software.

As shown in Figure 16 the hardware condition always allows in-system recovery when

user’s memory has been corrupted.

7.7.3 Programmed Condition

Boot Mapping

The programmed condition is based on the Boot Loader Jump Bit (BLJB) in HSB. As

shown in Figure 16 when this bit is programmed (by hardware or software programming

mode), the chip reset set ENBOOT and forces the reset vector to F000h instead of

0000h, in order to execute the boot loader software.

21

4109H–8051–01/05

Figure 16. Hardware Boot Process Algorithm

RESET

Hard Cond?

ISP = L?

Prog Cond?

BLJB = P?

Hard Cond Init

ENBOOT = 1

PC = F000h

FCON = 00h

Standard Init

ENBOOT = 0

PC = 0000h

FCON = F0h

Prog Cond Init

ENBOOT = 1

PC = F000h

FCON = F0h

User’s

Atmel’s

Application

Boot Loader

The software process (boot loader) is detailed in the “Boot Loader Datasheet”

Document.

7.8 Preventing Flash

Corruption

See Section “Reset Recommendation to Prevent Flash Corruption”, page 49.

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AT8xC51SND1C

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AT8xC51SND1C

7.9 Registers

Table 10. AUXR1 Register

AUXR1 (S:A2h) – Auxiliary Register 1

7

-

6

-

5

4

-

3

2

0

1

-

0

ENBOOT

GF3

DPS

Bit

Number

Mnemonic Description

Reserved

7 - 6

-

The value read from these bits are indeterminate. Do not set these bits.

Enable Boot Flash

Set this bit to map the boot Flash in the code space between at addresses F000h

to FFFFh.

5

ENBOOT¹

Clear this bit to disable boot Flash.

Reserved

4

3

-

The value read from this bit is indeterminate. Do not set this bit.

General Flag

This bit is a general-purpose user flag.

GF3

Always Zero

2

1

0

-

This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3

flag.

Reserved for Data Pointer Extension.

Data Pointer Select Bit

Set to select second data pointer: DPTR1.

Clear to select first data pointer: DPTR0.

DPS

Reset Value = XXXX 00X0b

Note: 1. ENBOOT bit is only available in AT89C51SND1C product.

23

4109H–8051–01/05

7.11 Hardware Bytes

Table 12. HSB Byte – Hardware Security Byte

7

6

5

-

4

-

3

-

2

1

0

X2B

BLJB

LB2

LB1

LB0

Bit

Number

Mnemonic Description

X2 Bit

7

6

X2B⁽¹⁾

BLJB⁽²⁾

-

Program this bit to start in X2 mode.

Unprogram (erase) this bit to start in standard mode.

Boot Loader Jump Bit

Program this bit to execute the boot loader at address F000h on next reset.

Unprogram (erase) this bit to execute user’s application at address 0000h on

next reset.

Reserved

5 - 4

The value read from these bits is always unprogrammed. Do not program these

bits.

Reserved

3

-

The value read from this bit is always unprogrammed. Do not program this bit.

Hardware Lock Bits

Refer to for bits description.

2 - 0

LB2:0

Reset Value = XXUU UXXX, UUUU UUUU after an hardware full chip erase.

Note:

1. X2B initializes the X2 bit in CKCON during the reset phase.

2. In order to ensure boot loader activation at first power-up, AT89C51SND1C products

are delivered with BLJB programmed.

3. Bits 0 to 3 (LSN) can only be programmed by hardware mode.

Table 13. SBV Byte – Software Boot Vector

7

6

5

4

3

2

1

0

ADD15

ADD14

ADD13

ADD12

ADD11

ADD10

ADD9

ADD8

Bit

Number

Mnemonic Description

MSB of the user’s boot loader 16-bit address location

Refer to the boot loader datasheet for usage information (boot loader dependent)

7 - 0

ADD15:8

Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase.

Table 14. SSB Byte – Software Security Byte

7

6

5

4

3

2

1

0

SSB7

SSB6

SSB5

SSB4

SSB3

SSB2

SSB1

SSB0

Bit

Number

Mnemonic Description

Software Security Byte Data

Refer to the boot loader datasheet for usage information (boot loader dependent)

7 - 0

SSB7:0

Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase.

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AT8xC51SND1C

4109H–8051–01/05

AT8xC51SND1C

8. Data Memory

The AT8xC51SND1C provides data memory access in 2 different spaces:

1. The internal space mapped in three separate segments:

–

The lower 128 Bytes RAM segment

The upper 128 Bytes RAM segment

The expanded 2048 Bytes RAM segment

2. The external space.

A fourth internal segment is available but dedicated to Special Function Registers,

SFRs, (addresses 80h to FFh) accessible by direct addressing mode. For information

on this segment, refer to the Section “Special Function Registers”, page 32.

Figure 17 shows the internal and external data memory spaces organization.

Figure 17. Internal and External Data Memory Organization

FFFFh

64K Bytes

External XRAM

7FFh

FFh

80h

Upper

128 Bytes

Special

Function

Internal RAM

Indirect Addressing

Registers

Direct Addressing

2K Bytes

Internal ERAM

EXTRAM = 0

80h

7Fh

Lower

128 Bytes

Internal RAM

Direct or Indirect

Addressing

0800h

0000h

EXTRAM = 1

00h

8.1 Internal Space

8.1.1 Lower 128 Bytes RAM

The lower 128 Bytes of RAM (see Figure 18) are accessible from address 00h to 7Fh

using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4

banks of 8 registers (R0 to R7). 2 bits RS0 and RS1 in PSW register (see Table 8)

select which bank is in use according to Table 2. This allows more efficient use of code

space, since register instructions are shorter than instructions that use direct address-

ing, and can be used for context switching in interrupt service routines.

Table 2. Register Bank Selection

RS1

RS0

Description

0

1

0

1

0

1

Register bank 0 from 00h to 07h

Register bank 1 from 08h to 0Fh

Register bank 2 from 10h to 17h

Register bank 3 from 18h to 1Fh

The next 16 Bytes above the register banks form a block of bit-addressable memory

space. The C51 instruction set includes a wide selection of single-bit instructions, and

the 128 bits in this area can be directly addressed by these instructions. The bit

addresses in this area are 00h to 7Fh.

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4109H–8051–01/05

Figure 18. Lower 128 Bytes Internal RAM Organization

7Fh

30h

2Fh

Bit-Addressable Space

(Bit Addresses 0-7Fh)

20h

18h

10h

08h

00h

1Fh

17h

0Fh

07h

4 Banks of

8 Registers

R0-R7

8.2.1 Upper 128 Bytes RAM

8.2.2 Expanded RAM

The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect

addressing mode.

The on-chip 2K Bytes of expanded RAM (ERAM) are accessible from address 0000h to

07FFh using indirect addressing mode through MOVX instructions. In this address

range, EXTRAM bit in AUXR register (see Table 9) is used to select the ERAM (default)

or the XRAM. As shown in Figure 17 when EXTRAM = 0, the ERAM is selected and

when EXTRAM = 1, the XRAM is selected (see Section “External Space”).

The ERAM memory can be resized using XRS1:0 bits in AUXR register to dynamically

increase external access to the XRAM space. Table 3 details the selected ERAM size

and address range.

Table 3. ERAM Size Selection

XRS1

XRS0

ERAM Size

256 Bytes

512 Bytes

1K Byte

Address

0

1

0

1

0

1

0 to 00FFh

0 to 01FFh

0 to 03FFh

0 to 07FFh

2K Bytes

Note:

Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile

memory cells. This means that the RAM content is indeterminate after power-up and

must then be initialized properly.

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AT8xC51SND1C

8.4 External Space

8.4.1 Memory Interface

The external memory interface comprises the external bus (port 0 and port 2) as well as

the bus control signals (RD, WR, and ALE).

Figure 19 shows the structure of the external address bus. P0 carries address A7:0

while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 5

describes the external memory interface signals.

Figure 19. External Data Memory Interface Structure

RAM

AT8xC51SND1C

PERIPHERAL

A15:8

P2

ALE

P0

A15:8

AD7:0

Latch A7:0

A7:0

D7:0

RD

OE

WR

Table 5. External Data Memory Interface Signals

Signal

Name

Alternate

Function

Type Description

Address Lines

Upper address lines for the external bus.

A15:8

O

P2.7:0

P0.7:0

Address/Data Lines

Multiplexed lower address lines and data for the external memory.

AD7:0

ALE

I/O

O

Address Latch Enable

ALE signals indicates that valid address information are available on lines

AD7:0.

-

Read

RD

O

P3.7

P3.6

Read signal output to external data memory.

Write

WR

Write signal output to external memory.

8.5.1 Page Access Mode

The AT8xC51SND1C implement a feature called Page Access that disables the output

of DPH on P2 when executing MOVX @DPTR instruction. Page Access is enable by

setting the DPHDIS bit in AUXR register.

Page Access is useful when application uses both ERAM and 256 Bytes of XRAM. In

this case, software modifies intensively EXTRAM bit to select access to ERAM or XRAM

and must save it if used in interrupt service routine. Page Access allows external access

above 00FFh address without generating DPH on P2. Thus ERAM is accessed using

MOVX @Ri or MOVX @DPTR with DPTR < 0100h, < 0200h, < 0400h or < 0800h

depending on the XRS1:0 bits value. Then XRAM is accessed using MOVX @DPTR

with DPTR ≥ 0800h regardless of XRS1:0 bits value while keeping P2 for general I/O

usage.

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4109H–8051–01/05

8.5.2 External Bus Cycles

This section describes the bus cycles the AT8xC51SND1C executes to read (see

Figure 20), and write data (see Figure 21) in the external data memory.

External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator

clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-

mation on X2 mode, refer to the Section “X2 Feature”, page 12.

Slow peripherals can be accessed by stretching the read and write cycles. This is done

using the M0 bit in AUXR register. Setting this bit changes the width of the RD and WR

signals from 3 to 15 CPU clock periods.

For simplicity, Figure 20 and Figure 21 depict the bus cycle waveforms in idealized form

and do not provide precise timing information. For bus cycle timing parameters refer to

the Section “AC Characteristics”.

Figure 20. External Data Read Waveforms

CPU Clock

ALE

RD⁽¹⁾

DPL or Ri

D7:0

P0

P2

DPH or P2^(2),(3)

P2

Notes: 1. RD signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instruction, P2 outputs SFR content.

3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),

P2 outputs SFR content instead of DPH.

Figure 21. External Data Write Waveforms

CPU Clock

ALE

WR⁽¹⁾

DPL or Ri

D7:0

P0

P2

DPH or P2^(2),(3)

P2

Notes: 1. WR signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instruction, P2 outputs SFR content.

3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),

P2 outputs SFR content instead of DPH.

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AT8xC51SND1C

8.6 Dual Data Pointer

8.6.1 Description

The AT8xC51SND1C implement a second data pointer for speeding up code execution

and reducing code size in case of intensive usage of external memory accesses.

DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR

addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1

register (see Table 10) is used to select whether DPTR is the data pointer 0 or the data

pointer 1 (see Figure 22).

Figure 22. Dual Data Pointer Implementation

0

1

DPL0

DPL1

DPL

DPTR0

DPTR1

AUXR1.0

DPTR

DPS

0

1

DPH0

DPH1

DPH

8.6.2 Application

Software can take advantage of the additional data pointers to both increase speed and

reduce code size, for example, block operations (copy, compare, search …) are well

served by using one data pointer as a “source” pointer and the other one as a “destina-

tion” pointer.

Below is an example of block move implementation using the 2 pointers and coded in

assembler. The latest C compiler also takes advantage of this feature by providing

enhanced algorithm libraries.

The INC instruction is a short (2 Bytes) and fast (6 CPU clocks) way to manipulate the

DPS bit in the AUXR1 register. However, note that the INC instruction does not directly

force the DPS bit to a particular state, but simply toggles it. In simple routines, such as

the block move example, only the fact that DPS is toggled in the proper sequence mat-

ters, not its actual value. In other words, the block move routine works the same whether

DPS is '0' or '1' on entry.

; ASCII block move using dual data pointers

; Modifies DPTR0, DPTR1, A and PSW

; Ends when encountering NULL character

; Note: DPS exits opposite of entry state unless an extra INC AUXR1 is added

AUXR1

move:

EQU

0A2h

mov

inc

mov

DPTR,#SOURCE ; address of SOURCE

AUXR1

DPTR,#DEST

AUXR1

; switch data pointers

; address of DEST

mv_loop: inc

; switch data pointers

; get a Byte from SOURCE

; increment SOURCE address

; switch data pointers

; write the Byte to DEST

; increment DEST address

; check for NULL terminator

movx A,@DPTR

inc

movx @DPTR,A

inc

jnz

DPTR

AUXR1

DPTR

mv_loop

end_move:

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4109H–8051–01/05

8.7 Registers

Table 8. PSW Register

PSW (S:8Eh) – Program Status Word Register

7

6

5

4

3

2

1

0

CY

AC

F0

RS1

RS0

OV

F1

P

Bit

Number

Mnemonic Description

Carry Flag

Carry out from bit 1 of ALU operands.

7

CY

Auxiliary Carry Flag

Carry out from bit 1 of addition operands.

6

5

AC

F0

User Definable Flag 0

Register Bank Select Bits

Refer to Table 2 for bits description.

4 - 3

RS1:0

Overflow Flag

Overflow set by arithmetic operations.

2

1

OV

F1

User Definable Flag 1

Parity Bit

0

P

Set when ACC contains an odd number of 1’s.

Cleared when ACC contains an even number of 1’s.

Reset Value = 0000 0000b

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AT8xC51SND1C

Table 9. AUXR Register

AUXR (S:8Eh) – Auxiliary Control Register

7

-

6

5

4

3

2

1

0

EXT16

M0

DPHDIS

XRS1

XRS0

EXTRAM

AO

Bit

Number

Mnemonic Description

Reserved

7

6

-

The value read from this bit is indeterminate. Do not set this bit.

External 16-bit Access Enable Bit

Set to enable 16-bit access mode during MOVX instructions.

Clear to disable 16-bit access mode and enable standard 8-bit access mode

during MOVX instructions.

EXT16

M0

External Memory Access Stretch Bit

Set to stretch RD or WR signals duration to 15 CPU clock periods.

Clear not to stretch RD or WR signals and set duration to 3 CPU clock periods.

5

DPH Disable Bit

4

DPHDIS Set to disable DPH output on P2 when executing MOVX @DPTR instruction.

Clear to enable DPH output on P2 when executing MOVX @DPTR instruction.

Expanded RAM Size Bits

XRS1:0

3 - 2

Refer to Table 3 for ERAM size description.

External RAM Enable Bit

Set to select the external XRAM when executing MOVX @Ri or MOVX @DPTR

EXTRAM instructions.

1

0

Clear to select the internal expanded RAM when executing MOVX @Ri or MOVX

@DPTR instructions.

ALE Output Enable Bit

AO

Set to output the ALE signal only during MOVX instructions.

Clear to output the ALE signal at a constant rate of F_CPU/3.

Reset Value = X000 1101b

31

4109H–8051–01/05

9. Special Function

Registers

The Special Function Registers (SFRs) of the AT8xC51SND1C derivatives fall into the

categories detailed in Table 1 to Table 17. The relative addresses of these SFRs are

provided together with their reset values in Table 18. In this table, the bit-addressable

registers are identified by Note 1.

Table 1. C51 Core SFRs

Mnemonic Add Name

7

6

5

4

3

2

1

0

ACC

B

E0h Accumulator

F0h B Register

PSW

SP

D0h Program Status Word

81h Stack Pointer

CY

AC

F0

RS1

RS0

OV

F1

P

DPL

DPH

82h Data Pointer Low Byte

83h Data Pointer High Byte

Table 2. System Management SFRs

Mnemonic Add Name

7

6

SMOD0

EXT16

-

5

4

3

2

GF0

XRS0

0

1

PD

0

PCON

AUXR

AUXR1

87h Power Control

SMOD1

-

M0

-

DPHDIS

-

GF1

XRS1

GF3

NV3

IDL

AO

8Eh Auxiliary Register 0

A2h Auxiliary Register 1

FBh Version Number

-

EXTRAM

-

ENBOOT⁽¹⁾

NV5

DPS

NV0

NVERS

Note:

NV7

NV6

NV4

NV2

NV1

1. ENBOOT bit is only available in AT89C51SND1C product.

Table 3. PLL and System Clock SFRs

Mnemonic Add Name

7

-

6

-

5

-

4

-

3

2

-

1

-

0

X2

CKCON

8Fh Clock Control

E9h PLL Control

EEh PLL N Divider

EFh PLL R Divider

-

PLLRES

N3

PLLCON

PLLNDIV

PLLRDIV

R1

-

R0

N6

R8

-

PLLEN

N1

PLOCK

N0

N5

R7

N4

R6

N2

R4

R9

R5

R3

R2

Table 4. Interrupt SFRs

Mnemonic Add Name

7

6

5

4

3

2

1

0

IEN0

IEN1

IPH0

IPL0

IPH1

IPL1

A8h Interrupt Enable Control 0

EA

EAUD

EMP3

ES

ET1

EX1

ET0

EX0

B1h Interrupt Enable Control 1

-

EUSB

-

EKB

EADC

IPHT1

IPLT1

IPHADC

IPLADC

ESPI

EI2C

EMMC

IPHX0

IPLX0

IPHMMC

IPLMMC

B7h Interrupt Priority Control High 0

B8h Interrupt Priority Control Low 0

B3h Interrupt Priority Control High 1

B2h Interrupt Priority Control Low 1

IPHAUD

IPLAUD

IPHUSB

IPLUSB

IPHMP3

IPHS

IPLS

IPHKB

IPLKB

IPHX1

IPLX1

IPHSPI

IPLSPI

IPHT0

IPLT0

IPHI2C

IPLI2C

IPLMP3

-

32

AT8xC51SND1C

4109H–8051–01/05

AT8xC51SND1C

Table 5. Port SFRs

Mnemonic Add Name

7

6

5

4

3

2

1

0

P0

P1

P2

P3

P4

P5

80h 8-bit Port 0

90h 8-bit Port 1

A0h 8-bit Port 2

B0h 8-bit Port 3

C0h 8-bit Port 4

D8h 4-bit Port 5

-

Table 6. Flash Memory SFR

Mnemonic Add Name

7

6

5

4

3

2

1

0

FCON⁽¹⁾

Note:

D1h Flash Control

FPL3

FPL2

FPL1

FPL0

FPS

FMOD1

FMOD0

FBUSY

1. FCON register is only available in AT89C51SND1C product.

Table 7. Timer SFRs

Mnemonic Add Name

7

6

5

4

3

2

1

0

TCON

TMOD

TL0

88h Timer/Counter 0 and 1 Control

TF1

TR1

TF0

M11

TR0

M01

IE1

IT1

IE0

M10

IT0

M00

89h Timer/Counter 0 and 1 Modes

8Ah Timer/Counter 0 Low Byte

8Ch Timer/Counter 0 High Byte

8Bh Timer/Counter 1 Low Byte

8Dh Timer/Counter 1 High Byte

A6h Watchdog Timer Reset

GATE1

C/T1#

GATE0

C/T0#

TH0

TL1

TH1

WDTRST

WDTPRG

A7h Watchdog Timer Program

-

WTO2

WTO1

WTO0

33

4109H–8051–01/05

Table 8. MP3 Decoder SFRs

Mnemonic Add Name

7

MPEN

MPANC

-

6

MPBBST

MPREQ

-

5

4

3

2

1

0

MP3CON

MP3STA

MP3STA1

MP3DAT

MP3ANC

MP3VOL

AAh MP3 Control

CRCEN

MSKANC MSKREQ MSKLAY MSKSYN MSKCRC

C8h MP3 Status

ERRLAY ERRSYN ERRCRC

MPFS1

-

MPFS0

-

MPVER

-

AFh MP3 Status 1

-

MPFREQ MPBREQ

ACh MP3 Data

MPD7

AND7

-

MPD6

AND6

-

MPD5

AND5

-

MPD4

AND4

VOL4

MPD3

AND3

VOL3

MPD2

AND2

VOL2

MPD1

AND1

VOL1

MPD0

AND0

VOL0

ADh MP3 Ancillary Data

9Eh MP3 Audio Volume Control Left

MP3 Audio Volume Control

Right

MP3VOR

9Fh

-

VOR4

VOR3

VOR2

VOR1

VOR0

MP3BAS

MP3MED

MP3TRE

MP3CLK

B4h MP3 Audio Bass Control

B5h MP3 Audio Medium Control

B6h MP3 Audio Treble Control

EBh MP3 Clock Divider

-

BAS4

MED4

TRE4

BAS3

MED3

TRE3

BAS2

MED2

TRE2

BAS1

MED1

TRE1

BAS0

MED0

TRE0

MPCD4

MPCD3

MPCD2

MPCD1

MPCD0

Table 9. Audio Interface SFRs

Mnemonic Add Name

7

6

5

4

3

JUST0

-

2

POL

DUP1

-

1

0

AUDCON0

AUDCON1

AUDSTA

AUDDAT

AUDCLK

9Ah Audio Control 0

9Bh Audio Control 1

9Ch Audio Status

JUST4

SRC

SREQ

AUD7

-

JUST3

DRQEN

UDRN

AUD6

-

JUST2

MSREQ

AUBUSY

AUD5

-

JUST1

MUDRN

-

DSIZ

DUP0

-

HLR

AUDEN

-

9Dh Audio Data

AUD4

AUCD4

AUD3

AUCD3

AUD2

AUCD2

AUD1

AUCD1

AUD0

AUCD0

ECh Audio Clock Divider

34

AT8xC51SND1C

4109H–8051–01/05

AT8xC51SND1C

Table 10. USB Controller SFRs

Mnemonic Add Name

7

6

5

4

3

2

1

0

USBCON

USBADDR

USBINT

BCh USB Global Control

USBE

SUSPCLK SDRMWUP

-

UPRSM RMWUPE CONFG

FADDEN

UADD0

SPINT

C6h USB Address

FEN

UADD6

UADD5

UADD4

UADD3

SOFINT

UADD2

UADD1

BDh USB Global Interrupt

BEh USB Global Interrupt Enable

C7h USB Endpoint Number

D4h USB Endpoint X Control

CEh USB Endpoint X Status

D5h USB Endpoint Reset

-

WUPCPU EORINT

-

USBIEN

-

EWUPCPU EEORINT ESOFINT

-

ESPINT

UEPNUM

UEPCONX

UEPSTAX

UEPRST

UEPINT

-

EPNUM1 EPNUM0

EPTYPE1 EPTYPE0

EPEN

NAKIEN NAKOUT

NAKIN

DTGL

EPDIR

DIR

RXOUTB1 STALLRQ TXRDY

STLCRC RXSETUP RXOUTB0 TXCMP

-

EP2RST

EP2INT

EP1RST

EP1INT

EP0RST

EP0INT

F8h USB Endpoint Interrupt

C2h USB Endpoint Interrupt Enable

CFh USB Endpoint X FIFO Data

E2h USB Endpoint X Byte Counter

BAh USB Frame Number Low

BBh USB Frame Number High

EAh USB Clock Divider

-

UEPIEN

-

FDAT6

BYCT6

FNUM6

-

FDAT3

BYCT3

FNUM3

-

EP2INTE EP1INTE EP0INTE

UEPDATX

UBYCTX

UFNUML

UFNUMH

USBCLK

FDAT7

FDAT5

BYCT5

FNUM5

FDAT4

BYCT4

FNUM4

FDAT2

BYCT2

FNUM2

FNUM10

-

FDAT1

BYCT1

FNUM1

FNUM9

FDAT0

BYCT0

FNUM0

FNUM8

-

FNUM7

-

CRCOK CRCERR

-

USBCD1 USBCD0

Table 11. MMC Controller SFRs

Mnemonic Add Name

7

6

5

4

3

MBLOCK

DATDIR

-

2

1

0

MMCON0

MMCON1

MMCON2

MMSTA

E4h MMC Control 0

E5h MMC Control 1

E6h MMC Control 2

DEh MMC Control and Status

E7h MMC Interrupt

DRPTR

BLEN3

MMCEN

-

DTPTR

BLEN2

DCR

CRPTR

BLEN1

CCR

CTPTR

BLEN0

-

DFMT

DATEN

DATD1

CRC7S

F1FI

RFMT

RESPEN

DATD0

RESPFS

F2EI

CRCDIS

CMDEN

FLOWC

CFLCK

F1EI

-

CBUSY

EOCI

CRC16S

EOFI

DATFS

F2FI

MMINT

MCBI

MCBM

MC7

EORI

EORM

MC6

MMMSK

MMCMD

MMDAT

MMCLK

DFh MMC Interrupt Mask

DDh MMC Command

DCh MMC Data

EOCM

MC5

EOFM

MC4

F2FM

MC3

F1FM

MC2

F2EM

MC1

F1EM

MC0

MD7

MD6

MD5

MD4

MD3

MD2

MD1

MD0

EDh MMC Clock Divider

MMCD7

MMCD6

MMCD5

MMCD4

MMCD3

MMCD2

MMCD1

MMCD0

Table 12. IDE Interface SFR

Mnemonic Add Name

7

6

5

4

3

2

1

0

DAT16H

F9h High Order Data Byte

D15

D14

D13

D12

D11

D10

D9

D8

35

4109H–8051–01/05

Table 13. Serial I/O Port SFRs

Mnemonic Add Name

7

6

5

4

3

2

1

0

SCON

SBUF

98h Serial Control

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

99h Serial Data Buffer

B9h Slave Address Mask

A9h Slave Address

SADEN

SADDR

BDRCON

BRL

92h Baud Rate Control

91h Baud Rate Reload

BRR

TBCK

RBCK

SPD

SRC

Table 14. SPI Controller SFRs

Mnemonic Add Name

7

6

5

SSDIS

-

4

3

2

1

0

SPCON

SPSTA

SPDAT

C3h SPI Control

C4h SPI Status

C5h SPI Data

SPR2

SPIF

SPD7

SPEN

WCOL

SPD6

MSTR

MODF

SPD4

CPOL

-

CPHA

-

SPR1

-

SPR0

-

SPD5

SPD3

SPD2

SPD1

SPD0

Table 15. Two Wire Controller SFRs

Mnemonic Add Name

7

6

5

4

3

2

1

0

SSCON

SSSTA

SSDAT

SSADR

93h Synchronous Serial Control

94h Synchronous Serial Status

95h Synchronous Serial Data

96h Synchronous Serial Address

SSCR2

SSC4

SSD7

SSA7

SSPE

SSC3

SSD6

SSA6

SSSTA

SSC2

SSD5

SSA5

SSSTO

SSC1

SSD4

SSA4

SSI

SSAA

0

SSCR1

0

SSCR0

0

SSC0

SSD3

SSA3

SSD2

SSA2

SSD1

SSA1

SSD0

SSGC

Table 16. Keyboard Interface SFRs

Mnemonic Add Name

7

6

KINL2

-

5

KINL1

-

4

KINL0

-

3

2

1

0

KBCON

KBSTA

A3h Keyboard Control

A4h Keyboard Status

KINL3

KPDE

KINM3

KINF3

KINM2

KINF2

KINM1

KINF1

KINM0

KINF0

Table 17. A/D Controller SFRs

Mnemonic Add Name

7

6

5

4

3

2

1

0

ADCON

ADCLK

ADDL

F3h ADC Control

-

ADIDL

ADEN

ADEOC

ADCD4

-

ADSST

ADCD3

-

ADCS

ADCD0

ADAT0

ADAT2

F2h ADC Clock Divider

F4h ADC Data Low Byte

F5h ADC Data High Byte

-

ADCD2

-

ADCD1

ADAT1

ADAT3

-

ADDH

ADAT9

ADAT8

ADAT7

ADAT6

ADAT5

ADAT4

36

AT8xC51SND1C

4109H–8051–01/05

AT8xC51SND1C

Table 18. SFR Addresses and Reset Values

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

UEPINT

0000 0000

DAT16H

XXXX XXXX

NVERS

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

A8h

A0h

98h

90h

88h

80h

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B7h

AFh

A7h

9Fh

97h

8Fh

87h

XXXX XXXX⁽²⁾

B⁽¹⁾

0000 0000

ADCLK

0000 0000

ADCON

0000 0000

ADDL

0000 0000

ADDH

0000 0000

PLLCON

0000 1000

USBCLK

0000 0000

MP3CLK

0000 0000

AUDCLK

0000 0000

MMCLK

0000 0000

PLLNDIV

0000 0000

PLLRDIV

0000 0000

ACC⁽¹⁾

UBYCTLX

0000 0000

MMCON0

0000 0000

MMCON1

0000 0000

MMCON2

0000 0000

MMINT

0000 0011

0000 0000

P5⁽¹⁾

XXXX 1111

MMDAT

1111 1111

MMCMD

1111 1111

MMSTA

0000 0000

MMMSK

1111 1111

PSW⁽¹⁾

0000 0000

FCON⁽³⁾

UEPCONX

1000 0000

UEPRST

0000 0000

1111 0000⁽⁴⁾

MP3STA⁽¹⁾

0000 0001

UEPSTAX

0000 0000

UEPDATX

XXXX XXXX

P4⁽¹⁾

1111 1111

UEPIEN

0000 0000

SPCON

0001 0100

SPSTA

0000 0000

SPDAT

XXXX XXXX

USBADDR

0000 0000

UEPNUM

0000 0000

IPL0⁽¹⁾

X000 0000

SADEN

0000 0000

UFNUML

0000 0000

UFNUMH

0000 0000

USBCON

0000 0000

USBINT

0000 0000

USBIEN

0001 0000

P3⁽¹⁾

1111 1111

IEN1

0000 0000

IPL1

0000 0000

IPH1

0000 0000

MP3BAS

0000 0000

MP3MED

0000 0000

MP3TRE

0000 0000

IPH0

X000 0000

IEN0⁽¹⁾

0000 0000

SADDR

0000 0000

MP3CON

0011 1111

MP3DAT

0000 0000

MP3ANC

0000 0000

MP3STA1

0100 0001

P2⁽¹⁾

1111 1111

AUXR1

XXXX 00X0

KBCON

0000 1111

KBSTA

0000 0000

WDTRST

XXX XXXX

WDTPRG

XXXX X000

SCON

0000 0000

SBUF

XXXX XXXX

AUDCON0

0000 1000

AUDCON1

1011 0010

AUDSTA

1100 0000

AUDDAT

1111 1111

MP3VOL

0000 0000

MP3VOR

0000 0000

P1⁽¹⁾

1111 1111

BRL

0000 0000

BDRCON

XXX0 0000

SSCON

0000 0000

SSSTA

1111 1000

SSDAT

1111 1111

SSADR

1111 1110

TCON⁽¹⁾

TMOD

0000 0000

TL0

0000 0000

TL1

0000 0000

TH0

0000 0000

TH1

0000 0000

AUXR

X000 1101

CKCON

0000 000X⁽⁵⁾

0000 0000

P0⁽¹⁾

1111 1111

SP

0000 0111

DPL

0000 0000

DPH

0000 0000

PCON

00XX 0000

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

Reserved

Notes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.

2. NVERS reset value depends on the silicon version: 1000 0100 for AT89C51SND1C product and 0000 0001 for AT83SND1C

product.

3. FCON register is only available in AT89C51SND1C product.

4. FCON reset value is 00h in case of reset with hardware condition.

5. CKCON reset value depends on the X2B bit (programmed or unprogrammed) in the Hardware Byte.

37

4109H–8051–01/05

10. Interrupt System

The AT8xC51SND1C, like other control-oriented computer architectures, employ a pro-

gram interrupt method. This operation branches to a subroutine and performs some

service in response to the interrupt. When the subroutine completes, execution resumes

at the point where the interrupt occurred. Interrupts may occur as a result of internal

AT8xC51SND1C activity (e.g., timer overflow) or at the initiation of electrical signals

external to the microcontroller (e.g., keyboard). In all cases, interrupt operation is pro-

grammed by the system designer, who determines priority of interrupt service relative to

normal code execution and other interrupt service routines. All of the interrupt sources

are enabled or disabled by the system designer and may be manipulated dynamically.

A typical interrupt event chain occurs as follows:

•

An internal or external device initiates an interrupt-request signal. The

AT8xC51SND1C, latches this event into a flag buffer.

The priority of the flag is compared to the priority of other interrupts by the interrupt

handler. A high priority causes the handler to set an interrupt flag.

This signals the instruction execution unit to execute a context switch. This context

switch breaks the current flow of instruction sequences. The execution unit

completes the current instruction prior to a save of the program counter (PC) and

reloads the PC with the start address of a software service routine.

•

The software service routine executes assigned tasks and as a final activity

performs a RETI (return from interrupt) instruction. This instruction signals

completion of the interrupt, resets the interrupt-in-progress priority and reloads the

program counter. Program operation then continues from the original point of

interruption.

Table 1. Interrupt System Signals

Signal

Name

Alternate

Function

Type Description

External Interrupt 0

See section "External Interrupts", page 41.

INT0

I

P3.2

P3.3

External Interrupt 1

See section “External Interrupts”, page 41.

INT1

Keyboard Interrupt Inputs

See section “Keyboard Interface”, page 182.

KIN3:0

P1.3:0

Six interrupt registers are used to control the interrupt system. 2 8-bit registers are used

to enable separately the interrupt sources: IEN0 and IEN1 registers (see Table 7 and

Table 8).

Four 8-bit registers are used to establish the priority level of the different sources: IPH0,

IPL0, IPH1 and IPL1 registers (see Table 9 to Table 12).

10.2 Interrupt System

Priorities

Each of the interrupt sources on the AT8xC51SND1C can be individually programmed

to one of four priority levels. This is accomplished by one bit in the Interrupt Priority High

registers (IPH0 and IPH1) and one bit in the Interrupt Priority Low registers (IPL0 and

IPL1). This provides each interrupt source four possible priority levels according to

Table 3.

38

AT8xC51SND1C

4109H–8051–01/05

AT8xC51SND1C

Table 3. Priority Levels

IPHxx

IPLxx

Priority Level

0

1

0

1

0

1

0 Lowest

1

2

3 Highest

A low-priority interrupt is always interrupted by a higher priority interrupt but not by

another interrupt of lower or equal priority. Higher priority interrupts are serviced before

lower priority interrupts. The response to simultaneous occurrence of equal priority inter-

rupts is determined by an internal hardware polling sequence detailed in Table 4. Thus,

within each priority level there is a second priority structure determined by the polling

sequence. The interrupt control system is shown in Figure 23.

Table 4. Priority within Same Level

Interrupt Request Flag

Interrupt Address

Vectors

Cleared by Hardware

(H) or by Software (S)

Interrupt Name

INT0

Priority Number

0 (Highest Priority)

C:0003h

C:000Bh

C:0013h

C:001Bh

C:0023h

C:002Bh

C:0033h

C:003Bh

C:0043h

C:004Bh

C:0053h

C:005Bh

C:0063h

C:006Bh

C:0073h

H if edge, S if level

Timer 0

1

H

INT1

2

H if edge, S if level

Timer 1

3

H

S

-

Serial Port

MP3 Decoder

Audio Interface

MMC Interface

Two Wire Controller

SPI Controller

A to D Converter

Keyboard

4

5

6

7

8

9

10

11

Reserved

12

13

USB

S

-

Reserved

14 (Lowest Priority)

39

4109H–8051–01/05

Figure 23. Interrupt Control System

Highest

Priority

00

01

10

11

External

Interrupts

INT0

Interrupt 0

EX0

IEN0.0

00

01

10

11

Timer 0

ET0

IEN0.1

00

01

10

11

External

Interrupt 1

INT1

EX1

IEN0.2

00

01

10

11

Timer 1

ET1

IEN0.3

00

01

10

11

TXD

Serial

Port

RXD

ES

IEN0.4

00

01

10

11

MP3

Decoder

EMP3

IEN0.5

00

01

10

11

Audio

Interface

EAUD

IEN0.6

00

01

10

11

MCLK

MDAT

MCMD

MMC

Controller

EMMC

IEN1.0

00

01

10

11

SCL

TWI

Controller

SDA

EI2C

IEN1.1

00

01

10

11

SCK

SI

SO

SPI

Controller

ESPI

IEN1.2

00

01

10

11

A to D

Converter

AIN1:0

EADC

IEN1.3

00

01

10

11

KIN3:0

Keyboard

EKB

IEN1.4

00

01

10

11

D+

D-

USB

Controller

EUSB

IEN1.6

EA

IEN0.7

IPH/L

Interrupt Enable

Priority Enable

Lowest Priority Interrupts

40

AT8xC51SND1C

4109H–8051–01/05

AT8xC51SND1C

10.5 External Interrupts

10.5.1 INT1:0 Inputs

External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to

be level-triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn, n = 0 or 1) in

TCON register as shown in Figure 24. If ITn = 0, INTn is triggered by a low level at the

pin. If ITn = 1, INTn is negative-edge triggered. External interrupts are enabled with bits

EX0 and EX1 (EXn, n = 0 or 1) in IEN0. Events on INTn set the interrupt request flag IEn

in TCON register. If the interrupt is edge-triggered, the request flag is cleared by hard-

ware when vectoring to the interrupt service routine. If the interrupt is level-triggered, the

interrupt service routine must clear the request flag and the interrupt must be deas-

serted before the end of the interrupt service routine.

INT0 and INT1 inputs provide both the capability to exit from Power-down mode on low

level signals as detailed in section “Exiting Power-down Mode”, page 50.

Figure 24. INT1:0 Input Circuitry

0

1

INT0/1

Interrupt

Request

INT0/1

IE0/1

TCON.1/3

EX0/1

IEN0.0/2

IT0/1

TCON.0/2

10.5.2 KIN3:0 Inputs

10.5.3 Input Sampling

External interrupts KIN0 to KIN3 provide the capability to connect a matrix keyboard. For

detailed information on these inputs, refer to section “Keyboard Interface”, page 182.

External interrupt pins (INT1:0 and KIN3:0) are sampled once per peripheral cycle (6

peripheral clock periods) (see Figure 25). A level-triggered interrupt pin held low or high

for more than 6 peripheral clock periods (12 oscillator in standard mode or 6 oscillator

clock periods in X2 mode) guarantees detection. Edge-triggered external interrupts

must hold the request pin low for at least 6 peripheral clock periods.

Figure 25. Minimum Pulse Timings

Level-Triggered Interrupt

> 1 Peripheral Cycle

1 cycle

Edge-Triggered Interrupt

> 1 Peripheral Cycle

1 cycle

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4109H–8051–01/05

10.6 Registers

Table 7. IEN0 Register

IEN0 (S:A8h) – Interrupt Enable Register 0

7

6

5

4

3

2

1

0

EA

EAUD

EMP3

ES

ET1

EX1

ET0

EX0

Bit

Number

Mnemonic Description

Enable All Interrupt Bit

Set to enable all interrupts.

Clear to disable all interrupts.

7

EA

If EA = 1, each interrupt source is individually enabled or disabled by setting or

clearing its interrupt enable bit.

Audio Interface Interrupt Enable Bit

Set to enable audio interface interrupt.

Clear to disable audio interface interrupt.

6

5

4

3

2

1

0

EAUD

EMP3

ES

MP3 Decoder Interrupt Enable Bit

Set to enable MP3 decoder interrupt.

Clear to disable MP3 decoder interrupt.

Serial Port Interrupt Enable Bit

Set to enable serial port interrupt.

Clear to disable serial port interrupt.

Timer 1 Overflow Interrupt Enable Bit

Set to enable timer 1 overflow interrupt.

Clear to disable timer 1 overflow interrupt.

ET1

External Interrupt 1 Enable bit

Set to enable external interrupt 1.

Clear to disable external interrupt 1.

EX1

ET0

Timer 0 Overflow Interrupt Enable Bit

Set to enable timer 0 overflow interrupt.

Clear to disable timer 0 overflow interrupt.

External Interrupt 0 Enable Bit

Set to enable external interrupt 0.

Clear to disable external interrupt 0.

EX0

Reset Value = 0000 0000b

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Table 8. IEN1 Register

IEN1 (S:B1h) – Interrupt Enable Register 1

7

-

6

5

-

4

3

2

1

0

EUSB

EKB

EADC

ESPI

EI2C

EMMC

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

-

The value read from this bit is always 0. Do not set this bit.

USB Interface Interrupt Enable Bit

Set this bit to enable USB interrupts.

Clear this bit to disable USB interrupts.

EUSB

-

Reserved

The value read from this bit is always 0. Do not set this bit.

Keyboard Interface Interrupt Enable Bit

Set to enable Keyboard interrupt.

EKB

Clear to disable Keyboard interrupt.

A to D Converter Interrupt Enable Bit

Set to enable ADC interrupt.

Clear to disable ADC interrupt.

3

2

1

0

EADC

ESPI

SPI Controller Interrupt Enable Bit

Set to enable SPI interrupt.

Clear to disable SPI interrupt.

Two Wire Controller Interrupt Enable Bit

Set to enable Two Wire interrupt.

Clear to disable Two Wire interrupt.

EI2C

MMC Interface Interrupt Enable Bit

Set to enable MMC interrupt.

EMMC

Clear to disable MMC interrupt.

Reset Value = 0000 0000b

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4109H–8051–01/05

Table 9. IPH0 Register

IPH0 (S:B7h) – Interrupt Priority High Register 0

7

-

6

5

4

3

2

1

0

IPHAUD

IPHMP3

IPHS

IPHT1

IPHX1

IPHT0

IPHX0

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Audio Interface Interrupt Priority Level MSB

Refer to Table 3 for priority level description.

IPHAUD

IPHMP3

IPHS

MP3 Decoder Interrupt Priority Level MSB

Refer to Table 3 for priority level description.

Serial Port Interrupt Priority Level MSB

Refer to Table 3 for priority level description.

Timer 1 Interrupt Priority Level MSB

Refer to Table 3 for priority level description.

IPHT1

IPHX1

IPHT0

IPHX0

External Interrupt 1 Priority Level MSB

Refer to Table 3 for priority level description.

Timer 0 Interrupt Priority Level MSB

Refer to Table 3 for priority level description.

External Interrupt 0 Priority Level MSB

Refer to Table 3 for priority level description.

Reset Value = X000 0000b

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Table 10. IPH1 Register

IPH1 (S:B3h) – Interrupt Priority High Register 1

7

-

6

5

-

4

3

2

1

0

IPHUSB

IPHKB

IPHADC

IPHSPI

IPHI2C

IPHMMC

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is always 0. Do not set this bit.

USB Interrupt Priority Level MSB

Refer to Table 3 for priority level description.

IPHUSB

-

Reserved

The value read from this bit is always 0. Do not set this bit.

Keyboard Interrupt Priority Level MSB

Refer to Table 3 for priority level description.

IPHKB

IPHADC

IPHSPI

IPHI2C

IPHMMC

A to D Converter Interrupt Priority Level MSB

Refer to Table 3 for priority level description.

SPI Interrupt Priority Level MSB

Refer to Table 3 for priority level description.

Two Wire Controller Interrupt Priority Level MSB

Refer to Table 3 for priority level description.

MMC Interrupt Priority Level MSB

Refer to Table 3 for priority level description.

Reset Value = 0000 0000b

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4109H–8051–01/05

Table 11. IPL0 Register

IPL0 (S:B8h) - Interrupt Priority Low Register 0

7

-

6

5

4

3

2

1

0

IPLAUD

IPLMP3

IPLS

IPLT1

IPLX1

IPLT0

IPLX0

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Audio Interface Interrupt Priority Level LSB

Refer to Table 3 for priority level description.

IPLAUD

IPLMP3

IPLS

MP3 Decoder Interrupt Priority Level LSB

Refer to Table 3 for priority level description.

Serial Port Interrupt Priority Level LSB

Refer to Table 3 for priority level description.

Timer 1 Interrupt Priority Level LSB

Refer to Table 3 for priority level description.

IPLT1

IPLX1

IPLT0

IPLX0

External Interrupt 1 Priority Level LSB

Refer to Table 3 for priority level description.

Timer 0 Interrupt Priority Level LSB

Refer to Table 3 for priority level description.

External Interrupt 0 Priority Level LSB

Refer to Table 3 for priority level description.

Reset Value = X000 0000b

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Table 12. IPL1 Register

IPL1 (S:B2h) – Interrupt Priority Low Register 1

7

-

6

5

-

4

3

2

1

0

IPLUSB

IPLKB

IPLADC

IPLSPI

IPLI2C

IPLMMC

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is always 0. Do not set this bit.

USB Interrupt Priority Level LSB

Refer to Table 3 for priority level description.

IPLUSB

-

Reserved

The value read from this bit is always 0. Do not set this bit.

Keyboard Interrupt Priority Level LSB

Refer to Table 3 for priority level description.

IPLKB

IPLADC

IPLSPI

IPLI2C

IPLMMC

A to D Converter Interrupt Priority Level LSB

Refer to Table 3 for priority level description.

SPI Interrupt Priority Level LSB

Refer to Table 3 for priority level description.

Two Wire Controller Interrupt Priority Level LSB

Refer to Table 3 for priority level description.

MMC Interrupt Priority Level LSB

Refer to Table 3 for priority level description.

Reset Value = 0000 0000b

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4109H–8051–01/05

11. Power

Management

2 power reduction modes are implemented in the AT8xC51SND1C: the Idle mode and

the Power-down mode. These modes are detailed in the following sections. In addition

to these power reduction modes, the clocks of the core and peripherals can be dynami-

cally divided by 2 using the X2 mode detailed in section “X2 Feature”, page 12.

11.1 Reset

In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an

high level has to be applied on the RST pin. A bad level leads to a wrong initialization of

the internal registers like SFRs, Program Counter… and to unpredictable behavior of

the microcontroller. A proper device reset initializes the AT8xC51SND1C and vectors

the CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset

by simply connecting an external capacitor to V_DDas shown in Figure 26. A warm reset

can be applied either directly on the RST pin or indirectly by an internal reset source

such as the watchdog timer. Resistor value and input characteristics are discussed in

the Section “DC Characteristics” of the AT8xC51SND1C datasheet. The status of the

Port pins during reset is detailed in Table 2.

Figure 26. Reset Circuitry and Power-On Reset

VDD

From Internal

Reset Source

P

VDD

To CPU Core

and Peripherals

RST

+

RST

VSS

RST input circuitry

Power-on Reset

Table 2. Pin Conditions in Special Operating Modes

Mode

Port 0

Floating

Data

Port 1

High

Port 2

High

Port 3

High

Port 4

High

Port 5

MMC

Floating

Data

Audio

1

Reset

Idle

High

Data

Power-down

Data

Note:

1. Refer to section “Audio Output Interface”, page 75.

11.2.1 Cold Reset

2 conditions are required before enabling a CPU start-up:

•

V

_DDmust reach the specified V_DDrange

The level on X1 input pin must be outside the specification (V_IH, V_IL)

If one of these 2 conditions are not met, the microcontroller does not start correctly and

can execute an instruction fetch from anywhere in the program space. An active level

applied on the RST pin must be maintained till both of the above conditions are met. A

reset is active when the level V_IH1is reached and when the pulse width covers the

period of time where V_DDand the oscillator are not stabilized. 2 parameters have to be

taken into account to determine the reset pulse width:

•

V

_DDrise time,

Oscillator startup time.

To determine the capacitor value to implement, the highest value of these 2 parameters

has to be chosen. Table 3 gives some capacitor values examples for a minimum R_RSTof

50 KΩ and different oscillator startup and V_DDrise times.

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Table 3. Minimum Reset Capacitor Value for a 50 kΩ Pull-down Resistor⁽¹⁾

VDD Rise Time

10 ms

Oscillator

Start-Up Time

1 ms

820 nF

2.7 µF

100 ms

12 µF

5 ms

1.2 µF

20 ms

3.9 µF

12 µF

Note:

1. These values assume V_DDstarts from 0V to the nominal value. If the time between 2

on/off sequences is too fast, the power-supply de-coupling capacitors may not be

fully discharged, leading to a bad reset sequence.

11.3.1 Warm Reset

To achieve a valid reset, the reset signal must be maintained for at least 2 machine

cycles (24 oscillator clock periods) while the oscillator is running. The number of clock

periods is mode independent (X2 or X1).

11.3.2 Watchdog Reset

As detailed in section “Watchdog Timer”, page 61, the WDT generates a 96-clock period

pulse on the RST pin. In order to properly propagate this pulse to the rest of the applica-

tion in case of external capacitor or power-supply supervisor circuit, a 1 kΩ resistor must

be added as shown in Figure 27.

Figure 27. Reset Circuitry for WDT Reset-out Usage

VDD

From WDT

+

Reset Source

P

RST

To CPU Core

and Peripherals

VDD

1K

RST

VSS

To Other

On-board

VSS

Circuitry

11.4 Reset

Recommendation to

Prevent Flash Corruption

An example of bad initialization situation may occur in an instance where the bit

ENBOOT in AUXR1 register is initialized from the hardware bit BLJB upon reset. Since

this bit allows mapping of the bootloader in the code area, a reset failure can be critical.

If one wants the ENBOOT cleared in order to unmap the boot from the code area (yet

due to a bad reset) the bit ENBOOT in SFRs may be set. If the value of Program

Counter is accidently in the range of the boot memory addresses then a Flash access

(write or erase) may corrupt the Flash on-chip memory.

It is recommended to use an external reset circuitry featuring power supply monitoring to

prevent system malfunction during periods of insufficient power supply voltage (power

supply failure, power supply switched off).

11.5 Idle Mode

Idle mode is a power reduction mode that reduces the power consumption. In this mode,

program execution halts. Idle mode freezes the clock to the CPU at known states while

the peripherals continue to be clocked (refer to section “Oscillator”, page 12). The CPU

status before entering Idle mode is preserved, i.e., the program counter and program

status word register retain their data for the duration of Idle mode. The contents of the

SFRs and RAM are also retained. The status of the Port pins during Idle mode is

detailed in Table 2.

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4109H–8051–01/05

11.5.1 Entering Idle Mode

11.5.2 Exiting Idle Mode

To enter Idle mode, the user must set the IDL bit in PCON register (see Table 8). The

AT8xC51SND1C enters Idle mode upon execution of the instruction that sets IDL bit.

The instruction that sets IDL bit is the last instruction executed.

Note:

If IDL bit and PD bit are set simultaneously, the AT8xC51SND1C enter Power-down

mode. Then it does not go in Idle mode when exiting Power-down mode.

There are 2 ways to exit Idle mode:

1. Generate an enabled interrupt.

–

Hardware clears IDL bit in PCON register which restores the clock to the

CPU. Execution resumes with the interrupt service routine. Upon completion

of the interrupt service routine, program execution resumes with the

instruction immediately following the instruction that activated Idle mode.

The general-purpose flags (GF1 and GF0 in PCON register) may be used to

indicate whether an interrupt occurred during normal operation or during Idle

mode. When Idle mode is exited by an interrupt, the interrupt service routine

may examine GF1 and GF0.

2. Generate a reset.

–

A logic high on the RST pin clears IDL bit in PCON register directly and

asynchronously. This restores the clock to the CPU. Program execution

momentarily resumes with the instruction immediately following the

instruction that activated the Idle mode and may continue for a number of

clock cycles before the internal reset algorithm takes control. Reset

initializes the AT8xC51SND1C and vectors the CPU to address C:0000h.

Note:

During the time that execution resumes, the internal RAM cannot be accessed; however,

it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port

pins, the instruction immediately following the instruction that activated Idle mode should

not write to a Port pin or to the external RAM.

11.6 Power-down Mode

The Power-down mode places the AT8xC51SND1C in a very low power state. Power-

down mode stops the oscillator and freezes all clocks at known states (refer to the Sec-

tion "Oscillator", page 12). The CPU status prior to entering Power-down mode is

preserved, i.e., the program counter, program status word register retain their data for

the duration of Power-down mode. In addition, the SFRs and RAM contents are pre-

served. The status of the Port pins during Power-down mode is detailed in Table 2.

Note:

V_DDmay be reduced to as low as V_RETduring Power-down mode to further reduce power

dissipation. Notice, however, that V_DDis not reduced until Power-down mode is invoked.

11.6.1 Entering Power-down

Mode

To enter Power-down mode, set PD bit in PCON register. The AT8xC51SND1C enters

the Power-down mode upon execution of the instruction that sets PD bit. The instruction

that sets PD bit is the last instruction executed.

11.6.2 Exiting Power-down

Mode

If V_DDwas reduced during the Power-down mode, do not exit Power-down mode until

V

_DDis restored to the normal operating level.

There are 2 ways to exit the Power-down mode:

1. Generate an enabled external interrupt.

–

The AT8xC51SND1C provides capability to exit from Power-down using

INT0, INT1, and KIN3:0 inputs. In addition, using KIN input provides high or

low level exit capability (see section “Keyboard Interface”, page 182).

Hardware clears PD bit in PCON register which starts the oscillator and

restores the clocks to the CPU and peripherals. Using INTn input, execution

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resumes when the input is released (see Figure 28) while using KINx input,

execution resumes after counting 1024 clock ensuring the oscillator is

restarted properly (see Figure 29). This behavior is necessary for decoding

the key while it is still pressed. In both cases, execution resumes with the

interrupt service routine. Upon completion of the interrupt service routine,

program execution resumes with the instruction immediately following the

instruction that activated Power-down mode.

Note:

1. The external interrupt used to exit Power-down mode must be configured as level

sensitive (INT0 and INT1) and must be assigned the highest priority. In addition, the

duration of the interrupt must be long enough to allow the oscillator to stabilize. The

execution will only resume when the interrupt is deasserted.

2. Exit from power-down by external interrupt does not affect the SFRs nor the internal

RAM content.

Figure 28. Power-down Exit Waveform Using INT1:0

INT1:0

OSC

Oscillator Restart Phase

Active phase

Power-down Phase

Active Phase

Figure 29. Power-down Exit Waveform Using KIN3:0

KIN3:0¹

OSC

Power-down Phase

Active phase

1024 clock count

Active phase

Note:

1. KIN3:0 can be high or low-level triggered.

2. Generate a reset.

–

A logic high on the RST pin clears PD bit in PCON register directly and

asynchronously. This starts the oscillator and restores the clock to the CPU

and peripherals. Program execution momentarily resumes with the

instruction immediately following the instruction that activated Power-down

mode and may continue for a number of clock cycles before the internal

reset algorithm takes control. Reset initializes the AT8xC51SND1C and

vectors the CPU to address 0000h.

Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; how-

ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at

the Port pins, the instruction immediately following the instruction that activated the

Power-down mode should not write to a Port pin or to the external RAM.

2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal

RAM content.

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4109H–8051–01/05

11.7 Registers

Table 8. PCON Register

PCON (S:87h) – Power Configuration Register

7

6

5

-

4

-

3

2

1

0

SMOD1

SMOD0

GF1

GF0

PD

IDL

Bit

Number

Mnemonic Description

Serial Port Mode Bit 1

Set to select double baud rate in mode 1,2 or 3.

7

6

SMOD1

Serial Port Mode Bit 0

SMOD0 Set to select FE bit in SCON register.

Clear to select SM0 bit in SCON register.

Reserved

5 - 4

3

-

The value read from these bits is indeterminate. Do not set these bits.

General-Purpose Flag 1

One use is to indicate whether an interrupt occurred during normal operation or

during Idle mode.

GF1

GF0

General-Purpose Flag 0

One use is to indicate whether an interrupt occurred during normal operation or

during Idle mode.

2

1

Power-Down Mode Bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Power-down mode.

If IDL and PD are both set, PD takes precedence.

PD

Idle Mode Bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Idle mode.

0

IDL

If IDL and PD are both set, PD takes precedence.

Reset Value = 00XX 0000b

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12. Timers/Counters

The AT8xC51SND1C implement 2 general-purpose, 16-bit Timers/Counters. They are

identified as Timer 0 and Timer 1, and can be independently configured to operate in a

variety of modes as a Timer or as an event Counter. When operating as a Timer, the

Timer/Counter runs for a programmed length of time, then issues an interrupt request.

When operating as a Counter, the Timer/Counter counts negative transitions on an

external pin. After a preset number of counts, the Counter issues an interrupt request.

The various operating modes of each Timer/Counter are described in the following

sections.

12.1 Timer/Counter

Operations

For instance, a basic operation is Timer registers THx and TLx (x = 0, 1) connected in

cascade to form a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see

Table 7) turns the Timer on by allowing the selected input to increment TLx. When TLx

overflows it increments THx; when THx overflows it sets the Timer overflow flag (TFx) in

TCON register. Setting the TRx does not clear the THx and TLx Timer registers. Timer

registers can be accessed to obtain the current count or to enter preset values. They

can be read at any time but TRx bit must be cleared to preset their values, otherwise,

the behavior of the Timer/Counter is unpredictable.

The C/Tx# control bit selects Timer operation or Counter operation by selecting the

divided-down peripheral clock or external pin Tx as the source for the counted signal.

TRx bit must be cleared when changing the mode of operation, otherwise the behavior

of the Timer/Counter is unpredictable.

For Timer operation (C/Tx# = 0), the Timer register counts the divided-down peripheral

clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock

periods). The Timer clock rate is F_PER/6, i.e., F_OSC/12 in standard mode or F_OSC/6 in X2

mode.

For Counter operation (C/Tx# = 1), the Timer register counts the negative transitions on

the Tx external input pin. The external input is sampled every peripheral cycles. When

the sample is high in one cycle and low in the next one, the Counter is incremented.

Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition,

the maximum count rate is F_PER/12, i.e., F_OSC/24 in standard mode or F_OSC/12 in X2

mode. There are no restrictions on the duty cycle of the external input signal, but to

ensure that a given level is sampled at least once before it changes, it should be held for

at least one full peripheral cycle.

12.2 Timer Clock

Controller

As shown in Figure 30, the Timer 0 (FT0) and Timer 1 (FT1) clocks are derived from

either the peripheral clock (F_PER) or the oscillator clock (F_OSC) depending on the T0X2

and T1X2 bits in CKCON register. These clocks are issued from the Clock Controller

block as detailed in Section “Clock Controller”, page 12. When T0X2 or T1X2 bit is set,

the Timer 0 or Timer 1 clock frequency is fixed and equal to the oscillator clock fre-

quency divided by 2. When cleared, the Timer clock frequency is equal to the oscillator

clock frequency divided by 2 in standard mode or to the oscillator clock frequency in X2

mode.

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4109H–8051–01/05

Figure 30. Timer 0 and Timer 1 Clock Controller and Symbols

PER

CLOCK

PER

CLOCK

0

1

Timer 0 Clock

Timer 1 Clock

1

OSC

CLOCK

OSC

CLOCK

÷ 2

T0X2

CKCON.1

T1X2

CKCON.2

TIM0

TIM1

CLOCK

Timer 0 Clock Symbol

Timer 1 Clock Symbol

12.3 Timer 0

Timer 0 functions as either a Timer or event Counter in four modes of operation.

Figure 31 through Figure 37 show the logical configuration of each mode.

Timer 0 is controlled by the four lower bits of TMOD register (see Table 8) and bits 0, 1,

4 and 5 of TCON register (see Table 7). TMOD register selects the method of Timer gat-

ing (GATE0), Timer or Counter operation (C/T0#) and mode of operation (M10 and

M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control

bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).

For normal Timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by

the selected input. Setting GATE0 and TR0 allows external pin INT0 to control Timer

operation.

Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter-

rupt request.

It is important to stop Timer/Counter before changing mode.

12.3.1 Mode 0 (13-bit Timer)

Mode 0 configures Timer 0 as a 13-bit Timer which is set up as an 8-bit Timer (TH0 reg-

ister) with a modulo 32 prescaler implemented with the lower five bits of TL0 register

(see Figure 31). The upper three bits of TL0 register are indeterminate and should be

ignored. Prescaler overflow increments TH0 register. Figure 32 gives the overflow

period calculation formula.

Figure 31. Timer/Counter x (x = 0 or 1) in Mode 0

TIMx

CLOCK

Timer x

Interrupt

Request

÷ 6

0

1

TLx

(5 Bits)

THx

(8 Bits)

Overflow

TFx

TCON reg

Tx

C/Tx#

TMOD Reg

INTx

GATEx

TMOD Reg

TRx

TCON Reg

Figure 32. Mode 0 Overflow Period Formula

6 ⋅ (16384 – (THx, TLx))

TFx_PER

=

F_TIMx

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12.3.2 Mode 1 (16-bit Timer)

Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in

cascade (see Figure 33). The selected input increments TL0 register. Figure 34 gives

the overflow period calculation formula when in timer mode.

Figure 33. Timer/Counter x (x = 0 or 1) in Mode 1

TIMx

CLOCK

Timer x

Interrupt

Request

÷ 6

0

1

Overflow

THx

(8 bits)

TLx

(8 bits)

TFx

TCON Reg

Tx

C/Tx#

TMOD Reg

INTx

GATEx

TMOD Reg

TRx

TCON Reg

Figure 34. Mode 1 Overflow Period Formula

6 ⋅ (65536 – (THx, TLx))

TFx_PER

=

F_TIMx

12.3.3 Mode 2 (8-bit Timer with Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads

Auto-Reload)

from TH0 register (see Table 9). TL0 overflow sets TF0 flag in TCON register and

reloads TL0 with the contents of TH0, which is preset by software. When the interrupt

request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next

reload value may be changed at any time by writing it to TH0 register. Figure 36 gives

the autoreload period calculation formula when in timer mode.

Figure 35. Timer/Counter x (x = 0 or 1) in Mode 2

TIMx

CLOCK

Timer x

Interrupt

Request

÷ 6

0

1

Overflow

TLx

(8 bits)

TFx

TCON reg

Tx

C/Tx#

TMOD reg

INTx

THx

(8 bits)

GATEx

TMOD reg

TRx

TCON reg

Figure 36. Mode 2 Autoreload Period Formula

6 ⋅ (256 – THx)

TFx_PER

=

F_TIMx

12.3.4 Mode 3 (2 8-bit Timers) Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit

Timers (see Figure 37). This mode is provided for applications requiring an additional 8-

bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg-

ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a

Timer function (counting F_TF1/6) and takes over use of the Timer 1 interrupt (TF1) and

run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode

55

4109H–8051–01/05

3. Figure 36 gives the autoreload period calculation formulas for both TF0 and TF1

flags.

Figure 37. Timer/Counter 0 in Mode 3: 2 8-bit Counters

TIM0

CLOCK

Timer 0

Interrupt

Request

÷ 6

0

1

Overflow

TL0

(8 bits)

TF0

TCON.5

T0

C/T0#

TMOD.2

INT0

GATE0

TMOD.3

TR0

TCON.4

Timer 1

Interrupt

Request

Overflow

TIM0

CLOCK

TH0

(8 bits)

÷ 6

TF1

TCON.7

TR1

TCON.6

Figure 38. Mode 3 Overflow Period Formula

6 ⋅ (256 – TH0)

6 ⋅ (256 – TL0)

TF1_PER

=

TF0_PER

=

F_TIM0

12.4 Timer 1

Timer 1 is identical to Timer 0 except for Mode 3 which is a hold-count mode. The fol-

lowing comments help to understand the differences:

•

Timer 1 functions as either a Timer or event Counter in three modes of operation.

Figure 31 through Figure 35 show the logical configuration for modes 0, 1, and 2.

Timer 1’s mode 3 is a hold-count mode.

•

Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 8) and

bits 2, 3, 6 and 7 of TCON register (see Figure 7). TMOD register selects the

method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of

operation (M11 and M01). TCON register provides Timer 1 control functions:

overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type

control bit (IT1).

•

Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best

suited for this purpose.

For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented

by the selected input. Setting GATE1 and TR1 allows external pin INT1 to control

Timer operation.

•

Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating

an interrupt request.

When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit

(TR1). For this situation, use Timer 1 only for applications that do not require an

interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in

and out of mode 3 to turn it off and on.

•

It is important to stop the Timer/Counter before changing modes.

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12.4.1 Mode 0 (13-bit Timer)

12.4.2 Mode 1 (16-bit Timer)

Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-

ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register

(see Figure 31). The upper 3 bits of TL1 register are ignored. Prescaler overflow incre-

ments TH1 register.

Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in

cascade (see Figure 33). The selected input increments TL1 register.

12.4.3 Mode 2 (8-bit Timer with Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from

Auto-Reload)

TH1 register on overflow (see Figure 35). TL1 overflow sets TF1 flag in TCON register

and reloads TL1 with the contents of TH1, which is preset by software. The reload

leaves TH1 unchanged.

12.4.4 Mode 3 (Halt)

Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt

Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.

12.5 Interrupt

Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This

flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer

interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This

assumes interrupts are globally enabled by setting EA bit in IEN0 register.

Figure 39. Timer Interrupt System

Timer 0

Interrupt Request

TF0

TCON.5

ET0

IEN0.1

Timer 1

Interrupt Request

TF1

TCON.7

ET1

IEN0.3

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12.6 Registers

Table 7. TCON Register

TCON (S:88h) – Timer/Counter Control Register

7

6

5

4

3

2

1

0

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit

Number

Mnemonic Description

Timer 1 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.

7

6

5

4

3

2

1

0

TF1

TR1

TF0

TR0

IE1

Timer 1 Run Control Bit

Clear to turn off Timer/Counter 1.

Set to turn on Timer/Counter 1.

Timer 0 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.

Timer 0 Run Control Bit

Clear to turn off Timer/Counter 0.

Set to turn on Timer/Counter 0.

Interrupt 1 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (see IT1).

Set by hardware when external interrupt is detected on INT1 pin.

Interrupt 1 Type Control Bit

Clear to select low level active (level triggered) for external interrupt 1 (INT1).

Set to select falling edge active (edge triggered) for external interrupt 1.

IT1

Interrupt 0 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (see IT0).

Set by hardware when external interrupt is detected on INT0 pin.

IE0

Interrupt 0 Type Control Bit

Clear to select low level active (level triggered) for external interrupt 0 (INT0).

Set to select falling edge active (edge triggered) for external interrupt 0.

IT0

Reset Value = 0000 0000b

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Table 8. TMOD Register

TMOD (S:89h) – Timer/Counter Mode Control Register

7

6

5

4

3

2

1

0

GATE1

C/T1#

M11

M01

GATE0

C/T0#

M10

M00

Bit

Number Mnemonic Description

Timer 1 Gating Control Bit

Clear to enable Timer 1 whenever TR1 bit is set.

7

GATE1

Set to enable Timer 1 only while INT1 pin is high and TR1 bit is set.

Timer 1 Counter/Timer Select Bit

6

5

C/T1#

M11

Clear for Timer operation: Timer 1 counts the divided-down system clock.

Set for Counter operation: Timer 1 counts negative transitions on external pin T1.

Timer 1 Mode Select Bits

M11 M01 Operating mode

0

1

0

1

0

Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1).

Mode 1: 16-bit Timer/Counter.

4

3

M01

Mode 2: 8-bit auto-reload Timer/Counter (TL1).⁽¹⁾

1

Mode 3: Timer 1 halted. Retains count.

Timer 0 Gating Control Bit

Clear to enable Timer 0 whenever TR0 bit is set.

Set to enable Timer/Counter 0 only while INT0 pin is high and TR0 bit is set.

GATE0

Timer 0 Counter/Timer Select Bit

2

1

C/T0#

M10

Clear for Timer operation: Timer 0 counts the divided-down system clock.

Set for Counter operation: Timer 0 counts negative transitions on external pin T0.

Timer 0 Mode Select Bit

M10 M00 Operating mode

0

1

0

1

0

Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0).

Mode 1: 16-bit Timer/Counter.

M00

Mode 2: 8-bit auto-reload Timer/Counter (TL0).⁽²⁾

0

1

Mode 3: TL0 is an 8-bit Timer/Counter.

TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.

Notes: 1. Reloaded from TH1 at overflow.

2. Reloaded from TH0 at overflow.

Reset Value = 0000 0000b

Table 9. TH0 Register

TH0 (S:8Ch) – Timer 0 High Byte Register

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

7:0

High Byte of Timer 0

Reset Value = 0000 0000b

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Table 10. TL0 Register

TL0 (S:8Ah) – Timer 0 Low Byte Register

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

7:0

Low Byte of Timer 0

Reset Value = 0000 0000b

Table 11. TH1 Register

TH1 (S:8Dh) – Timer 1 High Byte Register

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

7:0

High Byte of Timer 1

Reset Value = 0000 0000b

Table 12. TL1 Register

TL1 (S:8Bh) – Timer 1 Low Byte Register

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

7:0

Low Byte of Timer 1

Reset Value = 0000 0000b

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13. Watchdog Timer

The AT8xC51SND1C implement a hardware Watchdog Timer (WDT) that automatically

resets the chip if it is allowed to time out. The WDT provides a means of recovering from

routines that do not complete successfully due to software or hardware malfunctions.

13.1 Description

The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As

shown in Figure 40, the 14-bit prescaler is fed by the WDT clock detailed in

Section “Watchdog Clock Controller”, page 61.

The Watchdog Timer Reset register (WDTRST, see Table 6) provides control access to

the WDT, while the Watchdog Timer Program register (WDTPRG, see Figure 43) pro-

vides time-out period programming.

Three operations control the WDT:

•

Chip reset clears and disables the WDT.

Programming the time-out value to the WDTPRG register.

Writing a specific 2-Byte sequence to the WDTRST register clears and enables the

WDT.

Figure 40. WDT Block Diagram

14-bit Prescaler

7-bit Counter

WDT

CLOCK

÷ 6

OV

To internal reset

RST

SET

WTO2:0

WDTPRG.2:0

1Eh-E1h Decoder

EN

RST

System Reset

MATCH

OSC

CLOCK

Pulse Generator

RST

WDTRST

13.2 Watchdog Clock

Controller

As shown in Figure 41 the WDT clock (F_WDT) is derived from either the peripheral clock

(F_PER) or the oscillator clock (F_OSC) depending on the WTX2 bit in CKCON register.

These clocks are issued from the Clock Controller block as detailed in Section "Clock

Controller", page 12. When WTX2 bit is set, the WDT clock frequency is fixed and equal

to the oscillator clock frequency divided by 2. When cleared, the WDT clock frequency is

equal to the oscillator clock frequency divided by 2 in standard mode or to the oscillator

clock frequency in X2 mode.

Figure 41. WDT Clock Controller and Symbol

PER

CLOCK

0

WDT

CLOCK

WDT Clock

1

OSC

CLOCK

÷ 2

WDT Clock Symbol

WTX2

CKCON.6

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13.3 Watchdog Operation After reset, the WDT is disabled. The WDT is enabled by writing the sequence 1Eh and

E1h into the WDTRST register. As soon as it is enabled, there is no way except the chip

reset to disable it. If it is not cleared using the previous sequence, the WDT overflows

and forces a chip reset. This overflow generates a high level 96 oscillator periods pulse

on the RST pin to globally reset the application (refer to Section “Power Management”,

page 48).

The WDT time-out period can be adjusted using WTO2:0 bits located in the WDTPRG

register accordingly to the formula shown in Figure 42. In this formula, WTOval repre-

sents the decimal value of WTO2:0 bits. Table 4 reports the time-out period depending

on the WDT frequency.

Figure 42. WDT Time-Out Formula

6 ⋅ ((2¹⁴⋅ 2^WTOval) – 1)

WDT_TO

=

F_WDT

Table 4. WDT Time-Out Computation

F_WDT(ms)

WTO2 WTO1 WTO0

6 MHz⁽¹⁾

16.38

8 MHz⁽¹⁾

12.28

24.57

49.14

98.28

196.56

393.1

786.24

1572

10 MHz⁽¹⁾

12 MHz⁽²⁾

8.19

16 MHz⁽²⁾

6.14

20 MHz⁽²⁾

4.92

0

1

0

1

0

1

0

1

0

1

0

1

0

1

9.83

19.66

39.32

78.64

157.29

314.57

629.15

1258

32.77

16.38

12.28

9.83

65.54

32.77

24.57

19.66

131.07

262.14

524.29

1049

65.54

49.14

39.32

131.07

262.14

524.29

1049

98.28

78.64

196.56

393.12

786.24

157.29

314.57

629.15

2097

Notes: 1. These frequencies are achieved in X1 mode or in X2 mode when WTX2 = 1:

F_WDT= F_OSC÷ 2.

2. These frequencies are achieved in X2 mode when WTX2 = 0: F_WDT= F_OSC

.

13.4.1 WDT Behavior during

Idle and Power-down Modes

Operation of the WDT during power reduction modes deserves special attention.

The WDT continues to count while the AT8xC51SND1C is in Idle mode. This means

that you must dedicate some internal or external hardware to service the WDT during

Idle mode. One approach is to use a peripheral Timer to generate an interrupt request

when the Timer overflows. The interrupt service routine then clears the WDT, reloads

the peripheral Timer for the next service period and puts the AT8xC51SND1C back into

Idle mode.

The Power-down mode stops all phase clocks. This causes the WDT to stop counting

and to hold its count. The WDT resumes counting from where it left off if the Power-

down mode is terminated by INT0, INT1 or keyboard interrupt. To ensure that the WDT

does not overflow shortly after exiting the Power-down mode, it is recommended to clear

the WDT just before entering Power-down mode.

The WDT is cleared and disabled if the Power-down mode is terminated by a reset.

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13.5 Registers

Table 6. WDTRST Register

WDTRST (S:A6h Write only) – Watchdog Timer Reset Register

7

6

5

4

3

2

1

0

-

Bit

Number

Mnemonic Description

7 - 0

-

Watchdog Control Value

Reset Value = XXXX XXXXb

Figure 43. WDTPRG Register

WDTPRG (S:A7h) – Watchdog Timer Program Register

7

6

5

4

3

2

1

0

-

WTO2

WTO1

WTO0

Bit

Number

Mnemonic Description

Reserved

7 - 3

2 - 0

-

The value read from these bits is indeterminate. Do not set these bits.

Watchdog Timer Time-Out Selection Bits

Refer to Table 4 for time-out periods.

WTO2:0

Reset Value = XXXX X000b

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14. MP3 Decoder

The AT8xC51SND1C implement a MPEG I/II audio layer 3 decoder better known as

MP3 decoder.

In MPEG I (ISO 11172-3) three layers of compression have been standardized support-

ing three sampling frequencies: 48, 44.1, and 32 kHz. Among these layers, layer 3

allows highest compression rate of about 12:1 while still maintaining CD audio quality.

For example, 3 minutes of CD audio (16-bit PCM, 44.1 kHz) data, which needs about

32M bytes of storage, can be encoded into only 2.7M bytes of MPEG I audio layer 3

data.

In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16 kHz

are supported for low bit rates applications.

The AT8xC51SND1C can decode in real-time the MPEG I audio layer 3 encoded data

into a PCM audio data, and also supports MPEG II audio layer 3 additional frequencies.

Additional features are supported by the AT8xC51SND1C MP3 decoder such as volume

control, bass, medium, and treble controls, bass boost effect and ancillary data

extraction.

14.1 Decoder

14.1.1 Description

The C51 core interfaces to the MP3 decoder through nine special function registers:

MP3CON, the MP3 Control register (see Table 12); MP3STA, the MP3 Status register

(see Table 13); MP3DAT, the MP3 Data register (see Table 14); MP3ANC, the Ancillary

Data register (see Table 16); MP3VOL and MP3VOR, the MP3 Volume Left and Right

Control registers (see Table 17 and Table 18); MP3BAS, MP3MED, and MP3TRE, the

MP3 Bass, Medium, and Treble Control registers (see Table 19, Table 20, and

Table 21); and MPCLK, the MP3 Clock Divider register (see Table 22).

Figure 44 shows the MP3 decoder block diagram.

Figure 44. MP3 Decoder Block Diagram

1K Bytes

Frame Buffer

MP3DAT

Audio Data

From C51

Header Checker

Huffman Decoder

8

Dequantizer

Stereo Processor

Side Information

MPxREQ

MP3STA1.n

ERRxxx MPFS1:0 MPVER

MP3STA.5:3 MP3STA.2:1 MP3STA.0

MP3

CLOCK

Ancillary Buffer

MP3ANC

MPEN

MP3CON.7

Sub-band

Synthesis

Decoded Data

To Audio Interface

16

Anti-Aliasing

IMDCT

MPBBST

MP3CON.6

MP3VOL MP3VOR MP3BAS MP3MED MP3TRE

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14.1.2 MP3 Data

The MP3 decoder does not start any frame decoding before having a complete frame in

its input buffer⁽¹⁾. In order to manage the load of MP3 data in the frame buffer, a hard-

ware handshake consisting of data request and data acknowledgment is implemented.

Each time the MP3 decoder needs MP3 data, it sets the MPREQ, MPFREQ and

MPBREQ flags respectively in MP3STA and MP3STA1 registers. MPREQ flag can gen-

erate an interrupt if enabled as explained in Section “Interrupt”. The CPU must then load

data in the buffer by writing it through MP3DAT register thus acknowledging the previ-

ous request. As shown in Figure 45, the MPFREQ flag remains set while data (i.e a

frame) is requested by the decoder. It is cleared when no more data is requested and

set again when new data are requested. MPBREQ flag toggles at every Byte writing.

Note:

1. The first request after enable, consists in 1024 Bytes of data to fill in the input buffer.

Figure 45. Data Timing Diagram

Cleared when Reading MP3STA

MPREQ Flag

MPFREQ Flag

MPBREQ Flag

Write to MP3DAT

14.1.3 MP3 Clock

The MP3 decoder clock is generated by division of the PLL clock. The division factor is

given by MPCD4:0 bits in MP3CLK register. Figure 46 shows the MP3 decoder clock

generator and its calculation formula. The MP3 decoder clock frequency depends only

on the incoming MP3 frames.

Figure 46. MP3 Clock Generator and Symbol

MP3CLK

PLL

CLOCK

MP3

CLOCK

MPCD4:0

MP3 Decoder Clock

MP3 Clock Symbol

PLLclk

MPCD + 1

MP3clk = ----------------------------

As soon as the frame header has been decoded and the MPEG version extracted, the

minimum MP3 input frequency must be programmed according to Table 2.

Table 2. MP3 Clock Frequency

MPEG Version

Minimum MP3 Clock (MHz)

I

21

II

10.5

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14.3 Audio Controls

14.3.1 Volume Control

The MP3 decoder implements volume control on both right and left channels. The

MP3VOR and MP3VOL registers allow a 32-step volume control according to Table 4.

Table 4. Volume Control

VOL4:0 or VOR4:0

00000

Volume Gain (dB)

Mute

-33

-27

-1.5

0

00001

00010

11110

11111

14.4.1 Equalization Control

Sound can be adjusted using a 3-band equalizer: a bass band under 750 Hz, a medium

band from 750 Hz to 3300 Hz and a treble band over 3300 Hz. The MP3BAS, MP3MED,

and MP3TRE registers allow a 32-step gain control in each band according to Table 5.

Table 5. Bass, Medium, Treble Control

BAS4:0 or MED4:0 or TRE4:0

Gain (dB)

- ∞

00000

00001

00010

11110

11111

-14

-10

+1

+1.5

14.5.1 Special Effect

The MPBBST bit in MP3CON register allows enabling of a bass boost effect with the fol-

lowing characteristics: gain increase of +9 dB in the frequency under 375 Hz.

14.6 Decoding Errors

The three different errors that can appear during frame processing are detailed in the

following sections. All these errors can trigger an interrupt as explained in Section "Inter-

rupt", page 68.

14.6.1 Layer Error

The ERRSYN flag in MP3STA is set when a non-supported layer is decoded in the

header of the frame that has been sent to the decoder.

14.6.2 Synchronization Error

14.6.3 CRC Error

The ERRSYN flag in MP3STA is set when no synchronization pattern is found in the

data that have been sent to the decoder.

When the CRC of a frame does not match the one calculated, the flag ERRCRC in

MP3STA is set. In this case, depending on the CRCEN bit in MP3CON, the frame is

played or rejected. In both cases, noise may appear at audio output.

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14.7 Frame Information

The MP3 frame header contains information on the audio data contained in the frame.

These informations is made available in the MP3STA register for you information.

MPVER and MPFS1:0 bits allow decoding of the sampling frequency according to

Table 8. MPVER bit gives the MPEG version (2 or 1).

Table 8. MP3 Frame Frequency Sampling

MPVER

MPFS1

MPFS0

Fs (kHz)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

22.05 (MPEG II)

24 (MPEG II)

16 (MPEG II)

Reserved

44.1 (MPEG I)

48 (MPEG I)

32 (MPEG I)

Reserved

14.9 Ancillary Data

MP3 frames also contain data bits called ancillary data. These data are made available

in the MP3ANC register for each frame. As shown in Figure 47, the ancillary data are

available by Bytes when MPANC flag in MP3STA register is set. MPANC flag is set

when the ancillary buffer is not empty (at least one ancillary data is available) and is

cleared only when there is no more ancillary data in the buffer. This flag can generate an

interrupt as explained in Section "Interrupt", page 68. When set, software must read all

Bytes to empty the ancillary buffer.

Figure 47. Ancillary Data Block Diagram

Ancillary

Data To C51

7-Byte

Ancillary Buffer

8

MP3ANC

MPANC

MP3STA.7

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14.10 Interrupt

14.10.1 Description

As shown in Figure 48, the MP3 decoder implements five interrupt sources reported in

ERRCRC, ERRSYN, ERRLAY, MPREQ, and MPANC flags in MP3STA register.

All these sources are maskable separately using MSKCRC, MSKSYN, MSKLAY,

MSKREQ, and MSKANC mask bits respectively in MP3CON register.

The MP3 interrupt is enabled by setting EMP3 bit in IEN0 register. This assumes inter-

rupts are globally enabled by setting EA bit in IEN0 register.

All interrupt flags but MPREQ and MPANC are cleared when reading MP3STA register.

The MPREQ flag is cleared by hardware when no more data is requested (see

Figure 45) and MPANC flag is cleared by hardware when the ancillary buffer becomes

empty.

Figure 48. MP3 Decoder Interrupt System

MPANC

MP3STA.7

MSKANC

MP3CON.4

MPREQ

MP3STA.6

MSKREQ

MP3CON.3

MP3 Decoder

Interrupt Request

ERRLAY

MP3STA.5

MSKLAY

MP3CON.2

EMP3

IEN0.5

ERRSYN

MP3STA.4

MSKSYN

MP3CON.1

ERRCRC

MP3STA.3

MSKCRC

MP3CON.0

14.10.2 Management

Reading the MP3STA register automatically clears the interrupt flags (acknowledgment)

except the MPREQ and MPANC flags. This implies that register content must be saved

and tested, interrupt flag by interrupt flag to be sure not to forget any interrupts.

68

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Figure 49. MP3 Interrupt Service Routine Flow

MP3 Decoder

ISR

Read MP3STA

Data Request?

MPFREQ = 1?

Data Request

Handler

Ancillary Data?⁽¹⁾

MPANC = 1?

Write MP3 Data

to MP3DAT

Ancillary Data

Handler

Sync Error?⁽¹⁾

ERRSYN = 1?

Read ANN2:0 Ancillary

Bytes From MP3ANC

Synchro Error

Handler

Layer Error?⁽¹⁾

ERRSYN = 1?

Reload MP3 Frame

Through MP3DAT

Layer Error

Handler

CRC Error

Handler

Load New MP3 Frame

Through MP3DAT

Note:

1. Test these bits only if needed (unmasked interrupt).

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14.11 Registers

Table 12. MP3CON Register

MP3CON (S:AAh) – MP3 Decoder Control Register

7

6

5

4

3

2

1

0

MPEN

MPBBST

CRCEN

MSKANC

MSKREQ

MSKLAY

MSKSYN

MSKCRC

Bit

Number

Mnemonic Description

MP3 Decoder Enable Bit

7

6

MPEN

Set to enable the MP3 decoder.

Clear to disable the MP3 decoder.

Bass Boost Bit

MPBBST Set to enable the bass boost sound effect.

Clear to disable the bass boost sound effect.

CRC Check Enable Bit

Set to enable processing of frame that contains CRC error. Frame is played

whatever the error.

5

CRCEN

Clear to disable processing of frame that contains CRC error. Frame is skipped.

MPANC Flag Mask Bit

4

3

2

1

0

MSKANC Set to prevent the MPANC flag from generating a MP3 interrupt.

Clear to allow the MPANC flag to generate a MP3 interrupt.

MPREQ Flag Mask Bit

MSKREQ Set to prevent the MPREQ flag from generating a MP3 interrupt.

Clear to allow the MPREQ flag to generate a MP3 interrupt.

ERRLAY Flag Mask Bit

MSKLAY Set to prevent the ERRLAY flag from generating a MP3 interrupt.

Clear to allow the ERRLAY flag to generate a MP3 interrupt.

ERRSYN Flag Mask Bit

MSKSYN Set to prevent the ERRSYN flag from generating a MP3 interrupt.

Clear to allow the ERRSYN flag to generate a MP3 interrupt.

ERRCRC Flag Mask Bit

MSKCRC Set to prevent the ERRCRC flag from generating a MP3 interrupt.

Clear to allow the ERRCRC flag to generate a MP3 interrupt.

Reset Value = 0011 1111b

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Table 13. MP3STA Register

MP3STA (S:C8h Read Only) – MP3 Decoder Status Register

7

6

5

4

3

2

1

0

MPANC

MPREQ

ERRLAY

ERRSYN

ERRCRC

MPFS1

MPFS0

MPVER

Bit

Number

Mnemonic Description

Ancillary Data Available Flag

7

6

5

4

MPANC Set by hardware as soon as one ancillary data is available (buffer not empty).

Cleared by hardware when no more ancillary data is available (buffer empty).

MP3 Data Request Flag

MPREQ Set by hardware when MP3 decoder request data.

Cleared when reading MP3STA.

Invalid Layer Error Flag

ERRLAY Set by hardware when an invalid layer is encountered.

Cleared when reading MP3STA.

Frame Synchronization Error Flag

ERRSYN Set by hardware when no synchronization pattern is encountered in a frame.

Cleared when reading MP3STA.

CRC Error Flag

3

2 - 1

0

ERRCRC Set by hardware when a frame handling CRC is corrupted.

Cleared when reading MP3STA.

Frequency Sampling Bits

MPFS1:0

Refer to Table 8 for bits description.

MPEG Version Bit

MPVER Set by the MP3 decoder when the loaded frame is a MPEG I frame.

Cleared by the MP3 decoder when the loaded frame is a MPEG II frame.

Reset Value = 0000 0001b

Table 14. MP3DAT Register

MP3DAT (S:ACh) – MP3 Data Register

7

6

5

4

3

2

1

0

MPD7

MPD6

MPD5

MPD4

MPD3

MPD2

MPD1

MPD0

Bit

Number

Mnemonic Description

Input Stream Data Buffer

8-bit MP3 stream data input buffer.

7 - 0

MPD7:0

Reset Value = 0000 0000b

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Table 15. MP3STA1 Register

MP3STA1 (S:AFh) – MP3 Decoder Status Register 1

7

-

6

-

5

-

4

3

2

-

1

-

0

-

MPFREQ

Bit

Number

Mnemonic Description

Reserved

7 - 5

4

-

The value read from these bits is always 0. Do not set these bits.

MP3 Frame Data Request Flag

MPFREQ Set by hardware when MP3 decoder request data.

Cleared when MP3 decoder no more request data .

MP3 Byte Data Request Flag

MPBREQ Set by hardware when MP3 decoder request data.

Cleared when writing to MP3DAT.

3

Reserved

2 - 0

-

The value read from these bits is always 0. Do not set these bits.

Reset Value = 0001 0001b

Table 16. MP3ANC Register

MP3ANC (S:ADh Read Only) – MP3 Ancillary Data Register

7

6

5

4

3

2

1

0

AND7

AND6

AND5

AND4

AND3

AND2

AND1

AND0

Bit

Number

Mnemonic Description

Ancillary Data Buffer

MP3 ancillary data Byte buffer.

7 - 0

AND7:0

Reset Value = 0000 0000b

Table 17. MP3VOL Register

MP3VOL (S:9Eh) – MP3 Volume Left Control Register

7

-

6

-

5

-

4

3

2

1

0

VOL4

VOL3

VOL2

VOL1

VOL0

Bit

Number

Mnemonic Description

Reserved

7 - 5

4 - 0

-

The value read from these bits is always 0. Do not set these bits.

Volume Left Value

Refer to Table 4 for the left channel volume control description.

VOL4:0

Reset Value = 0000 0000b

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Table 18. MP3VOR Register

MP3VOR (S:9Fh) – MP3 Volume Right Control Register

7

-

6

-

5

-

4

3

2

1

0

VOR4

VOR3

VOR2

VOR1

VOR0

Bit

Number

Mnemonic Description

Reserved

7 - 5

4 - 0

-

The value read from these bits is always 0. Do not set these bits.

Volume Right Value

Refer to Table 4 for the right channel volume control description.

VOR4:0

Reset Value = 0000 0000b

Table 19. MP3BAS Register

MP3BAS (S:B4h) – MP3 Bass Control Register

7

-

6

-

5

-

4

3

2

1

0

BAS4

BAS3

BAS2

BAS1

BAS0

Bit

Number

Mnemonic Description

Reserved

7 - 5

4 - 0

-

The value read from these bits is always 0. Do not set these bits.

Bass Gain Value

Refer to Table 5 for the bass control description.

BAS4:0

Reset Value = 0000 0000b

Table 20. MP3MED Register

MP3MED (S:B5h) – MP3 Medium Control Register

7

-

6

-

5

4

3

2

1

0

MED5

MED4

MED3

MED2

MED1

MED0

Bit

Number

Mnemonic Description

Reserved

7 - 6

5-0

-

The value read from these bits is always 0. Do not set these bits.

Medium Gain Value

Refer to Table 5 for the medium control description.

MED5:0

Reset Value = 0000 0000b

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Table 21. MP3TRE Register

MP3TRE (S:B6h) – MP3 Treble Control Register

7

-

6

-

5

4

3

2

1

0

TRE5

TRE4

TRE3

TRE2

TRE1

TRE0

Bit

Number

Mnemonic Description

Reserved

7 - 6

5-0

-

The value read from these bits is always 0. Do not set these bits.

Treble Gain Value

Refer to Table 5 for the treble control description.

TRE5:0

Reset Value = 0000 0000b

Table 22. MP3CLK Register

MP3CLK (S:EBh) – MP3 Clock Divider Register

7

-

6

-

5

-

4

3

2

1

0

MPCD4

MPCD3

MPCD2

MPCD1

MPCD0

Bit

Number

Mnemonic Description

Reserved

7 - 5

4-0

-

The value read from these bits is always 0. Do not set these bits.

MP3 Decoder Clock Divider

5-bit divider for MP3 decoder clock generation.

MPCD4:0

Reset Value = 0000 0000b

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15. Audio Output

Interface

The AT8xC51SND1C implement an audio output interface allowing the audio bitstream

to be output in various formats. It is compatible with right and left justification PCM and

I²S formats and thanks to the on-chip PLL (see Section “Clock Controller”, page 12)

allows connection of almost all of the commercial audio DAC families available on the

market.

The audio bitstream can be from 2 different types:

•

The MP3 decoded bitstream coming from the MP3 decoder for playing songs.

The audio bitstream coming from the MCU for outputting voice or sounds.

15.1 Description

The C51 core interfaces to the audio interface through five special function registers:

AUDCON0 and AUDCON1, the Audio Control registers (see Table 11 and Table 12);

AUDSTA, the Audio Status register (see Table 13); AUDDAT, the Audio Data register

(see Table 14); and AUDCLK, the Audio Clock Divider register (see Table 15).

Figure 50 shows the audio interface block diagram, blocks are detailed in the following

sections.

Figure 50. Audio Interface Block Diagram

SCLK

DCLK

AUD

CLOCK

Clock Generator

0

1

DSEL

AUDEN

AUDCON1.0

HLR

AUDCON0.0

DSIZ

AUDCON0.1

POL

AUDCON0.2

Data Ready

Audio Data

From MP3

Decoder

16

Data Converter

DOUT

0

1

MP3 Buffer

Sample

Request To

MP3 Decoder

JUST4:0

AUDCON0.7:3

DRQEN

AUDCON1.6

SRC

AUDCON1.7

SREQ

AUDSTA.7

Audio Data

From C51

Audio Buffer

AUDDAT

8

UDRN

AUDSTA.6

AUBUSY

AUDSTA.5

DUP1:0

AUDCON1.2:1

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15.2 Clock Generator

The audio interface clock is generated by division of the PLL clock. The division factor is

given by AUCD4:0 bits in CLKAUD register. Figure 51 shows the audio interface clock

generator and its calculation formula. The audio interface clock frequency depends on

the incoming MP3 frames and the audio DAC used.

Figure 51. Audio Clock Generator and Symbol

AUDCLK

PLL

CLOCK

AUD

CLOCK

AUCD4:0

Audio Interface Clock

Audio Clock Symbol

PLLclk

AUCD + 1

AUDclk = ---------------------------

As soon as audio interface is enabled by setting AUDEN bit in AUDCON1 register, the

master clock generated by the PLL is output on the SCLK pin which is the DAC system

clock. This clock is output at 256 or 384 times the sampling frequency depending on the

DAC capabilities. HLR bit in AUDCON0 register must be set according to this rate for

properly generating the audio bit clock on the DCLK pin and the word selection clock on

the DSEL pin. These clocks are not generated when no data is available at the data

converter input.

For DAC compatibility, the bit clock frequency is programmable for outputting 16 bits or

32 bits per channel using the DSIZ bit in AUDCON0 register (see Section "Data Con-

verter", page 76), and the word selection signal is programmable for outputting left

channel on low or high level according to POL bit in AUDCON0 register as shown in

Figure 52.

Figure 52. DSEL Output Polarity

Left Channel

Right Channel

POL = 0

POL = 1

15.3 Data Converter

The data converter block converts the audio stream input from the 16-bit parallel format

to a serial format. For accepting all PCM formats and I²S format, JUST4:0 bits in

AUDCON0 register are used to shift the data output point. As shown in Figure 53, these

bits allow MSB justification by setting JUST4:0 = 00000, LSB justification by setting

JUST4:0 = 10000, I²S Justification by setting JUST4:0 = 00001, and more than 16-bit

LSB justification by filling the low significant bits with logic 0.

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Figure 53. Audio Output Format

Left Channel

Right Channel

DSEL

1

2

3

13

14

15

16

DCLK

DOUT

1

2

3

13

14

18

14

15

16

LSB MSB B14

B1 LSB MSB B14

I²S Format with DSIZ = 0 and JUST4:0 = 00001.

B1

Left Channel

Right Channel

DSEL

DCLK

DOUT

1

2

3

17

18

32

1

2

3

17

32

MSB B14

LSB

MSB B14

LSB

I²S Format with DSIZ = 1 and JUST4:0 = 00001.

Left Channel

Right Channel

DSEL

DCLK

DOUT

1

2

3

13

14

15

16

1

2

3

13

15

16

MSB B14

B1 LSB MSB B15

MSB/LSB Justified Format with DSIZ = 0 and JUST4:0 = 00000.

B1 LSB

Left Channel

16 17

Right Channel

16 17

DSEL

DCLK

DOUT

1

18

31

32

1

18

31

32

MSB B14

B1 LSB

MSB B14

B1 LSB

16-bit LSB Justified Format with DSIZ = 1 and JUST4:0 = 10000.

Left Channel

15 16

Right Channel

15 16

DSEL

DCLK

DOUT

1

30

31

32

1

30

31

32

MSB B16

B2

B1 LSB

MSB B16

B2

B1 LSB

18-bit LSB Justified Format with DSIZ = 1 and JUST4:0 = 01110.

The data converter receives its audio stream from 2 sources selected by the SRC bit in

AUDCON1 register. When cleared, the audio stream comes from the MP3 decoder (see

Section “MP3 Decoder”, page 64) for song playing. When set, the audio stream is com-

ing from the C51 core for voice or sound playing.

As soon as first audio data is input to the data converter, it enables the clock generator

for generating the bit and word clocks.

15.4 Audio Buffer

In voice or sound playing mode, the audio stream comes from the C51 core through an

audio buffer. The data is in 8-bit format and is sampled at 8 kHz. The audio buffer

adapts the sample format and rate. The sample format is extended to 16 bits by filling

the LSB to 00h. Rate is adapted to the DAC rate by duplicating the data using DUP1:0

bits in AUDCON1 register according to Table 5.

The audio buffer interfaces to the C51 core through three flags: the sample request flag

(SREQ in AUDSTA register), the under-run flag (UNDR in AUDSTA register) and the

busy flag (AUBUSY in AUDSTA register). SREQ and UNDR can generate an interrupt

request as explained in Section "Interrupt Request", page 78. The buffer size is 8 Bytes

large. SREQ is set when the samples number switches from 4 to 3 and reset when the

samples number switches from 4 to 5; UNDR is set when the buffer becomes empty sig-

naling that the audio interface ran out of samples; and AUBUSY is set when the buffer is

full.

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Table 5. Sample Duplication Factor

DUP1

DUP0

Factor

0

1

0

1

0

1

No sample duplication, DAC rate = 8 kHz (C51 rate).

One sample duplication, DAC rate = 16 kHz (2 x C51 rate).

2 samples duplication, DAC rate = 32 kHz (4 x C51 rate).

Three samples duplication, DAC rate = 48 kHz (6 x C51 rate).

15.6 MP3 Buffer

In song playing mode, the audio stream comes from the MP3 decoder through a buffer.

The MP3 buffer is used to store the decoded MP3 data and interfaces to the decoder

through a 16-bit data input and data request signal. This signal asks for data when the

buffer has enough space to receive new data. Data request is conditioned by the

DREQEN bit in AUDCON1 register. When set, the buffer requests data to the MP3

decoder. When cleared no more data is requested but data are output until the buffer is

empty. This bit can be used to suspend the audio generation (pause mode).

15.7 Interrupt Request

The audio interrupt request can be generated by 2 sources when in C51 audio mode: a

sample request when SREQ flag in AUDSTA register is set to logic 1, and an under-run

condition when UDRN flag in AUDSTA register is set to logic 1. Both sources can be

enabled separately by masking one of them using the MSREQ and MUDRN bits in

AUDCON1 register. A global enable of the audio interface is provided by setting the

EAUD bit in IEN0 register.

The interrupt is requested each time one of the 2 sources is set to one. The source flags

are cleared by writing some data in the audio buffer through AUDDAT, but the global

audio interrupt flag is cleared by hardware when the interrupt service routine is

executed.

Figure 54. Audio Interface Interrupt System

UDRN

AUDSTA.6

Audio

Interrupt

Request

MUDRN

AUDCON1.4

SREQ

AUDSTA.7

EAUD

IEN0.6

MSREQ

AUDCON1.5

15.8 MP3 Song Playing

In MP3 song playing mode, the operations to do are to configure the PLL and the audio

interface according to the DAC selected. The audio clock is programmed to generate

the 256·Fs or 384·Fs as explained in Section "Clock Generator", page 76. Figure 55

shows the configuration flow of the audio interface when in MP3 song mode.

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Figure 55. MP3 Mode Audio Configuration Flow

MP3 Mode

Configuration

Enable DAC System

Clock

Program Audio Clock

AUDEN = 1

Configure Interface

HLR = X

Wait For

DAC Set-up Time

DSIZ = X

POL = X

JUST4:0 = XXXXXb

SRC = 0

Enable Data Request

DRQEN = 1

15.9 Voice or Sound

Playing

In voice or sound playing mode, the operations required are to configure the PLL and

the audio interface according to the DAC selected. The audio clock is programmed to

generate the 256·Fs or 384·Fs as for the MP3 playing mode. The data flow sent by the

C51 is then regulated by interrupt and data is loaded 4 Bytes by 4 Bytes. Figure 56

shows the configuration flow of the audio interface when in voice or sound mode.

Figure 56. Voice or Sound Mode Audio Flows

Voice/Song Mode

Configuration

Audio Interrupt

Service Routine

Wait for DAC

Enable Time

Program Audio Clock

Sample Request?

SREQ = 1?

Configure Interface

HLR = X

Select Audio

SRC = 1

DSIZ = X

Load 4 Samples in the

Audio Buffer

Under-run Condition¹

POL = X

JUST4:0 = XXXXXb

DUP1:0 = XX

Load 8 Samples in the

Audio Buffer

Enable DAC System

Clock

Enable Interrupt

Set MSREQ & MUDRN¹

EAUD = 1

AUDEN = 1

Note:

1. An under-run occurrence signifies that C51 core did not respond to the previous sample request interrupt. It may never

occur for a correct voice/sound generation. It is the user’s responsibility to mask it or not.

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15.10 Registers

Table 11. AUDCON0 Register

AUDCON0 (S:9Ah) – Audio Interface Control Register 0

7

6

5

4

3

2

1

0

JUST4

JUST3

JUST2

JUST1

JUST0

POL

DSIZ

HLR

Bit

Number

Mnemonic Description

Audio Stream Justification Bits

Refer to Section "Data Converter", page 76 for bits description.

7 - 3

2

JUST4:0

POL

DSEL Signal Output Polarity

Set to output the left channel on high level of DSEL output (PCM mode).

Clear to output the left channel on the low level of DSEL output (I²S mode).

Audio Data Size

1

0

DSIZ

HLR

Set to select 32-bit data output format.

Clear to select 16-bit data output format.

High/Low Rate Bit

Set by software when the PLL clock frequency is 384·Fs.

Clear by software when the PLL clock frequency is 256·Fs.

Reset Value = 0000 1000b

Table 12. AUDCON1 Register

AUDCON1 (S:9Bh) – Audio Interface Control Register 1

7

6

5

4

3

-

2

1

0

SRC

DRQEN

MSREQ

MUDRN

DUP1

DUP0

AUDEN

Bit

Number

Mnemonic Description

Audio Source Bit

Set to select C51 as audio source for voice or sound playing.

Clear to select the MP3 decoder output as audio source for song playing.

7

6

5

4

SRC

MP3 Decoded Data Request Enable Bit

DRQEN Set to enable data request to the MP3 decoder and to start playing song.

Clear to disable data request to the MP3 decoder.

Audio Sample Request Flag Mask Bit

MSREQ Set to prevent the SREQ flag from generating an audio interrupt.

Clear to allow the SREQ flag to generate an audio interrupt.

Audio Sample Under-run Flag Mask Bit

MUDRN Set to prevent the UDRN flag from generating an audio interrupt.

Clear to allow the UDRN flag to generate an audio interrupt.

Reserved

3

-

The value read from this bit is always 0. Do not set this bit.

Audio Duplication Factor

DUP1:0

2 - 1

Refer to Table 5 for bits description.

Audio Interface Enable Bit

AUDEN Set to enable the audio interface.

Clear to disable the audio interface.

0

Reset Value = 1011 0010b

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Table 13. AUDSTA Register

AUDSTA (S:9Ch Read Only) – Audio Interface Status Register

7

6

5

4

-

3

-

2

-

1

-

0

-

SREQ

UDRN

AUBUSY

Bit

Number

Mnemonic Description

Audio Sample Request Flag

Set in C51 audio source mode when the audio interface request samples (buffer

half empty). This bit generates an interrupt if not masked and if enabled in IEN0.

Cleared by hardware when samples are loaded in AUDDAT.

7

6

SREQ

UDRN

Audio Sample Under-run Flag

Set in C51 audio source mode when the audio interface runs out of samples

(buffer empty). This bit generates an interrupt if not masked and if enabled in

IEN0.

Cleared by hardware when samples are loaded in AUDDAT.

Audio Interface Busy Bit

Set in C51 audio source mode when the audio interface can not accept more

sample (buffer full).

Cleared by hardware when buffer is no more full.

5

AUBUSY

-

Reserved

4 - 0

The value read from these bits is always 0. Do not set these bits.

Reset Value = 1100 0000b

Table 14. AUDDAT Register

AUDDAT (S:9Dh) – Audio Interface Data Register

7

6

5

4

3

2

1

0

AUD7

AUD6

AUD5

AUD4

AUD3

AUD2

AUD1

AUD0

Bit

Number

Mnemonic Description

Audio Data

8-bit sampling data for voice or sound playing.

7 - 0

AUD7:0

Reset Value = 1111 1111b

Table 15. AUDCLK Register

AUDCLK (S:ECh) – Audio Clock Divider Register

7

-

6

-

5

-

4

3

2

1

0

AUCD4

AUCD3

AUCD2

AUCD1

AUCD0

Bit

Number

Mnemonic Description

Reserved

7 - 5

4 - 0

-

The value read from these bits is always 0. Do not set these bits.

Audio Clock Divider

5-bit divider for audio clock generation.

AUCD4:0

Reset Value = 0000 0000b

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16. Universal Serial

Bus

The AT8xC51SND1C implements a USB device controller supporting full speed data

transfer. In addition to the default control endpoint 0, it provides 2 other endpoints, which

can be configured in control, bulk, interrupt or isochronous modes:

•

Endpoint 0: 32-Byte FIFO, default control endpoint

Endpoint 1, 2: 64-Byte Ping-pong FIFO,

This allows the firmware to be developed conforming to most USB device classes, for

example:

•

USB Mass Storage Class Bulk-only Transport, Revision 1.0 - September 31, 1999

USB Human Interface Device Class, Version 1.1 - April 7, 1999

USB Device Firmware Upgrade Class, Revision 1.0 - May 13, 1999

16.0.1 USB Mass Storage

Class Bulk-Only Transport

Within the Bulk-only framework, the Control endpoint is only used to transport class-

specific and standard USB requests for device set-up and configuration. One Bulk-out

endpoint is used to transport commands and data from the host to the device. One Bulk

in endpoint is used to transport status and data from the device to the host.

The following AT8xC51SND1C configuration adheres to those requirements:

•

Endpoint 0: 32 Bytes, Control In-Out

Endpoint 1: 64 Bytes, Bulk-in

Endpoint 2: 64 Bytes, Bulk-out

16.0.2 USB Device Firmware

Upgrade (DFU)

The USB Device Firmware Update (DFU) protocol can be used to upgrade the on-chip

Flash memory of the AT89C51SND1C. This allows installing product enhancements

and patches to devices that are already in the field. 2 different configurations and

descriptor sets are used to support DFU functions. The Run-Time configuration co-exist

with the usual functions of the device, which is USB Mass Storage for AT89C51SND1C.

It is used to initiate DFU from the normal operating mode. The DFU configuration is

used to perform the firmware update after device re-configuration and USB reset. It

excludes any other function. Only the default control pipe (endpoint 0) is used to support

DFU services in both configurations.

The only possible value for the MaxPacketSize in the DFU configuration is 32 Bytes,

which is the size of the FIFO implemented for endpoint 0.

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16.1 Description

The USB device controller provides the hardware that the AT8xC51SND1C needs to

interface a USB link to a data flow stored in a double port memory.

It requires a 48 MHz reference clock provided by the clock controller as detailed in Sec-

tion "Clock Controller", page 83. This clock is used to generate a 12 MHz Full Speed bit

clock from the received USB differential data flow and to transmit data according to full

speed USB device tolerance. Clock recovery is done by a Digital Phase Locked Loop

(DPLL) block.

The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuff-

ing, CRC generation and checking, and the serial-parallel data conversion.

The Universal Function Interface (UFI) controls the interface between the data flow and

the Dual Port RAM, but also the interface with the C51 core itself.

Figure 59 shows how to connect the AT8xC51SND1C to the USB connector. D+ and D-

pins are connected through 2 termination resistors. Value of these resistors is detailed in

the section “DC Characteristics”.

Figure 57. USB Device Controller Block Diagram

USB

CLOCK

48 MHz

12 MHz

DPLL

D+

D-

USB

Buffer

To/From

C51 Core

UFI

SIE

Figure 58. USB Connection

To Power Supply

VBUS

R_USB

D+

D-

D+

D-

GND

VSS

16.1.1 Clock Controller

The USB controller clock is generated by division of the PLL clock. The division factor is

given by USBCD1:0 bits in USBCLK register (see Table 24). Figure 59 shows the USB

controller clock generator and its calculation formula. The USB controller clock fre-

quency must always be 48 MHz.

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4109H–8051–01/05

Figure 59. USB Clock Generator and Symbol

USBCLK

PLL

CLOCK

USB

CLOCK

USBCD1:0

48 MHz USB Clock

USB Clock Symbol

PLLclk

USBCD + 1

USBclk = --------------------------------

16.1.2 Serial Interface Engine The SIE performs the following functions:

(SIE)

•

NRZI data encoding and decoding.

Bit stuffing and unstuffing.

CRC generation and checking.

ACKs and NACKs automatic generation.

TOKEN type identifying.

Address checking.

Clock recovery (using DPLL).

Figure 60. SIE Block Diagram

End of Packet

Detector

SYNC Detector

PID Decoder

Start of Packet

Detector

NRZI ‘ NRZ

Bit Unstuffing

Packet Bit Counter

Address Decoder

Serial to Parallel

Converter

D+

D-

8

Data Out

Clock

Recover

SysClk

(12 MHz)

USB

CLOCK

48 MHz

CRC5 & CRC16

Generator/Check

USB Pattern Generator

Parallel to Serial Converter

Bit Stuffing

8

Data In

NRZI Converter

CRC16 Generator

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16.1.3 Function Interface Unit The Function Interface Unit provides the interface between the AT8xC51SND1C and

(UFI)

the SIE. It manages transactions at the packet level with minimal intervention from the

device firmware, which reads and writes the endpoint FIFOs.

Figure 62 shows typical USB IN and OUT transactions reporting the split in the hard-

ware (UFI) and software (C51) load.

Figure 61. UFI Block Diagram

USBCON

USBADDR

USBINT

USBIEN

UEPNUM

UEPCONX

Transfer

Control

FSM

Asynchronous Information

UEPSTAX

UEPRST

UEPINT

12 MHz DPLL

To/From C51 Core

UEPIEN

UEPDATX

UBYCTX

UFNUMH

UFNUML

Endpoint 2

Endpoint 1

Endpoint 0

Endpoint Control

USB side

Endpoint Control

C51 side

To/From SIE

Figure 62. USB Typical Transaction Load

OUT Transactions:

OUT DATA0 (n Bytes)

OUT

DATA1

OUT

ACK

DATA1

HOST

UFI

ACK C51 interrupt

NACK

ACK

Endpoint FIFO read (n Bytes)

C51

IN Transactions:

IN

HOST

NACK

Endpoint FIFO Write

DATA1

UFI

C51 interrupt

Endpoint FIFO write

C51

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16.2 Configuration

16.2.1 General Configuration

•

USB controller enable

Before any USB transaction, the 48 MHz required by the USB controller must be

correctly generated (See “Clock Controller” on page 19).

The USB controller should be then enabled by setting the EUSB bit in the USBCON

register.

Set address

After a Reset or a USB reset, the software has to set the FEN (Function Enable) bit

in the USBADDR register. This action will allow the USB controller to answer to the

requests sent at the address 0.

When a SET_ADDRESS request has been received, the USB controller must only

answer to the address defined by the request. The new address should be stored in

the USBADDR register. The FEN bit and the FADDEN bit in the USBCON register

should be set to allow the USB controller to answer only to requests sent at the new

address.

•

Set configuration

The CONFG bit in the USBCON register should be set after a

SET_CONFIGURATION request with a non-zero value. Otherwise, this bit should

be cleared.

16.2.2 Endpoint Configuration

Selection of an Endpoint

The endpoint register access is performed using the UEPNUM register. The

registers

–

UEPSTAX

UEPCONX

UEPDATX

UBYCTX

Theses registers correspond to the endpoint whose number is stored in the UEP-

NUM register. To select an Endpoint, the firmware has to write the endpoint number

in the UEPNUM register.

Figure 63. Endpoint Selection

SFR Registers

UEPSTA0

UEPCON0

UEPDAT0

UEPDAT2

0

1

Endpoint 0

UBYCT0

UEPSTAX

UEPCONX

UBYCTX

UEPDATX

X

UEPSTA2

UEPCON2

2

Endpoint 2

UBYCT2

UEPNUM

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•

Endpoint enable

Before using an endpoint, this must be enabled by setting the EPEN bit in the UEP-

CONX register.

An endpoint which is not enabled won’t answer to any USB request. The Default

Control Endpoint (Endpoint 0) should always be enabled in order to answer to USB

standard requests.

Endpoint type configuration

All Standard Endpoints can be configured in Control, Bulk, Interrupt or Isochronous

mode. The Ping-pong Endpoints can be configured in Bulk, Interrupt or Isochronous

mode. The configuration of an endpoint is performed by setting the field EPTYPE

with the following values:

–

Control:

EPTYPE = 00b

Isochronous:EPTYPE = 01b

Bulk:

EPTYPE = 10b

EPTYPE = 11b

Interrupt:

The Endpoint 0 is the Default Control Endpoint and should always be configured in

Control type.

•

Endpoint direction configuration

For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the

EPDIR bit of the UEPCONX register with the following values:

–

IN:

EPDIR = 1b

EPDIR = 0b

OUT:

For Control endpoints, the EPDIR bit has no effect.

Summary of Endpoint Configuration:

Do not forget to select the correct endpoint number in the UEPNUM register before

accessing endpoint specific registers.

Table 3. Summary of Endpoint Configuration

Endpoint Configuration

EPEN

EPDIR

Xb

1b

EPTYPE

XXb

00b

UEPCONX

0XXX XXXb

80h

Disabled

0b

Control

1b

Bulk-in

1b

10b

86h

Bulk-out

1b

0b

10b

82h

Interrupt-In

1b

11b

87h

Interrupt-Out

Isochronous-In

Isochronous-Out

1b

0b

11b

83h

1b

01b

85h

1b

0b

01b

81h

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•

Endpoint FIFO reset

Before using an endpoint, its FIFO should be reset. This action resets the FIFO

pointer to its original value, resets the Byte counter of the endpoint (UBYCTX regis-

ter), and resets the data toggle bit (DTGL bit in UEPCONX).

The reset of an endpoint FIFO is performed by setting to 1 and resetting to 0 the

corresponding bit in the UEPRST register.

For example, in order to reset the Endpoint number 2 FIFO, write 0000 0100b then

0000 0000b in the UEPRST register.

Note that the endpoint reset doesn’t reset the bank number for ping-pong endpoints.

16.4 Read/Write Data

FIFO

16.4.1 Read Data FIFO

The read access for each OUT endpoint is performed using the UEPDATX register.

After a new valid packet has been received on an Endpoint, the data are stored into the

FIFO and the Byte counter of the endpoint is updated (UBYCTX registers). The firmware

has to store the endpoint Byte counter before any access to the endpoint FIFO. The

Byte counter is not updated when reading the FIFO.

To read data from an endpoint, select the correct endpoint number in UEPNUM and

read the UEPDATX register. This action automatically decreases the corresponding

address vector, and the next data is then available in the UEPDATX register.

16.4.2 Write Data FIFO

The write access for each IN endpoint is performed using the UEPDATX register.

To write a Byte into an IN endpoint FIFO, select the correct endpoint number in UEP-

NUM and write into the UEPDATX register. The corresponding address vector is

automatically increased, and another write can be carried out.

Warning 1: The Byte counter is not updated.

Warning 2: Do not write more Bytes than supported by the corresponding endpoint.

16.4.3 FIFO Mapping

Figure 64. Endpoint FIFO Configuration

SFR Registers

UEPSTA0

UEPSTA2

UEPCON0

UEPDAT0

UEPDAT2

0

1

2

Endpoint 0

Endpoint 2

UBYCT0

UEPSTAX

UEPCONX

UBYCTX

UEPDATX

X

UEPCON2

UBYCT2

UEPNUM

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16.5 Bulk/Interrupt

Transactions

Bulk and Interrupt transactions are managed in the same way.

16.5.1 Bulk/Interrupt OUT

Transactions in Standard

Mode

Figure 65. Bulk/Interrupt OUT transactions in Standard Mode

HOST

UFI

C51

OUT DATA0 (n Bytes)

ACK

RXOUTB0

Endpoint FIFO Read Byte 1

Endpoint FIFO Read Byte 2

OUT DATA1

NAK

Endpoint FIFO Read Byte n

Clear RXOUTB0

DATA1

OUT

ACK

RXOUTB0

Endpoint FIFO Read Byte 1

An endpoint should be first enabled and configured before being able to receive Bulk or

Interrupt packets.

When a valid OUT packet is received on an endpoint, the RXOUTB0 bit is set by the

USB controller. This triggers an interrupt if enabled. The firmware has to select the cor-

responding endpoint, store the number of data Bytes by reading the UBYCTX register. If

the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal

to 0 and no data has to be read.

When all the endpoint FIFO Bytes have been read, the firmware should clear the

RXOUTB0 bit to allow the USB controller to accept the next OUT packet on this end-

point. Until the RXOUTB0 bit has been cleared by the firmware, the USB controller will

answer a NAK handshake for each OUT requests.

If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data

won’t be stored, but the USB controller will consider that the packet is valid if the CRC is

correct and the endpoint Byte counter contains the number of Bytes sent by the Host.

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16.5.2 Bulk/Interrupt OUT

Transactions in Ping-pong

Mode

Figure 66. Bulk/Interrupt OUT Transactions in Ping-pong Mode

HOST

UFI

C51

OUT DATA0 (n Bytes)

ACK

RXOUTB0

Endpoint FIFO bank 0 - Read Byte 1

Endpoint FIFO bank 0 - Read Byte 2

DATA1 (m Bytes)

OUT

ACK

Endpoint FIFO bank 0 - Read Byte n

Clear RXOUTB0

RXOUTB1

RXOUTB0

OUT DATA0 (p Bytes)

Endpoint FIFO bank 1 - Read Byte 1

Endpoint FIFO bank 1 - Read Byte 2

Endpoint FIFO bank 1 - Read Byte m

Clear RXOUTB1

Endpoint FIFO bank 0 - Read Byte 1

Endpoint FIFO bank 0 - Read Byte 2

Endpoint FIFO bank 0 - Read Byte p

Clear RXOUTB0

An endpoint should be first enabled and configured before being able to receive Bulk or

Interrupt packets.

When a valid OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by

the USB controller. This triggers an interrupt if enabled. The firmware has to select the

corresponding endpoint, store the number of data Bytes by reading the UBYCTX regis-

ter. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is

equal to 0 and no data has to be read.

When all the endpoint FIFO Bytes have been read, the firmware should clear the

RXOUB0 bit to allow the USB controller to accept the next OUT packet on the endpoint

bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has

been cleared by the firmware, the USB controller will answer a NAK handshake for each

OUT requests on the bank 0 endpoint FIFO.

When a new valid OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is

set by the USB controller. This triggers an interrupt if enabled. The firmware empties the

bank 1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has

been cleared by the firmware, the USB controller will answer a NAK handshake for each

OUT requests on the bank 1 endpoint FIFO.

The RXOUTB0 and RXOUTB1 bits are, alternatively, set by the USB controller at each

new valid packet receipt.

The firmware has to clear one of these 2 bits after having read all the data FIFO to allow

a new valid packet to be stored in the corresponding bank.

A NAK handshake is sent by the USB controller only if the banks 0 and 1 has not been

released by the firmware.

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If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data

won’t be stored, but the USB controller will consider that the packet is valid if the CRC is

correct.

16.5.3 Bulk/Interrupt IN

Transactions in Standard

Mode

Figure 67. Bulk/Interrupt IN Transactions in Standard Mode

HOST

UFI

C51

Endpoint FIFO Write Byte 1

Endpoint FIFO Write Byte 2

IN

NAK

Endpoint FIFO Write Byte n

Set TXRDY

IN

DATA0 (n Bytes)

TXCMPL

ACK

Clear TXCMPL

Endpoint FIFO Write Byte 1

An endpoint should be first enabled and configured before being able to send Bulk or

Interrupt packets.

The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the

UEPSTAX register to allow the USB controller to send the data stored in FIFO at the

next IN request concerning this endpoint. To send a Zero Length Packet, the firmware

should set the TXRDY bit without writing any data into the endpoint FIFO.

Until the TXRDY bit has been set by the firmware, the USB controller will answer a NAK

handshake for each IN requests.

To cancel the sending of this packet, the firmware has to reset the TXRDY bit. The

packet stored in the endpoint FIFO is then cleared and a new packet can be written and

sent.

When the IN packet has been sent and acknowledged by the Host, the TXCMPL bit in

the UEPSTAX register is set by the USB controller. This triggers a USB interrupt if

enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO with

new data.

The firmware should never write more Bytes than supported by the endpoint FIFO.

All USB retry mechanisms are automatically managed by the USB controller.

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16.5.4 Bulk/Interrupt IN

Transactions in Ping-pong

Mode

Figure 68. Bulk/Interrupt IN transactions in Ping-pong mode

UFI

C51

HOST

Endpoint FIFO bank 0 - Write Byte 1

Endpoint FIFO bank 0 - Write Byte 2

IN

NACK

Endpoint FIFO bank 0 - Write Byte n

Set TXRDY

IN

Endpoint FIFO bank 1 - Write Byte 1

Endpoint FIFO bank 1 - Write Byte 2

DATA0 (n Bytes)

ACK

Endpoint FIFO bank 1 - Write Byte m

Clear TXCMPL

TXCMPL

Set TXRDY

IN

Endpoint FIFO bank 0 - Write Byte 1

Endpoint FIFO bank 0 - Write Byte 2

DATA1 (m Bytes)

ACK

Endpoint FIFO bank 0 - Write Byte p

Clear TXCMPL

TXCMPL

Set TXRDY

IN

Endpoint FIFO bank 1 - Write Byte 1

DATA0 (p Bytes)

ACK

An endpoint should be first enabled and configured before being able to send Bulk or

Interrupt packets.

The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit

in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at

the next IN request concerning the endpoint. The FIFO banks are automatically

switched, and the firmware can immediately write into the endpoint FIFO bank 1.

When the IN packet concerning the bank 0 has been sent and acknowledged by the

Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if

enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO

bank 0 with new data. The FIFO banks are then automatically switched.

When the IN packet concerning the bank 1 has been sent and acknowledged by the

Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if

enabled. The firmware should clear the TXCMPL bit before filling the endpoint FIFO

bank 1 with new data.

The bank switch is performed by the USB controller each time the TXRDY bit is set by

the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank,

the USB controller will answer a NAK handshake for each IN requests concerning this

bank.

Note that in the example above, the firmware clears the Transmit Complete bit

(TXCBulk-outMPL) before setting the Transmit Ready bit (TXRDY). This is done in order

to avoid the firmware to clear at the same time the TXCMPL bit for for bank 0 and the

bank 1.

The firmware should never write more Bytes than supported by the endpoint FIFO.

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16.6 Control

Transactions

16.6.1 Setup Stage

The DIR bit in the UEPSTAX register should be at 0.

Receiving Setup packets is the same as receiving Bulk Out packets, except that the

RXSETUP bit in the UEPSTAX register is set by the USB controller instead of the

RXOUTB0 bit to indicate that an Out packet with a Setup PID has been received on the

Control endpoint. When the RXSETUP bit has been set, all the other bits of the UEP-

STAX register are cleared and an interrupt is triggered if enabled.

The firmware has to read the Setup request stored in the Control endpoint FIFO before

clearing the RXSETUP bit to free the endpoint FIFO for the next transaction.

16.6.2 Data Stage: Control

Endpoint Direction

The data stage management is similar to Bulk management.

A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and

OUT. All other endpoint types are managed as half-duplex endpoint: IN or OUT. The

firmware has to specify the control endpoint direction for the data stage using the DIR bit

in the UEPSTAX register.

•

If the data stage consists of INs, the firmware has to set the DIR bit in the UEPSTAX

register before writing into the FIFO and sending the data by setting to 1 the TXRDY

bit in the UEPSTAX register. The IN transaction is complete when the TXCMPL has

been set by the hardware. The firmware should clear the TXCMPL bit before any

other transaction.

•

If the data stage consists of OUTs, the firmware has to leave the DIR bit at 0. The

RXOUTB0 bit is set by hardware when a new valid packet has been received on the

endpoint. The firmware must read the data stored into the FIFO and then clear the

RXOUTB0 bit to reset the FIFO and to allow the next transaction.

To send a STALL handshake, see “STALL Handshake” on page 96.

16.6.3 Status Stage

The DIR bit in the UEPSTAX register should be reset at 0 for IN and OUT status stage.

The status stage management is similar to Bulk management.

•

For a Control Write transaction or a No-Data Control transaction, the status stage

consists of a IN Zero Length Packet (see “Bulk/Interrupt IN Transactions in

Standard Mode” on page 91). To send a STALL handshake, see “STALL

Handshake” on page 96.

•

For a Control Read transaction, the status stage consists of a OUT Zero Length

Packet (see “Bulk/Interrupt OUT Transactions in Standard Mode” on page 89).

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Isochronous Transactions

16.6.4 Isochronous OUT

Transactions in Standard

Mode

An endpoint should be first enabled and configured before being able to receive Isochro-

nous packets.

When an OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB

controller. This triggers an interrupt if enabled. The firmware has to select the corre

Bulk-outsponding endpoint, store the number of data Bytes by reading the UBYCTX

register. If the received packet is a ZLP (Zero Length Packet), the UBYCTX register

value is equal to 0 and no data has to be read.

The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet

stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt.

When all the endpoint FIFO Bytes have been read, the firmware should clear the

RXOUTB0 bit to allow the USB controller to store the next OUT packet data into the

endpoint FIFO. Until the RXOUTB0 bit has been cleared by the firmware, the data sent

by the Host at each OUT transaction will be lost.

If the RXOUTB0 bit is cleared while the Host is sending data, the USB controller will

store only the remaining Bytes into the FIFO.

If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data

won’t be stored, but the USB controller will consider that the packet is valid if the CRC is

correct.

16.6.5 Isochronous OUT

Transactions in Ping-pong

Mode

An endpoint should be first enabled and configured before being able to receive Isochro-

nous packets.

When a OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the

USB controller. This triggers an interrupt if enabled. The firmware has to select the cor-

responding endpoint, store the number of data Bytes by reading the UBYCTX register. If

the received packet is a ZLP (Zero Length Packet), the UBYCTX register value is equal

to 0 and no data has to be read.

The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet

stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt.

When all the endpoint FIFO Bytes have been read, the firmware should clear the

RXOUB0 bit to allow the USB controller to store the next OUT packet data into the end-

point FIFO bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0

bit has been cleared by the firmware, the data sent by the Host on the bank 0 endpoint

FIFO will be lost.

If the RXOUTB0 bit is cleared while the Host is sending data on the endpoint bank 0, the

USB controller will store only the remaining Bytes into the FIFO.

When a new OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by

the USB controller. This triggers an interrupt if enabled. The firmware empties the bank

1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been

cleared by the firmware, the data sent by the Host on the bank 1 endpoint FIFO will be

lost.

The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each

new packet receipt.

The firmware has to clear one of these 2 bits after having read all the data FIFO to allow

a new packet to be stored in the corresponding bank.

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If the Host sends more Bytes than supported by the endpoint FIFO, the overflow data

won’t be stored, but the USB controller will consider that the packet is valid if the CRC is

correct.

16.6.6 Isochronous IN

Transactions in Standard

Mode

An endpoint should be first enabled and configured before being able to send Isochro-

nous packets.

The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the

UEPSTAX register to allow the USB controller to send the data stored in FIFO at the

next IN request concerning this endpoint.

If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB

controller.

When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by

the USB controller. This triggers a USB interrupt if enabled. The firmware should clear

the TXCMPL bit before filling the endpoint FIFO with new data.

The firmware should never write more Bytes than supported by the endpoint FIFO

16.6.7 Isochronous IN

Transactions in Ping-pong

Mode

An endpoint should be first enabled and configured before being able to send Isochro-

nous packets.

The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit

in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at

the next IN request concerning the endpoint. The FIFO banks are automatically

switched, and the firmware can immediately write into the endpoint FIFO bank 1.

If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB

controller.

When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the

USB controller. This triggers a USB interrupt if enabled. The firmware should clear the

TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks are

then automatically switched.

When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the

USB controller. This triggers a USB interrupt if enabled. The firmware should clear the

TXCMPL bit before filling the endpoint FIFO bank 1 with new data.

The bank switch is performed by the USB controller each time the TXRDY bit is set by

the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank,

the USB controller won’t send anything at each IN requests concerning this bank.

The firmware should never write more Bytes than supported by the endpoint FIFO.

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16.7 Miscellaneous

16.7.1 USB Reset

The EORINT bit in the USBINT register is set by hardware when a End Of Reset has

been detected on the USB bus. This triggers a USB interrupt if enabled. The USB con-

troller is still enabled, but all the USB registers are reset by hardware. The firmware

should clear the EORINT bit to allow the next USB reset detection.

16.7.2 STALL Handshake

This function is only available for Control, Bulk, and Interrupt endpoints.

The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL

handshake at the next request of the Host on the endpoint selected with the UEPNUM

register. The RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first

resseted to 0. The bit STLCRC is set at 1 by the USB controller when a STALL has been

sent. This triggers an interrupt if enabled.

The firmware should clear the STALLRQ and STLCRC bits after each STALL sent.

The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is

received on a CONTROL type endpoint.

Important note: when a Clear Halt Feature occurs for an endpoint, the firmware should

reset this endpoint using the UEPRST resgister in order to reset the data toggle

management.

16.7.3 Start of Frame

Detection

The SOFINT bit in the USBINT register is set when the USB controller detects a Start Of

Frame PID. This triggers an interrupt if enabled. The firmware should clear the SOFINT

bit to allow the next Start of Frame detection.

16.7.4 Frame Number

When receiving a Start Of Frame, the frame number is automatically stored in the

UFNUML and UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of

the last Start Of Frame is valid (CRCOK set at 1) or corrupted (CRCERR set at 1). The

UFNUML and UFNUMH registers are automatically updated when receiving a new Start

of Frame.

16.7.5 Data Toggle Bit

The Data Toggle bit is set by hardware when a DATA0 packet is received and accepted

by the USB controller and cleared by hardware when a DATA1 packet is received and

accepted by the USB controller. This bit is reset when the firmware resets the endpoint

FIFO using the UEPRST register.

For Control endpoints, each SETUP transaction starts with a DATA0 and data toggling

is then used as for Bulk endpoints until the end of the Data stage (for a control write

transfer). The Status stage completes the data transfer with a DATA1 (for a control read

transfer).

For Isochronous endpoints, the device firmware should ignore the data-toggle.

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Suspend/Resume Management

16.7.6 Suspend

The Suspend state can be detected by the USB controller if all the clocks are enabled

and if the USB controller is enabled. The bit SPINT is set by hardware when an idle

state is detected for more than 3 ms. This triggers a USB interrupt if enabled.

In order to reduce current consumption, the firmware can put the USB PAD in idle mode,

stop the clocks and put the C51 in Idle or Power-down mode. The Resume detection is

still active.

The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to

avoid a new suspend detection 3ms later, the firmware has to disable the USB clock

input using the SUSPCLK bit in the USBCON Register. The USB PAD automatically

exits of idle mode when a wake-up event is detected.

The stop of the 48 MHz clock from the PLL should be done in the following order:

1. Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUS-

PCLK bit in the USBCON register.

2. Disable the PLL by clearing the PLLEN bit in the PLLCON register.

16.7.7 Resume

When the USB controller is in Suspend state, the Resume detection is active even if all

the clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit

is set by hardware when a non-idle state occurs on the USB bus. This triggers an inter-

rupt if enabled. This interrupt wakes up the CPU from its Idle or Power-down state and

the interrupt function is then executed. The firmware will first enable the 48 MHz gener-

ation and then reset to 0 the SUSPCLK bit in the USBCON register if needed.

The firmware has to clear the SPINT bit in the USBINT register before any other USB

operation in order to wake up the USB controller from its Suspend mode.

The USB controller is then re-activated.

Figure 69. Example of a Suspend/Resume Management

USB Controller Init

SPINT

Detection of a SUSPEND State

Clear SPINT

Set SUSPCLK

Disable PLL

microcontroller in Power-down

WUPCPU

Detection of a RESUME State

Enable PLL

Clear SUSPCLK

Clear WUPCPU Bit

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16.7.8 Upstream Resume

A USB device can be allowed by the Host to send an upstream resume for Remote

Wake-up purpose.

When the USB controller receives the SET_FEATURE request:

DEVICE_REMOTE_WAKEUP, the firmware should set to 1 the RMWUPE bit in the

USBCON register to enable this functionality. RMWUPE value should be 0 in the other

cases.

If the device is in SUSPEND mode, the USB controller can send an upstream resume by

clearing first the SPINT bit in the USBINT register and by setting then to 1 the SDRM-

WUP bit in the USBCON register. The USB controller sets to 1 the UPRSM bit in the

USBCON register. All clocks must be enabled first. The Remote Wake is sent only if the

USB bus was in Suspend state for at least 5ms. When the upstream resume is com-

pleted, the UPRSM bit is reset to 0 by hardware. The firmware should then clear the

SDRMWUP bit.

Figure 70. Example of REMOTE WAKEUP Management

USB Controller Init

SET_FEATURE: DEVICE_REMOTE_WAKEUP

Set RMWUPE

SPINT

Detection of a SUSPEND state

Suspend Management

need USB resume

enable clocks

Clear SPINT

Set SDMWUP

UPRSM = 1

UPRSM

upstream RESUME sent

Clear SDRMWUP

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16.8 USB Interrupt

System

16.8.1 Interrupt System

Priorities

Figure 71. USB Interrupt Control System

00

01

10

11

D+

D-

USB

Controller

EUSB

IE1.6

EA

IE0.7

IPH/L

Interrupt Enable

Priority Enable

Lowest Priority Interrupts

Table 1. Priority Levels

IPHUSB

IPLUSB

USB Priority Level

0

1

0

1

0

1

0..................Lowest

1

2

3..................Highest

16.8.2 USB Interrupt Control

System

As shown in Figure 72, many events can produce a USB interrupt:

•

TXCMPL: Transmitted In Data (Table 16 on page 105). This bit is set by hardware

when the Host accept a In packet.

RXOUTB0: Received Out Data Bank 0 (Table 16 on page 105). This bit is set by

hardware when an Out packet is accepted by the endpoint and stored in bank 0.

RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (Table 16 on

page 105). This bit is set by hardware when an Out packet is accepted by the

endpoint and stored in bank 1.

•

RXSETUP: Received Setup (Table 16 on page 105). This bit is set by hardware

when an SETUP packet is accepted by the endpoint.

STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (Table 16 on

page 105). This bit is set by hardware when a STALL handshake has been sent as

requested by STALLRQ, and is reset by hardware when a SETUP packet is

received.

•

SOFINT: Start of Frame Interrupt (Table 12 on page 102). This bit is set by hardware

when a USB start of frame packet has been received.

WUPCPU: Wake-Up CPU Interrupt (Table 12 on page 102). This bit is set by

hardware when a USB resume is detected on the USB bus, after a SUSPEND state.

SPINT: Suspend Interrupt (Table 12 on page 102). This bit is set by hardware when

a USB suspend is detected on the USB bus.

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Figure 72. USB Interrupt Control Block Diagram

Endpoint X (X = 0..2)

TXCMP

UEPSTAX.0

RXOUTB0

UEPSTAX.1

RXOUTB1

UEPSTAX.6

EPXINT

UEPINT.X

RXSETUP

UEPSTAX.2

EPXIE

UEPIEN.X

STLCRC

UEPSTAX.3

NAKOUT

UEPCONX.5

NAKIN

UEPCONX.4

NAKIEN

UEPCONX.6

WUPCPU

USBINT.5

EUSB

IE1.6

EWUPCPU

USBIEN.5

EORINT

USBINT.4

EEORINT

USBIEN.4

SOFINT

USBINT.3

ESOFINT

USBIEN.3

SPINT

USBINT.0

ESPINT

USBIEN.0

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16.9 Registers

Table 10. USBCON Register

USBCON (S:BCh) – USB Global Control Register

7

6

5

4

-

3

2

1

0

USBE

SUSPCLK SDRMWUP

UPRSM

RMWUPE

CONFG

FADDEN

Bit

Number

Mnemonic Description

USB Enable Bit

Set this bit to enable the USB controller.

Clear this bit to disable and reset the USB controller, to disable the USB

transceiver an to disable the USB controllor clock inputs.

7

6

USBE

Suspend USB Clock Bit

SUSPCLK Set to disable the 48 MHz clock input (Resume Detection is still active).

Clear to enable the 48 MHz clock input.

Send Remote Wake-Up Bit

Set to force an external interrupt on the USB controller for Remote Wake UP

purpose.

SDRMWU

5

An upstream resume is send only if the bit RMWUPE is set, all USB clocks are

enabled AND the USB bus was in SUSPEND state for at least 5 ms. See

P

UPRSM below.

Cleared by software.

Reserved

4

3

-

The value read from this bit is always 0. Do not set this bit.

Upstream Resume Bit (read only)

UPRSM Set by hardware when SDRMWUP has been set and if RMWUPE is enabled.

Cleared by hardware after the upstream resume has been sent.

Remote Wake-Up Enable Bit

Set to enabled request an upstream resume signaling to the host.

Clear after the upstream resume has been indicated by RSMINPR.

RMWUPE

2

1

Note: Do not set this bit if the host has not set the DEVICE_REMOTE_WAKEUP

feature for the device.

Configuration Bit

This bit should be set by the device firmware after a SET_CONFIGURATION

request with a non-zero value has been correctly processed.

CONFG It should be cleared by the device firmware when a SET_CONFIGURATION

request with a zero value is received. It is cleared by hardware on hardware

reset or when an USB reset is detected on the bus (SE0 state for at least 32 Full

Speed bit times: typically 2.7 µs).

Function Address Enable Bit

This bit should be set by the device firmware after a successful status phase of a

SET_ADDRESS transaction.

It should not be cleared afterwards by the device firmware. It is cleared by

0

FADDEN

hardware on hardware reset or when an USB reset is received (see above).

When this bit is cleared, the default function address is used (0).

Reset Value = 0000 0000b

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Table 11. USBADDR Register

USBADDR (S:C6h) – USB Address Register

7

6

5

4

3

2

1

0

FEN

UADD6

UADD5

UADD4

UADD3

UADD2

UADD1

UADD0

Bit

Number

Mnemonic Description

Function Enable Bit

Set to enable the function. The device firmware should set this bit after it has

received a USB reset and participate in the following configuration process with

the default address (FEN is reset to 0).

7

FEN

Cleared by hardware at power-up, should not be cleared by the device firmware

once set.

USB Address Bits

This field contains the default address (0) after power-up or USB bus reset.

It should be written with the value set by a SET_ADDRESS request received by

the device firmware.

6 - 0

UADD6:0

Reset Value = 0000 0000b

Table 12. USBINT Register

USBINT (S:BDh) – USB Global Interrupt Register

7

-

6

-

5

4

3

2

-

1

-

0

WUPCPU

EORINT

SOFINT

SPINT

Bit

Number

Mnemonic Description

Reserved

7 - 6

-

The value read from these bits is always 0. Do not set these bits.

Wake Up CPU Interrupt Flag

Set by hardware when the USB controller is in SUSPEND state and is re-

WUPCPU activated by a non-idle signal from USB line (not by an upstream resume). This

triggers a USB interrupt when EWUPCPU is set in the USBIEN.

5

Cleared by software after re-enabling all USB clocks.

End of Reset Interrupt Flag

Set by hardware when a End of Reset has been detected by the USB controller.

This triggers a USB interrupt when EEORINT is set in USBIEN.

4

EORINT

Cleared by software.

Start of Frame Interrupt Flag

Set by hardware when an USB Start of Frame packet (SOF) has been properly

received. This triggers a USB interrupt when ESOFINT is set in USBIEN.

3

SOFINT

Cleared by software.

Reserved

2 - 1

-

The value read from these bits is always 0. Do not set these bits.

Suspend Interrupt Flag

Set by hardware when a USB Suspend (Idle bus for three frame periods: a J

0

SPINT

state for 3 ms) is detected. This triggers a USB interrupt when ESPINT is set in

USBIEN.

Cleared by software.

Reset Value = 0000 0000b

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Table 13. USBIEN Register

USBIEN (S:BEh) – USB Global Interrupt Enable Register

7

-

6

-

5

4

3

2

-

1

-

0

EWUPCPU EEORINT

ESOFINT

ESPINT

Bit

Number

Mnemonic Description

Reserved

7 - 6

5

-

The value read from these bits is always 0. Do not set these bits.

Wake Up CPU Interrupt Enable Bit

Set to enable the Wake Up CPU interrupt.

Clear to disable the Wake Up CPU interrupt.

EWUPCP

U

End Of Reset Interrupt Enable Bit

4

EEOFINT Set to enable the End Of Reset interrupt. This bit is set after reset.

Clear to disable End Of Reset interrupt.

Start Of Frame Interrupt Enable Bit

ESOFINT Set to enable the SOF interrupt.

Clear to disable the SOF interrupt.

3

2 - 1

0

Reserved

-

The value read from these bits is always 0. Do not set these bits.

Suspend Interrupt Enable Bit

ESPINT Set to enable Suspend interrupt.

Clear to disable Suspend interrupt.

Reset Value = 0001 0000b

Table 14. UEPNUM Register

UEPNUM (S:C7h) – USB Endpoint Number

7

-

6

-

5

-

4

-

3

-

2

-

1

0

EPNUM1

EPNUM0

Bit

Number

Mnemonic Description

Reserved

7 - 2

1 - 0

-

The value read from these bits is always 0. Do not set these bits.

Endpoint Number Bits

Set this field with the number of the endpoint which should be accessed when

reading or writing to registers UEPSTAX, UEPDATX, UBYCTX or UEPCONX.

EPNUM1:

0

Reset Value = 0000 0000b

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Table 15. UEPCONX Register

UEPCONX (S:D4h) – USB Endpoint X Control Register (X = EPNUM set in UEPNUM)

7

6

5

4

3

2

1

0

EPEN

NAKIEN

NAKOUT

NAKIN

DTGL

EPDIR

EPTYPE1

EPTYPE0

Bit

Number

Mnemonic Description

Endpoint Enable Bit

Set to enable the endpoint according to the device configuration. Endpoint 0

should always be enabled after a hardware or USB bus reset and participate in

the device configuration.

7

6

5

EPEN

Clear to disable the endpoint according to the device configuration.

NAK Interrupt enable

NAKIEN Set this bit to enable NAK IN or NAK OUT interrupt.

Clear this bit to disable NAK IN or NAK OUT Interrupt.

NAK OUT received

This bit is set by hardware when an NAK handshake has been sent in response

NAKOUT of a OUT request from the Host. This triggers a USB interrupt when NAKIEN is

set.

This bit should be cleared by software.

NAK IN received

This bit is set by hardware when an NAK handshake has been sent in response

of a IN request from the Host. This triggers a USB interrupt when NAKIEN is set.

This bit should be cleared by software.

4

3

2

NAKIN

Data Toggle Status Bit (Read-only)

Set by hardware when a DATA1 packet is received.

Cleared by hardware when a DATA0 packet is received.

DTGL

Endpoint Direction Bit

Set to configure IN direction for Bulk, Interrupt and Isochronous endpoints.

Clear to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.

This bit has no effect for Control endpoints.

EPDIR

Endpoint Type Bits

Set this field according to the endpoint configuration (Endpoint 0 should always

be configured as Control):

00 Control endpoint

EPTYPE1:

0

1-0

01 Isochronous endpoint

10 Bulk endpoint

11 Interrupt endpoint

Reset Value = 1000 0000b

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Table 16. UEPSTAX Register

UEPSTAX (S:CEh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM)

7

6

5

4

3

2

1

0

DIR

RXOUTB1 STALLRQ

TXRDY

STLCRC

RXSETUP RXOUTB0

TXCMP

Bit

Number

Mnemonic Description

Control Endpoint Direction Bit

This bit is relevant only if the endpoint is configured in Control type.

Set for the data stage. Clear otherwise.

7

DIR

Note: This bit should be configured on RXSETUP interrupt before any other bit is

changed. This also determines the status phase (IN for a control write and OUT

for a control read). This bit should be cleared for status stage of a Control Out

transaction.

Received OUT Data Bank 1 for Endpoints 1 and 2 (Ping-pong mode)

This bit is set by hardware after a new packet has been stored in the endpoint

FIFO data bank 1 (only in Ping-pong mode). Then, the endpoint interrupt is

triggered if enabled and all the following OUT packets to the endpoint bank 1 are

rejected (NAK’ed) until this bit has been cleared, excepted for Isochronous

Endpoints.

6

RXOUTB1

This bit should be cleared by the device firmware after reading the OUT data

from the endpoint FIFO.

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Bit

Number

Mnemonic Description

Stall Handshake Request Bit

Set to send a STALL answer to the host for the next handshake. Clear otherwise.

5

STALLRQ

TX Packet Ready Control Bit

Set after a packet has been written into the endpoint FIFO for IN data transfers.

Data should be written into the endpoint FIFO only after this bit has been cleared.

Set this bit without writing data to the endpoint FIFO to send a Zero Length

Packet, which is generally recommended and may be required to terminate a

transfer when the length of the last data packet is equal to MaxPacketSize (e.g.

for control read transfers).

4

TXRDY

Cleared by hardware, as soon as the packet has been sent for Isochronous

endpoints, or after the host has acknowledged the packet for Control, Bulk and

Interrupt endpoints.

Stall Sent Interrupt Flag/CRC Error Interrupt Flag

For Control, Bulk and Interrupt Endpoints:

Set by hardware after a STALL handshake has been sent as requested by

STALLRQ. Then, the endpoint interrupt is triggered if enabled in UEPIEN.

3

2

1

STLCRC Cleared by hardware when a SETUP packet is received (see RXSETUP).

For Isochronous Endpoints:

Set by hardware if the last data received is corrupted (CRC error on data). Then,

the endpoint interrupt is triggered if enabled in UEPIEN.

Cleared by hardware when a non corrupted data is received.

Received SETUP Interrupt Flag

Set by hardware when a valid SETUP packet has been received from the host.

RXSETUP Then, all the other bits of the register are cleared by hardware and the endpoint

interrupt is triggered if enabled in UEPIEN.

Clear by software after reading the SETUP data from the endpoint FIFO.

Received OUT Data Bank 0 (see also RXOUTB1 bit for Ping-pong Endpoints)

This bit is set by hardware after a new packet has been stored in the endpoint

FIFO data bank 0. Then, the endpoint interrupt is triggered if enabled and all the

following OUT packets to the endpoint bank 0 are rejected (NAK’ed) until this bit

RXOUTB0 has been cleared, excepted for Isochronous Endpoints. However, for control

endpoints, an early SETUP transaction may overwrite the content of the endpoint

FIFO, even if its Data packet is received while this bit is set.

This bit should be cleared by the device firmware after reading the OUT data

from the endpoint FIFO.

Transmitted IN Data Complete Interrupt Flag

Set by hardware after an IN packet has been transmitted for Isochronous

endpoints and after it has been accepted (ACK’ed) by the host for Control, Bulk

and Interrupt endpoints. Then, the endpoint interrupt is triggered if enabled in

0

TXCMP

UEPIEN.

Clear by software before setting again TXRDY.

Reset Value = 0000 0000b

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Table 17. UEPRST Register

UEPRST (S:D5h) – USB Endpoint FIFO Reset Register

7

-

6

-

5

-

4

-

3

-

2

1

0

EP2RST

EP1RST

EP0RST

Bit

Number

Mnemonic Description

Reserved

7 - 3

2

-

The value read from these bits is always 0. Do not set these bits.

Endpoint 2 FIFO Reset

EP2RST Set and clear to reset the endpoint 2 FIFO prior to any other operation, upon

hardware reset or when an USB bus reset has been received.

Endpoint 1 FIFO Reset

1

0

EP1RST Set and clear to reset the endpoint 1 FIFO prior to any other operation, upon

hardware reset or when an USB bus reset has been received.

Endpoint 0 FIFO Reset

EP0RST Set and clear to reset the endpoint 0 FIFO prior to any other operation, upon

hardware reset or when an USB bus reset has been received.

Reset Value = 0000 0000b

Table 18. UEPIEN Register

UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register

7

-

6

-

5

-

4

-

3

-

2

1

0

EP2INTE

EP1INTE

EP0INTE

Bit

Number

Mnemonic Description

Reserved

7 - 3

2

-

The value read from these bits is always 0. Do not set these bits.

Endpoint 2 Interrupt Enable Bit

EP2INTE Set to enable the interrupts for endpoint 2.

Clear this bit to disable the interrupts for endpoint 2.

Endpoint 1 Interrupt Enable Bit

1

0

EP1INTE Set to enable the interrupts for the endpoint 1.

Clear to disable the interrupts for the endpoint 1.

Endpoint 0 Interrupt Enable Bit

EP0INTE Set to enable the interrupts for the endpoint 0.

Clear to disable the interrupts for the endpoint 0.

Reset Value = 0000 0000b

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Table 19. UEPINT Register

UEPINT (S:F8h Read-only) – USB Endpoint Interrupt Register

7

-

6

-

5

-

4

-

3

-

2

1

0

EP2INT

EP1INT

EP0INT

Bit

Number

Mnemonic Description

Reserved

7 - 3

-

The value read from these bits is always 0. Do not set these bits.

Endpoint 2 Interrupt Flag

This bit is set by hardware when an endpoint interrupt source has been detected

on the endpoint 2. The endpoint interrupt sources are in the UEPSTAX register

and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

2

EP2INT

EP1INT

EP0INT

A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are

cleared.

Endpoint 1 Interrupt Flag

This bit is set by hardware when an endpoint interrupt source has been detected

on the endpoint 1. The endpoint interrupt sources are in the UEPSTAX register

and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

1

A USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are

cleared.

Endpoint 0 Interrupt Flag

This bit is set by hardware when an endpoint interrupt source has been detected

on the endpoint 0. The endpoint interrupt sources are in the UEPSTAX register

and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC.

0

A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set.

This bit is cleared by hardware when all the endpoint interrupt sources are

cleared.

Reset Value = 0000 0000b

Table 20. UEPDATX Register

UEPDATX (S:CFh) – USB Endpoint X FIFO Data Register (X = EPNUM set in UEPNUM)

7

6

5

4

3

2

1

0

FDAT7

FDAT6

FDAT5

FDAT4

FDAT3

FDAT2

FDAT1

FDAT0

Bit

Number

Mnemonic Description

Endpoint X FIFO Data

7 - 0

FDAT7:0 Data Byte to be written to FIFO or data Byte to be read from the FIFO, for the

Endpoint X (see EPNUM).

Reset Value = XXh

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Table 21. UBYCTX Register

UBYCTX (S:E2h) – USB Endpoint X Byte Count Register (X = EPNUM set in UEPNUM)

7

-

6

5

4

3

2

1

0

BYCT6

BYCT5

BYCT4

BYCT3

BYCT2

BYCT1

BYCT0

Bit

Number

Mnemonic Description

Reserved

7

-

The value read from this bits is always 0. Do not set this bit.

Byte Count

6 - 0

BYCT7:0 Byte count of a received data packet. This Byte count is equal to the number of

data Bytes received after the Data PID.

Reset Value = 0000 0000b

Table 22. UFNUML Register

UFNUML (S:BAh, Read-only) – USB Frame Number Low Register

7

6

5

4

3

2

1

0

FNUM7

FNUM6

FNUM5

FNUM4

FNUM3

FNUM2

FNUM1

FNUM0

Bit

Number

Mnemonic Description

Frame Number

Lower 8 bits of the 11-bit Frame Number.

7 - 0

FNUM7:0

Reset Value = 00h

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Table 23. UFNUMH Register

UFNUMH (S:BBh, Read-only) – USB Frame Number High Register

7

-

6

-

5

4

3

-

2

1

0

CRCOK

CRCERR

FNUM10

FNUM9

FNUM8

Bit

Number

Mnemonic Description

Reserved

7 - 3

-

The value read from these bits is always 0. Do not set these bits.

Frame Number CRC OK Bit

Set by hardware after a non corrupted Frame Number in Start of Frame Packet is

received.

5

CRCOK

Updated after every Start Of Frame packet reception.

Note: The Start Of Frame interrupt is generated just after the PID receipt.

Frame Number CRC Error Bit

Set by hardware after a corrupted Frame Number in Start of Frame Packet is

received.

4

CRCERR

Updated after every Start Of Frame packet reception.

Note: The Start Of Frame interrupt is generated just after the PID receipt.

Reserved

3

-

The value read from this bits is always 0. Do not set this bit.

Frame Number

2-0

FNUM10:8 Upper 3 bits of the 11-bit Frame Number. It is provided in the last received SOF

packet. FNUM does not change if a corrupted SOF is received.

Reset Value = 00h

Table 24. USBCLK Register

USBCLK (S:EAh) – USB Clock Divider Register

7

-

6

-

5

-

4

-

3

-

2

-

1

0

USBCD1

USBCD0

Bit

Number

Mnemonic Description

Reserved

7 - 2

1 - 0

-

The value read from these bits is always 0. Do not set these bits.

USB Controller Clock Divider

2-bit divider for USB controller clock generation.

USBCD1:0

Reset Value = 0000 0000b

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17. MultiMedia Card

Controller

The AT8xC51SND1C implements a MultiMedia Card (MMC) controller. The MMC is

used to store MP3 encoded audio files in removable Flash memory cards that can be

easily plugged or removed from the application.

17.1 Card Concept

The basic MultiMedia Card concept is based on transferring data via a minimum number

of signals.

17.1.1 Card Signals

The communication signals are:

•

CLK: with each cycle of this signal a one bit transfer on the command and data lines

is done. The frequency may vary from zero to the maximum clock frequency.

•

CMD: is a bi-directional command channel used for card initialization and data

transfer commands. The CMD signal has 2 operation modes: open-drain for

initialization mode and push-pull for fast command transfer. Commands are sent

from the MultiMedia Card bus master to the card and responses from the cards to

the host.

•

DAT: is a bi-directional data channel. The DAT signal operates in push-pull mode.

Only one card or the host is driving this signal at a time.

17.1.2 Card Registers

Within the card interface five registers are defined: OCR, CID, CSD, RCA and DSR.

These can be accessed only by the corresponding commands.

The 32-bit Operation Conditions Register (OCR) stores the V_DDvoltage profile of the

card. The register is optional and can be read only.

The 128-bit wide CID register carries the card identification information (Card ID) used

during the card identification procedure.

The 128-bit wide Card-Specific Data register (CSD) provides information on how to

access the card contents. The CSD defines the data format, error correction type, maxi-

mum data access time, data transfer speed, and whether the DSR register can be used.

The 16-bit Relative Card Address register (RCA) carries the card address assigned by

the host during the card identification. This address is used for the addressed host-card

communication after the card identification procedure.

The 16-bit Driver Stage Register (DSR) can be optionally used to improve the bus per-

formance for extended operating conditions (depending on parameters like bus length,

transfer rate or number of cards).

17.2 Bus Concept

The MultiMedia Card bus is designed to connect either solid-state mass-storage mem-

ory or I/O-devices in a card format to multimedia applications. The bus implementation

allows the coverage of application fields from low-cost systems to systems with a fast

data transfer rate. It is a single master bus with a variable number of slaves. The Multi-

Media Card bus master is the bus controller and each slave is either a single mass

storage card (with possibly different technologies such as ROM, OTP, Flash etc.) or an

I/O-card with its own controlling unit (on card) to perform the data transfer.

The MultiMedia Card bus also includes power connections to supply the cards.

The bus communication uses a special protocol (MultiMedia Card bus protocol) which is

applicable for all devices. Therefore, the payload data transfer between the host and the

cards can be bi-directional.

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17.2.1 Bus Lines

The MultiMedia Card bus architecture requires all cards to be connected to the same set

of lines. No card has an individual connection to the host or other devices, which

reduces the connection costs of the MultiMedia Card system.

The bus lines can be divided into three groups:

•

Power supply: V_SS1and V_SS2, V_DD– used to supply the cards.

Data transfer: MCMD, MDAT – used for bi-directional communication.

Clock: MCLK – used to synchronize data transfer across the bus.

17.2.2 Bus Protocol

After a power-on reset, the host must initialize the cards by a special message-based

MultiMedia Card bus protocol. Each message is represented by one of the following

tokens:

•

Command: a command is a token which starts an operation. A command is

transferred serially from the host to the card on the MCMD line.

•

Response: a response is a token which is sent from an addressed card (or all

connected cards) to the host as an answer to a previously received command. It is

transferred serially on the MCMD line.

•

Data: data can be transferred from the card to the host or vice-versa. Data is

transferred serially on the MDAT line.

Card addressing is implemented using a session address assigned during the initializa-

tion phase, by the bus controller to all currently connected cards. Individual cards are

identified by their CID number. This method requires that every card will have an unique

CID number. To ensure uniqueness of CIDs the CID register contains 24 bits (MID and

OID fields) which are defined by the MMCA. Every card manufacturers is required to

apply for an unique MID (and optionally OID) number.

MultiMedia Card bus data transfers are composed of these tokens. One data transfer is

a bus operation. There are different types of operations. Addressed operations always

contain a command and a response token. In addition, some operations have a data

token, the others transfer their information directly within the command or response

structure. In this case no data token is present in an operation. The bits on the MDAT

and the MCMD lines are transferred synchronous to the host clock.

2 types of data transfer commands are defined:

•

Sequential commands: These commands initiate a continuous data stream, they

are terminated only when a stop command follows on the MCMD line. This mode

reduces the command overhead to an absolute minimum.

•

Block-oriented commands: These commands send a data block succeeded by CRC

bits. Both read and write operations allow either single or multiple block

transmission. A multiple block transmission is terminated when a stop command

follows on the MCMD line similarly to the stream read.

Figure 73 through Figure 77 show the different types of operations, on these figures,

grayed tokens are from host to card(s) while white tokens are from card(s) to host.

Figure 73. Sequential Read Operation

Stop Command

MCMD

MDAT

Command Response

Data Stream

Data Transfer Operation

Data Stop Operation

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Figure 74. (Multiple) Block Read Operation

Stop Command

MCMD

MDAT

Command Response

Data Stop Operation

Data Block CRC Data Block CRC Data Block CRC

Block Read Operation

Multiple Block Read Operation

As shown in Figure 75 and Figure 76 the data write operation uses a simple busy signal-

ling of the write operation duration on the data line (MDAT).

Figure 75. Sequential Write Operation

Stop Command

MCMD

MDAT

Command Response

Data Stream

Busy

Data Transfer Operation

Data Stop Operation

Figure 76. Multiple Block Write Operation

Stop Command

MCMD

MDAT

Command Response

Data Block CRC Status Busy

Data Stop Operation

Block Write Operation

Multiple Block Write Operation

Figure 77. No Response and No Data Operation

MCMD

MDAT

Command

Command Response

No Response Operation

No Data Operation

17.2.3 Command Token

Format

As shown in Figure 78, commands have a fixed code length of 48 bits. Each command

token is preceded by a Start bit: a low level on MCMD line and succeeded by an End bit:

a high level on MCMD line. The command content is preceded by a Transmission bit: a

high level on MCMD line for a command token (host to card) and succeeded by a 7 - bit

CRC so that transmission errors can be detected and the operation may be repeated.

Command content contains the command index and address information or parameters.

Figure 78. Command Token Format

0

1

Content

CRC

1

Total Length = 48 bits

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Table 3. Command Token Format

Bit Position

Width (Bits)

Value

47

1

46

1

45:40

39:8

32

-

7:1

7

0

6

-

1

‘0’

‘1’

-

‘1’

Transmission

bit

Command

Index

Start bit

Argument

CRC7

End bit

Description

17.3.1 Response Token

Format

There are five types of response tokens (R1 to R5). As shown in Figure 79, responses

have a code length of 48 bits or 136 bits. A response token is preceded by a Start bit: a

low level on MCMD line and succeeded by an End bit: a high level on MCMD line. The

command content is preceded by a Transmission bit: a low level on MCMD line for a

response token (card to host) and succeeded (R1,R2,R4,R5) or not (R3) by a 7 - bit

CRC.

Response content contains mirrored command and status information (R1 response),

CID register or CSD register (R2 response), OCR register (R3 response), or RCA regis-

ter (R4 and R5 response).

Figure 79. Response Token Format

R1, R4, R5

0

Content

CRC

1

Total Length = 48 bits

R3

R2

Content

Total Length = 48 bits

Content = CID or CSD

Total Length = 136 bits

CRC

1

Table 4. R1 Response Format (Normal Response)

Bit Position

Width (bits)

Value

47

1

46

1

45:40

39:8

32

-

7:1

7

0

6

-

1

‘0’

-

‘1’

Transmission

bit

Command

Index

Start bit

Card Status

CRC7

End bit

Description

Table 5. R2 Response Format (CID and CSD registers)

Bit Position

Width (bits)

Value

135

1

134

1

[133:128]

6

[127:1]

0

32

-

1

‘0’

‘111111’

‘1’

Transmission

bit

Start bit

Reserved

Argument

End bit

Description

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Table 6. R3 Response Format (OCR Register)

Bit Position

Width (bits)

Value

47

1

46

1

[45:40]

6

[39:8]

[7:1]

7

0

32

-

1

‘0’

‘111111’

‘1111111’

‘1’

Transmission

bit

OCR

register

Start bit

Reserved

End bit

Description

Table 7. R4 Response Format (Fast I/O)

Bit Position

Width (bits)

Value

47

1

46

1

[45:40]

6

[39:8]

[7:1]

0

32

-

7

-

1

‘0’

‘100111’

‘1’

Transmission

bit

Command

Index

Start bit

Argument

CRC7

End bit

Description

Table 8. R5 Response Format

Bit Position

Width (bits)

Value

47

1

46

1

[45:40]

6

[39:8]

[7:1]

0

32

-

7

-

1

‘0’

‘101000’

‘1’

Transmission

bit

Command

Index

Start bit

Argument

CRC7

End bit

Description

17.8.1 Data Packet Format

There are 2 types of data packets: stream and block. As shown in Figure 80, stream

data packets have an indeterminate length while block packets have a fixed length

depending on the block length. Each data packet is preceded by a Start bit: a low level

on MCMD line and succeeded by an End bit: a high level on MCMD line. Due to the fact

that there is no predefined end in stream packets, CRC protection is not included in this

case. The CRC protection algorithm for block data is a 16-bit CCITT polynomial.

Figure 80. Data Token Format

Sequential Data

0

Content

1

Block Data

Content

CRC

Block Length

17.8.2 Clock Control

The MMC bus clock signal can be used by the host to turn the cards into energy saving

mode or to control the data flow (to avoid under-run or over-run conditions) on the bus.

The host is allowed to lower the clock frequency or shut it down.

There are a few restrictions the host must follow:

•

The bus frequency can be changed at any time (under the restrictions of maximum

data transfer frequency, defined by the cards, and the identification frequency

defined by the specification document).

•

It is an obvious requirement that the clock must be running for the card to output

data or response tokens. After the last MultiMedia Card bus transaction, the host is

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4109H–8051–01/05

required, to provide 8 (eight) clock cycles for the card to complete the operation

before shutting down the clock. Following is a list of the various bus transactions:

•

A command with no response. 8 clocks after the host command End bit.

A command with response. 8 clocks after the card command End bit.

A read data transaction. 8 clocks after the End bit of the last data block.

A write data transaction. 8 clocks after the CRC status token.

The host is allowed to shut down the clock of a “busy” card. The card will complete

the programming operation regardless of the host clock. However, the host must

provide a clock edge for the card to turn off its busy signal. Without a clock edge the

card (unless previously disconnected by a deselect command-CMD7) will force the

MDAT line down, forever.

17.9 Description

The MMC controller interfaces to the C51 core through the following eight special func-

tion registers:

MMCON0, MMCON1, MMCON2, the three MMC control registers (see Table 16 to

Table 24); MMSTA, the MMC status register (see Table 19); MMINT, the MMC interrupt

register (see Table 20); MMMSK, the MMC interrupt mask register (see Table 21);

MMCMD, the MMC command register (see Table 22); MMDAT, the MMC data register

(see Table 23); and MMCLK, the MMC clock register (see Table 24).

As shown in Figure 81, the MMC controller is divided in four blocks: the clock generator

that handles the MCLK (formally the MMC CLK) output to the card, the command line

controller that handles the MCMD (formally the MMC CMD) line traffic to or from the

card, the data line controller that handles the MDAT (formally the MMC DAT) line traffic

to or from the card, and the interrupt controller that handles the MMC controller interrupt

sources. These blocks are detailed in the following sections.

Figure 81. MMC Controller Block Diagram

MCLK

OSC

CLOCK

Clock

Generator

Command Line

Controller

MCMD

MMC

Interrupt

Request

Interrupt

Controller

Data Line

Controller

MDAT

Internal

8

Bus

17.10 Clock Generator

The MMC clock is generated by division of the oscillator clock (F_OSC) issued from the

Clock Controller block as detailed in Section "Oscillator", page 12. The division factor is

given by MMCD7:0 bits in MMCLK register, a value of 0x00 stops the MMC clock.

Figure 82 shows the MMC clock generator and its output clock calculation formula.

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Figure 82. MMC Clock Generator and Symbol

OSCclk

MMCD + 1

OSC

CLOCK

MMCclk = -----------------------------

Controller Clock

MMC Clock

MMCLK

MMC

CLOCK

MMCEN

MMCON2.7

MMCD7:0

MMC Clock Symbol

As soon as MMCEN bit in MMCON2 is set, the MMC controller receives its system

clock. The MMC command and data clock is generated on MCLK output and sent to the

command line and data line controllers. Figure 83 shows the MMC controller configura-

tion flow.

As exposed in Section “Clock Control”, page 115, MMCD7:0 bits can be used to dynam-

ically increase or reduce the MMC clock.

Figure 83. Configuration Flow

MMC Controller

Configuration

Configure MMC Clock

MMCLK = XXh

MMCEN = 1

FLOWC = 0

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17.11 Command Line

Controller

As shown in Figure 84, the command line controller is divided in 2 channels: the com-

mand transmitter channel that handles the command transmission to the card through

the MCMD line and the command receiver channel that handles the response reception

from the card through the MCMD line. These channels are detailed in the following

sections.

Figure 84. Command Line Controller Block Diagram

Data Converter

// -> Serial

CRC7

Generator

TX Pointer

5-Byte FIFO

MMCMD

Write

CTPTR

MMCON0.4

TX COMMAND Line

Finished State Machine

MMINT.5

EOCI

CFLCK

MMSTA.0

CMDEN

MMCON1.0

MCMD

Command Transmitter

MMSTA.2

MMSTA.1

CRC7S RESPFS

Data Converter

Serial -> //

CRC7 and Format

Checker

RX Pointer

17 - Byte FIFO

MMCMD

Read

CRPTR

MMCON0.5

RX COMMAND Line

Finished State Machine

MMINT.6

EORI

RESPEN RFMT CRCDIS

MMCON1.1 MMCON0.1 MMCON0.0

Command Receiver

17.11.1 Command Transmitter For sending a command to the card, user must load the command index (1 Byte) and

argument (4 Bytes) in the command transmit FIFO using the MMCMD register. Before

starting transmission by setting and clearing the CMDEN bit in MMCON1 register, user

must first configure:

•

RESPEN bit in MMCON1 register to indicate whether a response is expected or not.

RFMT bit in MMCON0 register to indicate the response size expected.

CRCDIS bit in MMCON0 register to indicate whether the CRC7 included in the

response will be computed or not. In order to avoid CRC error, CRCDIS may be set

for response that do not include CRC7.

Figure 85 summarizes the command transmission flow.

As soon as command transmission is enabled, the CFLCK flag in MMSTA is set indicat-

ing that write to the FIFO is locked. This mechanism is implemented to avoid command

overrun.

The end of the command transmission is signalled to you by the EOCI flag in MMINT

register becoming set. This flag may generate an MMC interrupt request as detailed in

Section "Interrupt", page 126. The end of the command transmission also resets the

CFLCK flag.

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User may abort command loading by setting and clearing the CTPTR bit in MMCON0

register which resets the write pointer to the transmit FIFO.

Figure 85. Command Transmission Flow

Command

Transmission

Load Command in

Buffer

MMCMD = index

MMCMD = argument

Configure Response

RESPEN = X

RFMT = X

CRCDIS = X

Transmit Command

CMDEN = 1

CMDEN = 0

17.11.2 Command Receiver

The end of the response reception is signalled to you by the EORI flag in MMINT regis-

ter. This flag may generate an MMC interrupt request as detailed in Section "Interrupt",

page 126. When this flag is set, 2 other flags in MMSTA register: RESPFS and CRC7S

give a status on the response received. RESPFS indicates if the response format is cor-

rect or not: the size is the one expected (48 bits or 136 bits) and a valid End bit has been

received, and CRC7S indicates if the CRC7 computation is correct or not. These Flags

are cleared when a command is sent to the card and updated when the response has

been received.

User may abort response reading by setting and clearing the CRPTR bit in MMCON0

register which resets the read pointer to the receive FIFO.

According to the MMC specification delay between a command and a response (for-

mally N_CRparameter) can not exceed 64 MMC clock periods. To avoid any locking of

the MMC controller when card does not send its response (e.g. physically removed from

the bus), user must launch a time-out period to exit from such situation. In case of time-

out user may reset the command controller and its internal state machine by setting and

clearing the CCR bit in MMCON2 register.

This time-out may be disarmed when receiving the response.

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17.12 Data Line

Controller

The data line controller is based on a 16-Byte FIFO used both by the data transmitter

channel and by the data receiver channel.

Figure 86. Data Line Controller Block Diagram

MMINT.0

MMINT.2

MMSTA.3

MMSTA.4

F1EI

F1FI

DATFS CRC16S

CRC16 and Format

Checker

Data Converter

Serial -> //

8-Byte

TX Pointer

FIFO 1

MCBI

MMINT.1

CBUSY

MMSTA.5

MDAT

DTPTR

MMCON0.6

16-Byte FIFO

MMDAT

Data Converter

// -> Serial

CRC16

Generator

RX Pointer

DRPTR

MMCON0.7

8-Byte

FIFO 2

MMINT.4

DATA Line

Finished State Machine

EOFI

DFMT

MBLOCK DATEN DATDIR BLEN3:0

MMCON0.2 MMCON0.3 MMCON1.2 MMCON1.3 MMCON1.7:4

F2EI

MMINT.1

F2FI

MMINT.3

17.12.1 FIFO Implementation

The 16-Byte FIFO is based on a dual 8-Byte FIFOs managed using 2 pointers and four

flags indicating the status full and empty of each FIFO.

Pointers are not accessible to user but can be reset at any time by setting and clearing

DRPTR and DTPTR bits in MMCON0 register. Resetting the pointers is equivalent to

abort the writing or reading of data.

F1EI and F2EI flags in MMINT register signal when set that respectively FIFO1 and

FIFO2 are empty. F1FI and F2FI flags in MMINT register signal when set that respec-

tively FIFO1 and FIFO2 are full. These flags may generate an MMC interrupt request as

detailed in Section “Interrupt”.

17.12.2 Data Configuration

Before sending or receiving any data, the data line controller must be configured accord-

ing to the type of the data transfer considered. This is achieved using the Data Format

bit: DFMT in MMCON0 register. Clearing DFMT bit enables the data stream format

while setting DFMT bit enables the data block format. In data block format, user must

also configure the single or multi-block mode by clearing or setting the MBLOCK bit in

MMCON0 register and the block length using BLEN3:0 bits in MMCON1 according to

Table 13. Figure 87 summarizes the data modes configuration flows.

Table 13. Block Length Programming

BLEN3:0

BLEN = 0000 to 1011

> 1011

Block Length (Byte)

Length = 2^BLEN: 1 to 2048

Reserved: do not program BLEN3:0 > 1011

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Figure 87. Data Controller Configuration Flows

Data Stream

Configuration

Data Single Block

Configuration

Data Multi-Block

Configuration

Configure Format

DFMT = 1

Configure Format

DFMT = 1

DFMT = 0

MBLOCK = 0

MBLOCK = 1

BLEN3:0 = XXXXb

17.13.1 Data Transmitter

Configuration

For transmitting data to the card user must first configure the data controller in transmis-

sion mode by setting the DATDIR bit in MMCON1 register.

Figure 88 summarizes the data stream transmission flows in both polling and interrupt

modes while Figure 89 summarizes the data block transmission flows in both polling

and interrupt modes, these flows assume that block length is greater than 16 data.

Data Loading

Data is loaded in the FIFO by writing to MMDAT register. Number of data loaded may

vary from 1 to 16 Bytes. Then if necessary (more than 16 Bytes to send) user must wait

that one FIFO becomes empty (F1EI or F2EI set) before loading 8 new data.

Data Transmission

Transmission is enabled by setting and clearing DATEN bit in MMCON1 register.

Data is transmitted immediately if the response has already been received, or is delayed

after the response reception if its status is correct. In both cases transmission is delayed

if a card sends a busy state on the data line until the end of this busy condition.

According to the MMC specification, the data transfer from the host to the card may not

start sooner than 2 MMC clock periods after the card response was received (formally

N_WRparameter). To address all card types, this delay can be programmed using

DATD1:0 bits in MMCON2 register from 3 MMC clock periods when DATD1:0 bits are

cleared to 9 MMC clock periods when DATD1:0 bits are set, by step of 2 MMC clock

periods.

End of Transmission

The end of a data frame (block or stream) transmission is signalled to you by the EOFI

flag in MMINT register. This flag may generate an MMC interrupt request as detailed in

Section "Interrupt", page 126.

In data stream mode, EOFI flag is set, after reception of the End bit. This assumes user

has previously sent the STOP command to the card, which is the only way to stop

stream transfer.

In data block mode, EOFI flag is set, after reception of the CRC status token (see

Figure 79). 2 other flags in MMSTA register: DATFS and CRC16S report a status on the

frame sent. DATFS indicates if the CRC status token format is correct or not, and

CRC16S indicates if the card has found the CRC16 of the block correct or not.

Busy Status

As shown in Figure 79 the card uses a busy token during a block write operation. This

busy status is reported to you by the CBUSY flag in MMSTA register and by the MCBI

flag in MMINT which is set every time CBUSY toggles, i.e. when the card enters and

exits its busy state. This flag may generate an MMC interrupt request as detailed in Sec-

tion "Interrupt", page 126.

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Figure 88. Data Stream Transmission Flows

Data Stream

Transmission

Data Stream

Initialization

Data Stream

Transmission ISR

FIFOs Filling

write 16 data to MMDAT

FIFOs Filling

write 16 data to MMDAT

FIFO Empty?

F1EI or F2EI = 1?

Start Transmission

DATEN = 1

Unmask FIFOs Empty

F1EM = 0

DATEN = 0

F2EM = 0

FIFO Filling

write 8 data to MMDAT

Start Transmission

DATEN = 1

FIFO Empty?

F1EI or F2EI = 1?

No More Data

To Send?

DATEN = 0

FIFO Filling

write 8 data to MMDAT

Mask FIFOs Empty

F1EM = 1

F2EM = 1

No More Data

To Send?

Send

STOP Command

Send

STOP Command

b. Interrupt mode

a. Polling mode

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Figure 89. Data Block Transmission Flows

Data Block

Transmission

Initialization

Transmission ISR

FIFOs Filling

write 16 data to MMDAT

FIFOs Filling

write 16 data to MMDAT

FIFO Empty?

F1EI or F2EI = 1?

Start Transmission

DATEN = 1

Unmask FIFOs Empty

F1EM = 0

DATEN = 0

F2EM = 0

FIFO Filling

write 8 data to MMDAT

Start Transmission

DATEN = 1

FIFO Empty?

F1EI or F2EI = 1?

No More Data

To Send?

DATEN = 0

FIFO Filling

write 8 data to MMDAT

Mask FIFOs Empty

F1EM = 1

F2EM = 1

No More Data

To Send?

b. Interrupt mode

a. Polling mode

17.13.2 Data Receiver

Configuration

To receive data from the card you must first configure the data controller in reception

mode by clearing the DATDIR bit in MMCON1 register.

Figure 90 summarizes the data stream reception flows in both polling and interrupt

modes while Figure 91 summarizes the data block reception flows in both polling and

interrupt modes, these flows assume that block length is greater than 16 Bytes.

Data Reception

The end of a data frame (block or stream) reception is signalled to you by the EOFI flag

in MMINT register. This flag may generate an MMC interrupt request as detailed in Sec-

tion "Interrupt", page 126. When this flag is set, 2 other flags in MMSTA register: DATFS

and CRC16S give a status on the frame received. DATFS indicates if the frame format

is correct or not: a valid End bit has been received, and CRC16S indicates if the CRC16

computation is correct or not. In case of data stream CRC16S has no meaning and

stays cleared.

According to the MMC specification data transmission from the card starts after the

access time delay (formally N_ACparameter) beginning from the End bit of the read com-

mand. To avoid any locking of the MMC controller when card does not send its data

(e.g. physically removed from the bus), you must launch a time-out period to exit from

such situation. In case of time-out you may reset the data controller and its internal state

machine by setting and clearing the DCR bit in MMCON2 register.

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This time-out may be disarmed after receiving 8 data (F1FI flag set) or after receiving

end of frame (EOFI flag set) in case of block length less than 8 data (1, 2 or 4).

Data Reading

Data is read from the FIFO by reading to MMDAT register. Each time one FIFO

becomes full (F1FI or F2FI set), user is requested to flush this FIFO by reading 8 data.

Figure 90. Data Stream Reception Flows

Data Stream

Reception

Data Stream

Initialization

Data Stream

Reception ISR

Unmask FIFOs Full

F1FM = 0

FIFO Full?

F1FI or F2FI = 1?

FIFO Full?

F1FI or F2FI = 1?

F2FM = 0

FIFO Reading

read 8 data from MMDAT

FIFO Reading

read 8 data from MMDAT

No More Data

To Receive?

No More Data

To Receive?

Mask FIFOs Full

F1FM = 1

Send

STOP Command

F2FM = 1

Send

a. Polling mode

STOP Command

b. Interrupt mode

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Figure 91. Data Block Reception Flows

Data Block

Reception

Data Block

Initialization

Data Block

Reception ISR

Start Transmission

DATEN = 1

Unmask FIFOs Full

F1FM = 0

FIFO Full?

F1EI or F2EI = 1?

DATEN = 0

F2FM = 0

Start Transmission

DATEN = 1

FIFO Reading

read 8 data from MMDAT

FIFO Full?

F1EI or F2EI = 1?

DATEN = 0

No More Data

To Receive?

FIFO Reading

read 8 data from MMDAT

Mask FIFOs Full

F1FM = 1

No More Data

To Receive?

F2FM = 1

a. Polling mode

b. Interrupt mode

17.13.3 Flow Control

To allow transfer at high speed without taking care of CPU oscillator frequency, the

FLOWC bit in MMCON2 allows control of the data flow in both transmission and

reception.

During transmission, setting the FLOWC bit has the following effects:

•

MMCLK is stopped when both FIFOs become empty: F1EI and F2EI set.

MMCLK is restarted when one of the FIFOs becomes full: F1EI or F2EI cleared.

During reception, setting the FLOWC bit has the following effects:

•

MMCLK is stopped when both FIFOs become full: F1FI and F2FI set.

MMCLK is restarted when one of the FIFOs becomes empty: F1FI or F2FI cleared.

As soon as the clock is stopped, the MMC bus is frozen and remains in its state until the

clock is restored by writing or reading data in MMDAT.

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17.14 Interrupt

17.14.1 Description

As shown in Figure 92, the MMC controller implements eight interrupt sources reported

in MCBI, EORI, EOCI, EOFI, F2FI, F1FI, and F2EI flags in MMCINT register. These

flags are detailed in the previous sections.

All these sources are maskable separately using MCBM, EORM, EOCM, EOFM, F2FM,

F1FM, and F2EM mask bits respectively in MMMSK register.

The interrupt request is generated each time an unmasked flag is set, and the global

MMC controller interrupt enable bit is set (EMMC in IEN1 register).

Reading the MMINT register automatically clears the interrupt flags (acknowledgment).

This implies that register content must be saved and tested interrupt flag by interrupt

flag to be sure not to forget any interrupts.

Figure 92. MMC Controller Interrupt System

MCBI

MMINT.7

MCBM

MMMSK.7

EORI

MMINT.6

EORM

MMMSK.6

EOCI

MMINT.5

EOCM

MMMSK.5

EOFI

MMINT.4

MMC Interface

Interrupt Request

EOFM

MMMSK.4

F2FI

MMINT.3

EMMC

IEN1.0

F2FM

MMMSK.3

F1FI

MMINT.2

F1FM

MMMSK.2

F2EI

MMINT.1

F2EM

MMMSK.1

F1EI

MMINT.0

F1EM

MMMSK.0

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17.15 Registers

Table 16. MMCON0 Register

MMCON0 (S:E4h) – MMC Control Register 0

7

6

5

4

3

2

1

0

DRPTR

DTPTR

CRPTR

CTPTR

MBLOCK

DFMT

RFMT

CRCDIS

Bit

Number

Mnemonic Description

Data Receive Pointer Reset Bit

7

6

5

4

3

2

1

0

DRPTR

DTPTR

CRPTR

CTPTR

Set to reset the read pointer of the data FIFO.

Clear to release the read pointer of the data FIFO.

Data Transmit Pointer Reset Bit

Set to reset the write pointer of the data FIFO.

Clear to release the write pointer of the data FIFO.

Command Receive Pointer Reset Bit

Set to reset the read pointer of the receive command FIFO.

Clear to release the read pointer of the receive command FIFO.

Command Transmit Pointer Reset Bit

Set to reset the write pointer of the transmit command FIFO.

Clear to release the read pointer of the transmit command FIFO.

Multi-block Enable Bit

MBLOCK Set to select multi-block data format.

Clear to select single block data format.

Data Format Bit

Set to select the block-oriented data format.

Clear to select the stream data format.

DFMT

RFMT

Response Format Bit

Set to select the 48-bit response format.

Clear to select the 136-bit response format.

CRC7 Disable Bit

CRCDIS Set to disable the CRC7 computation when receiving a response.

Clear to enable the CRC7 computation when receiving a response.

Reset Value = 0000 0000b

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Table 17. MMCON1 Register

MMCON1 (S:E5h) – MMC Control Register 1

7

6

5

4

3

2

1

0

BLEN3

BLEN2

BLEN1

BLEN0

DATDIR

DATEN

RESPEN

CMDEN

Bit

Number

Mnemonic Description

Block Length Bits

Refer to Table 13 for bits description. Do not program value > 1011b

7 - 4

3

BLEN3:0

Data Direction Bit

DATDIR Set to select data transfer from host to card (write mode).

Clear to select data transfer from card to host (read mode).

Data Transmission Enable Bit

2

DATEN

Set and clear to enable data transmission immediately or after response has

been received.

Response Enable Bit

1

0

RESPEN Set and clear to enable the reception of a response following a command

transmission.

Command Transmission Enable Bit

CMDEN

Set and clear to enable transmission of the command FIFO to the card.

Reset Value = 0000 0000b

Table 18. MMCON2 Register

MMCON2 (S:E6h) – MMC Control Register 2

7

6

5

4

-

3

-

2

1

0

MMCEN

DCR

CCR

DATD1

DATD0

FLOWC

Bit

Number

Mnemonic Description

MMC Clock Enable Bit

7

MMCEN Set to enable the MCLK clocks and activate the MMC controller.

Clear to disable the MMC clocks and freeze the MMC controller.

Data Controller Reset Bit

Set and clear to reset the data line controller in case of transfer abort.

6

5

DCR

Command Controller Reset Bit

Set and clear to reset the command line controller in case of transfer abort.

CCR

Reserved

4-3

-

The value read from these bits is always 0. Do not set these bits.

Data Transmission Delay Bits

Used to delay the data transmission after a response from 3 MMC clock periods

(all bits cleared) to 9 MMC clock periods (all bits set) by step of 2 MMC clock

periods.

2-1

0

DATD1:0

MMC Flow Control Bit

FLOWC Set to enable the flow control during data transfers.

Clear to disable the flow control during data transfers.

Reset Value = 0000 0000b

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Table 19. MMSTA Register

MMSTA (S:DEh Read Only) – MMC Control and Status Register

7

-

6

-

5

4

3

2

1

0

CBUSY

CRC16S

DATFS

CRC7S

RESPFS

CFLCK

Bit

Number

Mnemonic Description

Reserved

7 - 6

5

-

The value read from these bits is always 0. Do not set these bits.

Card Busy Flag

CBUSY

Set by hardware when the card sends a busy state on the data line.

Cleared by hardware when the card no more sends a busy state on the data line.

CRC16 Status Bit

Transmission mode

Set by hardware when the token response reports a good CRC.

4

3

CRC16S Cleared by hardware when the token response reports a bad CRC.

Reception mode

Set by hardware when the CRC16 received in the data block is correct.

Cleared by hardware when the CRC16 received in the data block is not correct.

Data Format Status Bit

Transmission mode

Set by hardware when the format of the token response is correct.

DATFS

CRC7S

Cleared by hardware when the format of the token response is not correct.

Reception mode

Set by hardware when the format of the frame is correct.

Cleared by hardware when the format of the frame is not correct.

CRC7 Status Bit

Set by hardware when the CRC7 computed in the response is correct.

Cleared by hardware when the CRC7 computed in the response is not correct.

2

1

This bit is not relevant when CRCDIS is set.

Response Format Status Bit

RESPFS Set by hardware when the format of a response is correct.

Cleared by hardware when the format of a response is not correct.

Command FIFO Lock Bit

Set by hardware to signal user not to write in the transmit command FIFO: busy

0

CFLCK

state.

Cleared by hardware to signal user the transmit command FIFO is available: idle

state.

Reset Value = 0000 0000b

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Table 20. MMINT Register

MMINT (S:E7h Read Only) – MMC Interrupt Register

7

6

5

4

3

2

1

0

MCBI

EORI

EOCI

EOFI

F2FI

F1FI

F2EI

F1EI

Bit

Number

Mnemonic Description

MMC Card Busy Interrupt Flag

Set by hardware when the card enters or exits its busy state (when the busy

signal is asserted or deasserted on the data line).

Cleared when reading MMINT.

7

MCBI

End of Response Interrupt Flag

6

5

4

3

2

1

0

EORI

EOCI

EOFI

F2FI

F1FI

F2EI

F1EI

Set by hardware at the end of response reception.

Cleared when reading MMINT.

End of Command Interrupt Flag

Set by hardware at the end of command transmission.

Clear when reading MMINT.

End of Frame Interrupt Flag

Set by hardware at the end of frame (stream or block) transfer.

Clear when reading MMINT.

FIFO 2 Full Interrupt Flag

Set by hardware when second FIFO becomes full.

Cleared by hardware when second FIFO becomes empty.

FIFO 1 Full Interrupt Flag

Set by hardware when first FIFO becomes full.

Cleared by hardware when first FIFO becomes empty.

FIFO 2 Empty Interrupt Flag

Set by hardware when second FIFO becomes empty.

Cleared by hardware when second FIFO becomes full.

FIFO 1 Empty Interrupt Flag

Set by hardware when first FIFO becomes empty.

Cleared by hardware when first FIFO becomes full.

Reset Value = 0000 0011b

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Table 21. MMMSK Register

MMMSK (S:DFh) – MMC Interrupt Mask Register

7

6

5

4

3

2

1

0

MCBM

EORM

EOCM

EOFM

F2FM

F1FM

F2EM

F1EM

Bit

Number

Mnemonic Description

MMC Card Busy Interrupt Mask Bit

7

6

5

4

3

2

1

0

MCBM

EORM

EOCM

EOFM

F2FM

F1FM

F2EM

F1EM

Set to prevent MCBI flag from generating an MMC interrupt.

Clear to allow MCBI flag to generate an MMC interrupt.

End Of Response Interrupt Mask Bit

Set to prevent EORI flag from generating an MMC interrupt.

Clear to allow EORI flag to generate an MMC interrupt.

End Of Command Interrupt Mask Bit

Set to prevent EOCI flag from generating an MMC interrupt.

Clear to allow EOCI flag to generate an MMC interrupt.

End Of Frame Interrupt Mask Bit

Set to prevent EOFI flag from generating an MMC interrupt.

Clear to allow EOFI flag to generate an MMC interrupt.

FIFO 2 Full Interrupt Mask Bit

Set to prevent F2FI flag from generating an MMC interrupt.

Clear to allow F2FI flag to generate an MMC interrupt.

FIFO 1 Full Interrupt Mask Bit

Set to prevent F1FI flag from generating an MMC interrupt.

Clear to allow F1FI flag to generate an MMC interrupt.

FIFO 2 Empty Interrupt Mask Bit

Set to prevent F2EI flag from generating an MMC interrupt.

Clear to allow F2EI flag to generate an MMC interrupt.

FIFO 1 Empty Interrupt Mask Bit

Set to prevent F1EI flag from generating an MMC interrupt.

Clear to allow F1EI flag to generate an MMC interrupt.

Reset Value = 1111 1111b

Table 22. MMCMD Register

MMCMD (S:DDh) – MMC Command Register

7

6

5

4

3

2

1

0

MC7

MC6

MC5

MC4

MC3

MC2

MC1

MC0

Bit

Number

Mnemonic Description

MMC Command Receive Byte

Output (read) register of the response FIFO.

7 - 0

MC7:0

MMC Command Transmit Byte

Input (write) register of the command FIFO.

Reset Value = 1111 1111b

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Table 23. MMDAT Register

MMDAT (S:DCh) – MMC Data Register

7

6

5

4

3

2

1

0

MD7

MD6

MD5

MD4

MD3

MD2

MD1

MD0

Bit

Number

Mnemonic Description

MMC Data Byte

Input (write) or output (read) register of the data FIFO.

7 - 0

MD7:0

Reset Value = 1111 1111b

Table 24. MMCLK Register

MMCLK (S:EDh) – MMC Clock Divider Register

7

6

5

4

3

2

1

0

MMCD7

MMCD6

MMCD5

MMCD4

MMCD3

MMCD2

MMCD1

MMCD0

Bit

Number

Mnemonic Description

MMC Clock Divider

8-bit divider for MMC clock generation.

7 - 0

MMCD7:0

Reset Value = 0000 0000b

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18. IDE/ATAPI

Interface

The AT8xC51SND1C provides an IDE/ATAPI interface allowing connection of devices

such as CD-ROM reader, CompactFlash cards, Hard Disk Drive, etc. It consists of a 16-

bit data transfer (read or write) between the AT8xC51SND1C and the IDE device.

18.1 Description

The IDE interface mode is enabled by setting the EXT16 bit in AUXR (see Figure 9,

page 31). As soon as this bit is set, all MOVX instructions read or write are done in a 16-

bit mode compare to the standard 8-bit mode. P0 carries the low order multiplexed

address and data bus (A7:0, D7:0) while P2 carries the high order multiplexed address

and data bus (A15:8, D15:8). When writing data in IDE mode, the ACC contains D7:0

data (as in 8-bit mode) while DAT16H register (see Table 4) contains D15:8 data. When

reading data in IDE mode, D7:0 data is returned in ACC while D15:8 data is returned in

DAT16H.

Figure 93 shows the IDE read bus cycle while Figure 94 shows the IDE write bus cycle.

For simplicity, these figures depict the bus cycle waveforms in idealized form and do not

provide precise timing information. For IDE bus cycle timing parameters refer to the

Section “AC Characteristics”.

IDE cycle takes 6 CPU clock periods which is equivalent to 12 oscillator clock periods in

standard mode or 6 oscillator clock periods in X2 mode. For further information on X2

mode, refer to the Section “X2 Feature”, page 12.

Slow IDE devices can be accessed by stretching the read and write cycles. This is done

using the M0 bit in AUXR. Setting this bit changes the width of the RD and WR signals

from 3 to 15 CPU clock periods.

Figure 93. IDE Read Waveforms

CPU Clock

ALE

RD⁽¹⁾

DPL or Ri

D7:0

P0

P2

DPH or P2^(2),(3)

D15:8

P2

Notes: 1. RD signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instruction, P2 outputs SFR content.

3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),

P2 outputs SFR content instead of DPH.

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Figure 94. IDE Write Waveforms

CPU Clock

ALE

WR⁽¹⁾

DPL or Ri

D7:0

P0

P2

DPH or P2^(2),(3)

D15:8

P2

Notes: 1. WR signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instruction, P2 outputs SFR content.

3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),

P2 outputs SFR content instead of DPH.

18.1.1 IDE Device Connection Figure 95 and Figure 96 show 2 examples on how to interface up to 2 IDE devices to the

AT8xC51SND1C. In both examples P0 carries IDE low order data bits D7:0, P2 carries

IDE high order data bits D15:8, while RD and WR signals are respectively connected to

the IDE nIOR and nIOW signals. Other IDE control signals are generated by the exter-

nal address latch outputs in the first example while they are generated by some port

I/Os in the second one. Using an external latch will achieve higher transfer rate.

Figure 95. IDE Device Connection Example 1

AT8xC51SND1C

P2

IDE Device 0

IDE Device 1

D15-8

D7:0

A2:0

D15-8

D7:0

A2:0

P0

Latch

nCS1:0

ALE

Px.y

nRESET

RD

nIOR

nIOW

nIOR

nIOW

WR

Figure 96. IDE Device Connection Example 2

AT8xC51SND1C

IDE Device 0

IDE Device 1

P2/A15:8

P0/AD7:0

D15-8

D7:0

D15-8

D7:0

P4.2:0

P4.4:3

P4.5

RD

A2:0

nCS1:0

nRESET

nIOR

nCS1:0

nRESET

nIOR

WR

nIOW

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Table 2. External Data Memory Interface Signals

Signal

Name

Alternate

Function

Type Description

Address Lines

A15:8

I/O Upper address lines for the external bus.

P2.7:0

Multiplexed higher address and data lines for the IDE interface.

Address/Data Lines

Multiplexed lower address and data lines for the IDE interface.

AD7:0

ALE

I/O

O

P0.7:0

-

Address Latch Enable

ALE signals indicates that valid address information is available on lines

AD7:0.

Read

RD

O

P3.7

P3.6

Read signal output to external data memory.

Write

WR

Write signal output to external memory.

18.3 Registers

Table 4. DAT16H Register

DAT16H (S:F9h) – Data 16 High Order Byte

7

6

5

4

3

2

1

0

D15

D14

D13

D12

D11

D10

D9

D8

Bit

Number

Mnemonic Description

Data 16 High Order Byte

When EXT16 bit is set, DAT16H is set by software with the high order data Byte

prior any MOVX write instruction.

7 - 0

D15:8

When EXT16 bit is set, DAT16H contains the high order data Byte after any

MOVX read instruction.

Reset Value =XXXX XXXXb

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19. Serial I/O Port

The serial I/O port in the AT8xC51SND1C provides both synchronous and asynchro-

nous communication modes. It operates as a Synchronous Receiver and Transmitter in

one single mode (Mode 0) and operates as an Universal Asynchronous Receiver and

Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous

modes support framing error detection and multiprocessor communication with auto-

matic address recognition.

19.1 Mode Selection

SM0 and SM1 bits in SCON register (see Figure 11) are used to select a mode among

the single synchronous and the three asynchronous modes according to Table 2.

Table 2. Serial I/O Port Mode Selection

SM0

SM1

Mode

Description

Baud Rate

Fixed/Variable

Variable

0

1

0

1

0

1

0

1

2

3

Synchronous Shift Register

8-bit UART

9-bit UART

Fixed

9-bit UART

Variable

19.3 Baud Rate

Generator

Depending on the mode and the source selection, the baud rate can be generated from

either the Timer 1 or the Internal Baud Rate Generator. The Timer 1 can be used in

Modes 1 and 3 while the Internal Baud Rate Generator can be used in Modes 0, 1

and 3.

The addition of the Internal Baud Rate Generator allows freeing of the Timer 1 for other

purposes in the application. It is highly recommended to use the Internal Baud Rate

Generator as it allows higher and more accurate baud rates than Timer 1.

Baud rate formulas depend on the modes selected and are given in the following mode

sections.

19.3.1 Timer 1

When using Timer 1, the Baud Rate is derived from the overflow of the timer. As shown

in Figure 97 Timer 1 is used in its 8-bit auto-reload mode (detailed in Section "Mode 2

(8-bit Timer with Auto-Reload)", page 55). SMOD1 bit in PCON register allows doubling

of the generated baud rate.

Figure 97. Timer 1 Baud Rate Generator Block Diagram

PER

CLOCK

÷ 6

0

1

Overflow

TL1

(8 bits)

÷ 2

0

1

To serial

Port

T1

C/T1#

TMOD.6

SMOD1

PCON.7

INT1

TH1

(8 bits)

GATE1

TMOD.7

T1

CLOCK

TR1

TCON.6

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19.3.2 Internal Baud Rate

Generator

When using the Internal Baud Rate Generator, the Baud Rate is derived from the over-

flow of the timer. As shown in Figure 98 the Internal Baud Rate Generator is an 8-bit

auto-reload timer fed by the peripheral clock or by the peripheral clock divided by 6

depending on the SPD bit in BDRCON register (see Table 15). The Internal Baud Rate

Generator is enabled by setting BBR bit in BDRCON register. SMOD1 bit in PCON reg-

ister allows doubling of the generated baud rate.

Figure 98. Internal Baud Rate Generator Block Diagram

PER

CLOCK

÷ 6

0

1

Overflow

BRG

(8 bits)

÷ 2

0

1

To serial

Port

SPD

BDRCON.1

BRR

BDRCON.4

SMOD1

PCON.7

BRL

(8 bits)

IBRG

CLOCK

19.4 Synchronous Mode Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/0

capabilities of a device with shift registers. The transmit data (TXD) pin outputs a set of

(Mode 0)

eight clock pulses while the receive data (RXD) pin transmits or receives a Byte of data.

The 8-bit data are transmitted and received least-significant bit (LSB) first. Shifts occur

at a fixed Baud Rate (see Section "Baud Rate Selection (Mode 0)", page 138).

Figure 99 shows the serial port block diagram in Mode 0.

Figure 99. Serial I/O Port Block Diagram (Mode 0)

SCON.6

SCON.7

SM1

SM0

SBUF Tx SR

SBUF Rx SR

RXD

Mode Decoder

M3 M2 M1 M0

Mode

Controller

PER

CLOCK

Baud Rate

Controller

TI

SCON.1

RI

SCON.0

TXD

BRG

CLOCK

19.4.1 Transmission (Mode 0) To start a transmission mode 0, write to SCON register clearing bits SM0, SM1.

As shown in Figure 100, writing the Byte to transmit to SBUF register starts the trans-

mission. Hardware shifts the LSB (D0) onto the RXD pin during the first clock cycle

composed of a high level then low level signal on TXD. During the eighth clock cycle the

MSB (D7) is on the RXD pin. Then, hardware drives the RXD pin high and asserts TI to

indicate the end of the transmission.

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Figure 100. Transmission Waveforms (Mode 0)

TXD

Write to SBUF

RXD

TI

D0

D1

D2

D3

D4

D5

D6

D7

19.4.2 Reception (Mode 0)

To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bits

and setting the REN bit.

As shown in Figure 101, Clock is pulsed and the LSB (D0) is sampled on the RXD pin.

The D0 bit is then shifted into the shift register. After eight samplings, the MSB (D7) is

shifted into the shift register, and hardware asserts RI bit to indicate a completed recep-

tion. Software can then read the received Byte from SBUF register.

Figure 101. Reception Waveforms (Mode 0)

TXD

Set REN, Clear RI

Write to SCON

RXD

RI

D0

D1

D2

D3

D4

D5

D6

D7

19.4.3 Baud Rate Selection

(Mode 0)

In mode 0, the baud rate can be either, fixed or variable.

As shown in Figure 102, the selection is done using M0SRC bit in BDRCON register.

Figure 103 gives the baud rate calculation formulas for each baud rate source.

Figure 102. Baud Rate Source Selection (mode 0)

PER

CLOCK

÷ 6

0

To Serial Port

1

IBRG

CLOCK

M0SRC

BDRCON.0

Figure 103. Baud Rate Formulas (Mode 0)

2^SMOD1⋅ F_PER

Baud_Rate=

6^(1-SPD)⋅ 32 ⋅ (256 -BRL)

F_PER

2^SMOD1⋅ F_PER

Baud_Rate=

6

BRL= 256 -

6^(1-SPD)⋅ 32 ⋅ Baud_Rate

a. Fixed Formula

b. Variable Formula

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19.5 Asynchronous

Modes (Modes 1, 2 and 3)

The Serial Port has one 8-bit and 2 9-bit asynchronous modes of operation. Figure 104

shows the Serial Port block diagram in such asynchronous modes.

Figure 104. Serial I/O Port Block Diagram (Modes 1, 2 and 3)

SCON.6

SCON.7

SCON.3

SM1

SM0

TB8

SBUF Tx SR

Rx SR

TXD

RXD

Mode Decoder

M3 M2 M1 M0

T1

CLOCK

IBRG

CLOCK

Mode & Clock

Controller

SBUF Rx

RB8

SCON.2

PER

CLOCK

SM2

SCON.4

TI

SCON.1

RI

SCON.0

Mode 1

Mode 1 is a full-duplex, asynchronous mode. The data frame (see Figure 105) consists

of 10 bits: one start, eight data bits and one stop bit. Serial data is transmitted on the

TXD pin and received on the RXD pin. When a data is received, the stop bit is read in

the RB8 bit in SCON register.

Figure 105. Data Frame Format (Mode 1)

Mode 1

D0

D1

D2

D3

D4

D5

D6

D7

Start bit

8-bit data

Stop bit

Modes 2 and 3

Modes 2 and 3 are full-duplex, asynchronous modes. The data frame (see Figure 106)

consists of 11 bits: one start bit, eight data bits (transmitted and received LSB first), one

programmable ninth data bit and one stop bit. Serial data is transmitted on the TXD pin

and received on the RXD pin. On receive, the ninth bit is read from RB8 bit in SCON

register. On transmit, the ninth data bit is written to TB8 bit in SCON register. Alterna-

tively, you can use the ninth bit can be used as a command/data flag.

Figure 106. Data Frame Format (Modes 2 and 3)

D0

D1

D2

D3

D4

D5

D6

D7

D8

Start bit

9-bit data

Stop bit

19.5.1 Transmission (Modes 1, To initiate a transmission, write to SCON register, set the SM0 and SM1 bits according

2

to Table 2, and set the ninth bit by writing to TB8 bit. Then, writing the Byte to be trans-

mitted to SBUF register starts the transmission.

and 3)

19.5.2 Reception (Modes 1, 2

and 3)

To prepare for reception, write to SCON register, set the SM0 and SM1 bits according to

Table 2, and set the REN bit. The actual reception is then initiated by a detected high-to-

low transition on the RXD pin.

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19.5.3 Framing Error

Detection (Modes 1, 2 and 3)

Framing error detection is provided for the three asynchronous modes. To enable the

framing bit error detection feature, set SMOD0 bit in PCON register as shown in

Figure 107.

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by 2 devices. If a valid stop bit is not found, the software sets FE bit in

SCON register.

Software may examine FE bit after each reception to check for data errors. Once set,

only software or a chip reset clear FE bit. Subsequently received frames with valid stop

bits cannot clear FE bit. When the framing error detection feature is enabled, RI rises on

stop bit instead of the last data bit as detailed in Figure 113.

Figure 107. Framing Error Block Diagram

Framing Error

Controller

FE

1

0

SM0/FE

SCON.7

SM0

SMOD0

PCON.6

19.5.4 Baud Rate Selection

(Modes 1 and 3)

In modes 1 and 3, the Baud Rate is derived either from the Timer 1 or the Internal Baud

Rate Generator and allows different baud rate in reception and transmission.

As shown in Figure 108 the selection is done using RBCK and TBCK bits in BDRCON

register.

Figure 109 gives the baud rate calculation formulas for each baud rate source while

Table 6 details Internal Baud Rate Generator configuration for different peripheral clock

frequencies and giving baud rates closer to the standard baud rates.

Figure 108. Baud Rate Source Selection (Modes 1 and 3)

T1

CLOCK

0

1

To Serial

Rx Port

To Serial

Tx Port

÷ 16

1

IBRG

CLOCK

IBRG

CLOCK

RBCK

BDRCON.2

TBCK

BDRCON.3

Figure 109. Baud Rate Formulas (Modes 1 and 3)

2^SMOD1⋅ F_PER

6 ⋅ 32 ⋅ (256 -TH1)

Baud_Rate=

TH1= 256 -

6^(1-SPD)⋅ 32 ⋅ (256 -BRL)

2^SMOD1⋅ F_PER

6^(1-SPD)⋅ 32 ⋅ Baud_Rate

2^SMOD1⋅ F_PER

192 ⋅ Baud_Rate

BRL= 256 -

a. IBRG Formula

b. T1 Formula

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Table 6. Internal Baud Rate Generator Value

F_PER= 6 MHz⁽¹⁾

F_PER= 8 MHz⁽¹⁾

F_PER= 10 MHz⁽¹⁾

Baud Rate

115200

57600

38400

19200

9600

SPD

SMOD1

BRL

-

Error %

-

SPD

SMOD1

BRL

-

Error %

-

SPD

SMOD1

BRL

-

Error %

-

1

247

243

230

204

152

3.55

0.16

1

245

240

223

191

126

1.36

1.73

1.36

0.16

1

246

236

217

178

2.34

0.16

4800

F

_PER= 12 MHz⁽²⁾

F_PER= 16 MHz⁽²⁾

F_PER= 20 MHz⁽²⁾

Baud Rate

115200

57600

38400

19200

9600

SPD

SMOD1

BRL

-

Error %

-

SPD

SMOD1

BRL

247

239

230

204

152

48

Error %

3.55

SPD

SMOD1

BRL

245

234

223

191

126

Error %

1.36

-

1

0

1

243

236

217

178

100

0.16

2.34

0.16

2.12

1.36

0.16

1.36

0.16

4800

0.16

Notes: 1. These frequencies are achieved in X1 mode, F_PER= F_OSC÷ 2.

2. These frequencies are achieved in X2 mode, F_PER= F_OSC

.

19.6.1 Baud Rate Selection

(Mode 2)

In mode 2, the baud rate can only be programmed to 2 fixed values: 1/16 or 1/32 of the

peripheral clock frequency.

As shown in Figure 110 the selection is done using SMOD1 bit in PCON register.

Figure 111 gives the baud rate calculation formula depending on the selection.

Figure 110. Baud Rate Generator Selection (Mode 2)

PER

CLOCK

÷ 2

0

1

÷ 16

To Serial Port

SMOD1

PCON.7

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Figure 111. Baud Rate Formula (Mode 2)

2^SMOD1⋅ F_PER

Baud_Rate=

32

19.7 Multiprocessor

Communication (Modes

2 and 3)

Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. To

enable this feature, set SM2 bit in SCON register. When the multiprocessor communica-

tion feature is enabled, the serial Port can differentiate between data frames (ninth bit

clear) and address frames (ninth bit set). This allows the AT8xC51SND1C to function as

a slave processor in an environment where multiple slave processors share a single

serial line.

When the multiprocessor communication feature is enabled, the receiver ignores frames

with the ninth bit clear. The receiver examines frames with the ninth bit set for an

address match. If the received address matches the slaves address, the receiver hard-

ware sets RB8 and RI bits in SCON register, generating an interrupt.

The addressed slave’s software then clears SM2 bit in SCON register and prepares to

receive the data Bytes. The other slaves are unaffected by these data Bytes because

they are waiting to respond to their own addresses.

19.8 Automatic Address

Recognition

The automatic address recognition feature is enabled when the multiprocessor commu-

nication feature is enabled (SM2 bit in SCON register is set).

Implemented in hardware, automatic address recognition enhances the multiprocessor

communication feature by allowing the Serial Port to examine the address of each

incoming command frame. Only when the Serial Port recognizes its own address, the

receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU

is not interrupted by command frames addressed to other devices.

If desired, the automatic address recognition feature in mode 1 may be enabled. In this

configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the

received command frame address matches the device’s address and is terminated by a

valid stop bit.

To support automatic address recognition, a device is identified by a given address and

a broadcast address.

Note:

The multiprocessor communication and automatic address recognition features cannot

be enabled in mode 0 (i.e, setting SM2 bit in SCON register in mode 0 has no effect).

19.8.1 Given Address

Each device has an individual address that is specified in SADDR register; the SADEN

register is a mask Byte that contains don’t care bits (defined by zeros) to form the

device’s given address. The don’t care bits provide the flexibility to address one or more

slaves at a time. The following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask Byte must be

1111 1111b.

For example:

SADDR = 0101 0110b

SADEN = 1111 1100b

Given = 0101 01XXb

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The following is an example of how to use given addresses to address different slaves:

Slave A:SADDR = 1111 0001b

SADEN = 1111 1010b

Given = 1111 0X0Xb

Slave B:SADDR = 1111 0011b

SADEN = 1111 1001b

Given = 1111 0XX1b

Slave C:SADDR = 1111 0011b

SADEN = 1111 1101b

Given = 1111 00X1b

The SADEN Byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com-

municate with slave A only, the master must send an address where bit 0 is clear (e.g.

1111 0000B).

For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with

slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both

set (e.g. 1111 0011B).

To communicate with slaves A, B and C, the master must send an address with bit 0 set,

bit 1 clear, and bit 2 clear (e.g. 1111 0001B).

19.8.2 Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers

with zeros defined as don’t-care bits, e.g.:

SADDR = 0101 0110b

SADEN = 1111 1100b

(SADDR | SADEN)=1111 111Xb

The use of don’t-care bits provides flexibility in defining the broadcast address, however

in most applications, a broadcast address is FFh.

The following is an example of using broadcast addresses:

Slave A:SADDR = 1111 0001b

SADEN = 1111 1010b

Given = 1111 1X11b,

Slave B:SADDR = 1111 0011b

SADEN = 1111 1001b

Given = 1111 1X11b,

Slave C:SADDR = 1111 0010b

SADEN = 1111 1101b

Given = 1111 1111b,

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with

all of the slaves, the master must send the address FFh.

To communicate with slaves A and B, but not slave C, the master must send the

address FBh.

19.8.3 Reset Address

On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and

broadcast addresses are XXXX XXXXb(all don’t care bits). This ensures that the Serial

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Port is backwards compatible with the 80C51 microcontrollers that do not support auto-

matic address recognition.

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19.9 Interrupt

The Serial I/O Port handles 2 interrupt sources that are the “end of reception” (RI in

SCON) and “end of transmission” (TI in SCON) flags. As shown in Figure 112 these

flags are combined together to appear as a single interrupt source for the C51 core.

Flags must be cleared by software when executing the serial interrupt service routine.

The serial interrupt is enabled by setting ES bit in IEN0 register. This assumes interrupts

are globally enabled by setting EA bit in IEN0 register.

Depending on the selected mode and weather the framing error detection is enabled or

disabled, RI flag is set during the stop bit or during the ninth bit as detailed in Figure 113.

Figure 112. Serial I/O Interrupt System

SCON.0

RI

Serial I/O

Interrupt Request

TI

ES

SCON.1

IEN0.4

Figure 113. Interrupt Waveforms

a. Mode 1

RXD

D0

D1

D2

D3

D4

D5

D6

D7

Start Bit

8-bit Data

Stop Bit

RI

SMOD0 = X

FE

SMOD0 = 1

b. Mode 2 and 3

RXD

D0

D1

D2

D3

D4

D5

D6

D7

D8

Start bit

9-bit data

Stop bit

RI

SMOD0 = 0

RI

SMOD0 = 1

FE

SMOD0 = 1

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19.10 Registers

Table 11. SCON Register

SCON (S:98h) – Serial Control Register

7

6

5

4

3

2

1

0

FE/SM0

OVR/SM1

SM2

REN

TB8

RB8

TI

RI

Bit

Number

Mnemonic Description

Framing Error Bit

To select this function, set SMOD0 bit in PCON register.

Set by hardware to indicate an invalid stop bit.

Must be cleared by software.

FE

7

Serial Port Mode Bit 0

Refer to Table 2 for mode selection.

SM0

SM1

Serial Port Mode Bit 1

Refer to Table 2 for mode selection.

6

5

Serial Port Mode Bit 2

Set to enable the multiprocessor communication and automatic address

recognition features.

SM2

Clear to disable the multiprocessor communication and automatic address

recognition features.

Receiver Enable Bit

4

3

REN

TB8

Set to enable reception.

Clear to disable reception.

Transmit Bit 8

Modes 0 and 1: Not used.

Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8.

Receiver Bit 8

Mode 0: Not used.

Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit

received.

2

RB8

Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit

received.

Transmit Interrupt Flag

1

0

TI

Set by the transmitter after the last data bit is transmitted.

Must be cleared by software.

Receive Interrupt Flag

Set by the receiver after the stop bit of a frame has been received.

Must be cleared by software.

RI

Reset Value = 0000 0000b

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Table 12. SBUF Register

SBUF (S:99h) – Serial Buffer Register

7

6

5

4

3

2

1

0

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

Bit

Number

Mnemonic Description

Serial Data Byte

7 - 0

SD7:0

Read the last data received by the serial I/O Port.

Write the data to be transmitted by the serial I/O Port.

Reset value = XXXX XXXXb

Table 13. SADDR Register

SADDR (S:A9h) – Slave Individual Address Register

7

6

5

4

3

2

1

0

SAD7

SAD6

SAD5

SAD4

SAD3

SAD2

SAD1

SAD0

Bit

Number

Mnemonic Description

7 - 0

SAD7:0 Slave Individual Address

Reset Value = 0000 0000b

Table 14. SADEN Register

SADEN (S:B9h) – Slave Individual Address Mask Byte Register

7

6

5

4

3

2

1

0

SAE7

SAE6

SAE5

SAE4

SAE3

SAE2

SAE1

SAE0

Bit

Number

Mnemonic Description

7 - 0

SAE7:0 Slave Address Mask Byte

Reset Value = 0000 0000b

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Table 15. BDRCON Register

BDRCON (S:92h) – Baud Rate Generator Control Register

7

-

6

-

5

-

4

3

2

1

0

BRR

TBCK

RBCK

SPD

M0SRC

Bit

Number

Mnemonic Description

Reserved

7 - 5

4

-

The value read from these bits are indeterminate. Do not set these bits.

Baud Rate Run Bit

Set to enable the baud rate generator.

Clear to disable the baud rate generator.

BRR

TBCK

RBCK

SPD

Transmission Baud Rate Selection Bit

Set to select the baud rate generator as transmission baud rate generator.

Clear to select the Timer 1 as transmission baud rate generator.

3

2

1

0

Reception Baud Rate Selection Bit

Set to select the baud rate generator as reception baud rate generator.

Clear to select the Timer 1 as reception baud rate generator.

Baud Rate Speed Bit

Set to select high speed baud rate generation.

Clear to select low speed baud rate generation.

Mode 0 Baud Rate Source Bit

M0SRC Set to select the variable baud rate generator in Mode 0.

Clear to select fixed baud rate in Mode 0.

Reset Value = XXX0 0000b

Table 16. BRL Register

BRL (S:91h) – Baud Rate Generator Reload Register

7

6

5

4

3

2

1

0

BRL7

BRL6

BRL5

BRL4

BRL3

BRL2

BRL1

BRL0

Bit

Number

Mnemonic Description

7 - 0

BRL7:0 Baud Rate Reload Value

Reset Value = 0000 0000b

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20. Synchronous

Peripheral Interface

The AT8xC51SND1C implements a Synchronous Peripheral Interface with master and

slave modes capability.

Figure 114 shows an SPI bus configuration using the AT8xC51SND1C as master con-

nected to slave peripherals while Figure 115 shows an SPI bus configuration using the

AT8xC51SND1C as slave of an other master.

The bus is made of three wires connecting all the devices together:

•

Master Output Slave Input (MOSI): it is used to transfer data in series from the

master to a slave.

It is driven by the master.

Master Input Slave Output (MISO): it is used to transfer data in series from a slave

to the master.

It is driven by the selected slave.

Serial Clock (SCK): it is used to synchronize the data transmission both in and out

the devices through their MOSI and MISO lines. It is driven by the master for eight

clock cycles which allows to exchange one Byte on the serial lines.

Each slave peripheral is selected by one Slave Select pin (SS). If there is only one

slave, it may be continuously selected with SS tied to a low level. Otherwise, the

AT8xC51SND1C may select each device by software through port pins (Pn.x). Special

care should be taken not to select 2 slaves at the same time to avoid bus conflicts.

Figure 114. Typical Master SPI Bus Configuration

Pn.z

Pn.y

LCD

Controller

Pn.x

SS

SO

SS

DataFlash 1

DataFlash 2

AT8xC51SND1C

SI

SCK

SO

SI

SCK

SO

SI

SCK

MISO

MOSI

SCK

P4.0

P4.1

P4.2

Figure 115. Typical Slave SPI Bus Configuration

SSn

SS1

SS

AT8xC51SND1C

Slave n

SS0

SS

SO

Slave 1

Slave 2

SO

SI

SCK

SI

SCK

MISO MOSI SCK

MASTER

MISO

MOSI

SCK

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20.1 Description

The SPI controller interfaces with the C51 core through three special function registers:

SPCON, the SPI control register (see Table 6); SPSTA, the SPI status register (see

Table 7); and SPDAT, the SPI data register (see Table 8).

20.1.1 Master Mode

The SPI operates in master mode when the MSTR bit in SPCON is set.

Figure 116 shows the SPI block diagram in master mode. Only a master SPI module

can initiate transmissions. Software begins the transmission by writing to SPDAT. Writ-

ing to SPDAT writes to the shift register while reading SPDAT reads an intermediate

register updated at the end of each transfer.

The Byte begins shifting out on the MOSI pin under the control of the bit rate generator.

This generator also controls the shift register of the slave peripheral through the SCK

output pin. As the Byte shifts out, another Byte shifts in from the slave peripheral on the

MISO pin. The Byte is transmitted most significant bit (MSB) first. The end of transfer is

signaled by SPIF being set.

When the AT8xC51SND1C is the only master on the bus, it can be useful not to use SS

pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON.

Figure 116. SPI Master Mode Block Diagram

MOSI/P4.1

I

Q

MISO/P4.0

SCK/P4.2

SS/P4.3

8-bit Shift Register

SPDAT WR

SPDAT RD

MODF

SSDIS

SPCON.5

SPSTA.4

Control and Clock Logic

WCOL

SPSTA.6

PER

Bit Rate Generator

CLOCK

SPIF

SPSTA.7

SPEN

SPCON.6

SPR2:0

SPCON

CPHA

SPCON.2

CPOL

SPCON.3

Note:

MSTR bit in SPCON is set to select master mode.

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20.1.2 Slave Mode

The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has

been loaded in SPDAT.

Figure 117 shows the SPI block diagram in slave mode. In slave mode, before a data

transmission occurs, the SS pin of the slave SPI must be asserted to low level. SS must

remain low until the transmission of the Byte is complete. In the slave SPI module, data

enters the shift register through the MOSI pin under the control of the serial clock pro-

vided by the master SPI module on the SCK input pin. When the master starts a

transmission, the data in the shift register begins shifting out on the MISO pin. The end

of transfer is signaled by SPIF being set.

When the AT8xC51SND1C is the only slave on the bus, it can be useful not to use SS

pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON.

This bit has no effect when CPHA is cleared (see Section "SS Management",

page 153).

Figure 117. SPI Slave Mode Block Diagram

MISO/P4.2

I

Q

MOSI/P4.1

8-bit Shift Register

SPDAT WR

SPDAT RD

SCK/P4.2

SS/P4.3

Control and Clock Logic

SPIF

SPSTA.7

SSDIS

SPCON.5

CPHA

SPCON.2

CPOL

SPCON.3

Note:

1. MSTR bit in SPCON is cleared to select slave mode.

20.1.3 Bit Rate

The bit rate can be selected from seven predefined bit rates using the SPR2, SPR1 and

SPR0 control bits in SPCON according to Table 2. These bit rates are derived from the

peripheral clock (F_PER) issued from the Clock Controller block as detailed in Section

"Oscillator", page 12.

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Table 2. Serial Bit Rates

Bit Rate (kHz) Vs F_PER

SPR2 SPR1 SPR0 6 MHz⁽¹⁾8 MHz⁽¹⁾10 MHz⁽¹⁾12 MHz⁽²⁾16 MHz⁽²⁾20 MHz⁽²⁾F_PERDivider

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3000

1500

750

4000

2000

1000

500

5000

2500

6000

3000

1500

750

8000

4000

2000

1000

500

10000

5000

2

4

1250

2500

8

375

625

1250

16

32

64

128

1

187.5

93.75

46.875

6000

250

312.5

156.25

78.125

10000

375

625

125

187.5

93.75

12000

250

312.5

156.25

20000

62.5

8000

125

16000

Notes: 1. These frequencies are achieved in X1 mode, F_PER= F_OSC÷ 2.

2. These frequencies are achieved in X2 mode, F_PER= F_OSC

.

20.2.1 Data Transfer

The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle

state⁽¹⁾while the Clock Phase bit (CPHA in SPCON) defines the edges on which the

input data are sampled and the edges on which the output data are shifted (see

Figure 118 and Figure 119). The SI signal is output from the selected slave and the SO

signal is the output from the master. The AT8xC51SND1C captures data from the SI line

while the selected slave captures data from the SO line.

For simplicity, Figure 118 and Figure 119 depict the SPI waveforms in idealized form

and do not provide precise timing information. For timing parameters refer to the Section

“AC Characteristics”.

Note:

1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.

Figure 118. Data Transmission Format (CPHA = 0)

1

2

3

4

5

6

7

8

SCK Cycle Number

SPEN (Internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MSB

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

LSB

MOSI (From Master)

MISO (From Slave)

MSB

SS (to slave)

Capture point

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Figure 119. Data Transmission Format (CPHA = 1)

1

2

3

4

5

6

7

8

SCK cycle number

SPEN (internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MSB

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

LSB

MOSI (from master)

MISO (from slave)

SS (to slave)

Capture point

20.2.2 SS Management

Figure 118 shows an SPI transmission with CPHA = 0, where the first SCK edge is the

MSB capture point. Therefore the slave starts to output its MSB as soon as it is

selected: SS asserted to low level. SS must then be deasserted between each Byte

transmission (see Figure 120). SPDAT must be loaded with a data before SS is

asserted again.

Figure 119 shows an SPI transmission with CPHA = 1, where the first SCK edge is used

by the slave as a start of transmission signal. Therefore, SS may remain asserted

between each Byte transmission (see Figure 120).

Figure 120. SS Timing Diagram

Byte 1

Byte 2

Byte 3

SI/SO

SS (CPHA = 0)

SS (CPHA = 1)

20.2.3 Error Conditions

The following flags signal the SPI error conditions:

•

MODF in SPSTA signals a mode fault.

MODF flag is relevant only in master mode when SS usage is enabled (SSDIS bit

cleared). It signals when set that an other master on the bus has asserted SS pin

and so, may create a conflict on the bus with 2 master sending data at the same

time.

A mode fault automatically disables the SPI (SPEN cleared) and configures the SPI

in slave mode (MSTR cleared).

MODF flag can trigger an interrupt as explained in Section "Interrupt", page 154.

MODF flag is cleared by reading SPSTA and re-configuring SPI by writing to

SPCON.

WCOL in SPSTA signals a write collision.

WCOL flag is set when SPDAT is loaded while a transfer is on-going. In this case

data is not written to SPDAT and transfer continue uninterrupted. WCOL flag does

not trigger any interrupt and is relevant jointly with SPIF flag.

WCOL flag is cleared after reading SPSTA and writing new data to SPDAT while no

transfer is on-going.

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20.3 Interrupt

The SPI handles 2 interrupt sources that are the “end of transfer” and the “mode fault”

flags.

As shown in Figure 121, these flags are combined toghether to appear as a single inter-

rupt source for the C51 core. The SPIF flag is set at the end of an 8-bit shift in and out

and is cleared by reading SPSTA and then reading from or writing to SPDAT.

The MODF flag is set in case of mode fault error and is cleared by reading SPSTA and

then writing to SPCON.

The SPI interrupt is enabled by setting ESPI bit in IEN1 register. This assumes inter-

rupts are globally enabled by setting EA bit in IEN0 register.

Figure 121. SPI Interrupt System

SPIF

SPI Controller

Interrupt Request

SPSTA.7

MODF

SPSTA.4

ESPI

IEN1.2

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20.4 Configuration

The SPI configuration is made through SPCON.

20.4.1 Master Configuration

20.4.2 Slave Configuration

The SPI operates in master mode when the MSTR bit in SPCON is set.

The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has

been loaded is SPDAT.

20.4.3 Data Exchange

There are 2 possible methods to exchange data in master and slave modes:

•

polling

interrupts

20.4.4 Master Mode with

Polling Policy

Figure 122 shows the initialization phase and the transfer phase flows using the polling

method. Using this flow prevents any overrun error occurrence.

The bit rate is selected according to Table 2. The transfer format depends on the slave

peripheral.

SS may be deasserted between transfers depending also on the slave peripheral.

SPIF flag is cleared when reading SPDAT (SPSTA has been read before by the “end of

transfer” check).

This polling method provides the fastest effective transmission and is well adapted when

communicating at high speed with other microcontrollers. However, the procedure may

then be interrupted at any time by higher priority tasks.

Figure 122. Master SPI Polling Flows

SPI Initialization

Polling Policy

SPI Transfer

Polling Policy

Disable interrupt

Select Slave

SPIE = 0

Pn.x = L

Select Master Mode

Start Transfer

MSTR = 1

write data in SPDAT

Select Bit Rate

program SPR2:0

End Of Transfer?

SPIF = 1?

Select Format

program CPOL & CPHA

Get Data Received

read SPDAT

Enable SPI

SPEN = 1

Last Transfer?

Deselect Slave

Pn.x = H

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20.4.5 Master Mode with

Interrupt

Figure 123 shows the initialization phase and the transfer phase flows using the inter-

rupt. Using this flow prevents any overrun error occurrence.

The bit rate is selected according to Table 2.

The transfer format depends on the slave peripheral.

SS may be deasserted between transfers depending also on the slave peripheral.

Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag.

Clear is effective when reading SPDAT.

Figure 123. Master SPI Interrupt Flows

SPI Initialization

Interrupt Policy

SPI Interrupt

Service Routine

Select Master Mode

Read Status

MSTR = 1

Read SPSTA

Select Bit Rate

Get Data Received

program SPR2:0

read SPDAT

Select Format

Start New Transfer

program CPOL & CPHA

write data in SPDAT

Enable interrupt

ESPI =1

Last Transfer?

Enable SPI

SPEN = 1

Deselect Slave

Pn.x = H

Select Slave

Pn.x = L

Disable interrupt

SPIE = 0

Start Transfer

write data in SPDAT

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20.4.6 Slave Mode with Polling Figure 124 shows the initialization phase and the transfer phase flows using the polling.

Policy

The transfer format depends on the master controller.

SPIF flag is cleared when reading SPDAT (SPSTA has been read before by the “end of

reception” check).

This provides the fastest effective transmission and is well adapted when communicat-

ing at high speed with other Microcontrollers. However, the process may then be

interrupted at any time by higher priority tasks.

Figure 124. Slave SPI Polling Flows

SPI Initialization

Polling Policy

SPI Transfer

Polling Policy

Disable interrupt

Data Received?

SPIE = 0

SPIF = 1?

Select Slave Mode

MSTR = 0

Get Data Received

read SPDAT

Select Format

program CPOL & CPHA

Prepare Next Transfer

write data in SPDAT

Enable SPI

SPEN = 1

Prepare Transfer

write data in SPDAT

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20.4.7 Slave Mode with

Interrupt Policy

Figure 123 shows the initialization phase and the transfer phase flows using the

interrupt.

The transfer format depends on the master controller.

Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag.

Clear is effective when reading SPDAT.

Figure 125. Slave SPI Interrupt Policy Flows

SPI Initialization

Interrupt Policy

SPI Interrupt

Service Routine

Select Slave Mode

Get Status

MSTR = 0

Read SPSTA

Select Format

Get Data Received

program CPOL & CPHA

read SPDAT

Enable interrupt

Prepare New Transfer

ESPI =1

write data in SPDAT

Enable SPI

SPEN = 1

Prepare Transfer

write data in SPDAT

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20.5 Registers

Table 6. SPCON Register

SPCON (S:C3h) – SPI Control Register

7

6

5

4

3

2

1

0

SPR2

SPEN

SSDIS

MSTR

CPOL

CPHA

SPR1

SPR0

Bit

Number

Mnemonic Description

SPI Rate Bit 2

Refer to Table 2 for bit rate description.

7

6

SPR2

SPI Enable Bit

Set to enable the SPI interface.

Clear to disable the SPI interface.

SPEN

Slave Select Input Disable Bit

Set to disable SS in both master and slave modes. In slave mode this bit has no

effect if CPHA = 0.

5

SSDIS

Clear to enable SS in both master and slave modes.

Master Mode Select

4

3

MSTR

CPOL

Set to select the master mode.

Clear to select the slave mode.

SPI Clock Polarity Bit⁽¹⁾

Set to have the clock output set to high level in idle state.

Clear to have the clock output set to low level in idle state.

SPI Clock Phase Bit

2

CPHA

Set to have the data sampled when the clock returns to idle state (see CPOL).

Clear to have the data sampled when the clock leaves the idle state (see CPOL).

SPI Rate Bits 0 and 1

Refer to Table 2 for bit rate description.

1 - 0

SPR1:0

Reset Value = 0001 0100b

Note: 1. When the SPI is disabled, SCK outputs high level.

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Table 7. SPSTA Register

SPSTA (S:C4h) – SPI Status Register

7

6

5

-

4

3

-

2

-

1

-

0

-

SPIF

WCOL

MODF

Bit

Number

Mnemonic Description

SPI Interrupt Flag

Set by hardware when an 8-bit shift is completed.

7

SPIF

Cleared by hardware when reading or writing SPDAT after reading SPSTA.

Write Collision Flag

6

5

WCOL

Set by hardware to indicate that a collision has been detected.

Cleared by hardware to indicate that no collision has been detected.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Mode Fault

4

MODF

-

Set by hardware to indicate that the SS pin is at an appropriate level.

Cleared by hardware to indicate that the SS pin is at an inappropriate level.

Reserved

3 - 0

The value read from these bits is indeterminate. Do not set these bits.

Reset Value = 00000 0000b

Table 8. SPDAT Register

SPDAT (S:C5h) – Synchronous Serial Data Register

7

6

5

4

3

2

1

0

SPD7

SPD6

SPD5

SPD4

SPD3

SPD2

SPD1

SPD0

Bit

Number

Mnemonic Description

7 - 0

SPD7:0 Synchronous Serial Data.

Reset Value = XXXX XXXXb

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21. Two-wire

Interface (TWI)

Controller

The AT8xC51SND1C implements a TWI controller supporting the four standard master

and slave modes with multimaster capability. Thus, it allows connection of slave devices

like LCD controller, audio DAC, etc., but also external master controlling where the

AT8xC51SND1C is used as a peripheral of a host.

The TWI bus is a bi-directional TWI serial communication standard. It is designed prima-

rily for simple but efficient integrated circuit control. The system is comprised of 2 lines,

SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs con-

nected to them. The serial data transfer is limited to 100 Kbit/s in low speed mode,

however, some higher bit rates can be achieved depending on the oscillator frequency.

Various communication configurations can be designed using this bus. Figure 126

shows a typical TWI bus configuration using the AT8xC51SND1C in master and slave

modes. All the devices connected to the bus can be master and slave.

Figure 126. Typical TWI Bus Configuration

AT8xC51SND1C

Master/Slave

HOST

Microprocessor

LCD

Display

Audio

DAC

Rp Rp

P1.6/SCL

P1.7/SDA

SCL

SDA

21.1 Description

The CPU interfaces to the TWI logic via the following four 8-bit special function regis-

ters: the Synchronous Serial Control register (SSCON SFR, see Table 10), the

Synchronous Serial Data register (SSDAT SFR, see Table 12), the Synchronous Serial

Status register (SSSTA SFR, see Table 11) and the Synchronous Serial Address regis-

ter (SSADR SFR, see Table 13).

SSCON is used to enable the controller, to program the bit rate (see Table 10), to

enable slave modes, to acknowledge or not a received data, to send a START or a

STOP condition on the TWI bus, and to acknowledge a serial interrupt. A hardware

reset disables the TWI controller.

SSSTA contains a status code which reflects the status of the TWI logic and the TWI

bus. The three least significant bits are always zero. The five most significant bits con-

tains the status code. There are 26 possible status codes. When SSSTA contains F8h,

no relevant state information is available and no serial interrupt is requested. A valid sta-

tus code is available in SSSTA after SSI is set by hardware and is still present until SSI

has been reset by software. Table 3 to Table 131 give the status for both master and

slave modes and miscellaneous states.

SSDAT contains a Byte of serial data to be transmitted or a Byte which has just been

received. It is addressable while it is not in process of shifting a Byte. This occurs when

TWI logic is in a defined state and the serial interrupt flag is set. Data in SSDAT remains

stable as long as SSI is set. While data is being shifted out, data on the bus is simulta-

neously shifted in; SSDAT always contains the last Byte present on the bus.

SSADR may be loaded with the 7 - bit slave address (7 most significant bits) to which

the controller will respond when programmed as a slave transmitter or receiver. The

LSB is used to enable general call address (00h) recognition.

Figure 127 shows how a data transfer is accomplished on the TWI bus.

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Figure 127. Complete Data Transfer on TWI Bus

SDA

MSB

Slave Address

R/W

ACK

Nth data Byte

ACK

signal

from

direction signal

bit

from

receiver

1

2

8

9

1

2

8

9

SCL

S

P/S

Clock Line Held Low While Serial Interrupts Are Serviced

The four operating modes are:

•

Master transmitter

Master receiver

Slave transmitter

Slave receiver

Data transfer in each mode of operation are shown in Figure 128 through Figure 131.

These figures contain the following abbreviations:

A

Acknowledge bit (low level at SDA)

Not acknowledge bit (high level on SDA)

8-bit data Byte

A

Data

S

START condition

P

STOP condition

MR

MT

SLA

GCA

R

Master Receive

Master Transmit

Slave Address

General Call Address (00h)

Read bit (high level at SDA)

Write bit (low level at SDA)

W

In Figure 128 through Figure 131, circles are used to indicate when the serial interrupt

flag is set. The numbers in the circles show the status code held in SSSTA. At these

points, a service routine must be executed to continue or complete the serial transfer.

These service routines are not critical since the serial transfer is suspended until the

serial interrupt flag is cleared by software.

When the serial interrupt routine is entered, the status code in SSSTA is used to branch

to the appropriate service routine. For each status code, the required software action

and details of the following serial transfer are given in Table 3 through Table 131.

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21.1.1 Bit Rate

The bit rate can be selected from seven predefined bit rates or from a programmable bit

rate generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see

Table 10). The predefined bit rates are derived from the peripheral clock (F_PER) issued

from the Clock Controller block as detailed in section "Oscillator", page 12, while bit rate

generator is based on timer 1 overflow output.

Table 2. Serial Clock Rates

SSCRx

Bit Frequency (kHz)

2

1

0

1

0

1

0

F_PER= 6 MHz

F_PER= 8 MHz

62.5

F_PER= 10 MHz

78.125

89.3

F

_PERDivided By

0

47

53.5

62.5

75

128

112

96

0

1

0

1

0

1

0

71.5

83

104.2⁽¹⁾

125⁽¹⁾

100

80

12.5

100

16.5

20.83

480

60

133.3⁽¹⁾

266.7⁽¹⁾

166.7⁽¹⁾

333.3⁽¹⁾

200⁽¹⁾

30

0.67 < ⋅ <

0.81 < ⋅ <

1

0.5 < ⋅ < 125⁽¹⁾

96 ⋅ (256 – reload value Timer 1)

166.7⁽¹⁾

208.3⁽¹⁾

Note:

1. These bit rates are outside of the low speed standard specification limited to 100 kHz

but can be used with high speed TWI components limited to 400 kHz.

21.2.1 Master Transmitter

Mode

In the master transmitter mode, a number of data Bytes are transmitted to a slave

receiver (see Figure 128). Before the master transmitter mode can be entered, SSCON

must be initialized as follows:

SSCR2

Bit Rate

SSPE

1

SSSTA

0

SSSTO

0

SSI

0

SSAA

X

SSCR1

Bit Rate

SSCR0

Bit Rate

SSCR2:0 define the serial bit rate (see Table 2). SSPE must be set to enable the con-

troller. SSSTA, SSSTO and SSI must be cleared.

The master transmitter mode may now be entered by setting the SSSTA bit. The TWI

logic will now monitor the TWI bus and generate a START condition as soon as the bus

becomes free. When a START condition is transmitted, the serial interrupt flag (SSI bit

in SSCON) is set, and the status code in SSSTA is 08h. This status must be used to

vector to an interrupt routine that loads SSDAT with the slave address and the data

direction bit (SLA+W). The serial interrupt flag (SSI) must then be cleared before the

serial transfer can continue.

When the slave address and the direction bit have been transmitted and an acknowl-

edgment bit has been received, SSI is set again and a number of status code in SSSTA

are possible. There are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if

the slave mode was enabled (SSAA = logic 1). The appropriate action to be taken for

each of these status code is detailed in Table 3. This scheme is repeated until a STOP

condition is transmitted.

SSPE and SSCR2:0 are not affected by the serial transfer and are not referred to in

Table 3. After a repeated START condition (state 10h) the controller may switch to the

master receiver mode by loading SSDAT with SLA+R.

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21.2.2 Master Receiver Mode

In the master receiver mode, a number of data Bytes are received from a slave transmit-

ter (see Figure 129). The transfer is initialized as in the master transmitter mode. When

the START condition has been transmitted, the interrupt routine must load SSDAT with

the 7 - bit slave address and the data direction bit (SLA+R). The serial interrupt flag

(SSI) must then be cleared before the serial transfer can continue.

When the slave address and the direction bit have been transmitted and an acknowl-

edgment bit has been received, the serial interrupt flag is set again and a number of

status code in SSSTA are possible. There are 40h, 48h or 38h for the master mode and

also 68h, 78h or B0h if the slave mode was enabled (SSAA = logic 1). The appropriate

action to be taken for each of these status code is detailed in Table 131. This scheme is

repeated until a STOP condition is transmitted.

SSPE and SSCR2:0 are not affected by the serial transfer and are not referred to in

Table 131. After a repeated START condition (state 10h) the controller may switch to

the master transmitter mode by loading SSDAT with SLA+W.

21.2.3 Slave Receiver Mode

In the slave receiver mode, a number of data Bytes are received from a master transmit-

ter (see Figure 130). To initiate the slave receiver mode, SSADR and SSCON must be

loaded as follows:

SSA6

SSA5

SSA4

SSA3

SSA2

SSA1

SSA0

SSGC

X

←⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯

Own Slave Address

⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯→

The upper 7 bits are the addresses to which the controller will respond when addressed

by a master. If the LSB (SSGC) is set, the controller will respond to the general call

address (00h); otherwise, it ignores the general call address.

SSCR2

X

SSPE

1

SSSTA

0

SSSTO

0

SSI

0

SSAA

1

SSCR1

X

SSCR0

X

SSCR2:0 have no effect in the slave mode. SSPE must be set to enable the controller.

The SSAA bit must be set to enable the own slave address or the general call address

acknowledgment. SSSTA, SSSTO and SSI must be cleared.

When SSADR and SSCON have been initialized, the controller waits until it is

addressed by its own slave address followed by the data direction bit which must be

logic 0 (W) for operating in the slave receiver mode. After its own slave address and the

W bit has been received, the serial interrupt flag is set and a valid status code can be

read from SSSTA. This status code is used to vector to an interrupt service routine, and

the appropriate action to be taken for each of these status code is detailed in Table 131

and Table 7. The slave receiver mode may also be entered if arbitration is lost while the

controller is in the master mode (see states 68h and 78h).

If the SSAA bit is reset during a transfer, the controller will return a not acknowledge

(logic 1) to SDA after the next received data Byte. While SSAA is reset, the controller

does not respond to its own slave address. However, the TWI bus is still monitored and

address recognition may be resumed at any time by setting SSAA. This means that the

SSAA bit may be used to temporarily isolate the controller from the TWI bus.

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21.2.4 Slave Transmitter Mode In the slave transmitter mode, a number of data Bytes are transmitted to a master

receiver (see Figure 131). Data transfer is initialized as in the slave receiver mode.

When SSADR and SSCON have been initialized, the controller waits until it is

addressed by its own slave address followed by the data direction bit which must be

logic 1 (R) for operating in the slave transmitter mode. After its own slave address and

the R bit have been received, the serial interrupt flag is set and a valid status code can

be read from SSSTA. This status code is used to vector to an interrupt service routine,

and the appropriate action to be taken for each of these status code is detailed in

Table 7. The slave transmitter mode may also be entered if arbitration is lost while the

controller is in the master mode (see state B0h).

If the SSAA bit is reset during a transfer, the controller will transmit the last Byte of the

transfer and enter state C0h or C8h. The controller is switched to the not addressed

slave mode and will ignore the master receiver if it continues the transfer. Thus the mas-

ter receiver receives all 1’s as serial data. While SSAA is reset, the controller does not

respond to its own slave address. However, the TWI bus is still monitored and address

recognition may be resumed at any time by setting SSAA. This means that the SSAA bit

may be used to temporarily isolate the controller from the TWI bus.

21.2.5 Miscellaneous States

There are 2 SSSTA codes that do not correspond to a defined TWI hardware state (see

Table 8). These are discussed below.

Status F8h indicates that no relevant information is available because the serial interrupt

flag is not yet set. This occurs between other states and when the controller is not

involved in a serial transfer.

Status 00h indicates that a bus error has occurred during a serial transfer. A bus error is

caused when a START or a STOP condition occurs at an illegal position in the format

frame. Examples of such illegal positions are during the serial transfer of an address

Byte, a data Byte, or an acknowledge bit. When a bus error occurs, SSI is set. To

recover from a bus error, the SSSTO flag must be set and SSI must be cleared. This

causes the controller to enter the not addressed slave mode and to clear the SSSTO

flag (no other bits in S1CON are affected). The SDA and SCL lines are released and no

STOP condition is transmitted.

Note:

The TWI controller interfaces to the external TWI bus via 2 port 1 pins: P1.6/SCL (serial

clock line) and P1.7/SDA (serial data line). To avoid low level asserting and conflict on

these lines when the TWI controller is enabled, the output latches of P1.6 and P1.7 must

be set to logic 1.

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Figure 128. Format and States in the Master Transmitter Mode

MT

Successful transmis-

sion to a slave receiver

S

SLA

W

A

Data

A

P

08h

18h

28h

Next transfer started with

a repeated start condition

S

SLA

W

R

10h

Not acknowledge received

after the slave address

A

P

MR

20h

Not acknowledge received

after a data Byte

A

P

30h

Arbitration lost in slave

address or data Byte

Other master

continues

Other master

continues

A or A

38h

A

38h

Arbitration lost and

addressed as slave

Other master

continues

To corresponding

states in slave mode

68h 78h B0h

Any number of data Bytes and their associated

acknowledge bits

From master to slave

From slave to master

Data

nnh

A

This number (contained in SSSTA) corresponds

to a defined state of the TWI bus

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Figure 129. Format and States in the Master Receiver Mode

MR

Successful reception

from a slave transmitter

S

SLA

R

A

Data

A

Data

A

P

08h

40h

50h

58h

Next transfer started with

a repeated start condition

S

SLA

R

10h

W

Not acknowledge received

after the slave address

A

P

MT

48h

Arbitration lost in slave

address or data Byte

Other master

continues

Other master

continues

A or A

A

38h

A

38h

Arbitration lost and

addressed as slave

Other master

continues

To corresponding

states in slave mode

68h 78h B0h

Any number of data Bytes and their associated

acknowledge bits

From master to slave

From slave to master

Data

nnh

A

This number (contained in SSSTA) corresponds

to a defined state of the TWI bus

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Figure 130. Format and States in the Slave Receiver Mode

Reception of the own slave

address and one or more

S

SLA

W

A

Data

A

Data

A

P or S

data Bytes.

All are acknowledged

60h

80h

80h A0h

Last data Byte received

is not acknowledged

A

P or S

88h

Arbitration lost as master and

addressed as slave

A

68h

A

Reception of the general call

address and one or more data Bytes

General Call

Data

A

Data

A

P or S

70h

90h

90h A0h

Last data Byte received

is not acknowledged

A

P or S

98h

Arbitration lost as master and

addressed as slave by general call

A

78h

Any number of data Bytes and their associated

acknowledge bits

From master to slave

From slave to master

Data

nnh

A

This number (contained in SSSTA) corresponds

to a defined state of the TWI bus

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Figure 131. Format and States in the Slave Transmitter Mode

Reception of the own slave

address and transmission

of one or more data Bytes.

S

SLA

R

A

Data

A

Data

A

P or S

A8h

A

B8h

C0h

Arbitration lost as master and

addressed as slave

B0h

Last data Byte transmitted.

Switched to not addressed

slave (SSAA = 0).

A

All 1’s P or S

C8h

Any number of data Bytes and their associated

acknowledge bits

From master to slave

From slave to master

Data

A

This number (contained in SSSTA) corresponds

to a defined state of the TWI bus

nnh

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Table 3. Status for Master Transmitter Mode

Application Software Response

To SSCON

SSSTO SSI

Status

Code Status of the TWI Bus

SSSTA and TWI Hardware

To/From SSDAT

SSSTA

SSAA Next Action Taken by TWI Hardware

A START condition has Write SLA+W

been transmitted

SLA+W will be transmitted.

X

08h

X

0

Write SLA+W

SLA+W will be transmitted.

X

0

A repeated START

condition has been

10h

Write SLA+R

transmitted

SLA+R will be transmitted.

X

Logic will switch to master receiver mode

Write data Byte

Data Byte will be transmitted.

X

0

1

0

1

0

No SSDAT action

SLA+W has been

Repeated START will be transmitted.

X

No SSDAT action

STOP condition will be transmitted and SSSTO flag

will be reset.

18h

20h

28h

transmitted; ACK has

been received

X

No SSDAT action

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

1

0

X

Write data Byte

Data Byte will be transmitted.

X

0

1

0

1

0

No SSDAT action

SLA+W has been

Repeated START will be transmitted.

X

No SSDAT action

STOP condition will be transmitted and SSSTO flag

will be reset.

transmitted; NOT ACK

X

has been received

No SSDAT action

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

1

0

X

Write data Byte

Data Byte will be transmitted.

X

0

1

0

1

0

No SSDAT action

Repeated START will be transmitted.

X

Data Byte has been

transmitted; ACK has

been received

No SSDAT action

STOP condition will be transmitted and SSSTO flag

will be reset.

X

No SSDAT action

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

1

0

X

Write data Byte

Data Byte will be transmitted.

X

0

1

0

1

0

No SSDAT action

Repeated START will be transmitted.

X

Data Byte has been

transmitted; NOT ACK

No SSDAT action

STOP condition will be transmitted and SSSTO flag

will be reset.

30h

38h

X

has been received

No SSDAT action

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

1

0

X

No SSDAT action

Arbitration lost in

TWI bus will be released and not addressed slave

mode will be entered.

0

1

0

X

SLA+W or data Bytes

No SSDAT action

A START condition will be transmitted when the bus

becomes free.

X

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Table 4. Status for Master Receiver Mode

Application Software Response

To SSCON

SSSTO SSI

Status

Code Status of the TWI Bus

SSSTA and TWI Hardware

To/From SSDAT

SSSTA

SSAA Next Action Taken by TWI Hardware

A START condition has Write SLA+R

been transmitted

SLA+R will be transmitted.

08h

X

0

X

Write SLA+R

SLA+R will be transmitted.

X

0

X

A repeated START

condition has been

10h

Write SLA+W

transmitted

SLA+W will be transmitted.

Logic will switch to master transmitter mode.

No SSDAT action

Arbitration lost in

TWI bus will be released and not addressed slave

mode will be entered.

0

1

0

X

0

1

38h

40h

SLA+R or NOT ACK

No SSDAT action

bit

A START condition will be transmitted when the bus

becomes free.

No SSDAT action

Data Byte will be received and NOT ACK will be

returned.

SLA+R has been

transmitted; ACK has

been received

Data Byte will be received and ACK will be returned.

No SSDAT action

Repeated START will be transmitted.

1

0

1

0

X

SLA+R has been

transmitted; NOT ACK

has been received

STOP condition will be transmitted and SSSTO flag

will be reset.

48h

50h

58h

No SSDAT action

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

1

0

1

0

X

0

1

Read data Byte

Data Byte will be received and NOT ACK will be

returned.

Data Byte has been

received; ACK has

been returned

Data Byte will be received and ACK will be returned.

Read data Byte

Repeated START will be transmitted.

1

0

1

0

X

Data Byte has been

received; NOT ACK

has been returned

STOP condition will be transmitted and SSSTO flag

will be reset.

Read data Byte

STOP condition followed by a START condition will

be transmitted and SSSTO flag will be reset.

1

0

X

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Table 5. Status for Slave Receiver Mode with Own Slave Address

Application Software Response

Status

To SSCON

SSSTO SSI

Code Status of the TWI Bus

SSSTA and TWI Hardware

To/From SSDAT

SSSTA

SSAA Next Action Taken by TWI Hardware

No SSDAT action

X

0

1

Data Byte will be received and NOT ACK will be

returned.

Own SLA+W has been

received; ACK has

been returned

60h

68h

No SSDAT action

X

Data Byte will be received and ACK will be returned.

Arbitration lost in

Data Byte will be received and NOT ACK will be

returned.

X

0

1

SLA+R/W as master;

own SLA+W has been

received; ACK has

been returned

No SSDAT action

Data Byte will be received and ACK will be returned.

Previously addressed Read data Byte

with own SLA+W; data

Data Byte will be received and NOT ACK will be

returned.

X

0

1

80h

has been received;

ACK has been

returned

Read data Byte

Data Byte will be received and ACK will be returned.

Read data Byte

Switched to the not addressed slave mode; no

recognition of own SLA or GCA.

0

1

Switched to the not addressed slave mode; own

SLA will be recognized; GCA will be recognized if

SSGC = logic 1.

Previously addressed

with own SLA+W; data

has been received;

NOT ACK has been

returned

Read data Byte

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START condition

will be transmitted when the bus becomes free.

88h

1

0

1

Switched to the not addressed slave mode; own

SLA will be recognized; GCA will be recognized if

SSGC = logic 1. A START condition will be

transmitted when the bus becomes free.

No SSDAT action

Switched to the not addressed slave mode; no

recognition of own SLA or GCA.

0

1

Switched to the not addressed slave mode; own

SLA will be recognized; GCA will be recognized if

SSGC = logic 1.

A STOP condition or

repeated START

condition has been

received while still

addressed as slave

No SSDAT action

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START condition

will be transmitted when the bus becomes free.

A0h

1

0

1

Switched to the not addressed slave mode; own

SLA will be recognized; GCA will be recognized if

SSGC = logic 1. A START condition will be

transmitted when the bus becomes free.

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Table 6. Status for Slave Receiver Mode with General Call Address

Application Software Response

Status

To SSCON

SSSTO SSI

Code Status of the TWI Bus

SSSTA and TWI Hardware

To/From SSDAT

SSSTA

SSAA Next Action Taken by TWI Hardware

General call address

has been received;

ACK has been

returned

No SSDAT action

Data Byte will be received and NOT ACK will be

returned.

X

0

1

70h

No SSDAT action

Data Byte will be received and ACK will be returned.

Arbitration lost in

SLA+R/W as master;

general call address

has been received;

ACK has been

returned

No SSDAT action

Data Byte will be received and NOT ACK will be

returned.

X

0

1

Data Byte will be received and ACK will be returned.

78h

Previously addressed Read data Byte

with general call; data

Data Byte will be received and NOT ACK will be

returned.

X

0

1

90h

has been received;

ACK has been

returned

Read data Byte

Data Byte will be received and ACK will be returned.

Read data Byte

Switched to the not addressed slave mode; no

recognition of own SLA or GCA.

0

1

Switched to the not addressed slave mode; own

SLA will be recognized; GCA will be recognized if

SSGC = logic 1.

Previously addressed

with general call; data

has been received;

NOT ACK has been

returned

Read data Byte

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START condition

will be transmitted when the bus becomes free.

98h

1

0

1

Switched to the not addressed slave mode; own

SLA will be recognized; GCA will be recognized if

SSGC = logic 1. A START condition will be

transmitted when the bus becomes free.

No SSDAT action

Switched to the not addressed slave mode; no

recognition of own SLA or GCA.

0

1

Switched to the not addressed slave mode; own

SLA will be recognized; GCA will be recognized if

SSGC = logic 1.

A STOP condition or

repeated START

condition has been

received while still

addressed as slave

No SSDAT action

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START condition

will be transmitted when the bus becomes free.

A0h

1

0

1

Switched to the not addressed slave mode; own

SLA will be recognized; GCA will be recognized if

SSGC = logic 1. A START condition will be

transmitted when the bus becomes free.

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4109H–8051–01/05

Table 7. Status for Slave Transmitter Mode

Application Software Response

To SSCON

SSSTO SSI

Status of the TWI Bus

and TWI Hardware

Status

Code

SSSTA

To/From SSDAT

SSSTA

SSAA Next Action Taken by TWI Hardware

Write data Byte

X

0

1

Last data Byte will be transmitted.

Own SLA+R has been

received; ACK has

been returned

A8h

B0h

Write data Byte

X

Data Byte will be transmitted.

Arbitration lost in

Last data Byte will be transmitted.

X

0

1

SLA+R/W as master;

own SLA+R has been

received; ACK has

been returned

Write data Byte

Data Byte will be transmitted.

Data Byte in SSDAT

has been transmitted;

ACK has been

Write data Byte

Last data Byte will be transmitted.

Data Byte will be transmitted.

X

0

1

B8h

received

No SSDAT action

Switched to the not addressed slave mode; no

recognition of own SLA or GCA.

0

1

Switched to the not addressed slave mode; own

SLA will be recognized; GCA will be recognized if

SSGC = logic 1.

Data Byte in SSDAT

has been transmitted;

NOT ACK has been

received

No SSDAT action

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START condition

will be transmitted when the bus becomes free.

C0h

1

0

1

Switched to the not addressed slave mode; own

SLA will be recognized; GCA will be recognized if

SSGC = logic 1. A START condition will be

transmitted when the bus becomes free.

No SSDAT action

Switched to the not addressed slave mode; no

recognition of own SLA or GCA.

0

1

Switched to the not addressed slave mode; own

SLA will be recognized; GCA will be recognized if

SSGC = logic 1.

Last data Byte in

SSDAT has been

transmitted

(SSAA= 0); ACK has

been received

No SSDAT action

Switched to the not addressed slave mode; no

recognition of own SLA or GCA. A START condition

will be transmitted when the bus becomes free.

C8h

1

0

1

Switched to the not addressed slave mode; own

SLA will be recognized; GCA will be recognized if

SSGC = logic 1. A START condition will be

transmitted when the bus becomes free.

Table 8. Status for Miscellaneous States

Application Software Response

Status

To SSCON

Code Status of the TWI Bus

SSSTA and TWI Hardware

To/From SSDAT

SSSTA

SSSTO

SSI

SSAA Next Action Taken by TWI Hardware

No relevant state

No SSDAT action

Wait or proceed current transfer.

F8h

00h

information available;

SSI = 0

No SSCON action

Bus error due to an

illegal START or STOP

condition

No SSDAT action

Only the internal hardware is affected, no STOP

condition is sent on the bus. In all cases, the bus is

released and SSSTO is reset.

0

1

0

X

174

AT8xC51SND1C

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AT8xC51SND1C

21.9 Registers

Table 10. SSCON Register

SSCON (S:93h) – Synchronous Serial Control Register

7

6

5

4

3

2

1

0

SSCR2

SSPE

SSSTA

SSSTO

SSI

SSAA

SSCR1

SSCR0

Bit

Number

Mnemonic Description

Synchronous Serial Control Rate Bit 2

Refer to Table 2 for rate description.

7

6

SSCR2

SSPE

Synchronous Serial Peripheral Enable Bit

Set to enable the controller.

Clear to disable the controller.

Synchronous Serial Start Flag

5

4

3

SSSTA

SSSTO

SSI

Set to send a START condition on the bus.

Clear not to send a START condition on the bus.

Synchronous Serial Stop Flag

Set to send a STOP condition on the bus.

Clear not to send a STOP condition on the bus.

Synchronous Serial Interrupt Flag

Set by hardware when a serial interrupt is requested.

Must be cleared by software to acknowledge interrupt.

Synchronous Serial Assert Acknowledge Flag

Set to enable slave modes. Slave modes are entered when SLA or GCA (if

SSGC set) is recognized.

Clear to disable slave modes.

Master Receiver Mode in progress

Clear to force a not acknowledge (high level on SDA).

Set to force an acknowledge (low level on SDA).

Master Transmitter Mode in progress

2

SSAA

This bit has no specific effect when in master transmitter mode.

Slave Receiver Mode in progress

Clear to force a not acknowledge (high level on SDA).

Set to force an acknowledge (low level on SDA).

Slave Transmitter Mode in progress

Clear to isolate slave from the bus after last data Byte transmission.

Set to enable slave mode.

Synchronous Serial Control Rate Bit 1

Refer to Table 2 for rate description.

1

0

SSCR1

SSCR0

Synchronous Serial Control Rate Bit 0

Refer to Table 2 for rate description.

Reset Value = 0000 0000b

175

4109H–8051–01/05

Table 11. SSSTA Register

SSSTA (S:94h) – Synchronous Serial Status Register

7

6

5

4

3

2

0

1

0

SSC4

SSC3

SSC2

SSC1

SSC0

Bit

Number

Mnemonic Description

Synchronous Serial Status Code Bits 0 to 4

Refer to Table 3 to Table 131 for status description.

7:3

2:0

SSC4:0

0

Always 0.

Reset Value = F8h

Table 12. SSDAT Register

SSDAT (S:95h) – Synchronous Serial Data Register

7

6

5

4

3

2

1

0

SSD7

SSD6

SSD5

SSD4

SSD3

SSD2

SSD1

SSD0

Bit

Number

Mnemonic Description

Synchronous Serial Address bits 7 to 1 or Synchronous Serial Data Bits 7

to 1

7:1

0

SSD7:1

SSD0

Synchronous Serial Address bit 0 (R/W) or Synchronous Serial Data Bit 0

Reset Value = 1111 1111b

Table 13. SSADR Register

SSADR (S:96h) – Synchronous Serial Address Register

7

6

5

4

3

2

1

0

SSA7

SSA6

SSA5

SSA4

SSA3

SSA2

SSA1

SSGC

Bit

Number

Mnemonic Description

7:1

SSA7:1

Synchronous Serial Slave Address Bits 7 to 1

Synchronous Serial General Call Bit

0

SSGC

Set to enable the general call address recognition.

Clear to disable the general call address recognition.

Reset Value = 1111 1110b

176

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AT8xC51SND1C

22. Analog to Digital

Converter

The AT8xC51SND1C implement a 2-channel 10-bit (8 true bits) analog to digital con-

verter (ADC). First channel of this ADC can be used for battery monitoring while the

second one can be used for voice sampling at 8 kHz.

22.1 Description

The A/D converter interfaces with the C51 core through four special function registers:

ADCON, the ADC control register (see Table 4); ADDH and ADDL, the ADC data regis-

ters (see Table 6 and Table 7); and ADCLK, the ADC clock register (see Table 5).

As shown in Figure 132, the ADC is composed of a 10-bit cascaded potentiometric digi-

tal to analog converter, connected to the negative input of a comparator. The output

voltage of this DAC is compared to the analog voltage stored in the Sample and Hold

and coming from AIN0 or AIN1 input depending on the channel selected (see Table 2).

The 10-bit ADDAT converted value (see formula in Figure 132) is delivered in ADDH

and ADDL registers, ADDH is giving the 8 most significant bits while ADDL is giving the

2 least significant bits. ADDAT

Figure 132. ADC Structure

ADCON.5

ADCON.3

ADEN

ADSST

ADCON.4

ADC

Interrupt

Request

ADEOC

ADC

CLOCK

CONTROL

EADC

IEN1.3

8

2

0

1

AIN1

AIN0

ADDH

ADDL

+

-

SAR

AVSS

ADCS

ADCON.0

Sample and Hold

10

R/2R DAC

1023 ⋅ V

IN

---------------------------

ADDAT =

V

REF

AREFP AREFN

Figure 133 shows the timing diagram of a complete conversion. For simplicity, the figure

depicts the waveforms in idealized form and do not provide precise timing information.

For ADC characteristics and timing parameters refer to the section “AC Characteristics”.

Figure 133. Timing Diagram

CLK

T_ADCLK

ADEN

T_SETUP

ADSST

T_CONV

ADEOC

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4109H–8051–01/05

22.1.1 Clock Generator

The ADC clock is generated by division of the peripheral clock (see details in

section “X2 Feature”, page 12). The division factor is then given by ADCP4:0 bits in

ADCLK register. Figure 134 shows the ADC clock generator and its calculation

formula⁽¹⁾.

Figure 134. ADC Clock Generator and Symbol Caution:

ADCLK

PER

CLOCK

ADC

CLOCK

÷ 2

ADCD4:0

ADC Clock

ADC Clock Symbol

PERclk

ADCclk = -------------------------

2 ⋅ ADCD

Note:

1. In all cases, the ADC clock frequency may be higher than the maximum F_ADCLK

parameter reported in the section “Analog to Digital Converter”, page 202.

2. The ADCD value of 0 is equivalent to an ADCD value of 32.

22.1.2 Channel Selection

The channel on which conversion is performed is selected by the ADCS bit in ADCON

register according to Table 2.

Table 2. ADC Channel Selection

ADCS

Channel

AIN1

0

1

AIN0

22.2.1 Conversion Precision

The 10-bit precision conversion is achieved by stopping the CPU core activity during

conversion for limiting the digital noise induced by the core. This mode called the

Pseudo-Idle mode^(1),(2)is enabled by setting the ADIDL bit in ADCON register⁽³⁾. Thus,

when conversion is launched (see Section "Conversion Launching", page 179), the

CPU core is stopped until the end of the conversion (see Section "End Of Conversion",

page 179). This bit is cleared by hardware at the end of the conversion.

Notes: 1. Only the CPU activity is frozen, peripherals are not affected by the Pseudo-Idle

mode.

2. If some interrupts occur during the Pseudo-Idle mode, they will be delayed and pro-

cessed, according to their priority after the end of the conversion.

3. Concurrently with ADSST bit.

22.2.2 Configuration

The ADC configuration consists in programming the ADC clock as detailed in the Sec-

tion "Clock Generator", page 178. The ADC is enabled using the ADEN bit in ADCON

register. As shown in Figure 93, user must wait the setup time (T_SETUP) before launching

any conversion.

178

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4109H–8051–01/05

AT8xC51SND1C

Figure 135. ADC Configuration Flow

ADC

Configuration

Program ADC Clock

ADCD4:0 = xxxxxb

Enable ADC

ADIDL = x

ADEN = 1

Wait Setup Time

22.2.3 Conversion Launching The conversion is launched by setting the ADSST bit in ADCON register, this bit

remains set during the conversion. As soon as the conversion is started, it takes 11

clock periods (T_CONV) before the data is available in ADDH and ADDL registers.

Figure 136. ADC Conversion Launching Flow

ADC

Conversion Start

Select Channel

ADCS = 0-1

Start Conversion

ADSST = 1

22.2.4 End Of Conversion

The end of conversion is signalled by the ADEOC flag in ADCON register becoming set

or by the ADSST bit in ADCON register becoming cleared. ADEOC flag can generate an

interrupt if enabled by setting EADC bit in IEN1 register. This flag is set by hardware and

must be reset by software.

179

4109H–8051–01/05

22.3 Registers

Table 4. ADCON Register

ADCON (S:F3h) – ADC Control Register

7

-

6

5

4

3

2

-

1

-

0

ADIDL

ADEN

ADEOC

ADSST

ADCS

Bit

Number

Mnemonic Description

Reserved

7

6

-

The value read from this bit is always 0. Do not set this bit.

ADC Pseudo-Idle Mode

Set to suspend the CPU core activity (pseudo-idle mode) during conversion.

Clear by hardware at the end of conversion.

ADIDL

ADEN

ADC Enable Bit

Set to enable the A to D converter.

Clear to disable the A to D converter and put it in low power stand by mode.

5

4

End Of Conversion Flag

Set by hardware when ADC result is ready to be read. This flag can generate an

interrupt.

ADEOC

Must be cleared by software.

Start and Status Bit

3

2 - 1

0

ADSST

-

Set to start an A to D conversion on the selected channel.

Cleared by hardware at the end of conversion.

Reserved

The value read from these bits is always 0. Do not set these bits.

Channel Selection Bit

Set to select channel 0 for conversion.

Clear to select channel 1 for conversion.

ADCS

Reset Value = 0000 0000b

Table 5. ADCLK Register

ADCLK (S:F2h) – ADC Clock Divider Register

7

-

6

-

5

-

4

3

2

1

0

ADCD4

ADCD3

ADCD2

ADCD1

ADCD0

Bit

Number

Mnemonic Description

Reserved

7 - 5

4 - 0

-

The value read from these bits is always 0. Do not set these bits.

ADC Clock Divider

5-bit divider for ADC clock generation.

ADCD4:0

Reset Value = 0000 0000b

180

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4109H–8051–01/05

AT8xC51SND1C

Table 6. ADDH Register

ADDH (S:F5h Read Only) – ADC Data High Byte Register

7

6

5

4

3

2

1

0

ADAT9

ADAT8

ADAT7

ADAT6

ADAT5

ADAT4

ADAT3

ADAT2

Bit

Number

Mnemonic Description

ADC Data

7 - 0

ADAT9:2

8 Most Significant Bits of the 10-bit ADC data.

Reset Value = 0000 0000b

Table 7. ADDL Register

ADDL (S:F4h Read Only) – ADC Data Low Byte Register

7

6

5

4

3

2

1

0

-

ADAT1

ADAT0

Bit

Number

Mnemonic Description

Reserved

7 - 2

1 - 0

-

The value read from these bits is always 0. Do not set these bits.

ADC Data

ADAT1:0

2 Least Significant Bits of the 10-bit ADC data.

Reset Value = 0000 0000b

181

4109H–8051–01/05

23. Keyboard

Interface

The AT8xC51SND1C implement a keyboard interface allowing the connection of a 4 x n

matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both

high or low level. These inputs are available as alternate function of P1.3:0 and allow

exit from idle and power down modes.

23.1 Description

The keyboard interfaces with the C51 core through 2 special function registers: KBCON,

the keyboard control register (see Table 3); and KBSTA, the keyboard control and sta-

tus register (see Table 4).

The keyboard inputs are considered as 4 independent interrupt sources sharing the

same interrupt vector. An interrupt enable bit (EKB in IEN1 register) allows global

enable or disable of the keyboard interrupt (see Figure 137). As detailed in Figure 138

each keyboard input has the capability to detect a programmable level according to

KINL3:0 bit value in KBCON register. Level detection is then reported in interrupt flags

KINF3:0 in KBSTA register.

A keyboard interrupt is requested each time one of the four flags is set, i.e. the input

level matches the programmed one. Each of these four flags can be masked by soft-

ware using KINM3:0 bits in KBCON register and is cleared by reading KBSTA register.

This structure allows keyboard arrangement from 1 by n to 4 by n matrix and allow

usage of KIN inputs for any other purposes.

Figure 137. Keyboard Interface Block Diagram

KIN0

KIN1

KIN2

KIN3

Input Circuitry

Keyboard Interface

Interrupt Request

EKB

IEN1.4

Figure 138. Keyboard Input Circuitry

0

1

KIN3:0

KINF3:0

KBSTA.3:0

KINM3:0

KBCON.3:0

KINL3:0

KBCON.7:4

23.1.1 Power Reduction Mode KIN3:0 inputs allow exit from idle and power-down modes as detailed in section “Power

Management”, page 48. To enable this feature, KPDE bit in KBSTA register must be set

to logic 1.

Due to the asynchronous keypad detection in power down mode (all clocks are

stopped), exit may happen on parasitic key press. In this case, no key is detected and

software must enter power down again.

182

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AT8xC51SND1C

23.2 Registers

Table 3. KBCON Register

KBCON (S:A3h) – Keyboard Control Register

7

6

5

4

3

2

1

0

KINL3

KINL2

KINL1

KINL0

KINM3

KINM2

KINM1

KINM0

Bit

Number

Mnemonic Description

Keyboard Input Level Bit

7 - 4

3 - 0

KINL3:0 Set to enable a high level detection on the respective KIN3:0 input.

Clear to enable a low level detection on the respective KIN3:0 input.

Keyboard Input Mask Bit

KINM3:0 Set to prevent the respective KINF3:0 flag from generating a keyboard interrupt.

Clear to allow the respective KINF3:0 flag to generate a keyboard interrupt.

Reset Value = 0000 1111b

Table 4. KBSTA Register

KBSTA (S:A4h) – Keyboard Control and Status Register

7

6

-

5

-

4

-

3

2

1

0

KPDE

KINF3

KINF2

KINF1

KINF0

Bit

Number

Mnemonic Description

Keyboard Power Down Enable Bit

7

KPDE

-

Set to enable exit of power down mode by the keyboard interrupt.

Clear to disable exit of power down mode by the keyboard interrupt.

Reserved

6 - 4

3 - 0

The value read from these bits is always 0. Do not set these bits.

Keyboard Input Interrupt Flag

KINF3:0 Set by hardware when the respective KIN3:0 input detects a programmed level.

Cleared when reading KBSTA.

Reset Value = 0000 0000b

183

4109H–8051–01/05

24. Electrical Characteristics

24.1 Absolute Maximum Rating

*NOTICE:

Stressing the device beyond the “Absolute Maxi-

mum Ratings” may cause permanent damage.

These are stress ratings only. Operation beyond

the “operating conditions” is not recommended

and extended exposure beyond the “Operating

Conditions” may affect device reliability.

Storage Temperature......................................... -65 to +150°C

Voltage on any other Pin to V_{SS ....................................}-0.3 to +4.0 V

I_OLper I/O Pin ................................................................. 5 mA

Power Dissipation............................................................. 1 W

Operating Conditions

Ambient Temperature Under Bias........................ -40 to +85°C

V_{DD ........................................................................................................................}4.0V

24.2 DC Characteristics

24.2.1 Digital Logic

Table 3. Digital DC Characteristics

V

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

Symbol

Parameter

Min

-0.5

Typ⁽¹⁾

Max

0.2·V_DD- 0.1

V_DD

Units

Test Conditions

V_IL

Input Low Voltage

V

(2)

V_IH1

Input High Voltage (except RST, X1)

Input High Voltage (RST, X1)

0.2·V_DD+ 1.1

0.7·V_DD

V_IH2

V_DD+ 0.5

Output Low Voltage

V_OL1

(except P0, ALE, MCMD, MDAT, MCLK,

SCLK, DCLK, DSEL, DOUT)

0.45

V

I_OL= 1.6 mA

Output Low Voltage

(P0, ALE, MCMD, MDAT, MCLK, SCLK,

DCLK, DSEL, DOUT)

V_OL2

V

I_OL= 3.2 mA

Output High Voltage

(P1, P2, P3, P4 and P5)

V_OH1

V_DD- 0.7

I_OH= -30 µA

Output High Voltage

(P0, P2 address mode, ALE, MCMD,

MDAT, MCLK, SCLK, DCLK, DSEL,

DOUT, D+, D-)

V_OH2

V

I_OH= -3.2 mA

Logical 0 Input Current (P1, P2, P3, P4

and P5)

I_IL

-50

10

µA

V_IN= 0.45 V

0.45< V_IN< V_DD

V_IN= 2.0 V

Input Leakage Current (P0, ALE, MCMD,

MDAT, MCLK, SCLK, DCLK, DSEL,

DOUT)

I_LI

Logical 1 to 0 Transition Current

(P1, P2, P3, P4 and P5)

I_TL

-650

200

R_RST

C_IO

Pull-Down Resistor

Pin Capacitance

50

90

10

kΩ

pF

V

T_A= 25°C

V_RET

V_DDData Retention Limit

1.8

184

AT8xC51SND1C

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AT8xC51SND1C

Table 3. Digital DC Characteristics

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

V

Symbol

Parameter

Min

Typ⁽¹⁾

Max

Units

Test Conditions

V_DD< 3.3 V

X1 / X2 mode

6.5 / 10.5

8 / 13.5

AT89C51SND1C

Operating Current

12 MHz

16 MHz

20 MHz

(3)

mA

9.5 / 17

V_DD< 3.3 V

X1 / X2 mode

6.5 / 10.5

8 / 13.5

AT83SND1C

Operating Current

12 MHz

16 MHz

20 MHz

I_DD

mA

9.5 / 17

V_DD< 3.3 V

X1 / X2 mode

6.5 / 10.5

8 / 13.5

AT80C51SND1C

Idle Mode Current

12 MHz

16 MHz

20 MHz

9.5 / 17

V_DD< 3.3 V

X1 / X2 mode

5.3 / 8.1

6.4 / 10.3

7.5 / 13

AT89C51SND1C

Idle Mode Current

12 MHz

16 MHz

20 MHz

(3)

V_DD< 3.3 V

X1 / X2 mode

5.3 / 8.1

6.4 / 10.3

7.5 / 13

AT83SND1C

Idle Mode Current

12 MHz

16 MHz

20 MHz

I_DL

V_DD< 3.3 V

X1 / X2 mode

5.3 / 8.1

6.4 / 10.3

7.5 / 13

AT80C51SND1C

Idle Mode Current

12 MHz

16 MHz

20 MHz

AT89C51SND1C

Power-Down Mode Current

20

500

15

µA

mA

V

_RET< V_DD< 3.3 V

AT83SND1C

Power-Down Mode Current

I_PD

AT80C51SND1C

Power-Down Mode Current

V_RET< V_DD< 3.3 V

AT89C51SND1C

Flash Programming Current

I_FP

V_DD< 3.3 V

Notes: 1. Typical values are obtained using V_DD= 3 V and T_A= 25°C. They are not tested and

there is no guarantee on these values.

2. Flash retention is guaranteed with the same formula for V_DDmin down to 0V.

3. See Table 4 for typical consumption in player mode.

Table 4. Typical Reference Design AT89C51SND1C Power Consumption

Player Mode

I_DD

Test Conditions

AT89C51SND1C at 16 MHz, X2 mode, V_DD= 3 V

No song playing

Stop

10 mA

AT89C51SND1C at 16 MHz, X2 mode, V_DD= 3 V

MP3 Song with Fs= 44.1 KHz, at any bit rates (Variable Bit Rate)

Playing

30 mA

185

4109H–8051–01/05

I_DD,I_DLand I_PDTest Conditions

Figure 139. I_DDTest Condition, Active Mode

VDD

RST

VDD

PVDD

UVDD

AVDD

I_DD

(NC)

Clock Signal

X2

X1

VDD

P0

VSS

PVSS

UVSS

AVSS

TST

VSS

All other pins are unconnected

Figure 140. I_DLTest Condition, Idle Mode

VDD

PVDD

UVDD

AVDD

I_DL

RST

VSS

(NC)

Clock Signal

X2

X1

VDD

P0

VSS

PVSS

UVSS

AVSS

TST

VSS

All other pins are unconnected

Figure 141. I_PDTest Condition, Power-Down Mode

VDD

I_PD

RST

PVDD

UVDD

AVDD

VSS

(NC)

VDD

X2

X1

P0

MCMD

MDAT

TST

VSS

PVSS

UVSS

AVSS

VSS

All other pins are unconnected

186

AT8xC51SND1C

4109H–8051–01/05

AT8xC51SND1C

24.4.1 A to D Converter

Table 5. A to D Converter DC Characteristics

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

V

Symbol

Parameter

Min

Typ

Max

Units

Test Conditions

AV_DD

Analog Supply Voltage

2.7

3.3

V

AV_DD= 3.3V

AIN1:0= 0 to AV_DD

ADEN= 1

Analog Operating Supply

Current

AI_DD

600

µA

AV_DD= 3.3V

ADEN= 0 or PD= 1

AI_PD

AV_IN

Analog Standby Current

Analog Input Voltage

2

µA

AV_SS

AV_DD

V

Reference Voltage

A_REFN

AV_REF

AV_SS

2.4

V

A_REFP

AV_DD

30

R_REF

C_IA

AREF Input Resistance

Analog Input capacitance

10

KΩ

T_A= 25°C

10

pF

24.5.1 Oscillator & Crystal

Schematic

Figure 142. Crystal Connection

X1

X2

C1

C2

Q

VSS

Note:

For operation with most standard crystals, no external components are needed on X1

and X2. It may be necessary to add external capacitors on X1 and X2 to ground in spe-

cial cases (max 10 pF). X1 and X2 may not be used to drive other circuits.

Parameters

Table 6. Oscillator & Crystal Characteristics

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

V

Symbol

C_X1

C_X2

C_L

Parameter

Internal Capacitance (X1 - VSS)

Internal Capacitance (X2 - VSS)

Equivalent Load Capacitance (X1 - X2)

Drive Level

Min

Typ

10

5

Max

Unit

pF

DL

50

20

40

6

µW

MHz

Ω

F

Crystal Frequency

RS

Crystal Series Resistance

Crystal Shunt Capacitance

CS

pF

187

4109H–8051–01/05

24.6.1 Phase Lock Loop

Schematic

Figure 143. PLL Filter Connection

FILT

R

C2

C1

VSS

Parameters

Table 7. PLL Filter Characteristics

V

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

Symbol

Parameter

Min

Typ

100

10

Max

Unit

Ω

R

Filter Resistor

C1

C2

Filter Capacitance 1

Filter Capacitance 2

nF

2.2

24.7.1 USB Connection

Schematic

Figure 144. USB Connection

To Power Supply

R_USB

VBUS

D+

D-

D+

D-

R_USB

GND

VSS

Parameters

Table 8. USB Termination Characteristics

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

V

Symbol

Parameter

USB Termination Resistor

Min

Typ

Max

Unit

R_USB

27

Ω

24.8.1 In System Programming

Schematic

Figure 145. ISP Pull-Down Connection

ISP

R_ISP

VSS

Parameters

Table 9. ISP Pull-Down Characteristics

V

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

Symbol

Parameter

ISP Pull-Down Resistor

Min

Typ

Max

Unit

R_ISP

2.2

KΩ

188

AT8xC51SND1C

4109H–8051–01/05

AT8xC51SND1C

24.10 AC Characteristics

24.10.1 External Program Bus Cycles

Definition of Symbols

Table 11. External Program Bus Cycles Timing Symbol Definitions

Signals

Address

Conditions

High

A

I

H

L

Instruction In

ALE

Low

L

P

V

X

Z

Valid

PSEN

No Longer Valid

Floating

Timings

Test conditions: capacitive load on all pins= 50 pF.

Table 12. External Program Bus Cycle - Read AC Timings

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

V

Variable Clock

Standard Mode

Variable Clock

X2 Mode

Symbol

Parameter

Min

Max

Min

Max

Unit

ns

T_CLCLClock Period

50

T_LHLLALE Pulse Width

2·T_CLCL-15

T_CLCL-15

ns

0.5·T_CLCL

20

-

T_AVLLAddress Valid to ALE Low

T_CLCL-20

ns

0.5·T_CLCL

20

-

T_LLAXAddress hold after ALE Low

T_LLIVALE Low to Valid Instruction

T_PLPHPSEN Pulse Width

T_CLCL-20

4·T_CLCL-35

3·T_CLCL-25

ns

2·T_CLCL-35

1.5·T_CLCL

25

-

1.5·T_CLCL

35

-

T_PLIVPSEN Low to Valid Instruction

T_PXIXInstruction Hold After PSEN High

T_PXIZInstruction Float After PSEN High

3·T_CLCL-35

ns

0

0.5·T_CLCL

10

-

T_CLCL-10

2.5·T_CLCL

35

T_AVIVAddress Valid to Valid Instruction

T_PLAZPSEN Low to Address Float

5·T_CLCL-35

10

ns

10

189

4109HS–8051–01/05

Waveforms

Figure 146. External Program Bus Cycle - Read Waveforms

ALE

T_LHLL

T_PLPH

T_LLPL

PSEN

T_PLIV

T_PXAV

T_PXIZ

T_PLAZ

T_AVLLT_LLAX

T_PXIX

P0

P2

D7:0

A7:0

D7:0

Instruction In

A7:0

D7:0

Instruction In

A15:8

24.12.1 External Data 8-bit Bus Cycles

Definition of Symbols

Table 13. External Data 8-bit Bus Cycles Timing Symbol Definitions

Signals

Address

Conditions

A

D

L

H

L

High

Data In

ALE

Low

V

X

Z

Valid

Q

R

W

Data Out

RD

No Longer Valid

Floating

WR

Timings

Test conditions: capacitive load on all pins= 50 pF.

Table 14. External Data 8-bit Bus Cycle - Read AC Timings

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

V

Variable Clock

Standard Mode

Variable Clock

X2 Mode

Symbol

Parameter

Min

Max

Min

Max

Unit

ns

T_CLCLClock Period

50

T_LHLLALE Pulse Width

2·T_CLCL-15

T_CLCL-20

3·T_CLCL-30

T_CLCL-15

ns

T_AVLLAddress Valid to ALE Low

T_LLAXAddress hold after ALE Low

T_LLRLALE Low to RD Low

0.5·T_CLCL-20

1.5·T_CLCL-30

ns

190

AT8xC51SND1C

4109HS–8051–01/05

AT8xC51SND1C

Variable Clock

Standard Mode

Variable Clock

X2 Mode

Symbol

Parameter

Min

Max

Min

Max

Unit

T_RLRHRD Pulse Width

6·T_CLCL-25

T_CLCL-20

3·T_CLCL-25

ns

0.5·T_CLCL+2

0

T_RHLHRD high to ALE High

T_CLCL+20

0.5·T_CLCL-20

ns

T_AVDVAddress Valid to Valid Data In

T_AVRLAddress Valid to RD Low

T_RLDVRD Low to Valid Data

9·T_CLCL-65

4.5·T_CLCL-65

ns

4·T_CLCL-30

2·T_CLCL-30

5·T_CLCL-30

0

2.5·T_CLCL-30

0

T_RLAZRD Low to Address Float

T_RHDXData Hold After RD High

T_RHDZInstruction Float After RD High

0

2·T_CLCL-25

T_CLCL-25

191

4109HS–8051–01/05

Table 15. External Data 8-bit Bus Cycle - Write AC Timings

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

V

Variable Clock

Standard Mode

Variable Clock

X2 Mode

Symbol

Parameter

Min

Max

Min

Max

Unit

ns

T_CLCLClock Period

50

T_LHLLALE Pulse Width

2·T_CLCL-15

T_CLCL-20

3·T_CLCL-30

6·T_CLCL-25

T_CLCL-15

ns

T_AVLLAddress Valid to ALE Low

T_LLAXAddress hold after ALE Low

T_LLWLALE Low to WR Low

T_WLWHWR Pulse Width

0.5·T_CLCL-20

1.5·T_CLCL-30

3·T_CLCL-25

ns

0.5·T_CLCL+2

0

T_WHLHWR High to ALE High

T_CLCL-20

T_CLCL+20

0.5·T_CLCL-20

ns

T_AVWLAddress Valid to WR Low

T_QVWHData Valid to WR High

T_WHQXData Hold after WR High

4·T_CLCL-30

7·T_CLCL-20

T_CLCL-15

2·T_CLCL-30

3.5·T_CLCL-20

0.5·T_CLCL-15

ns

Waveforms

Figure 147. External Data 8-bit Bus Cycle - Read Waveforms

ALE

T_LHLL

T_LLRL

T_RLRH

T_RHLH

RD

T_RLDV

T_RHDZ

T_RHDX

T_RLAZ

T_LLAX

T_AVLL

P0

P2

A7:0

T_AVRL

T_AVDV

D7:0

Data In

A15:8

192

AT8xC51SND1C

4109HS–8051–01/05

AT8xC51SND1C

Figure 148. External Data 8-bit Bus Cycle - Write Waveforms

ALE

T_LHLL

T_WHLH

T_LLWL

T_WLWH

WR

T_AVWL

T_LLAX

T_AVLL

T_QVWH

T_WHQX

P0

P2

A7:0

D7:0

Data Out

A15:8

24.15.1 External IDE 16-bit Bus Cycles

Definition of Symbols

Table 16. External IDE 16-bit Bus Cycles Timing Symbol Definitions

Signals

Address

Conditions

High

A

D

L

H

L

Data In

ALE

Low

V

X

Z

Valid

Q

R

W

Data Out

RD

No Longer Valid

Floating

WR

193

4109HS–8051–01/05

Timings

Test conditions: capacitive load on all pins= 50 pF.

Table 17. External IDE 16-bit Bus Cycle - Data Read AC Timings

V

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

Variable Clock

Standard Mode

Variable Clock

X2 Mode

Symbol

Parameter

Min

Max

Min

Max

Unit

ns

T_CLCLClock Period

50

T_LHLLALE Pulse Width

2·T_CLCL-15

T_CLCL-20

3·T_CLCL-30

6·T_CLCL-25

T_CLCL-15

ns

T_AVLLAddress Valid to ALE Low

T_LLAXAddress hold after ALE Low

T_LLRLALE Low to RD Low

T_RLRHRD Pulse Width

0.5·T_CLCL-20

1.5·T_CLCL-30

3·T_CLCL-25

ns

0.5·T_CLCL+2

0

T_RHLHRD high to ALE High

T_CLCL-20

T_CLCL+20

0.5·T_CLCL-20

ns

T_AVDVAddress Valid to Valid Data In

T_AVRLAddress Valid to RD Low

T_RLDVRD Low to Valid Data

9·T_CLCL-65

4.5·T_CLCL-65

ns

4·T_CLCL-30

2·T_CLCL-30

5·T_CLCL-30

0

2.5·T_CLCL-30

0

T_RLAZRD Low to Address Float

T_RHDXData Hold After RD High

T_RHDZInstruction Float After RD High

0

2·T_CLCL-25

T_CLCL-25

Table 18. External IDE 16-bit Bus Cycle - Data Write AC Timings

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

V

Variable Clock

Standard Mode

Variable Clock

X2 Mode

Symbol

Parameter

Min

Max

Min

Max

Unit

ns

T_CLCLClock Period

50

T_LHLLALE Pulse Width

2·T_CLCL-15

T_CLCL-20

3·T_CLCL-30

6·T_CLCL-25

T_CLCL-15

ns

T_AVLLAddress Valid to ALE Low

T_LLAXAddress hold after ALE Low

T_LLWLALE Low to WR Low

T_WLWHWR Pulse Width

0.5·T_CLCL-20

1.5·T_CLCL-30

3·T_CLCL-25

ns

0.5·T_CLCL+2

0

T_WHLHWR High to ALE High

T_CLCL-20

T_CLCL+20

0.5·T_CLCL-20

ns

T_AVWLAddress Valid to WR Low

T_QVWHData Valid to WR High

T_WHQXData Hold after WR High

4·T_CLCL-30

7·T_CLCL-20

T_CLCL-15

2·T_CLCL-30

3.5·T_CLCL-20

0.5·T_CLCL-15

ns

194

AT8xC51SND1C

4109HS–8051–01/05

AT8xC51SND1C

Waveforms

Figure 149. External IDE 16-bit Bus Cycle - Data Read Waveforms

ALE

T_LHLL

T_LLRL

T_RLRH

T_RHLH

RD

T_RLDV

T_RHDZ

T_RHDX

T_RLAZ

T_LLAX

T_AVLL

P0

P2

A7:0

T_AVRL

T_AVDV

D7:0

Data In

A15:8

D15:8⁽¹⁾

Data In

Note:

1. D15:8 is written in DAT16H SFR.

Figure 150. External IDE 16-bit Bus Cycle - Data Write Waveforms

ALE

T_LHLL

T_WHLH

T_LLWL

T_WLWH

WR

T_AVWL

T_LLAX

T_AVLL

T_QVWH

T_WHQX

P0

P2

A7:0

D7:0

Data Out

A15:8

D15:8⁽¹⁾

Data Out

Note:

1. D15:8 is the content of DAT16H SFR.

24.19 SPI Interface

Definition of Symbols

Table 20. SPI Interface Timing Symbol Definitions

Signals

Conditions

High

C

I

Clock

H

L

Data In

Data Out

Low

O

V

X

Z

Valid

No Longer Valid

Floating

195

4109HS–8051–01/05

Timings

Test conditions: capacitive load on all pins= 50 pF.

Table 21. SPI Interface Master AC Timing

V

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

Symbol

Parameter

Slave Mode

Min

Max

Unit

T_CHCH

Clock Period

2

T_PER

ns

T_CHCX

Clock High Time

Clock Low Time

SS Low to Clock edge

0.8

100

40

T_CLCX

T_SLCH, T_SLCL

T

_IVCL, T_IVCH

_CLIX, T_CHIX

_CLOV,T_CHOV

_CLOX, T_CHOX

_CLSH, T_CHSH

Input Data Valid to Clock Edge

Input Data Hold after Clock Edge

Output Data Valid after Clock Edge

Output Data Hold Time after Clock Edge

SS High after Clock Edge

SS Low to Output Data Valid

Output Data Hold after SS High

SS High to SS Low

ns

40

ns

40

ns

0

ns

T_SLOV

T_SHOX

T_SHSL

T_ILIH

50

ns

(1)

Input Rise Time

2

µs

ns

T_IHIL

Input Fall Time

2

T_OLOH

T_OHOL

Output Rise time

100

Output Fall Time

Master Mode

T_CHCH

Clock Period

2

T_PER

ns

T_CHCX

Clock High Time

0.8

20

T_CLCX

Clock Low Time

T_IVCL, T_IVCH

Input Data Valid to Clock Edge

Input Data Hold after Clock Edge

Output Data Valid after Clock Edge

Output Data Hold Time after Clock Edge

Input Data Rise Time

T

_CLIX, T_CHIX

_CLOV,T_CHOV

_CLOX, T_CHOX

ns

40

ns

0

ns

T_ILIH

T_IHIL

2

µs

Input Data Fall Time

µs

T_OLOH

T_OHOL

Note:

Output Data Rise time

50

ns

Output Data Fall Time

ns

1. Value of this parameter depends on software.

196

AT8xC51SND1C

4109HS–8051–01/05

AT8xC51SND1C

Waveforms

Figure 151. SPI Slave Waveforms (SSCPHA= 0)

SS

(input)

T_CLSH

T_SLCH

T_SLCL

T_CHCH

T_SHSL

T_CHSH

T_CLCH

SCK

(SSCPOL= 0)

(input)

T_CHCX

T_CLCX

T_CHCL

SCK

(SSCPOL= 1)

(input)

T_CLOX

T_CHOX

T_CLOV

T_CHOV

T_SLOV

SLAVE MSB OUT

T_SHOX

MISO

(output)

(1)

BIT 6

SLAVE LSB OUT

T_CHIX

T_CLIX

T_IVCH

T_IVCL

MOSI

(input)

MSB IN

BIT 6

LSB IN

Note:

1. Not Defined but generally the MSB of the character which has just been received.

Figure 152. SPI Slave Waveforms (SSCPHA= 1)

SS

(input)

T_SLCH

T_SLCL

T_CLSH

T_CHSH

T_CHCH

T_SHSL

T_CLCH

SCK

(SSCPOL= 0)

(input)

T_CHCX

T_CLCX

T_CHCL

SCK

(SSCPOL= 1)

(input)

T_CHOV

T_CLOV

T_CHOX

T_CLOX

T_SLOV

T_SHOX

MISO

(output)

(1)

SLAVE MSB OUT

BIT 6

SLAVE LSB OUT

T_IVCH

T_IVCL

T_CHIX

T_CLIX

MOSI

(input)

MSB IN

BIT 6

LSB IN

Note:

1. Not Defined but generally the LSB of the character which has just been received.

197

4109HS–8051–01/05

Figure 153. SPI Master Waveforms (SSCPHA= 0)

SS

(output)

T_CHCH

T_CLCH

SCK

(SSCPOL= 0)

(output)

T_CHCX

T_CLCX

T_CHCL

SCK

(SSCPOL= 1)

(output)

T_IVCH

T_CHIX

T_IVCLT_CLIX

MOSI

(input)

MSB IN

BIT 6

T_CLOV

T_CHOV

LSB IN

T_CLOX

T_CHOX

MISO

(output)

Port Data

MSB OUT

BIT 6

LSB OUT

Port Data

Note:

1. SS handled by software using general purpose port pin.

Figure 154. SPI Master Waveforms (SSCPHA= 1)

SS⁽¹⁾

(output)

T_CHCH

T_CLCH

SCK

(SSCPOL= 0)

(output)

T_CHCX

T_CLCX

T_CHCL

SCK

(SSCPOL= 1)

(output)

T_IVCH

T_CHIX

T_IVCLT_CLIX

MOSI

(input)

MSB IN

T_CLOV

BIT 6

LSB IN

T_CLOX

T_CHOX

T_CHOV

MISO

(output)

Port Data

MSB OUT

BIT 6

LSB OUT

Port Data

Note:

1. SS handled by software using general purpose port pin.

198

AT8xC51SND1C

4109HS–8051–01/05

AT8xC51SND1C

24.21.1 Two-wire Interface

Timings

Table 22. TWI Interface AC Timing

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

V

INPUT

Min

OUTPUT

Min

Symbol

T^HD; STA

TLOW

Parameter

Max

(4)

Start condition hold time

SCL low time

14·TCLCL

16·TCLCL

14·TCLCL

1 µs

4.0 µs⁽¹⁾

4.7 µs⁽¹⁾

4.0 µs⁽¹⁾

THIGH

TRC

SCL high time

SCL rise time

(2)

-

TFC

SCL fall time

0.3 µs

0.3 µs⁽³⁾

(4)

20·T^CLCL

T^RD

-

TSU; DAT1

Data set-up time

250 ns

TSU; DAT2

TSU; DAT3

THD; DAT

TSU; STA

TSU; STO

TBUF

SDA set-up time (before repeated START condition)

SDA set-up time (before STOP condition)

Data hold time

250 ns

0 ns

1 µs⁽¹⁾

(4)

8·TCLCL

8·TCLCL⁽⁴⁾- TFC

4.7 µs⁽¹⁾

(4)

Repeated START set-up time

STOP condition set-up time

Bus free time

14·TCLCL

1 µs

(4)

4.0 µs⁽¹⁾

4.7 µs⁽¹⁾

(2)

TRD

SDA rise time

-

TFD

SDA fall time

0.3 µs

0.3 µs⁽³⁾

Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of

100 kbit/s.

2. Determined by the external bus-line capacitance and the external bus-line pull-up

resistor, this must be < 1 µs.

3. Spikes on the SDA and SCL lines with a duration of less than 3·T^CLCLwill be filtered

out. Maximum capacitance on bus-lines SDA and

SCL= 400 pF.

4. T^CLCL= T_OSC= one oscillator clock period.

Waveforms

Figure 155. Two Wire Waveforms

Repeated START condition

T_su;STA

START or Repeated START condition

T_rd

START condition

STOP condition

0.7 V_DD

0.3 V_DD

SDA

SCL

(INPUT/OUTPUT)

T_su;STO

T_su;DAT3

T_buf

T_fd

T_rc

T_fc

0.7 V_DD

0.3 V_DD

(INPUT/OUTPUT)

T_high

Tsu;DAT2

T_low

T_hd;STA

T_hd;DAT

Tsu;DAT1

199

4109HS–8051–01/05

24.22.1 MMC Interface

Definition of symbols

Table 23. MMC Interface Timing Symbol Definitions

Signals

Conditions

High

C

D

O

Clock

H

L

Data In

Data Out

Low

V

X

Valid

No Longer Valid

Timings

Table 24. MMC Interface AC timings

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C, CL ≤ 100pF (10 cards)

V

Symbol

T_CHCH

Parameter

Min

50

Max

Unit

ns

Clock Period

T_CHCX

T_CLCX

T_CLCH

T_CHCL

T_DVCH

T_CHDX

T_CHOX

T_OVCH

Clock High Time

Clock Low Time

Clock Rise Time

Clock Fall Time

10

Input Data Valid to Clock High

Input Data Hold after Clock High

Output Data Hold after Clock High

Output Data Valid to Clock High

3

5

Waveforms

Figure 156. MMC Input-Output Waveforms

T_CHCH

T_CHCX

T_CLCX

MCLK

T_CHCL

T_CLCH

T_IVCH

T_CHIX

MCMD Input

MDAT Input

T_CHOX

T_OVCH

MCMD Output

MDAT Output

200

AT8xC51SND1C

4109HS–8051–01/05

AT8xC51SND1C

24.24.1 Audio Interface

Definition of symbols

Table 25. Audio Interface Timing Symbol Definitions

Signals

Conditions

High

C

O

S

Clock

H

L

Data Out

Data Select

Low

V

X

Valid

No Longer Valid

Timings

Table 26. Audio Interface AC timings

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C, CL≤ 30pF

V

Symbol

Parameter

Clock Period

Min

Max

Unit

ns

T_CHCH

325.5⁽¹⁾

T_CHCX

T_CLCX

T_CLCH

T_CHCL

T_CLSV

T_CLOV

Clock High Time

30

ns

Clock Low Time

ns

Clock Rise Time

10

ns

Clock Fall Time

ns

Clock Low to Select Valid

Clock Low to Data Valid

ns

Note:

1. 32-bit format with Fs= 48 KHz.

Waveforms

Figure 157. Audio Interface Waveforms

T_CHCH

T_CHCX

T_CLCX

DCLK

T_CHCL

T_CLCH

T_CLSV

DSEL

DDAT

Right

Left

T_CLOV

201

4109HS–8051–01/05

24.26.1 Analog to Digital Converter

Definition of symbols Table 27. Analog to Digital Converter Timing Symbol Definitions

Signals

Clock

Conditions

High

C

E

H

L

Enable (ADEN bit)

Low

Start Conversion

(ADSST bit)

S

Characteristics

Table 28. Analog to Digital Converter AC Characteristics

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

V

Symbol

Parameter

Clock Period

Min

Max

Unit

µs

T_CLCL

T_EHSH

T_SHSL

4

Start-up Time

4

µs

Conversion Time

11·T_CLCL

µs

Differential non-

linearity error⁽¹⁾⁽²⁾

DLe

ILe

1

2

LSB

Integral non-

linearity errorss⁽¹⁾⁽³⁾

OSe

Ge

Offset error⁽¹⁾⁽⁴⁾

Gain error⁽¹⁾⁽⁵⁾

4

LSB

Notes: 1. AV_DD= AV_REFP= 3.0 V, AV_SS= AV_REFN= 0 V. ADC is monotonic with no missing code.

2. The differential non-linearity is the difference between the actual step width and the

ideal step width (see Figure 159).

3. The integral non-linearity is the peak difference between the center of the actual step

and the ideal transfer curve after appropriate adjustment of gain and offset errors

(see Figure 159).

4. The offset error is the absolute difference between the straight line which fits the

actual transfer curve (after removing of gain error), and the straight line which fits the

ideal transfer curve (see Figure 159).

5. The gain error is the relative difference in percent between the straight line which fits

the actual transfer curve (after removing of offset error), and the straight line which

fits the ideal transfer curve (see Figure 159).

Waveforms

Figure 158. Analog to Digital Converter Internal Waveforms

CLK

T_CLCL

ADEN Bit

T_EHSH

ADSST Bit

T_SHSL

202

AT8xC51SND1C

4109HS–8051–01/05

AT8xC51SND1C

Figure 159. Analog to Digital Converter Characteristics

Offset Gain

Error Error

Code Out

OSe

Ge

1023

1022

1021

1020

1019

1018

Ideal Transfer curve

7

6

5

4

3

2

1

Example of an actual transfer curve

Center of a step

Integral non-linearity (ILe)

Differential non-linearity (DLe)

1 LSB

(ideal)

0

AVIN

(LSB ideal)

1

2

3

4

5

6

7

1018 1019 1020 1021 1022 1023 1024

Offset

Error OSe

24.28.1 Flash Memory

Definition of symbols

Table 29. Flash Memory Timing Symbol Definitions

Signals

Conditions

Low

S

R

B

ISP

L

RST

V

X

Valid

FBUSY flag

No Longer Valid

Timings

Table 30. Flash Memory AC Timing

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

V

Symbol

T_SVRL

Parameter

Min

Typ

Max

Unit

Input ISP Valid to RST Edge

Input ISP Hold after RST Edge

FLASH Internal Busy (Programming) Time

Number of Flash Write Cycles

Flash Data Retention Time

50

ns

T_RLSX

T_BHBL

N_FCY

T_FDR

10

ms

100K

10

Cycle

Years

203

4109HS–8051–01/05

Waveforms

Figure 160. FLASH Memory - ISP Waveforms

RST

T_SVRL

T_RLSX

ISP⁽¹⁾

Note:

1. ISP must be driven through a pull-down resistor (see Section “In System Program-

ming”, page 188).

Figure 161. FLASH Memory - Internal Busy Waveforms

FBUSY bit

T_BHBL

24.30.1 External Clock Drive and Logic Level References

Definition of symbols Table 31. External Clock Timing Symbol Definitions

Signals

Clock

Conditions

High

C

H

L

Low

X

No Longer Valid

Timings

Table 32. External Clock AC Timings

_DD= 2.7 to 3.3 V, T_A= -40 to +85°C

V

Symbol

T_CLCL

T_CHCX

T_CLCX

T_CLCH

T_CHCL

T_CR

Parameter

Min

50

10

3

Max

Unit

ns

%

Clock Period

High Time

Low Time

Rise Time

Fall Time

3

Cyclic Ratio in X2 mode

40

60

Waveforms

Figure 162. External Clock Waveform

T_CLCH

T_CHCX

V_DD- 0.5

V_IH1

T_CLCX

V_IL

0.45 V

T_CHCL

T_CLCL

204

AT8xC51SND1C

4109HS–8051–01/05

AT8xC51SND1C

Figure 163. AC Testing Input/Output Waveforms

INPUTS

OUTPUTS

V_DD- 0.5

0.7 V_DD

V_IHmin

V_ILmax

0.3 V_DD

0.45 V

Note:

1. During AC testing, all inputs are driven at V_DD-0.5 V for a logic 1 and 0.45 V for a

logic 0.

2. Timing measurements are made on all outputs at V_IHmin for a logic 1 and V_ILmax for

a logic 0.

Figure 164. Float Waveforms

V_LOAD+ 0.1 V

V_LOAD

V_OH- 0.1 V

V_OL+ 0.1 V

Timing Reference Points

V_LOAD- 0.1 V

Note:

For timing purposes, a port pin is no longer floating when a 100 mV change from load

voltage occurs and begins to float when a 100 mV change from the loading V_OH/V_OLlevel

occurs with I_OL/I_OH= 20 mA.

205

4109HS–8051–01/05

25. Ordering Information

Temperature

Range

Memory

Size

Supply

Voltage

Max

Frequency

Product

Marking

Part Number

Package⁽²⁾

TQFP80

BGA81

Dice

Packing

Tray

AT89C51SND1C-ROTIL

AT89C51SND1C-7HTIL

AT89C51SND1C-DDV

AT83SND1Cxxx⁽¹⁾-ROTIL

AT83SND1Cxxx⁽¹⁾-7HTIL

AT83SND1Cxxx-DDV

AT80C51SND1C-ROTIL

AT80C51SND1C-7HTIL

AT80C51SND1C-DDV

64K Flash

64K ROM

ROMless

3V

Industrial

40 MHz

89C51SND1C-IL

Tray

89C51SND1C-IL

Tray

-

TQFP80

BGA81

Dice

Tray

89C51SND1C-IL

-

Tray

TQFP80

BGA81

Dice

Tray

89C51SND1C-IL

-

Tray

Notes: 1. Refers to ROM code.

2. PLCC84 package only available for development board.

206

AT8xC51SND1C

4109HS–8051–01/05

AT8xC51SND1C

26. Package Information

26.1 TQFP80

207

4109H–8051–01/05

26.2 BGA81

208

AT8xC51SND1C

4109H–8051–01/05

AT8xC51SND1C

26.3 PLCC84

209

4109H–8051–01/05

27. Datasheet Change Log for AT8xC51SND1C

27.1 Changes from

4109D-10/02 to 4109E-

06/03

1. Additional information on AT83SND1C product.

2. Added BGA81 package.

3. Updated AC/DC characteristics for AT89C51SND1C product.

4. Changed the endurance of Flash to 100, 000 Write/Erase cycles.

5. Added note on Flash retention formula for V_IH1, in Section "DC Characteristics",

page 184.

27.2 Changes from

4109E-06/03 to 4109F-

01/04

1. Added AT80C51SND1C ROMless product.

2. Updated DC characteristics for AT83SND1C product.

27.3 Changes from

4109F-01/04 to 4109G-

07/04

1. UART bootloader now flagged as option in Features section.

2. Add USB connection schematic in USB section.

3. Add USB termination characteristics in DC Characteristics section.

4. Page access mode clarification in Data Memory section.

27.4 Changes from

4109G-07/04 to 4109H-

01/05

1. Clarify EA pin not present on packages but on dice.

2. Interrupt priority number clarification to match number defined by development

tools

210

AT8xC51SND1C

4109H–8051–01/05

AT8xC51SND1C

211

4109H–8051–01/05

Table of Contents

1. Features ............................................................................................. 1

2. Description ........................................................................................ 2

3. Typical Applications ......................................................................... 2

4. Block Diagram ................................................................................... 2

5. Pin Description .................................................................................. 3

5.1 Pinouts ........................................................................................................... 3

5.2 Signals............................................................................................................. 6

5.3 Internal Pin Structure.................................................................................... 11

6. Clock Controller .............................................................................. 12

6.1 Oscillator ...................................................................................................... 12

6.2 X2 Feature.................................................................................................... 12

6.3 PLL............................................................................................................... 13

6.4 Registers ....................................................................................................... 15

7. Program/Code Memory .................................................................. 17

7.1 ROMLESS Memory Architecture................................................................... 18

7.2 ROM Memory Architecture........................................................................... 19

7.3 Flash Memory Architecture .......................................................................... 19

7.4 Hardware Security System............................................................................ 21

7.5 Boot Memory Execution ............................................................................... 21

7.6 Preventing Flash Corruption......................................................................... 22

7.7 Registers ....................................................................................................... 23

7.8 Hardware Bytes............................................................................................. 24

8. Data Memory ................................................................................... 25

8.1 Internal Space .............................................................................................. 25

8.2 External Space .............................................................................................. 27

8.3 Dual Data Pointer ......................................................................................... 29

8.4 Registers ...................................................................................................... 30

9. Special Function Registers ............................................................ 32

10. Interrupt System ........................................................................... 38

10.1 Interrupt System Priorities.......................................................................... 38

10.2 External Interrupts...................................................................................... 41

10.3 Registers ..................................................................................................... 42

i

AT8xC51SND1C

11. Power Management ...................................................................... 48

11.1 Reset .......................................................................................................... 48

11.2 Reset Recommendation to Prevent Flash Corruption ................................ 49

11.3 Idle Mode.................................................................................................... 49

11.4 Power-down Mode...................................................................................... 50

11.5 Registers......................................................................................................52

12. Timers/Counters ........................................................................... 53

12.1 Timer/Counter Operations .......................................................................... 53

12.2 Timer Clock Controller................................................................................ 53

12.3 Timer 0........................................................................................................ 54

12.4 Timer 1........................................................................................................ 56

12.5 Interrupt ...................................................................................................... 57

12.6 Registers......................................................................................................58

13. Watchdog Timer ............................................................................ 61

13.1 Description.................................................................................................. 61

13.2 Watchdog Clock Controller......................................................................... 61

13.3 Watchdog Operation....................................................................................62

13.4 Registers......................................................................................................63

14. MP3 Decoder ................................................................................. 64

14.1 Decoder ...................................................................................................... 64

14.2 Audio Controls .............................................................................................66

14.3 Decoding Errors.......................................................................................... 66

14.4 Frame Information .......................................................................................67

14.5 Ancillary Data.............................................................................................. 67

14.6 Interrupt .......................................................................................................68

14.7 Registers......................................................................................................70

15. Audio Output Interface ................................................................. 75

15.1 Description.................................................................................................. 75

15.2 Clock Generator...........................................................................................76

15.3 Data Converter ........................................................................................... 76

15.4 Audio Buffer................................................................................................ 77

15.5 MP3 Buffer.................................................................................................. 78

15.6 Interrupt Request........................................................................................ 78

15.7 MP3 Song Playing ...................................................................................... 78

15.8 Voice or Sound Playing .............................................................................. 79

15.9 Registers......................................................................................................80

16. Universal Serial Bus ..................................................................... 82

16.1 Description...................................................................................................83

16.2 Configuration .............................................................................................. 86

16.3 Read/Write Data FIFO................................................................................ 88

16.4 Bulk/Interrupt Transactions......................................................................... 89

ii

4109H–8051–01/05

16.5 Control Transactions................................................................................... 93

16.6 Isochronous Transactions............................................................................94

16.7 Miscellaneous..............................................................................................96

16.8 Suspend/Resume Management ..................................................................97

16.9 USB Interrupt System................................................................................. 99

16.10 Registers..................................................................................................101

17. MultiMedia Card Controller ........................................................ 111

17.1 Card Concept............................................................................................ 111

17.2 Bus Concept ............................................................................................. 111

17.3 Description................................................................................................ 116

17.4 Clock Generator........................................................................................ 116

17.5 Command Line Controller......................................................................... 118

17.6 Data Line Controller...................................................................................120

17.7 Interrupt .....................................................................................................126

17.8 Registers....................................................................................................127

18. IDE/ATAPI Interface .................................................................... 133

18.1 Description................................................................................................ 133

18.2 Registers................................................................................................... 135

19. Serial I/O Port .............................................................................. 136

19.1 Mode Selection......................................................................................... 136

19.2 Baud Rate Generator................................................................................ 136

19.3 Synchronous Mode (Mode 0) ................................................................... 137

19.4 Asynchronous Modes (Modes 1, 2 and 3).................................................139

19.5 Multiprocessor Communication (Modes 2 and 3) ..................................... 142

19.6 Automatic Address Recognition................................................................ 142

19.7 Interrupt .....................................................................................................145

19.8 Registers....................................................................................................146

20. Synchronous Peripheral Interface ............................................ 149

20.1 Description.................................................................................................150

20.2 Interrupt .................................................................................................... 154

20.3 Configuration .............................................................................................155

20.4 Registers....................................................................................................159

21. Two-wire Interface (TWI) Controller .......................................... 161

21.1 Description................................................................................................ 161

21.2 Registers................................................................................................... 175

22. Analog to Digital Converter ....................................................... 177

22.1 Description................................................................................................ 177

22.2 Registers....................................................................................................180

23. Keyboard Interface ..................................................................... 182

iii

AT8xC51SND1C

4109H–8051–01/05

AT8xC51SND1C

23.1 Description................................................................................................ 182

23.2 Registers....................................................................................................183

24. Electrical Characteristics ........................................................... 184

24.1 Absolute Maximum Rating........................................................................ 184

24.2 DC Characteristics.................................................................................... 184

24.3 AC Characteristics.................................................................................... 189

24.4 SPI Interface............................................................................................. 195

25. Ordering Information .................................................................. 206

26. Package Information .................................................................. 207

26.1 TQFP80 .................................................................................................... 207

26.2 BGA81 ...................................................................................................... 208

26.3 PLCC84 .................................................................................................... 209

27. Datasheet Change Log for AT8xC51SND1C ............................ 210

27.1 Changes from 4109D-10/02 to 4109E-06/03............................................ 210

27.2 Changes from 4109E-06/03 to 4109F-01/04 ............................................ 210

27.3 Changes from 4109F-01/04 to 4109G-07/04............................................ 210

27.4 Changes from 4109G-07/04 to 4109H-01/05 ........................................... 210

iv

4109H–8051–01/05

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

Fax: (41) 26-426-5500

Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

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38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

Fax: (33) 4-76-58-34-80

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use

as critical components in life support devices or systems.

subsidiaries. Other terms and product names may be the trademarks of others.

Printed on recycled paper.

4109H–8051–01/05

/0M


型号：	AT89C51SND1C-7HTUL
厂家：	ATMEL
描述：	暂无描述解码器闪存微控制器和处理器外围集成电路异步传输模式 ATM 时钟
文件：	总216页 (文件大小：2734K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AT89C51SND1C-7HTUL [ATMEL]

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