AT89C51SND1A-ROTIL [ATMEL]
RISC Microcontroller, 8-Bit, FLASH, 8051 CPU, 20MHz, CMOS, PQFP80,;
| 型号： | AT89C51SND1A-ROTIL |
| 厂家： | 
ATMEL |
| 描述： | RISC Microcontroller, 8-Bit, FLASH, 8051 CPU, 20MHz, CMOS, PQFP80, 微控制器 外围集成电路 |
| 文件： | 总55页 (文件大小：516K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• MPEGI/II-Layer 3 Hardwired Decoder
– Stand-alone MP3 Decoder
– 48, 44.1, 32, 24, 22.05, 16 KHz Sampling Frequency
– Separated Digital Volume Control on Left and Right Channels (Software Control
Using 31 Steps)
– Bass, Medium, and Treble Control (31 Steps)
– Bass Boost Sound Effect
– Ancillary Data Extraction
– “CRC Error” and “MPEG Frame Synchronization” Indicators
• Programmable Audio Output for Interfacing With Common Audio DAC
– PCM Format Compatible
Single Chip
Microcontroller
with MP3
– I2S Format Compatible
• 8-bit MCU C51 Core Based (FMAX = 20 MHz)
• 2304 bytes of Internal RAM
• 64 Kbytes of Code Memory
– Flash: AT89C51SND1A, ROM: AT83C51SND1A
• 4 Kbytes of Boot Flash Memory (AT89C51SND1A)
– ISP: Download from USB or UART to any External Memory Cards
• USB Rev 1.1 Controller
– “Full Speed” Data Transmission
• Built-in PLL
Decoder and
Man Machine
Interface
– MP3 Audio Clocks
– USB Clock
• MultiMediaCard™ Interface Compatibility
• Atmel DataFlash™ SPI Interface Compatibility
• IDE/ATAPI Interface
• 2 Channels 10-bit ADC, 8 KHz (8 True Bit)
– Battery Voltage Monitoring
– Voice Recording Controlled by Software
• Up to 44 bits of General-purpose I/Os for:
– 4-bit Interrupt Keyboard Port for a 4 x n Matrix
– Smartmedia™ Software Interface
• Standard Two 16-bit Timers/Counters
• Hardware Watchdog Timer
AT8xC51SND1A
Preliminary
• Standard Full Duplex UART with Baud Rate Generator
• 2-wire Master and Slave Modes Controller
• SPI Master and Slave Modes Controller
• Power Management
– Power-on reset
– Software Programmable MCU Clock
– Idle Mode, Power-down Mode
• Operating Conditions:
– 3V, ±10%, 25 mA Typical Operating at 25°C
– Temperature Range: -40°C to +85°C
• Packages
– TQFP80, PLCC84 (Development Board)
– Dice
Description
The AT8xC51SND1A is a fully integrated stand-alone hardwired MPEGI/II-Layer 3
decoder with a C51 microcontroller core handling data flow and MP3-player control.
The AT89C51SND1A includes 64 Kbytes of Flash memory and allows In-System Pro-
gramming through an embedded 4 Kbytes of Boot Flash Memory.
Rev. 4106E–8051–03/02
1
The AT83C51SND1A includes 64 Kbytes of ROM memory.
The AT8xC51SND1A includes 2304 bytes of RAM memory.
The AT8xC51SND1A provides all necessary features for man machine interface like
timers, keyboard port, serial or parallel interface (USB, 2-wire, SPI, IDE), ADC input, I2S
output, and all external memory interface (NAND or NOR Flash, SmartMedia,
MultiMedia).
Typical Applications
•
•
•
•
MP3 Player
PDA, Camera, Mobile Phone MP3
Car Audio/Multimedia MP3
Home Audio/Multimedia MP3
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AT8xC51SND1A
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AT8xC51SND1A
Pin Description
Pinouts
Figure 1. AT8xC51SND1A 80-pin TQFP Package
ALE
ISP#
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P4.5
2
P4.4
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
3
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
VSS
4
5
6
7
P1.5
8
AT89C51SND1A-RO (Flash)
AT83C51SND1A-RO (ROM)
P1.6/SCL
P1.7/SDA
VDD
9
10
11
12
13
14
15
16
17
18
19
20
VDD
MCLK
MDAT
MCMD
RST
PVDD
FILT
PVSS
VSS
SCLK
X2
DSEL
X1
DCLK
DOUT
VSS
TST#
UVDD
UVSS
VDD
3
4106E–8051–03/02
Figure 2. AT8xC51SND1A 84-pin PLCC Package
ALE 12
ISP# 13
74 NC
73 P4.5
P1.0/KIN0 14
P1.1/KIN1 15
P1.2/KIN2 16
P1.3/KIN3 17
P1.4 18
72 P4.4
71 P2.2/A10
70 P2.3/A11
69 P2.4/A12
68 P2.5/A13
67 P2.6/A14
66 P2.7/A15
65 VSS
P1.5 19
P1.6/SCL 20
P1.7/SDA 21
VDD 22
PAVDD 23
FILT 24
PAVSS 25
VSS 26
X2 27
AT89C51SND1A-SR (Flash)
64 VDD
63 MCLK
62 MDAT
61 MCMD
60 RST
59 SCLK
58 DSEL
57 DCLK
56 DOUT
55 VSS
NC 28
X1 29
TST# 30
UVDD 31
UVSS 32
54 VDD
Signals
All AT8xC51SND1A signals are detailed by functionality in Table 1 to Table 14.
Table 1. Ports Signal Description
Signal
Name
Alternate
Function
Type
Description
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. To
avoid any parasitic current consumption, floating P0 inputs must be
P0.7:0
P1.7:0
I/O
AD7:0
polarized to VDD or VSS
.
KIN3:0
SCL
SDA
Port 1
I/O
P1 is an 8-bit bidirectional I/O port with internal pull-ups.
4
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4106E–8051–03/02
AT8xC51SND1A
Table 1. Ports Signal Description (Continued)
Signal
Name
Alternate
Function
Type
Description
Port 2
P2.7:0
I/O
A15:8
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
RXD
TXD
INT0#
INT1#
T0
Port 3
P3.7:0
I/O
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
T1
WR#
RD#
MISO
MOSI
SCK
Port 4
P4.7:0
P5.3:0
I/O
I/O
P4 is an 8-bit bidirectional I/O port with internal pull-ups.
SS#
Port 5
-
P5 is a 4-bit bidirectional I/O port with internal pull-ups.
Table 2. Clock Signal Description
Signal
Name
Alternate
Function
Type
Description
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, its output is connected to this
pin. X1 is the clock source for internal timing.
X1
I
-
Output of the on-chip inverting oscillator amplifier
X2
O
I
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, leave X2 unconnected.
-
-
PLL Low Pass Filter input
FILT receives the RC network of the PLL low pass filter.
FILT
Table 3. Timer 0 and Timer 1 Signal Description
Signal
Name
Alternate
Function
Type
Description
Timer 0 Gate Input
INT0# serves as external run control for timer 0, when selected by
GATE0 bit in TCON register.
INT0#
I
P3.2
External Interrupt 0
INT0# input sets IE0 in the TCON register. If bit IT0 in this register is
set, bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0
is set by a low level on INT0#.
Timer 1 Gate Input
INT1# serves as external run control for timer 1, when selected by
GATE1 bit in TCON register.
INT1#
I
P3.3
External Interrupt 1
INT1# input sets IE1 in the TCON register. If bit IT1 in this register is
set, bit IE1 is set by a falling edge on INT1#. If bit IT1 is cleared, bit IE1
is set by a low level on INT1#.
5
4106E–8051–03/02
Table 3. Timer 0 and Timer 1 Signal Description (Continued)
Signal
Name
Alternate
Function
Type
Description
Timer 0 External Clock Input
T0
I
When timer 0 operates as a counter, a falling edge on the T0 pin
increments the count.
P3.4
P3.5
Timer 1 External Clock Input
When timer 1 operates as a counter, a falling edge on the T1 pin
increments the count.
T1
I
Table 4. Audio Interface Signal Description
Signal
Alternate
Function
Name
DCLK
DOUT
Type
O
Description
DAC Data Bit Clock
DAC Audio Data
-
-
O
DAC Channel Select Signal
DSEL is the sample rate clock output.
DSEL
SCLK
O
O
-
-
DAC System Clock
SCLK is the oversampling clock synchronized to the digital audio data
(DOUT) and the channel selection signal (DSEL).
Table 5. USB Controller Signal Description
Signal
Name
Alternate
Function
Type
I/O
Description
USB Positive Data Upstream Port
This pin requires an external 1.5 kΩ pull-up to VDD for full speed
operation.
D+
-
-
D-
I/O
USB Negative Data Upstream Port
Table 6. MutiMediaCard Interface Signal Description
Signal
Name
Alternate
Function
Type
Description
MMC Clock output
Data or command clock transfer.
MCLK
O
-
MMC Command line
Bidirectional command channel used for card initialization and data
transfer commands. To avoid any parasitic current consumption,
MCMD
MDAT
I/O
I/O
-
unused MCMD input must be polarized to VDD or VSS
.
MMC Data line
Bidirectional data channel. To avoid any parasitic current consumption,
unused MDAT input must be polarized to VDD or VSS
-
.
6
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Table 7. UART Signal Description
Signal
Name
Alternate
Function
Type
Description
Receive Serial Data
RXD
I/O
RXD sends and receives data in serial I/O mode 0 and receives data in
serial I/O modes 1, 2 and 3.
P3.0
P3.1
Transmit Serial Data
TXD outputs the shift clock in serial I/O mode 0 and transmits data in
serial I/O modes 1, 2 and 3.
TXD
O
Table 8. SPI Controller Signal Description
Signal
Name
Alternate
Function
Type
Description
SPI Master Input Slave Output Data Line
MISO
I/O
When in master mode, MISO receives data from the slave peripheral.
When in slave mode, MISO outputs data to the master controller.
P4.0
P4.1
SPI Master Output Slave Input Data Line
When in master mode, MOSI outputs data to the slave peripheral.
When in slave mode, MOSI receives data from the master controller.
MOSI
I/O
SPI Clock Line
SCK
SS#
I/O
I
When in master mode, SCK outputs clock to the slave peripheral. When
in slave mode, SCK receives clock from the master controller.
P4.2
P4.3
SPI Slave Select Line
When in controlled slave mode, SS# enables the slave mode.
Table 9. Two-wire Controller Signal Description
Signal
Name
Alternate
Function
Type
Description
2-wire Serial Clock
When 2-wire controller is in master mode, SCL outputs the serial clock
to the slave peripherals. When 2-wire controller is in slave mode, SCL
receives clock from the master controller.
SCL
I/O
P1.6
P1.7
2-wire Serial Data
SDA is the bidirectional 2-wire data line.
SDA
I/O
Table 10. A/D Converter Signal Description
Signal
Alternate
Function
Name
AIN1:0
AREFP
Type
Description
I
I
A/D Converter Analog Inputs
Analog Positive Voltage Reference Input
-
-
Analog Negative Voltage Reference Input
This pin is internally connected to AVSS.
AREFN
I
-
7
4106E–8051–03/02
Table 11. Keypad Interface Signal Description
Signal
Name
Alternate
Function
Type
Description
Keypad Input Lines
KIN3:0
I
Holding one of these pins high or low for 24 oscillator periods triggers a
keypad interrupt.
P1.3:0
Table 12. External Access Signal Description
Signal
Name
Alternate
Function
Type
Description
Address Lines
A15:8
I/O
Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
P2.7:0
P0.7:0
Address/Data Lines
Multiplexed lower address and data lines for the external memory or the
IDE interface.
AD7:0
ALE
I/O
O
Address Latch Enable Output
ALE signals the start of an external bus cycle and indicates that valid
address information is available on lines A7:0. An external latch is used
to demultiplex the address from address/data bus.
-
-
ISP Enable Input
This signal must be held to GND through a pull-down resistor at the
falling reset to force execution of the internal bootloader.
ISP#
I/O
Read Signal
RD#
O
O
P3.7
P3.6
Read signal asserted during external data memory read operation.
Write Signal
WR#
Write signal asserted during external data memory write operation.
Table 13. System Signal Description
Signal
Name
Alternate
Function
Type
Description
Reset Input
Holding this pin high for 64 oscillator periods while the oscillator is
running resets the device. The Port pins are driven to their reset
conditions when a voltage lower than VIL is applied, whether or not the
oscillator is running.
RST
I
-
This pin has an internal pull-down resistor which allows the device to be
reset by connecting a capacitor between this pin and VDD
.
Asserting RST when the chip is in Idle mode or Power-down mode
returns the chip to normal operation.
Test Input
TST#
I
-
Test mode entry signal. This pin must be set to VDD
.
8
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Table 14. Power Signal Description
Signal
Name
Alternate
Function
Type
Description
Digital Supply Voltage
Connect these pins to +3V supply voltage.
VDD
PWR
-
-
-
-
-
-
-
-
Circuit Ground
Connect these pins to ground.
VSS
GND
PWR
GND
PWR
GND
PWR
GND
Analog Supply Voltage
Connect this pin to +3V supply voltage.
AVDD
AVSS
PVDD
PVSS
UVDD
UVSS
Analog Ground
Connect this pin to ground.
PLL Supply voltage
Connect this pin to +3V supply voltage.
PLL Circuit Ground
Connect this pin to ground.
USB Supply Voltage
Connect this pin to +3V supply voltage.
USB Ground
Connect this pin to ground.
9
4106E–8051–03/02
Internal Pin Structure
Table 15. Detailed Internal Pin Structure
Circuit(1)
Type
Pins
VDD
Input
TST#
VDD
P
Watchdog Output
Input/Output
RST
VSS
VDD
VDD
P2
VDD
P3
2 osc
periods
P1(2)
P2(3)
P3
Latch Output
P1
Input/Output
P4
N
P53:0
VSS
VDD
P0
MCMD
MDAT
P
Input/Output
N
ISP#
VSS
VDD
P
ALE
SCLK
DCLK
Output
DOUT
DSEL
MCLK
N
VSS
D+
D-
Input/Output
D+
D-
Note:
1. For information on resistors value, input/output levels, and drive capability, refer to the Section “DC Characteristics”,
page 32.
2. When the 2-wire controller is enabled, P1, P2, and P3 transistors are disabled allowing pseudo open-drain structure.
3. In Port 2, P1 transistor is continuously driven when outputting a high level bit address (A15:8).
10
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Block Diagram
Figure 3. AT8xC51SND1A Block Diagram
INT0# INT1# VDD VSS UVDD UVSS AVDD AVSS AREF AIN1:0 TXD RXD
T0
T1 SS# MISO MOSI SCK SCL SDA
3
3
3
3
4
4
4
4
1
1
3
3
Interrupt
Handler Unit
Flash
ROM
UART
and
BRG
RAM
2304 bytes
10-bit A to D
Converter
or
Timers 0/1
Watchdog
SPI/DataFlash
Controller
2-wire
Controller
64 Kbytes
Flash Boot
4 Kbytes
10-bit ADC
8-BIT INTERNAL BUS
C51 (X2 CORE)
I/O
Ports
MP3 Decoder
Unit
I2S / PCM
Audio Interface
USB
Controller
Keyboard
Interface
MMC
Interface
IDE
Clock and PLL
Unit
Interface
1
FILT
X1 X2
RST
ISP# ALE
DOUT DCLK DSEL SCLK D+ D-
MCLK
KIN3:0
P0-P5
MDAT MCMD
1 Alternate function of Port 1
3 Alternate function of Port 3
4 Alternate function of Port 4
11
4106E–8051–03/02
Application Information
Figure 4. AT8xC51SND1A Typical Application with On-board Atmel DataFlash and 2-wire LCD
LCD
Ref.
P1.0/KIN0
MMC1
MMC2
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
MCLK
MDAT
MCMD
P0.0
P0.1
P0.2
AT8xC51SND1A
P0.3
UVDD
X1
D+
D-
X2
USB PORT
UVSS
FILT
PVSS
DataFlash
Memories
Audio DAC
Figure 5. AT8xC51SND1A Typical Application with On-board Atmel DataFlash and LCD
LCD
Ref.
MMC1
MMC2
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
MCLK
MDAT
MCMD
P0.0
P0.1
P0.2
AT8xC51SND1A
UVDD
P0.3
D+
D-
X1
X2
USB PORT
UVSS
FILT
PVSS
DataFlash
Memories
Audio DAC
12
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Figure 6. AT8xC51SND1A Typical Application with On-board SSFDC Flash
LCD
Ref.
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P0.0
MMC1
MMC2
MCLK
MDAT
MCMD
P0.1
P0.2
AT8xC51SND1A
UVDD
P0.3
D+
D-
X1
X2
USB PORT
UVSS
FILT
PVSS
Audio DAC
SSFDC Memories
or SmartMedia Cards
SmartMedia
Figure 7. AT8xC51SND1A Typical Application with IDE CD-ROM Drive
LCD
Ref.
MMC1
MMC2
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P0.0
MCLK
MDAT
MCMD
P0.1
P0.2
AT8xC51SND1A
P0.3
UVDD
X1
D+
D-
X2
USB PORT
UVSS
FILT
PVSS
Audio DAC
IDE CD-ROM
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4106E–8051–03/02
Address Spaces
The AT8xC51SND1A derivatives implement four different address spaces:
•
•
•
•
Program/Code Memory
Boot Memory
Data Memory
Special Function Registers (SFRs)
Code Memory
The AT89C51SND1A and AT83C51SND1A implement 64 Kbytes of on-chip pro-
gram/code memory. The AT83C51SND1A product provides the internal program/code
memory in ROM technology while the AT89C51SND1A product provides it in Flash
technology.
The Flash memory increases ROM functionality by enabling in-circuit electrical erasure
and programming. Thanks to the internal charge pump, the high voltage needed for pro-
gramming or erasing Flash cells is generated on-chip using the standard VDD voltage.
Thus, the AT89C51SND1A can be programmed using only one voltage and allows in
application software programming commonly known as IAP. Hardware programming
mode is also available using specific programming tool.
Boot Memory
Data Memory
The AT89C51SND1A implements 4 Kbytes of on-chip boot memory provided in Flash
technology. This boot memory is delivered programmed with a standard boot loader
software allowing in system programming commonly known as ISP. It also contains
some Application Programming Interfaces routines commonly known as API allowing
user to develop his own boot loader.
The T89C51CC01 derivatives implement 2304 bytes of on-chip data RAM. This memory
is divided in two separate areas:
•
•
256 bytes of on-chip RAM memory (standard C51 memory).
2048 bytes of on-chip expanded RAM memory (ERAM accessible via MOVX
instructions).
14
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Special Function
Registers
The Special Function Registers (SFRs) of the T89C51CC01 derivatives fall into the cat-
egories detailed in Table 16 to Table 32. The relative addresses of these SFRs are
provided together with their reset values in Table 33. In this table, the bit-addressable
registers are identified by Note 1.
Table 16. C51 Core SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
ACC
B
E0h Accumulator
F0h B Register
Program Status
Word
PSW
SP
D0h
CY
AC
F0
RS1
RS0
OV
F1
P
81h Stack Pointer
Data Pointer Low
byte
DPL
82h
Data Pointer High
byte
DPH
83h
Table 17. System Management SFRs
Mnemonic Add Name
7
6
5
-
4
3
2
1
PD
0
PCON
AUXR
87h Power Control
SMOD1
SMOD0
EXT16
-
-
DPHDIS
-
GF1
XRS1
GF3
NV3
GF0
XRS0
0
IDL
AO
8Eh Auxiliary Register 0
A2h Auxiliary Register 1
FBh Version Number
-
-
M0
EXTRAM
-
AUXR1
NVERS
ENBOOT
NV5
DPS
NV0
NV7
NV6
NV4
NV2
NV1
Table 18. PLL and System Clock SFRs
Mnemonic Add Name
7
6
5
4
-
3
2
-
1
-
0
X2
CKCON
8Fh Clock Control
-
-
-
-
PLLRES
N3
PLLCON
PLLNDIV
PLLRDIV
E9h PLL Control
EEh PLL N Divider
EFh PLL R Divider
R1
-
R0
N6
R8
-
-
-
PLLEN
N1
PLOCK
N0
N5
R7
N4
R6
N2
R4
R9
R5
R3
R2
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4106E–8051–03/02
Table 19. Interrupt SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
Interrupt Enable
Control 0
IEN0
IEN1
IPH0
IPL0
IPH1
IPL1
A8h
B1h
B7h
B8h
B3h
B2h
EA
EAUD
EMP3
ES
ET1
EX1
ET0
EX0
Interrupt Enable
Control 1
-
-
-
-
-
EUSB
IPHAUD
IPLAUD
IPHUSB
IPLUSB
-
EKB
IPHS
EADC
IPHT1
ESPI
IPHX1
IPLX1
IPHSPI
IPLSPI
EI2C
IPHT0
IPLT0
EMMC
IPHX0
Interrupt Priority
Control High 0
IPHMP3
Interrupt Priority
Control Low 0
IPLMP3
IPLS
IPLT1
IPLX0
Interrupt Priority
Control High 1
-
-
IPHKB
IPLKB
IPHADC
IPLADC
IPHI2C
IPLI2C
IPHMMC
IPLMMC
Interrupt Priority
Control Low 1
Table 20. Port SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
P0
P1
P2
P3
P4
P5
80h 8-bit Port 0
90h 8-bit Port 1
A0h 8-bit Port 2
B0h 8-bit Port 3
C0h 8-bit Port 4
D8h 4-bit Port 5
-
-
-
-
Table 21. Flash Memory SFR
Mnemonic Add Name
7
6
5
4
3
2
1
0
FCON
D1h Flash Control
FPL3
FPL2
FPL1
FPL0
FPS
FMOD1
FMOD0
FBUSY
Table 22. Timer SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
Timer/Counter 0 and
1 Control
TCON
TMOD
TL0
88h
89h
8Ah
8Ch
8Bh
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer/Counter 0 and
1 Modes
GATE1
C/T1#
M11
M01
GATE0
C/T0#
M10
M00
Timer/Counter 0 Low
Byte
Timer/Counter 0
High Byte
TH0
Timer/Counter 1 Low
Byte
TL1
16
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Table 22. Timer SFRs (Continued)
Mnemonic Add Name
7
6
5
4
3
2
1
0
Timer/Counter 1
High Byte
TH1
8Dh
A6h
A7h
WatchDog Timer
Reset
WDTRST
WDTPRG
WatchDog Timer
Program
-
-
-
-
-
WTO2
WTO1
WTO0
Table 23. MP3 Decoder SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
MP3CON
MP3STA
MP3STA1
MP3DAT
MP3ANC
AAh MP3 Control
C8h MP3 Status
MPEN
MPANC
-
MPBBST
MPREQ
-
CRCEN
ERRLAY
-
MSKANC
ERRSYN
MPFREQ
MPD4
MSKREQ
ERRCRC
MPBREQ
MPD3
MSKLAY
MPFS1
-
MSKSYN
MPFS0
-
MSKCRC
MPVER
-
AFh MP3 Status 1
ACh MP3 Data
MPD7
AND7
MPD6
AND6
MPD5
AND5
MPD2
AND2
MPD1
AND1
MPD0
AND0
ADh MP3 Ancillary Data
AND4
AND3
MP3 Audio Volume
9Eh
MP3VOL
MP3VOR
MP3BAS
MP3MED
-
-
-
-
-
-
-
-
-
-
-
-
VOL4
VOR4
BAS4
MED4
VOL3
VOR3
BAS3
MED3
VOL2
VOR2
BAS2
MED2
VOL1
VOR1
BAS1
MED1
VOL0
VOR0
BAS0
MED0
Control Left
MP3 Audio Volume
9Fh
Control Right
MP3 Audio Bass
Control
B4h
MP3 Audio Medium
Control
B5h
MP3 Audio Treble
Control
MP3TRE
MP3CLK
B6h
-
-
-
-
-
-
TRE4
TRE3
TRE2
TRE1
TRE0
EBh MP3 Clock Divider
MPCD4
MPCD3
MPCD2
MPCD1
MPCD0
Table 24. Audio Interface SFRs
Mnemonic Add Name
7
6
5
4
3
JUST0
-
2
1
0
AUDCON0
AUDCON1
AUDSTA
AUDDAT
AUDCLK
9Ah Audio Control 0
9Bh Audio Control 1
9Ch Audio Status
JUST4
SRC
SREQ
AUD7
-
JUST3
DRQEN
UDRN
AUD6
-
JUST2
MSREQ
AUBUSY
AUD5
-
JUST1
MUDRN
-
POL
DUP1
-
DSIZ
DUP0
-
HLR
AUDEN
-
-
9Dh Audio Data
AUD4
AUCD4
AUD3
AUCD3
AUD2
AUCD2
AUD1
AUCD1
AUD0
AUCD0
ECh Audio Clock Divider
Table 25. USB Controller SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
USBCON
BCh USB Global Control
USBE
SUSPCLK SDRMWUP
-
UPRSM
RMWUPE
CONFG
FADDEN
17
4106E–8051–03/02
Table 25. USB Controller SFRs
Mnemonic Add Name
7
FEN
-
6
5
4
3
2
1
0
USBADDR
USBINT
C6h USB Address
UADD6
-
UADD5
WUPCPU
UADD4
EORINT
UADD3
SOFINT
UADD2
-
UADD1
-
UADD0
SPINT
BDh USB Global Interrupt
USB Global Interrupt
Enable
USBIEN
BEh
-
-
-
-
-
EWUPCPU
EEORINT
ESOFINT
-
-
ESPINT
EPNUM0
EPTYPE0
USB Endpoint
C7h
UEPNUM
UEPCONX
-
-
-
-
-
-
EPNUM1
EPTYPE1
Number
USB Endpoint X
Control
D4h
EPEN
DTGL
EPDIR
USB Endpoint X
Status
UEPSTAX
UEPRST
UEPINT
CEh
DIR
-
-
-
STALLRQ
TXRDY
STLCRC
EP3RST
EP3INT
RXSETUP
EP2RST
EP2INT
RXOUT
EP1RST
EP1INT
TXCMP
EP0RST
EP0INT
D5h USB Endpoint Reset
-
-
-
-
-
-
USB Endpoint
F8h
Interrupt
USB Endpoint
C2h
UEPIEN
-
-
-
-
EP3INTE
FDAT3
EP2INTE
FDAT2
EP1INTE
FDAT1
EP0INTE
FDAT0
Interrupt Enable
USB Endpoint X Fifo
Data
UEPDATX
UBYCTX
UFNUML
CFh
FDAT7
-
FDAT6
BYCT6
FNUM6
FDAT5
BYCT5
FNUM5
FDAT4
BYCT4
FNUM4
USB Endpoint X Byte
Counter
E2h
BYCT3
FNUM3
BYCT2
FNUM2
BYCT1
FNUM1
BYCT0
FNUM0
USB Frame Number
BAh
Low
FNUM7
USB Frame Number
UFNUMH
USBCLK
BBh
High
-
-
-
-
CRCOK
-
CRCERR
-
-
-
FNUM10
-
FNUM9
FNUM8
EAh USB Clock Divider
USBCD1
USBCD0
Table 26. MMC Controller SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
MMCON0
MMCON1
MMCON2
E4h MMC Control 0
E5h MMC Control 1
E6h MMC Control 2
DRPTR
BLEN3
MMCEN
DTPTR
BLEN2
DCR
CRPTR
BLEN1
CCR
CTPTR
BLEN0
-
MBLOCK
DATDIR
-
DFMT
DATEN
DATD1
RFMT
CRCDIS
CMDEN
FLOWC
RESPEN
DATD0
MMC Control and
Status
MMSTA
MMINT
MMMSK
DEh
-
-
CBUSY
EOCI
CRC16S
EOFI
DATFS
F2FI
CRC7S
F1FI
RESPFS
F2EI
CFLCK
F1EI
E7h MMC Interrupt
MCBI
MCBM
EORI
EORM
MMC Interrupt
Mask
DFh
EOCM
EOFM
F2FM
F1FM
F2EM
F1EM
MMCMD
MMDAT
MMCLK
DDh MMC Command
DCh MMC Data
MC7
MD7
MC6
MD6
MC5
MD5
MC4
MD4
MC3
MD3
MC2
MD2
MC1
MD1
MC0
MD0
EDh MMC Clock Divider
MMCD7
MMCD6
MMCD5
MMCD4
MMCD3
MMCD2
MMCD1
MMCD0
18
AT8xC51SND1A
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AT8xC51SND1A
Table 27. IDE Interface SFR
Mnemonic Add Name
7
6
5
4
3
2
1
0
High Order Data
Byte
DAT16H
F9h
D15
D14
D13
D12
D11
D10
D9
D8
Table 28. Serial I/O Port SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
SCON
SBUF
98h Serial Control
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
99h Serial Data Buffer
B9h Slave Address Mask
A9h Slave Address
SADEN
SADDR
BDRCON
BRL
92h Baud Rate Control
91h Baud Rate Reload
BRR
TBCK
RBCK
SPD
SRC
Table 29. SPI Controller SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
SPCON
SPSTA
SPDAT
C3h SPI Control
C4h SPI Status
C5h SPI Data
SPR2
SPIF
SPD7
SPEN
WCOL
SPD6
SSDIS
-
MSTR
MODF
SPD4
CPOL
CPHA
-
SPR1
-
SPR0
-
-
SPD5
SPD3
SPD2
SPD1
SPD0
Table 30. 2-wire Controller SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
Synchronous Serial
Control
SSCON
SSSTA
SSDAT
SSADR
93h
94h
95h
96h
SSCR2
SSPE
SSSTA
SSSTO
SSI
SSAA
SSCR1
SSCR0
Synchronous Serial
Status
SSC4
SSD7
SSA7
SSC3
SSD6
SSA6
SSC2
SSD5
SSA5
SSC1
SSD4
SSA4
SSC0
SSD3
SSA3
0
0
0
Synchronous Serial
Data
SSD2
SSA2
SSD1
SSA1
SSD0
SSGC
Synchronous Serial
Address
Table 31. Keyboard Interface SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
KBCON
KBSTA
A3h Keyboard Control
A4h Keyboard Status
KINL3
KPDE
KINL2
-
KINL1
-
KINL0
-
KINM3
KINF3
KINM2
KINF2
KINM1
KINF1
KINM0
KINF0
19
4106E–8051–03/02
Table 32. A/D Controller SFRs
Mnemonic Add Name
7
6
5
4
3
2
1
0
ADCON
ADCLK
ADDL
F3h ADC Control
-
ADIDL
ADEN
ADEOC
ADCD4
-
ADSST
ADCD3
-
-
-
ADCS
ADCD0
ADAT0
ADAT2
F2h ADC Clock Divider
F4h ADC Data Low Byte
F5h ADC Data High Byte
-
-
-
ADCD2
-
ADCD1
ADAT1
ADAT3
-
-
-
ADDH
ADAT9
ADAT8
ADAT7
ADAT6
ADAT5
ADAT4
20
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Table 33. SFR Addresses and Reset Values
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
UEPINT
0000 0000
DAT16H
XXXX XXXX
NVERS2
1000 0010
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
9Fh
97h
8Fh
87h
B1
ADCLK
0000 0000
ADCON
0000 0000
ADDL
0000 0000
ADDH
0000 0000
0000 0000
PLLCON
0000 1000
USBCLK
0000 0000
MP3CLK
0000 0000
AUDCLK
0000 0000
MMCLK
0000 0000
PLLNDIV
0000 0000
PLLRDIV
0000 0000
ACC1
0000 0000
UBYCTLX
0000 0000
MMCON0
0000 0000
MMCON1
0000 0000
MMCON2
0000 0000
MMINT
0000 0011
P51
XXXX 1111
MMDAT
1111 1111
MMCMD
1111 1111
MMSTA
0000 0000
MMMSK
1111 1111
PSW1
0000 0000
FCON3
UEPCONX
0000 0000
UEPRST
0000 0000
1111 00004
MP3STA1
0000 0001
UEPSTAX
0000 0000
UEPDATX
0000 0000
P41
1111 1111
UEPIEN
0000 0000
SPCON
0001 0100
SPSTA
0000 0000
SPDAT
XXXX XXXX
USBADDR
1000 0000
UEPNUM
0000 0000
IPL01
X000 0000
SADEN
0000 0000
UFNUML
0000 0000
UFNUMH
0000 0000
USBCON
0000 0000
USBINT
0000 0000
USBIEN
0001 0000
P31
1111 1111
IEN1
0000 0000
IPL1
0000 0000
IPH1
0000 0000
MP3BAS
0000 0000
MP3MED
0000 0000
MP3TRE
0000 0000
IPH0
X000 0000
IEN01
0000 0000
SADDR
0000 0000
MP3CON
0011 1111
MP3DAT
0000 0000
MP3ANC
0000 0000
MP3STA1
0100 0001
P21
1111 1111
AUXR1
XXXX 00X0
KBCON
0000 1111
KBSTA
0000 0000
WDTRST
0000 1000
WDTPRG
0000 1000
SCON
0000 0000
SBUF
XXXX XXXX
AUDCON0
0000 1000
AUDCON1
1011 0010
AUDSTA
1100 0000
AUDDAT
1111 1111
MP3VOL
0000 0000
MP3VOR
0000 0000
P11
1111 1111
BRL
0000 0000
BDRCON
XXX0 0000
SSCON
0000 0000
SSSTA
1111 1000
SSDAT
1111 1111
SSADR
1111 1110
TCON1
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
AUXR
X000 1101
CKCON
0000 000X5
P01
1111 1111
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
PCON
XXXX 0000
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
Reserved
Notes: 1. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable.
2. NVERS reset value depends on the silicon version.
3. FCON register is only available in AT89C51SND1A product.
4. FCON reset value is 00h in case of reset with hardware condition.
5. CKCON reset value depends on the X2B bit (programmed or unprogrammed) in the Hardware Byte.
21
4106E–8051–03/02
In-System and
In-application
Programming
As described in the section “Program/Code Memory” of the AT8xC51SND1A design
guide, The AT89C51SND1A implements a 4 Kbytes Flash boot memory. This boot
memory is delivered programmed with a standard boot loader software allowing In-Sys-
tem Programming (ISP). It also contains some Application Programming Interface
routines named API routines allowing In Application Programming (IAP) by using user’s
own boot loader.
In-System Programming The ISP boot process is divided in two different processes: the hardware and software
boot process detailed in the following sections.
Hardware Boot Process
As detailed in Figure 8 there are two hardware conditions that allow the user to execute
the boot loader: the hardware and the programmed conditions.
Hardware Condition
The hardware condition is based on the ISP# pin. When driving this pin to low level, the
chip reset forces the execution of the boot loader software.
The hardware condition takes precedence on the programmed condition and always
allows in-system recovery when the user’s memory has been corrupted.
Programmed Condition
The programmed condition is based on the Boot Loader Jump Bit (BLJB) in the hard-
ware security bytes (HSB). When this bit is programmed (by hardware or software
programming mode), the chip reset forces the execution of the boot loader software.
Software Boot Process
Whatever the physical medium may be, the boot loader software always starts execu-
tion by testing FCON to know if execution comes from hardware or programmed
condition. If it is from hardware condition, Atmel’s boot loader is executed. If it is from
programmed condition, the Software Boot Vector (SBV) is used to build a 16-bit
address, SBV content being the MSB and the LSB at 00h. If this address is valid (<
F000h), a jump occurs at this address to execute the user’s boot loader. Otherwise,
jump is performed to Atmel’s boot loader. This implies that the user’s boot loader does
not execute any code mapped from F000h to FFFFh.
22
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Figure 8. Boot Process Algorithm
RESET
Hard Cond?
ISP#= L?
Prog Cond?
BLJB= P?
Hard Cond Init
ENBOOT= 1
PC= F000h
FCON= 00h
Standard Init
ENBOOT= 0
PC= 0000h
FCON= F0h
Prog Cond Init
ENBOOT= 1
PC= F000h
FCON= F0h
Hard Cond?
FCON= 00h?
User Vector?
SBV< F0h?
User Init
PCH= SBV
PCL= 00h
User’s
User’s
Atmel’s
Application
Boot Loader
Boot Loader
23
4106E–8051–03/02
Serial Boot Loader
Configuration
The serial boot loader is based on the internal UART and needs only 3 pins: the TXD
and RXD pins of the UART and the VSS pin.
The data transmission format on the serial link must be set to 8 data bits with 1 stop bit.
The baud rate is automatically recognized during the synchronization phase.
Synchronization Phase
Before any data may be sent to the boot loader, a synchronization must be achieved
with the host so that both sides converse at the same baud rate. This is done by sending
the “U” character (ASCII 35h) to the boot loader. The boot loader acknowledges the syn-
chronization by responding the same “U” character.
At this time, the boot loader is able to receive data, then all data received are echoed to
the host.
Command Protocol
Definition
The protocol is based on the INTEL‚ HEX type records. These records are composed of
seven fields of ASCII characters as detailed in Table 34. All fields except SOR (Start Of
Record) end EOR (End Of Record) are ASCII coded hexadecimal values. The SOR field
is always a “:” character. The EOR field is always a Carriage Return (ASCII 13h) fol-
lowed by a Line Feed (ASCII 0Ah). The SIZE field is the size of the DATA field. The
ADDRESS field is the address where to store data contained in the DATA field. The
TYPE field is the record type detailed in Table 35. The DATA field contains the data and
must never exceed 128 data bytes (256 ASCII characters). The CKSUM field is the
checksum computed on the SIZE, ADDRESS, TYPE, DATA fields.
Table 34. Hex Record Format
SOR
SIZE
ADDRESS
TYPE
DATA
CKSUM
EOR
:
NN
AAAA
RR
DD…DD
CC
CR LF
Error Handling
All received records that present a checksum error, a data length greater than 128 bytes
or a bad type record are immediately acknowledged to the host by sending an “X” char-
acter followed by a CRLF sequence.
Command Description
Table 35. Hex Record Commands
TYPE
SIZE
ADDRESS
Description
Program Data
Program the data in the DATA field at the address contained in the ADDRESS field.
0000h to
FFFFh
00h
01h to 80h
Return
“.”Done.
“P”Not done. Part protected (secured by level 1 or 2).
End of File
No operation.
01h
00h
0000h
Return
“.”
24
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Table 35. Hex Record Commands (Continued)
TYPE
SIZE
ADDRESS
Description
Block Erase: DATA[0] = 01h
DATA[1] = 00h
Erase block 0 from address 0000h to 1FFFh.
DATA[1] = 20h
Erase block 1 from address 2000h to 3FFFh.
DATA[1] = 40h
Erase block 2 from address 4000h to 7FFFh.
DATA[1] = 80h
02h
XXXX
Erase block 3 from address 8000h to BFFFh.
DATA[1] = C0h
Erase block 4 from address C000h to FFFFh.
Return
“.”Done.
“P”Not done. Part protected (secured by level 1 or 2).
Reset Software Boot Vector and Boot Status Byte: DATA[0] = 04h
Set SBV to F0h and BSB to FFh.
01h
02h
XXXX
XXXX
Return
“.”Done.
“P”Not done. Part protected (secured by level 1 or 2).
Program Software Security Bits: DATA[0] = 05h
DATA[1] = 00h
Program level 1. Disable Flash programming.
DATA[1] = 01h
Program level 2. Disable Flash programming and verifying.
Return
“.”Done.
“P”Not done. Part protected (secured by level 1 or 2).
03h
Program Software Boot Vector or Boot Status Byte: DATA[0] = 06h
DATA[1] = 00h
Program BSB with DATA[2].
DATA[1] = 01h
Program SBV with DATA[2].
03h
XXXX
Return
“.”Done.
“P”Not done. Part already protected (secured by level 2).
Full Chip Erase: DATA[0] = 07h
Erase user memory from address 0000h to FFFFh.
Set SBV to F0h and BSB to FFh.
Program software security to level 0.
01h
XXXX
Return
“.”
Program Fuse bits: DATA[0] = 0Ah
DATA[1] = 04h
DATA[2] = 00h
Program BLJB bit.
DATA[2] = 01h
Erase BLJB bit.
DATA[1] = 08h
DATA[2] = 00h
03h
XXXX
Program X2 bit.
DATA[2] = 01h
Erase X2 bit.
Return
“.”Done.
“P”Not done. Part protected (secured by level 1 or 2).
25
4106E–8051–03/02
Table 35. Hex Record Commands (Continued)
TYPE
SIZE
ADDRESS
Description
Read Data: DATA[4] = 00h
Read data from address given by DATA[1:0] (start address) to address given by DATA[3:2] (end
address).
05h
XXXX
Return
“AAAA=DD…DD” up to 16 data bytes by line.
04h
Blank Check: DATA[4] = 01h
Check blanked data from address given by DATA[1:0] (start address) to address given by
DATA[3:2] (end address).
05h
XXXX
Return
“.”Done.
“XXXX”First address not blanked.
Read Id: DATA[0] = 00h
DATA[1] = 00h
Return manufacturer id.
DATA[1] = 01h
Return device id 1.
DATA[1] = 02h
02h
XXXX
Return device id 2.
DATA[1] = 03h
Return device id 3.
Return
“XX”Selected id value.
Read Special Bytes: DATA[0] = 07h
DATA[1] = 00h
Return SSB.
DATA[1] = 01h
Return BSB.
02h
XXXX
DATA[1] = 02h
Return SBV.
05h
Return
“XX”Selected byte value.
Read HSB: DATA[0] = 0Bh
Return HSB.
01h
02h
01h
XXXX
XXXX
XXXX
Return
“XX”HSB value.
Read Boot Id: DATA[0] = 0Eh
DATA[1] = 00h
Return boot id 1.
DATA[1] = 01h
Return boot id 1.
Return
“XX”Selected id value.
Read Boot Loader Version: DATA[0] = 0Fh
Return boot loader version.
Return
“XX”Boot loader version.
26
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
In-application
Programming
The IAP is based on several Application Program Interface routines (APIs) that may be
called by the user’s boot loader to allow programming of the Flash memory.
The APIs are executed by calling the API_CALL function at address FFF0h and by
passing the API routine number in R1 register. Some other parameters may also be
passed in registers as detailed in Table 36.
Table 36. API Routines and Parameters
R1
Description
PROGRAM DATA BYTE
Program data in the Flash memory at a given address.
Parameters
02h
DPTRAddress of the byte to program.
ACCData to program.
Return
None.
PROGRAM DATA PAGE
Program a page of data in the Flash memory at a given page address.
Parameters
DPTR0Address of the page to program.
DPTR1Address in ERAM of the first data to program.
ACCNumber of bytes to program limited to 128.
09h
Return
None.
PROGRAM SOFTWARE SECURITY BYTE
Program SSB.
Parameters
05h
06h
06h
DPL00hProgram level 1. Disable Flash programming.
01hProgram level 2. Disable Flash programming and verifying.
Return
None.
PROGRAM BOOT STATUS BYTE
Program BSB.
Parameters
DPL00hSelect BSB programming.
ACCData to program in BSB.
Return
None.
PROGRAM SOFTWARE BOOT VECTOR
Program SBV.
Parameters
DPL01hSelect SBV programming.
ACCData to program in SBV.
Return
None.
PROGRAM BOOT LOADER JUMP BIT
Program BLJB.
Parameters
DPL04hSelect BLJB programming.
ACC00hProgram BLJB.
01hErase BLJB.
06h
Return
None.
27
4106E–8051–03/02
Table 36. API Routines and Parameters (Continued)
R1
Description
PROGRAM X2 BIT
Program X2B.
Parameters
DPL08hSelect X2B programming.
ACC00hProgram X2B.
01hErase X2B.
06h
Return
None.
Erase BLOCK
Erase one of the 5 available blocks.
Parameters
DPH00hErase block 0 from address 0000h to 1FFFh.
20hErase block 1 from address 2000h to 3FFFh.
40hErase block 2 from address 4000h to 7FFFh.
80hErase block 3 from address 8000h to BFFFh.
01h
C0hErase block 4 from address C000h to FFFFh.
Return
None.
ERASE SOFTWARE BOOT VECTOR and BOOT STATUS BYTE
Erase SBV and BSB.
Parameters
None.
04h
03h
00h
00h
00h
Return
None.
READ DATA BYTE
Read data at a given address.
Parameters
DPTRAddress of the byte to program.
Return
ACCData read.
READ MANUFACTURER ID
Read manufacturer Id.
Parameters
DPL00hSelect manufacturer Id.
Return
ACCId value.
READ DEVICE ID 1
Read device Id 1
Parameters
DPL01hSelect device Id 1.
Return
ACCId value.
READ DEVICE ID 2
Read device Id 2.
Parameters
DPL02hSelect device Id 2.
Return
ACCId value.
28
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Table 36. API Routines and Parameters (Continued)
R1
Description
READ DEVICE ID 3
Read device Id 3.
Parameters
DPL03hSelect device Id 3.
00h
Return
ACCId value.
READ SOFTWARE SECURITY BYTE
Read SSB.
Parameters
DPL00hSelect SSB.
07h
07h
07h
0Bh
0Eh
0Eh
0Fh
Return
ACCSSB value.
READ BOOT STATUS BYTE
Read BSB.
Parameters
DPL01hSelect BSB.
Return
ACCBSB value.
READ SOFTWARE BOOT VECTOR
Read SBV.
Parameters
DPL02hSelect SBV.
Return
ACCSBV value.
READ HARDWARE SECURITY BYTE
Read HSB.
Parameters
None.
Return
ACCHSB value.
READ BOOT ID 1
Read boot Id 1.
Parameters
DPL00hSelect boot Id 1.
Return
ACCId value.
READ BOOT ID 2
Read boot Id 2.
Parameters
DPL01hSelect boot Id 2.
Return
ACCId value.
READ BOOT LOADER VERSION
Read BLV.
Parameters
None.
Return
ACCBLV value.
29
4106E–8051–03/02
Peripherals
The AT8xC51SND1A peripherals are briefly described in the following sections. For fur-
ther details on how to interface (hardware and software) to these peripherals, please
refer to the AT8xC51SND1A design guide.
Clock Generator System The AT8xC51SND1A internal clocks are extracted from an on-chip PLL fed by an on-
chip oscillator. Four clocks are generated respectively for the C51 core, the MP3
decoder, the audio interface, and the other peripherals. The C51 and peripheral clocks
are derived from the oscillator clock. The MP3 decoder clock is generated by dividing
the PLL output clock. The audio interface sample rates are also obtained by dividing the
PLL output clock.
Ports
The AT8xC51SND1A implements five 8-bit ports (P0 to P4) and one 4-bit port (P5). In
addition to performing general-purpose I/O, some ports are capable of external data
memory operations; others allow for alternate functions. All I/O Ports are bidirectional.
Each Port contains a latch, an output driver and an input buffer. Port 0 and Port 2 output
drivers and input buffers facilitate external memory operations. Some Port 1, Port 3 and
Port 4 pins serve for both general-purpose I/O and alternate functions.
Timers/Counters
The AT8xC51SND1A implements the two general-purpose, 16-bit Timers/Counters of a
standard C51. They are identified as Timer 0, Timer 1, and can independently be config-
ured each to operate in a variety of modes as a Timer or as an event Counter. When
operating as a Timer, a Timer/Counter runs for a programmed length of time, then
issues an interrupt request. When operating as a Counter, a Timer/Counter counts neg-
ative transitions on an external pin. After a preset number of counts, the Counter issues
an interrupt request.
Watchdog Timer
MP3 Decoder
The AT8xC51SND1A implements a hardware Watchdog Timer that automatically resets
the chip if it is allowed to time out. The WDT provides a means of recovering from rou-
tines that do not complete successfully due to software or hardware malfunctions.
The AT8xC51SND1A implements a MPEG I/II audio layer 3 decoder (known as MP3
decoder).
In MPEG I (ISO 11172-3) three layers of compression have been standardized support-
ing three sampling frequencies: 48, 44.1, and 32 KHz. Among these layers, layer 3
allows highest compression rate of about 12:1 while still maintaining CD audio quality.
For example, 3 minutes of CD audio (16-bit PCM, 44.1 KHz) data, which needs about 32
MBytes of storage, can be encoded into only 2.7 MBytes of MPEG I audio layer 3 data.
In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16
KHz are supported for low bit rates applications.
The AT8xC51SND1A can decode in real-time the MPEG I audio layer 3 encoded data
into a PCM audio data, and also supports MPEG II audio layer 3 additional frequencies.
Additional features are supported by the AT8xC51SND1A MP3 decoder such as vol-
ume, bass, medium, and treble controls, bass boost effect and ancillary data extraction.
Audio Output Interface
The AT8xC51SND1A implements an audio output interface allowing the decoded audio
bitstream to be output in various formats. It is compatible with right and left justification
PCM and I2S formats and the on-chip PLL (see Section ) allows connection of almost all
of the commercial audio DAC families available on the market.
Universal Serial Bus
Interface
The AT8xC51SND1A implements a full-speed Universal Serial Bus Interface. It can be
used for the following purposes:
30
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
•
•
Download of MP3 encoded audio files by supporting the USB mass storage class.
In-System Programming by supporting the USB firmware upgrade class.
MultiMediaCard Interface The AT8xC51SND1A implements a MultiMediaCard (MMC) interface compliant to the
V2.2 specification in MultiMediaCard Mode. The MMC allows storage of MP3 encoded
audio files in removable flash memory cards that can be easily plugged or removed from
the application. It can also be used for In-System Programming.
IDE/ATAPI interface
The AT8xC51SND1A provides an IDE/ATAPI interface allowing connexion of devices
such as CD-ROM reader, CompactFlash™ cards, Hard Disk Drive, etc. It consists in a
16-bit bidirectional bus part of the low-level ANSI ATA/ATAPI specification. It is provided
for mass storage interface but could be used for In-System Programming using CD-
ROM.
Serial I/O Interface
The AT8xC51SND1A implements a serial port with its own baud rate generator provid-
ing one single synchronous communication mode and three full-duplex Universal
Asynchronous Receiver Transmitter (UART) communication modes. It is provided for
the following purposes:
•
•
In-System Programming.
Remote control of the AT8xC51SND1A by a host.
Serial Peripheral
Interface
The AT8xC51SND1A implements a Serial Peripheral Interface (SPI) supporting master
and slave modes. It is provided for the following purposes:
•
•
•
Interfacing DataFlash memory for MP3 encoded audio files storage.
Remote control of the AT8xC51SND1A by a host.
In-System Programming.
Two-wire Controller
The AT8xC51SND1A implements a two-wire controller supporting the four standard
master and slave modes with multimaster capability. It is provided for the following
purposes:
•
•
•
Connection of slave devices like LCD controller, audio DAC…
Remote control of the AT8xC51SND1A by a host.
In-System Programming.
A/D Controller
The AT8xC51SND1A implements a 2-channel 10-bit (8 true bits) analog to digital con-
verter (ADC). It is provided for the following purposes:
•
•
•
Battery monitoring.
Voice recording.
Corded remote control.
Keyboard Interface
The AT8xC51SND1A implements a keyboard interface allowing connection of 4 x n
matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both
high or low level. These inputs are available as alternate function of P1.3:0 and allow
exit from idle and power down modes.
31
4106E–8051–03/02
Electrical Characterstics
Absolute Maximum Rating and Operating Conditions
*NOTICE:
Stressing the device beyond the “Absolute Maxi-
mum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond
the “operating conditions” is not recommended
and extended exposure beyond the “Operating
Conditions” may affect device reliability.
Storage Temperature......................................... -65 to +150°C
Voltage on any other Pin to VSS ......................................-0.3 to+4.0V
IOL per I/O Pin ................................................................. 5 mA
Power Dissipation............................................................. 1 W
Ambient Temperature Under Bias........................ -40 to +85°C
VDD ...........................................................................................2.7 to 3.3V
DC Characteristics
Digital Logic
Table 37. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C
Symbol Parameter
Min
Typ(1)
Max
Units Test Conditions
VIL
Input Low Voltage
-0.5
0.2·VDD - 0.1
V
Input High Voltage (except
RST)
VIH1
VIH2
0.2·VDD + 0.9
0.7·VDD
VDD
V
V
Input High Voltage (RST)
VDD + 0.5
Output Low Voltage
(except P0, ALE, MCMD,
MDAT, MCLK, SCLK, DCLK,
DSEL, DOUT)
VOL1
0.45
0.45
V
IOL = 1.6 mA
Output Low Voltage
(P0, ALE, MCMD, MDAT,
MCLK, SCLK, DCLK, DSEL,
DOUT)
VOL2
V
V
IOL = 3.2 mA
Output High Voltage
(P1, P2, P3, P4 and P5)
VOH1
VDD - 0.7
VDD - 0.7
IOH = -30 µA
Output High Voltage
(P0, P2 address mode, ALE,
VOH2 MCMD, MDAT, MCLK,
SCLK, DCLK, DSEL, DOUT,
D+, D-)
V
IOH = -3.2 mA
Logical 0 Input Current (P1,
P2, P3, P4 and P5)
IIL
-50
µA Vin = 0.45V
32
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Table 37. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C
Symbol Parameter
Input Leakage Current (P0,
Min
Typ(1)
Max
Units Test Conditions
ILI
ALE, MCMD, MDAT, MCLK,
SCLK, DCLK, DSEL, DOUT)
10
µA 0.45 < VIN < VDD
Logical 1 to 0 Transition
Current
(P1, P2, P3, P4 and P5)
ITL
-650
200
µA Vin = 2.0V
RRST Pull-Down Resistor
CIO Pin Capacitance
VRET VDD Data Retention Limit
50
90
10
kΩ
pF TA = 25°C
1.8
V
12 MHz, VDD < 3.3V
mA 16 MHz, VDD < 3.3V
20 MHz, VDD < 3.3V
IDD
Operating Current
TBD
TBD
12 MHz, VDD < 3.3V
mA 16 MHz, VDD < 3.3V
20 MHz, VDD < 3.3V
IDL
Idle Mode Current
TBD
TBD
TBD
TBD
IPD
Power-Down Current
µA VRET < VDD < 3.3V
Note:
1. Typical values are obtained using VDD = 3V and TA = 25°C. They are not tested and
there is no guarantee on these values.
Figure 9. IDD/IDL Versus XTAL Frequency; VDD = 2.7 to 3.3V
TBD
TBD
TBD
0
2
4
6
8
10
12
14
16
18
20
max Active mode (mA)
typ Active mode (mA)
max Idle mode (mA)
typ Idle mode (mA)
Frequency at XTAL (MHz)
33
4106E–8051–03/02
IDD, DL
I
and IPD Test Conditions Figure 10. IDD Test Condition, Active Mode
VDD
RST
VDD
IDD
VDD
VDD
P0
(NC)
Clock Signal
X2
X1
TST#
VSS
VSS
All other pins are unconnected
Figure 11. IDL Test Condition, Idle Mode
VDD
IDL
RST
VSS
VDD
VDD
P0
(NC)
Clock Signal
X2
X1
TST#
VSS
VSS
All other pins are unconnected
Figure 12. IPD Test Condition, Power-Down Mode
VDD
IPD
RST
VDD
VSS
VDD
P0
(NC)
X2
X1
MCMD
MDAT
TST#
VSS
VSS
All other pins are unconnected
34
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
A to D Converter
Table 38. A to D Converter DC Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C
Symbol
Parameter
Min
Typ
Max
Units Test Conditions
AVDD
Analog Supply Voltage
2.7
3.3
V
Analog Operating Supply
Current
AVDD = 3.3V
µA
AIDD
600
AIN1:0 = 0 to AVDD
AVDD = 3.3V
µA
AIPD
AVIN
Analog Standby Current
Analog Input Voltage
2
ADEN = 0 or PD = 1
AVSS
AVDD
V
Reference Voltage
AREFN
AREFP
AVREF
AVSS
2.4
V
V
AVDD
30
RREF
CIA
AREF Input Resistance
Analog Input capacitance
10
kΩ
TA = 25°C
TA = 25°C
10
pF
Oscillator and Crystal
Schematic
Figure 13. Crystal Connection
X1
X2
C1
C2
Q
VSS
Note:
For operation with most standard crystals, no external components are needed on X1
and X2. It may be necessary to add external capacitors on X1 and X2 to ground in spe-
cial cases (max 10 pF). X1 and X2 may not be used to drive other circuits.
Parameters
Table 39. Oscillator and Crystal Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C
Symbol
CX1
CX2
CL
Parameter
Min
Typ
10
10
5
Max
Unit
pF
Internal Capacitance (X1 - VSS)
Internal Capacitance (X2 - VSS)
Equivalent Load Capacitance (X1 - X2)
Drive Level
pF
pF
DL
50
20
40
6
µW
MHz
Ω
F
Crystal Frequency
RS
Crystal Series Resistance
Crystal Shunt Capacitance
CS
pF
35
4106E–8051–03/02
Phase Lock Loop
Schematic
Figure 14. PLL Filter Connection
PFILT
R
C2
C1
VSS
VSS
Parameters
Table 40. PLL Filter Characteristics
VDD = 2.7 to 3.3V , TA = -40° to +85°C
Symbol
Parameter
Min
Typ
100
10
Max
Unit
Ω
R
Filter Resistor
C1
C2
Filter Capacitance 1
Filter Capacitance 2
nF
nF
2.2
In-System Programming
Schematic
Figure 15. ISP Pull-down Connection
ISP#
RISP
VSS
Parameters
Table 41. ISP Pull-Down Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C
Symbol
Parameter
Min
Typ
Max
Unit
RISP
ISP Pull-Down Resistor
2.2
kΩ
36
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
AC Characteristics
External 8-bit Bus Cycles
Definition of Symbols
Table 42. External 8-bit Bus Cycles Timing Symbol Definitions
Signals
Address
Conditions
High
A
D
L
H
L
Data In
ALE
Low
V
X
Z
Valid
Q
R
W
Data Out
RD#
No Longer Valid
Floating
WR#
Timings
Test conditions: capacitive load on all pins = 50 pF.
Table 43. External 8-bit Bus Cycle – Data Read AC Timings
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol Parameter
Min
Max
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLCL Clock Period
50
50
TLHLL
TAVLL
TLLAX
TLLRL
ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
TCLCL-15
Address Valid to ALE Low
Address hold after ALE Low
ALE Low to RD# Low
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
TRLRH RD# Pulse Width
TRHLH RD# high to ALE High
TAVDV Address Valid to Valid Data In
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20
9·TCLCL-65
4.5·TCLCL-65
TAVRL
Address Valid to RD# Low
4·TCLCL-30
2·TCLCL-30
TRLDV RD# Low to Valid Data
TRLAZ RD# Low to Address Float
TRHDX Data Hold After RD# High
5·TCLCL-30
2.5·TCLCL-30
0
0
0
0
Instruction Float After RD#
TRHDZ
High
2·TCLCL-25
TCLCL-25
ns
37
4106E–8051–03/02
Table 44. External 8-bit Bus Cycle – Data Write AC Timings
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol Parameter
Min
50
Max
Min
Max
Unit
ns
TCLCL
TLHLL
TAVLL
Clock Period
50
ALE Pulse Width
Address Valid to ALE Low
2·TCLCL-15
TCLCL-20
TCLCL-15
0.5·TCLCL-20
ns
ns
Address hold after ALE
Low
TLLAX
TLLWL
TCLCL-20
0.5·TCLCL-20
ns
ALE Low to WR# Low
3·TCLCL-30
6·TCLCL-25
TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
ns
ns
ns
TWLWH WR# Pulse Width
TWHLH WR# High to ALE High
TCLCL+20
0.5·TCLCL-20
0.5·TCLCL+20
Address Valid to WR#
TAVWL
Low
4·TCLCL-30
2·TCLCL-30
ns
TQVWH Data Valid to WR# High
TWHQX Data Hold after WR# High
7·TCLCL-20
3.5·TCLCL-20
0.5·TCLCL-15
ns
ns
TCLCL-15
Waveforms
Figure 16. External 8-bit Bus Cycle – Data Read Waveforms
ALE
TLHLL
TLLRL
TRLRH
TRHLH
RD#
TRLDV
TRHDZ
TRHDX
TRLAZ
TLLAX
TAVLL
P0
P2
A7:0
TAVRL
TAVDV
D7:0
Data In
A15:8
38
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Figure 17. External 8-bit Bus Cycle – Data Write Waveforms
ALE
TLHLL
TWHLH
TLLWL
TWLWH
WR#
TAVWL
TLLAX
A7:0
TAVLL
TQVWH
TWHQX
P0
P2
D7:0
Data Out
A15:8
External IDE 16-bit Bus Cycles
Definition of Symbols
Table 45. External IDE 16-bit Bus Cycles Timing Symbol Definitions
Signals
Address
Conditions
A
D
L
H
L
High
Data In
ALE
Low
V
X
Z
Valid
Q
R
W
Data Out
RD#
No Longer Valid
Floating
WR#
Timings
Test conditions: capacitive load on all pins = 50 pF.
39
4106E–8051–03/02
Table 46. External IDE 16-bit Bus Cycle – Data Read AC Timings
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol Parameter
Min
Max
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
TCLCL-15
TAVLL Address Valid to ALE Low
TLLAX Address hold after ALE Low
TLLRL ALE Low to RD# Low
TRLRH RD# Pulse Width
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
TRHLH RD# high to ALE High
TAVDV Address Valid to Valid Data In
TAVRL Address Valid to RD# Low
TRLDV RD# Low to Valid Data
TRLAZ RD# Low to Address Float
TRHDX Data Hold After RD# High
TCLCL+20
0.5·TCLCL-20
0.5·TCLCL+20
4.5·TCLCL-65
9·TCLCL-65
4·TCLCL-30
2·TCLCL-30
5·TCLCL-30
2.5·TCLCL-30
0
0
0
0
Instruction Float After RD#
TRHDZ
High
2·TCLCL-25
TCLCL-25
ns
Table 47. External IDE 16-bit Bus Cycle – Data Write AC Timings
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol Parameter
Min
Max
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
4·TCLCL-30
7·TCLCL-20
TCLCL-15
TCLCL-15
TAVLL Address Valid to ALE Low
TLLAX Address hold after ALE Low
TLLWL ALE Low to WR# Low
TWLWH WR# Pulse Width
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
TWHLH WR# High to ALE High
TAVWL Address Valid to WR# Low
TQVWH Data Valid to WR# High
TWHQX Data Hold after WR# High
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20
2·TCLCL-30
3.5·TCLCL-20
0.5·TCLCL-15
40
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Waveforms
Figure 18. External IDE 16-bit Bus Cycle – Data Read Waveforms
ALE
TLHLL
TLLRL
TRLRH
TRHLH
RD#
TRLDV
TRHDZ
TRHDX
TRLAZ
TLLAX
TAVLL
P0
P2
A7:0
TAVRL
TAVDV
D7:0
Data In
A15:8
D15:81
Data In
Note:
D15:8 is written in DAT16H SFR.
Figure 19. External IDE 16-bit Bus Cycle – Data Write Waveforms
ALE
TLHLL
TWHLH
TLLWL
TWLWH
WR#
TAVWL
TLLAX
A7:0
TAVLL
TQVWH
TWHQX
P0
P2
D7:0
Data Out
A15:8
D15:81
Data Out
Note:
D15:8 is the content of DAT16H SFR.
SPI Interface
Definition of Symbols
Table 48. SPI Interface Timing Symbol Definitions
Signals
Conditions
High
C
I
Clock
H
L
Data In
Data Out
Low
O
V
X
Z
Valid
No Longer Valid
Floating
41
4106E–8051–03/02
Timings
Test conditions: capacitive load on all pins = 100 pF
Table 49. SPI Interface Master AC Timing
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Symbol
Parameter
Min
Max
Unit
Slave mode
TCHCH
Clock Period
8
TOSC
TOSC
TOSC
ns
TCHCX
Clock High Time
Clock Low Time
SS# Low to Clock edge
3.2
3.2
200
100
100
TCLCX
TSLCH, TSLCL
TIVCL, TIVCH
TCLIX, TCHIX
TCLOV, TCHOV
TCLOX, TCHOX
TCLSH, TCHSH
TIVCL, TIVCH
TCLIX, TCHIX
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
SS# High after Clock Edge
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
SS# Low to Output Data Valid
Output Data Hold after SS# High
SS# High to SS# Low
ns
ns
100
ns
0
ns
0
ns
100
100
ns
ns
TSLOV
TSHOX
TSHSL
TILIH
130
130
ns
ns
(1)
Input Rise Time
2
µs
µs
ns
ns
TIHIL
Input Fall Time
2
TOLOH
TOHOL
Output Rise time
100
100
Output Fall Time
Master mode
TCHCH
Clock Period
4
TOSC
TOSC
TOSC
ns
TCHCX
Clock High Time
1.6
1.6
50
50
TCLCX
Clock Low Time
TIVCL, TIVCH
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
Input Data Rise Time
TCLIX, TCHIX
TCLOV, TCHOV
TCLOX, TCHOX
ns
65
ns
0
ns
TILIH
TIHIL
2
2
µs
Input Data Fall Time
µs
TOLOH
TOHOL
Note:
Output Data Rise time
50
50
ns
Output Data Fall Time
ns
1. Value of this parameter depends on software.
42
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Waveforms
Figure 20. SPI Slave Waveforms (SSCPHA = 0)
SS#
(input)
TCLSH
TCHSH
TSLCH
TSLCL
TCHCH
TSHSL
TCLCH
SCK
(SSCPOL = 0)
(input)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL = 1)
(input)
TCLOX
TCHOX
TCLOV
TCHOV
TSLOV
SLAVE MSB OUT
TSHOX
MISO
(output)
BIT 6
SLAVE LSB OUT
1
TCHIX
TCLIX
TIVCH
TIVCL
MOSI
(input)
MSB IN
BIT 6
LSB IN
Note:
Not Defined but generally the MSB of the character which has just been received.
Figure 21. SPI Slave Waveforms (SSCPHA = 1)
SS#1
(output)
TCHCH
TCLCH
SCK
(SSCPOL = 0)
(output)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL = 1)
(output)
TIVCH
TCHIX
TIVCL TCLIX
SI
(input)
MSB IN
BIT 6
TCLOV
TCHOV
LSB IN
TCLOX
TCHOX
SO
(output)
Port Data
MSB OUT
BIT 6
LSB OUT
Port Data
Note:
Not Defined but generally the LSB of the character which has just been received.
43
4106E–8051–03/02
Figure 22. SPI Master Waveforms (SSCPHA = 0)
SS#1
(input)
TSLCH
TSLCL
TCLSH
TCHSH
TCHCH
TSHSL
TCLCH
SCK
(SSCPOL = 0)
(input)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL = 1)
(input)
TCHOV
TCLOV
TCHOX
TCLOX
TSLOV
SLAVE MSB OUT
TSHOX
MISO
(output)
BIT 6
SLAVE LSB OUT
1
TIVCH
TIVCL
TCHIX
TCLIX
MOSI
(input)
MSB IN
BIT 6
LSB IN
Note:
SS# handled by software using general purpose port pin.
Figure 23. SPI Master Waveforms (SSCPHA = 1)
SS#1
(output)
TCHCH
TCLCH
SCK
(SSCPOL = 0)
(output)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL = 1)
(output)
TIVCH
TCHIX
TIVCL TCLIX
SI
(input)
MSB IN
TCLOV
BIT 6
TCLOX
TCHOX
BIT 6
LSB IN
TCHOV
SO
(output)
Port Data
MSB OUT
LSB OUT
Port Data
Note:
SS# handled by software using general purpose port pin.
44
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Two-wire Interface
Timings
Table 50. Two-wire Interface AC Timing
VDD = 2.7 to 3.3V, TA = -40° to +85°C
INPUT
M in
OUTPUT
Min
Symbol
THD; STA
TLOW
Parameter
Max
Max
(4)
(4)
(4)
Start condition hold time
SCL low time
14·TCLCL
16·TCLCL
14·TCLCL
1 µs
4.0 µs(1)
4.7 µs(1)
4.0 µs(1)
THIGH
SCL high time
(2)
TRC
SCL rise time
-
TFC
SCL fall time
0.3 µs
0.3 µs(3)
20·TCLCL(4)- TRD
1 µs(1)
TSU; DAT1
TSU; DAT2
TSU; DAT3
THD; DAT
TSU; STA
TSU; STO
TBUF
Data set-up time
250 ns
250 ns
250 ns
0 ns
SDA set-up time (before repeated START condition)
SDA set-up time (before STOP condition)
Data hold time
(4)
8·TCLCL
8·TCLCL(4) - TFC
4.7 µs(1)
(4)
Repeated START set-up time
STOP condition set-up time
Bus free time
14·TCLCL
14·TCLCL
14·TCLCL
1 µs
(4)
(4)
4.0 µs(1)
4.7 µs(1)
(2)
TRD
SDA rise time
-
TFD
SDA fall time
0.3 µs
0.3 µs(3)
Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of
100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up
resistor, this must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered
out. Maximum capacitance on bus-lines SDA and
SCL = 400 pF.
4. TCLCL = TOSC = one oscillator clock period.
Waveforms
Figure 24. Two-wire Waveforms
Repeated START condition
START or Repeated START condition
START condition
Tsu;STA
STOP condition
Trd
0.7 VDD
0.3 VDD
SDA
(INPUT/OUTPUT)
Tsu;STO
Tbuf
Tfd
Tsu;DAT3
Trc
Tfc
0.7 VDD
0.3 VDD
SCL
(INPUT/OUTPUT)
Thigh
Tsu;DAT2
Tlow
Thd;STA
Thd;DAT
Tsu;DAT1
45
4106E–8051–03/02
MMC Interface
Definition of Symbols
Table 51. MMC Interface Timing Symbol Definitions
Signals
Conditions
High
C
D
O
Clock
H
L
Data In
Data Out
Low
V
X
Valid
No Longer Valid
Timings
Table 52. MMC Interface AC timings
VDD = 2.7 to 3.3V, TA = 0 to 70°C, CL ≤ 100pF (10 cards)
Symbol
TCHCH
Parameter
Min
50
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Period
TCHCX
TCLCX
TCLCH
TCHCL
TDVCH
TCHDX
TCHOX
TOVCH
Clock High Time
10
Clock Low Time
10
Clock Rise Time
10
10
Clock Fall Time
Input Data Valid to Clock High
Input Data Hold after Clock High
Output Data Hold after Clock High
Output Data Valid to Clock High
3
3
5
5
Waveforms
Figure 25. MMC Input-Output Waveforms
TCHCH
TCHCX
TCLCX
MCLK
TCHCL
TCLCH
TIVCH
TCHIX
MCMD Input
MDAT Input
TCHOX
TOVCH
MCMD Output
MDAT Output
46
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Audio Interface
Definition of Symbols
Table 53. Audio Interface Timing Symbol Definitions
Signals
Conditions
High
C
O
S
Clock
H
L
Data Out
Data Select
Low
V
X
Valid
No Longer Valid
Timings
Table 54. Audio Interface AC timings
VDD = 2.7 to 3.3V, TA = 0 to 70°C, CL ≤ 30pF
Symbol
TCHCH
TCHCX
TCLCX
TCLCH
TCHCL
TCLSV
Parameter
Min
Max
Unit
ns
Clock Period
325.5(1)
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
Clock Low to Select Valid
30
30
ns
ns
10
10
10
10
ns
ns
ns
TCLOV
Note:
Clock Low to Data Valid
ns
32-bit format with Fs = 48 KHz.
Waveforms
Figure 26. Audio Interface Waveforms
TCHCH
TCHCX
TCLCX
DCLK
TCHCL
TCLCH
TCLSV
DSEL
DDAT
Right
Left
TCLOV
47
4106E–8051–03/02
Analog to Digital Converter
Definition of Symbols
Table 55. Analog to Digital Converter Timing Symbol Definitions
Signals
Conditions
High
C
E
Clock
H
L
Enable (ADEN bit)
Low
Start Conversion
(ADSST bit)
S
Characteristics
Table 56. Analog to Digital Converter AC Characteristics
VDD = 2.7 to 3.3V, TA = 0 to 70°C
Symbol
TCLCL
Parameter
Min
Max
Unit
µs
Clock Period
Start-up Time
Conversion Time
1.43
TEHSH
TSHSL
4
µs
11·TCLCL
µs
Differential non-
linearity error1, 2
DLe
TBD
TBD
LSB
LSB
Integral non-
linearity error1, 3
ILe
OSe
Offset error1, 4
Gain error1, 5
TBD
TBD
LSB
%
Ge
Note:
1. AVDD = AVREFP = 3.0 V, AVSS = AVREFN = 0 V. ADC is monotonic with no missing code.
2. The differential non-linearity is the difference between the actual step width and the
ideal step width (see Figure 28).
3. The integral non-linearity is the peak difference between the center of the actual step
and the ideal transfer curve after appropriate adjustment of gain and offset errors
(see Figure 28).
4. The offset error is the absolute difference between the straight line which fits the
actual transfer curve (after removing of gain error), and the straight line which fits the
ideal transfer curve (see Figure 28).
5. The gain error is the relative difference in percent between the straight line which fits
the actual transfer curve (after removing of offset error), and the straight line which
fits the ideal transfer curve (see Figure 28).
Waveforms
Figure 27. Analog to Digital Converter Internal Waveforms
CLK
TCLCL
ADEN Bit
TEHSH
ADSST Bit
TSHSL
48
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Figure 28. Analog to Digital Converter Characteristics
Offset Gain
Error Error
Code Out
OSe
Ge
1023
1022
1021
1020
1019
1018
Ideal Transfer curve
7
6
5
4
Example of an actual transfer curve
Center of a step
Integral non-linearity (ILe)
3
2
1
Differential non-linearity (DLe)
1 LSB
(ideal)
0
0
AVIN (LSBideal)
1
2
3
4
5
6
7
1018 1019 1020 1021 1022 1023 1024
Offset
Error
OSe
Flash Memory
Definition of Symbols
Table 57. Flash Memory Timing Symbol Definitions
Signals
Conditions
S
R
B
ISP#
L
Low
RST
V
X
Valid
FBUSY flag
No Longer Valid
Timings
Table 58. Flash Memory AC Timing
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Symbol
TSVRL
Parameter
Min
Typ
Max
Unit
Input ISP# Valid to RST Edge
Input ISP# Hold after RST Edge
Flash Internal Busy (Programming) Time
50
50
ns
ns
TRLSX
TBHBL
10
ms
49
4106E–8051–03/02
Waveforms
Figure 29. Flash Memory – ISP Waveforms
RST
TSVRL
TRLSX
ISP#1
Note:
ISP# must be driven through a pull-down resistor (see Section “In-System Program-
ming”, page 36).
Figure 30. Flash Memory – Internal Busy Waveforms
FBUSY bit
TBHBL
External Clock Drive and Logic Level References
Definition of Symbols Table 59. External Clock Timing Symbol Definitions
Signals
Clock
Conditions
High
C
H
L
Low
X
No Longer Valid
Timings
Table 60. External Clock AC Timings
VDD = 2.7 to 3.3V, TA= 0 to 70°C
Symbol
TCLCL
Parameter
Min
50
10
10
3
Max
Unit
ns
ns
ns
ns
ns
%
Clock Period
High Time
TCHCX
TCLCX
TCLCH
TCHCL
TCR
Low Time
Rise Time
Fall Time
3
Cyclic Ratio in X2 mode
40
60
Waveforms
Figure 31. External Clock Waveform
TCLCH
TCHCX
VDD - 0.5
VIH1
TCLCX
VIL
0.45 V
TCHCL
TCLCL
50
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Figure 32. AC Testing Input/Output Waveforms
INPUTS
OUTPUTS
VIH min
VIL max
VDD - 0.5
0.7 VDD
0.3 VDD
0.45 V
Note:
1. During AC testing, all inputs are driven at VDD -0.5V for a logic 1 and 0.45V for a logic 0.
2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0.
Figure 33. Float Waveforms
V
LOAD + 0.1 V
VOH - 0.1 V
VOL + 0.1 V
Timing Reference Points
VLOAD
VLOAD - 0.1 V
Note:
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a
100 mV change from the loading VOH/VOL level occurs with IOL/IOH = ±20 mA.
51
4106E–8051–03/02
Ordering Information
Table 61. Ordering Information
Temperature
Range
Supply
Voltage
Part Number
Memory Size
Max Frequency
40 MHz
Package
TQFP80
TQFP80
Packing
Tray
AT89C51SND1A-ROTIL
AT83SND1Axxx(1)-ROTIL
64K Flash
3V
3V
Industrial
Industrial
64K ROM
40 MHz
Tray
Note:
(1)Refers to ROM code.
PLCC84 package only available for development board.
52
AT8xC51SND1A
4106E–8051–03/02
AT8xC51SND1A
Package Information
TQFP80
53
4106E–8051–03/02
Package Information
PLCC84
54
AT8xC51SND1A
4106E–8051–03/02
Atmel Headquarters
Atmel Operations
Corporate Headquarters
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TEL 1(408) 436-4270
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Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
Europe
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Microcontrollers
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© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
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Other terms and product names may be the trademarks of others.
Printed on recycled paper.
4106E–8051–03/02
/0M
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