AT80C51RD2-SLSUM [ATMEL]
80C51 High Performance ROM 8-bit Microcontroller; 80C51高性能ROM的8位微控制器
| 型号： | AT80C51RD2-SLSUM |
| 厂家： | 
ATMEL |
| 描述： | 80C51 High Performance ROM 8-bit Microcontroller |
| 文件： | 总83页 (文件大小：1109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• 80C52 Compatible
– Four 8-bit I/O Ports
– Three 16-bit Timer/Counters
– 256 Bytes Scratch Pad RAM
– 8 Interrupt Sources with 4 Priority Levels
– Dual Data Pointer
• Variable Length MOVX for Slow RAM/Peripherals
• High-speed Architecture
– 10 to 40 MHz in Standard Mode
• 16K/32K Bytes On-Chip ROM Program
• T80C51RD2 ROMless Versions
• On-Chip 1024 bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024 bytes)
– 256 Bytes Selected at Reset for AT87C51RB2/RC2 Compatibility
• Keyboard Interrupt Interface on Port P1
• 8-bit Clock Prescaler
• 64K Program and Data Memory Spaces
• Improved X2 Mode with Independant Selection for CPU and Each Peripheral
• Programmable Counter Array 5 Channels with:
– High-speed Output
80C51 High
Performance
ROM 8-bit
Microcontroller
AT80C51RD2
AT83C51RB2
AT83C51RC2
– Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
• Asynchronous Port Reset
• Full Duplex Enhanced UART
• Dedicated Baud Rate Generator for UART
• Low EMI (Inhibit ALE)
• Hardware Watchdog Timer (One-time Enabled with Reset-out)
• Power Control Modes
– Idle Mode
– Power-down Mode
– Power-off Flag
• Power Supply: 2.7V to 5.5V or 2.7V to 3.6V
• Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C)
• Packages: PDIL40, PLCC44, VQFP44
Description
AT8xC51Rx2 microcontrollers are high performance ROM versions of the 80C51 8-bit
microcontrollers. They contain a 0K, 16K or 32K bytes ROM memory block for
program.
The microcontrollers retain all features of the Atmel 80C52 with 256 bytes of internal
RAM, a 7-source 4-level interrupt controller and three timer/counters.
In addition, the microcontrollers have a Programmable Counter Array, an XRAM of
1024 byte, a Hardware Watchdog Timer, a Keyboard Interface, a more versatile serial
channel that facilitates multiprocessor communication (EUART) and a speed improve-
ment mechanism (X2 mode).
The microcontrollers have 2 software-selectable modes of reduced activity and 8 bit
clock prescaler for further reduction in power consumption. In Idle mode, the CPU is
frozen while the peripherals and the interrupt system are still operating. In the Power-
down mode, the RAM is saved and all other functions are inoperative.
Rev. 4113B–8051–03/05
Table 1. Memory Size
TOTAL RAM
(Bytes)
ROM (Bytes)
16K
XRAM (Bytes)
1024
I/O
32
32
32
AT83C51RB2
AT83C51RC2
AT80C51RD2
1280
1280
1280
32K
1024
ROMless
1024
Block Diagram
(2) (2)
(1)
(1) (1)
(1)
XTAL1
XTAL2
EUART
RAM
+
ROM
32Kx8 or
16Kx8
XRAM
1Kx8
PCA
Timer2
256x8
BRG
ALE/PROG
PSEN
C51
CORE
IB-bus
CPU
EA
(2)
(2)
Key
Board
Timer 0
Timer 1
Parallel I/O Ports & Ext. Bus
Port 0Port 1 Port 3
Watch
Dog
INT
Ctrl
RD
Port 2
WR
(2) (2)
(2) (2)
Notes: 1. Alternate function of Port 1
2. Alternate function of Port 3
2
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Pin Configurations
P1.0/T2
40
39
38
1
2
VCC
P0.0/AD0
P0.1/AD1
P1.1/T2EX
P1.2/ECI
3
4
37 P0.2/AD2
P1.3CEX0
P1.4/CEX1
P0.3/AD3
P0.4/AD4
36
35
34
33
5
P1.5/CEX2
P1.6/CEX3
P1.7CEX4
RST
6
7
8
P0.5/AD5
P0.6/AD6
P0.7/AD7
9
32
31
30
EA
P3.0/RxD 10
PDIL40
ALE/PROG
PSEN
P3.1/TxD
P3.2/INT0
11
12
29
28
P2.7/AD15
P2.6/AD14
P3.3/INT1 13
P3.4/T0 14
27
26
P2.5/AD13
15
16
17
18
19
20
P3.5/T1
6
5 4 3 2 1
44 43 42 41 40
P2.4/AD12
P2.3/AD11
25
P3.6/WR
P1.5/CEX2
P1.6/CEX3
P1.7/CEx4
RST
39
38
7
8
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
24
23
22
21
P3.7/RD
XTAL2
P2.2/AD10
P2.1/AD9
P2.0/AD8
37
9
XTAL1
VSS
10
11
12
13
36
35
34
33
P3.0/RxD
NIC*
PLCC44
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
ALE/PROG
PSEN
14
15
16
17
32
31
30
29
P2.7/A15
P2.6/A14
P2.5/A13
P3.5/T1
18 19 20 21 22 23 24 25 26 27 28
44 43 42 41 40 39 38 37 36 35 34
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
P1.5/CEX2
33
32
1
2
P1.6/CEX3
P1.7/CEX4
RST
31
3
4
30
29
28
27
P3.0/RxD
NIC*
5
VQFP44 1.4
NIC*
6
7
8
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
ALE/PROG
PSEN
26
25
24
23
P2.7/A15
P2.6/A14
P2.5/A13
9
10
11
P3.5/T1
1213141516171819202122
*NIC: No Internal Connection
3
4113B–8051–03/05
Table 2. Pin Description
Pin Number
Mnemonic
DIL
PLCC44
VQFP44 1.4
Type
Name and Function
VSS
20
22
16
38
I
Ground: 0V reference
Power Supply: This is the power supply voltage for normal, idle and power-down
operation
VCC
40
44
I
P0.0 - P0.7
39 - 32
43 - 36
37 - 30
I/O
Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. Port 0 must be
polarized to VCC or VSS in order to prevent any parasitic current consumption. Port
0 is also the multiplexed low-order address and data bus during access to external
program and data memory. In this application, it uses strong internal pull-up when
emitting 1s. Port 0 also inputs the code bytes during EPROM programming.
External pull-ups are required during program verification during which P0 outputs
the code bytes.
P1.0 - P1.7
1 - 8
2 - 9
40 - 44
1 - 3
I/O
Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs. As inputs, Port 1 pins that are externally pulled low will source
current because of the internal pull-ups. Port 1 also receives the low-order address
byte during memory programming and verification.
Alternate functions for T89C51RB2/RC2 Port 1 include:
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
40
41
42
43
44
1
I/O
I/O
I/O
I
P1.0: Input/Output
T2 (P1.0): Timer/Counter 2 external count input/Clockout
P1.1: Input/Output
T2EX: Timer/Counter 2 Reload/Capture/Direction Control
P1.2: Input/Output
I/O
I
ECI: External Clock for the PCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P1.3: Input/Output
CEX0: Capture/Compare External I/O for PCA module 0
P1.4: Input/Output
CEX1: Capture/Compare External I/O for PCA module 1
P1.5: Input/Output
CEX2: Capture/Compare External I/O for PCA module 2
P1.6: Input/Output
2
CEX3: Capture/Compare External I/O for PCA module 3
P1.7: Input/Output:
3
CEX4: Capture/Compare External I/O for PCA module 4
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
XTAL1
XTAL2
19
18
21
20
15
14
I
O
Crystal 2: Output from the inverting oscillator amplifier
4
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 2. Pin Description (Continued)
Pin Number
Mnemonic
DIL
PLCC44
VQFP44 1.4
Type
Name and Function
P2.0 - P2.7
21 - 28
24 - 31
18 - 25
I/O
Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs. As inputs, Port 2 pins that are externally pulled low will source
current because of the internal pull-ups. Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 SFR.
Some Port 2 pins receive the high order address bits during ROM reading and
verification:
P2.0 to P2.5 for 16 KB devices
P2.0 to P2.6 for 32 KB devices
P3.0 - P3.7
10 - 17
11,
13 - 19
5,
7 - 13
I/O
Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs. As inputs, Port 3 pins that are externally pulled low will source
current because of the internal pull-ups. Port 3 also serves the special features of
the 80C51 family, as listed below.
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
I
O
I
RXD (P3.0): Serial input port
TXD (P3.1): Serial output port
8
INT0 (P3.2): External interrupt 0
INT1 (P3.3): External interrupt 1
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
9
I
10
11
12
13
I
I
O
O
Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSS permits a power-on reset
using only an external capacitor to VCC. This pin is an output when the hardware
watchdog forces a system reset.
RST
9
10
33
4
I/O
ALE/PROG
30
27
O (I)
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of
the address during an access to external memory. In normal operation, ALE is
emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can
be used for external timing or clocking. Note that one ALE pulse is skipped during
each access to external data memory. This pin is also the program pulse input
(PROG) during Flash programming. ALE can be disabled by setting SFR’s AUXR.0
bit. With this bit set, ALE will be inactive during internal fetches.
PSEN
29
31
32
35
26
29
O
Program Strobe Enable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
External Access Enable: EA must be externally held low to enable the device to
fetch code from external program memory locations 0000H to 3FFFH (16K),
7FFFH (32K). If security level 1 is programmed, EA will be internally latched on
Reset.
EA
I
5
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
SFR Mapping
The Special Function Registers (SFRs) of the microcontroller fall into the following
categories:
•
•
•
C51 core registers: ACC, B, DPH, DPL, PSW, SP
I/O port registers: P0, P1, P2, P3
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
•
•
Serial I/O port registers: SADDR, SADEN, SBUF, SCON
PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH,
CCAPxH, CCAPxL (x: 0 to 4)
•
•
•
•
•
•
•
Power and clock control registers: PCON
Hardware Watchdog Timer registers: WDTRST, WDTPRG
Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1
Keyboard Interface registers: KBE, KBF, KBLS
BRG (Baud Rate Generator) registers: BRL, BDRCON
Clock Prescaler register: CKRL
Others: AUXR, AUXR1, CKCON0, CKCON1
7
4113B–8051–03/05
Table 3 shows all SFRs with their address and their reset value.
Table 3. SFR Mapping
Bit
Addressable
Non-bit Addressable
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
CH
CCAP0H
CCAP1H
CCAPL2H
CCAPL3H
CCAPL4H
F8h
FFh
F7h
EFh
E7h
DFh
0000 0000
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
F0h
E8h
E0h
D8h
B
0000 0000
CL
CCAP0L
CCAP1L
CCAPL2L
CCAPL3L
CCAPL4L
0000 0000
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
XXXX XXXX
ACC
0000 0000
CCON
CMOD
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
00X0 0000
00XX X000
X000 0000
X000 0000
X000 0000
X000 0000
X000 0000
PSW
0000 0000
D0h
C8h
C0h
D7h
CFh
C7h
T2CON
0000 0000
T2MOD
XXXX XX00
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
IPL0
SADEN
B8h
B0h
A8h
A0h
98h
90h
88h
80h
BFh
B7h
AFh
A7h
9Fh
97h
8Fh
87h
X000 000
0000 0000
P3
IE1
IPL1
IPH1
IPH0
1111 1111
XXXX XXX0b
XXXX XXX0b
XXXX XXX0b
X000 0000
IE0
SADDR
0000 0000
0000 0000
P2
AUXR1
WDTRST
WDTPRG
1111 1111
XXXX XXX0
XXXX XXXX
XXXX X000
SCON
SBUF
BRL
BDRCON
KBLS
KBE
KBF
0000 0000
XXXX XXXX
0000 0000
XXX0 0000
0000 0000
0000 0000
0000 0000
P1
CKRL
1111 1111
1111 1111
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON0
AUXR
XX0X 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
P0
PCON
SP
DPL
DPH
0000 0111
0000 0000
0000 0000
1111 1111
00X1 0000
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
Reserved
8
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Oscillators
Overview
One oscillator is available for CPU:
OSC used for high frequency (3 MHz to 40 MHz)
•
In order to optimize the power consumption and the execution time needed for a specific
task, an internal prescaler feature has been implemented between the selected oscilla-
tor and the CPU.
Registers
Table 4. Clock Reload Register
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Bit
Bit
Number Mnemonic Description
7:0 CKRL Clock Reload Register: Prescaler value
Reset Value = 1111 1111b
Not bit addressable
Prescaler Divider
A hardware RESET puts the prescaler divider in the following state:
•
CKRL = FFh: FCLK CPU = FCLK PERIPH = FOSC/2 (Standard C51 feature)
KS signal selects OSC: FCLK OUT = FOSC
•
Any value between FFh down to 00h can be written by software into CKRL register
in order to divide frequency of the selected oscillator:
–
–
–
CKRL = 00h: minimum frequency
F
F
CLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode)
CLK CPU = FCLK PERIPH = FOSC/510 (X2 Mode)
CKRL = FFh: maximum frequency
F
F
CLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode)
CLK CPU = FCLK PERIPH = FOSC (X2 Mode)
F
CLK CPU and FCLK PERIPH
In X2 mode:
FOSC
---------------------------------------------
2 × (255 – CKRL)
FCPU = FCLKPERIPH
=
FOSCA
4 × (255 – CKRL)
In X1 mode:
----------------------------------------------
=
FCPU = FCLKPERIPH
9
4113B–8051–03/05
Enhanced Features
In comparison to the original 80C52, the microcontrollers implement the following new
features:
•
•
•
•
•
•
•
•
•
•
•
X2 option
Dual Data Pointer
Extended RAM
Programmable Counter Array (PCA)
Hardware Watchdog
4-level Interrupt Priority System
Power-off Flag
Power On Reset
ONCE mode
ALE disabling
Some enhanced features are also located in the UART and the Timer 2
X2 Feature and OSC
Clock Generation
The microcontroller core needs only 6 clock periods per machine cycle. This feature
called ”X2” provides the following advantages:
•
•
Divides frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
Saves power consumption while keeping same CPU power (oscillator power
saving).
•
•
Saves power consumption by dividing dynamically the operating frequency by 2 in
operating and idle modes.
Increases CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
Description
The clock for the whole circuit and peripherals is first divided by two before being used
by the CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 2 shows the clock generation block diagram. X2 bit is validated on the rising edge
of the XTAL1 ÷ 2 to avoid glitches when switching from X2 to standard mode. Figure 3
shows the switching mode waveforms.
Figure 2. Clock Generation Diagram
CKRL
FOSC
XTAL1:2
CLK Periph
CLK CPU
2
XTAL1
0
1
8-bit Prescaler
FXTAL
Idle
X2
CKCON0
10
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Figure 3. Mode Switching Waveforms
XTAL1
XTAL1:2
X2 Bit
FOSC
CPU Block
STD Mode
X2 Mode
STD Mode
The X2 bit in the CKCON0 register (see Table 5) allows to switch from 12 clock periods
per instruction to 6 clock periods and vice versa. At reset, the speed is set according to
X2 bit of Hardware Config Byte (HCB). By default, Standard mode is activated. Setting
the X2 bit activates the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, UARTX2, PCAX2 and WDX2 bits in the CKCON0 register
(Table 5) allow to switch from standard peripheral speed (12 clock periods per periph-
eral clock cycle) to fast peripheral speed (6 clock periods per peripheral clock cycle).
These bits are active only in X2 mode.
11
4113B–8051–03/05
Table 5. CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
7
-
6
5
4
3
2
1
0
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit
Bit
Number
Mnemonic
Description
Reserved
7
6
-
Do not set this bit.
Watchdog clock (This control bit is validated when the CPU clock X2 is set;
when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
WDX2
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array clock (This control bit is validated when the
CPU clock X2 is set; when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
5
4
3
2
1
PCAX2
SIX2
Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the
CPU clock X2 is set; when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer 2 clock (This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
T2X2
T1X2
T0X2
Set to select 12 clock periods per peripheral clock cycle.
Timer 1 clock (This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
Timer 0 clock (This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
CPU clock
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and
all the peripherals.
0
X2
Set to select 6clock periods per machine cycle (X2 mode) and to enable the
individual peripherals "X2" bits.
Programmed by hardware after Power-up regarding Hardware Config Byte
(HCB).
Reset Value = 0000 000’HCB.X2’b (see Hardware Config Byte)
Not bit addressable
12
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Dual Data Pointer
Register
The additional data pointer can be used to speed up code execution and reduce code
size.
The dual DPTR structure is a way by which the chip will specify the address of an exter-
nal data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1.0 (see Table 6) that allows the program
code to switch between them (Refer to Figure 4).
Figure 4. Use of Dual Pointer
External Data Memory
7
0
DPS
DPTR1
DPTR0
AUXR1(A2H)
DPH(83H) DPL(82H)
Table 6. AUXR1 Register
AUXR1- Auxiliary Register 1(0A2h)
7
-
6
-
5
-
4
-
3
2
0
1
-
0
GF3
DPS
Bit
Bit
Number
Mnemonic Description
Reserved
7
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
6
5
4
-
-
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
2
GF3
0
This bit is a general purpose user flag.
Always cleared(1)
.
Reserved
1
0
-
The value read from this bit is indeterminate. Do not set this bit.
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
DPS
Reset Value: XXXX XXXX0b
Not bit addressable
Note:
1. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
13
4113B–8051–03/05
Assembly Language
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2
;
AUXR1 EQU 0A2H
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a par-
ticular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value. In
other words, the block move routine works the same whether DPS is '0' or '1' on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
14
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Expanded RAM
(XRAM)
The T8xc51Rx2 devices provide additional Bytes of Random Access Memory (RAM)
space for increased data parameter handling and high level language usage.
The devices have expanded RAM in external data space; maximum size and location
are described in Table 7.
Table 7. Expanded RAM
Address
XRAM size
Start
End
T83C51RB2/RC2
T80C51RD2
1024
00h
3FFh
The T8xc51Rx2 has internal data memory that is mapped into four separate segments.
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable
only.
3. The Special Function Registers (SFRs) (addresses 80h to FFh) are directly
addressable only.
4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and
with the EXTRAM bit cleared in the AUXR register (see Table 7).
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper
128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy
the same address space as the SFR. That means they have the same address, but are
physically separate from SFR space.
Figure 5. Internal and External Data Memory Address
0FFh or 3FFh
0FFh
0FFh
0FFFFh
Upper
128 Bytes
Internal
Special
Function
External
Data
Memory
Register
RAM
Direct Accesses
indirect accesses
80h
7Fh
80h
XRAM
Lower
128 Bytes
Internal
RAM
Direct or Indirect
Accesses
00FFh up to 03FFh
0000
00
00
15
4113B–8051–03/05
When an instruction accesses an internal location above address 7Fh, the CPU knows
whether the access is to the upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction.
•
Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data, accesses the SFR at location 0A0h (which is P2).
•
Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte
at address 0A0h, rather than P2 (whose address is 0A0h).
•
•
The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared
and MOVX instructions. This part of memory which is physically located on-chip,
logically occupies the first bytes of external data memory. The bits XRS0 and XRS1
are used to hide a part of the available XRAM as explained in Table 7. This can be
useful if external peripherals are mapped at addresses already used by the internal
XRAM.
With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An
access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For
example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H,
accesses the XRAM at address 0A0H rather than external memory. An access to
external data memory locations higher than the accessible size of the XRAM will be
performed with the MOVX DPTR instructions in the same way as in the standard
80C51, with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and
read timing signals. Accesses to XRAM above 0FFH can only be done by the use of
DPTR.
•
With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard
80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port 0
and any output port pins can be used to output higher order address bits. This is to
provide the external paging capability. MOVX @DPTR will generate a sixteen-bit
address. Port2 outputs the high-order eight address bits (the contents of DPH) while
Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and
MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7
(RD).
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and
upper RAM) internal data memory. The stack may not be located in the XRAM.
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses
are extended from 6 to 30 clock periods. This is useful to access external slow
peripherals.
16
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 8. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
-
6
-
5
4
-
3
2
1
0
M0
XRS1
XRS0
EXTRAM
AO
Bit
Bit
Number
Mnemonic Description
Reserved
7
-
The value read from this bit is indeterminate. Do not set this bit
Reserved
6
5
-
The value read from this bit is indeterminate. Do not set this bit
M0
Pulse length
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock
periods (default).
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.
Reserved
4
-
The value read from this bit is indeterminate. Do not set this bit
3
2
XRS1
XRS0
XRAM Size
XRS1
0
XRS0
0
XRAM Size
256 bytes (default)
0
1
1
1
0
1
512 bytes
768 bytes
1024 bytes
1
0
EXTRAM EXTRAM bit
Cleared to access internal XRAM using MOVX @ Ri/ @ DPTR.
Set to access external memory.
Programmed by hardware after Power-up regarding Hardware Security Byte
(HSB), default setting, XRAM selected.
AO
ALE Output bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used) (default). Set, ALE is active only if a MOVX or MOVC
instruction is used.
Reset Value = XX0X 00’HSB.XRAM’0b (see Table 7)
Not bit addressable
17
4113B–8051–03/05
Timer 2
The Timer 2 in the T8xc51Rx2 is the standard C52 Timer 2.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2
and TL2 are cascaded. It is controlled by T2CON (Table 9) and T2MOD (Table 10) reg-
isters. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer
operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2
allows TL2 to be incremented by the selected input.
Timer 2 has 3 operating modes: capture, auto-reload and Baud Rate Generator. These
modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON).
Refer to the Atmel 8-bit Microcontroller Hardware description for Capture and Baud
Rate Generator Modes.
Timer 2 includes the following enhancements:
•
•
Auto-reload mode with up or down counter
Programmable clock-output
Auto-reload Mode
The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with auto-
matic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to
the Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, Timer 2 acts
as an Up/down timer/counter as shown in Figure 6. In this mode the T2EX pin controls
the direction of count.
When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the
TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value
in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when Timer 2 overflows or underflows according to the direction of
the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit
resolution.
18
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Figure 6. Auto-Reload Mode Up/Down Counter (DCEN = 1)
FCLK PERIPH
:6
0
1
T2
TR2
C/T2
T2CON
T2CON
T2EX:
(DOWN COUNTING RELOAD VALUE)
if DCEN = 1, 1 = UP
FFh
FFh
if DCEN = 1, 0 = DOWN
if DCEN = 0, up counting
(8-bit)
(8-bit)
T2CON
EXF2
TOGGLE
TL2
(8-bit)
TH2
(8-bit)
TIMER 2
INTERRUPT
TF2
T2CON
RCAP2L
(8-bit)
RCAP2H
(8-bit)
(UP COUNTING RELOAD VALUE)
Programmable Clock-
Output
In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock gen-
erator (see Figure 7). The input clock increments TL2 at frequency FCLK PERIPH/2. The
timer repeatedly counts to overflow from a loaded value. At overflow, the contents of
RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2
overflows do not generate interrupts. The formula gives the clock-out frequency as a
function of the system oscillator frequency and the value in the RCAP2H and RCAP2L
registers:
FCLKPERIPH
----------------------------------------------------------------------------------------
Clock – OutFrequency =
4 × (65536 – RCAP2H ⁄ RCAP2L)
For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz
(FCLK PERIPH/216) to 4 MHz (FCLK PERIPH/4). The generated clock signal is brought out to
T2 pin (P1.0).
Timer 2 is programmed for the clock-out mode as follows:
•
•
•
Set T2OE bit in T2MOD register.
Clear C/T2 bit in T2CON register.
Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
•
Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the
reload value or a different one depending on the application.
•
To start the timer, set TR2 run control bit in T2CON register.
It is possible to use Timer 2 as a baud rate generator and a clock generator simulta-
neously. For this configuration, the baud rates and clock frequencies are not
independent since both functions use the values in the RCAP2H and RCAP2L registers.
19
4113B–8051–03/05
Figure 7. Clock-Out Mode C/T2 = 07
:6
FCLK PERIPH
TR2
T2CON
TH2
(8-bit)
TL2
(8-bit)
OVEFLOW
RCAP2H
(8-bit)
RCAP2L
(8-bit)
Toggle
T2
Q
D
T2OE
T2MOD
TIMER 2
INTERRUPT
T2EX
EXF2
T2CON
EXEN2
T2CON
20
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 9. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Bit
Number
Mnemonic Description
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.
7
6
TF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin
if EXEN2 = 1.
When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2
interrupt is enabled.
EXF2
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN = 1)
Receive Clock bit
5
4
RCLK
TCLK
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if Timer 2 is not used to clock the serial port.
3
2
1
EXEN2
TR2
Timer 2 Run control bit
Cleared to turn off Timer 2.
Set to turn on Timer 2.
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be
0 for clock out mode.
C/T2#
Timer 2 Capture/Reload bit
If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload
on Timer 2 overflow.
Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX
pin if EXEN2 = 1.
0
CP/RL2#
Set to capture on negative transitions on T2EX pin if EXEN2 = 1.
Reset Value = 0000 0000b
Bit addressable
21
4113B–8051–03/05
Table 10. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
7
-
6
-
5
-
4
-
3
-
2
-
1
0
T2OE
DCEN
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
-
-
-
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Timer 2 Output Enable bit
1
0
T2OE
DCEN
Cleared to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
Down Counter Enable bit
Cleared to disable Timer 2 as up/down counter.
Set to enable Timer 2 as up/down counter.
Reset Value = XXXX XX00b
Not bit addressable
22
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Programmable
Counter Array (PCA)
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accu-
racy. The PCA consists of a dedicated timer/counter which serves as the time base for
an array of five compare/capture modules. Its clock input can be programmed to count
any one of the following signals:
•
•
•
•
Peripheral clock frequency (FCLK PERIPH) ÷ 6
Peripheral clock frequency (FCLK PERIPH) ÷ 2
Timer 0 overflow
External input on ECI (P1.2)
Each compare/capture modules can be programmed in any one of the following modes:
•
•
•
•
Rising and/or falling edge capture
Software timer
High-speed output
Pulse width modulator
Module 4 can also be programmed as a Watchdog Timer (see Section "PCA Watchdog
Timer", page 34).
When the compare/capture modules are programmed in the capture mode, software
timer, or high-speed output mode, an interrupt can be generated when the module exe-
cutes its function. All five modules plus the PCA timer overflow share one interrupt
vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O.
These pins are listed below. If the port is not used for the PCA, it can still be used for
standard I/O.
PCA Component
16-bit Counter
External I/O Pin
P1.2/ECI
16-bit Module 0
16-bit Module 1
16-bit Module 2
16-bit Module 3
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
The PCA timer is a common time base for all five modules (see Figure 8). The timer
count source is determined from the CPS1 and CPS0 bits in the CMOD register
(Table 11) and can be programmed to run at:
•
•
•
•
1/6 the peripheral clock frequency (FCLK PERIPH
1/2 the peripheral clock frequency (FCLK PERIPH
The Timer 0 overflow
)
)
The input on the ECI pin (P1.2)
23
4113B–8051–03/05
Figure 8. PCA Timer/Counter
To PCA
Modules
FCLK PERIPH /6
FCLK PERIPH/2
T0 OVF
Overflow
It
CH
CL
16-Bit Up/Down Counter
P1.2
CMOD
0xD9
CIDL WDTE
CPS1 CPS0 ECF
Idle
CCON
0xD8
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
24
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 11. CMOD Register
CMOD - PCA Counter Mode Register (D9h)
7
6
5
-
4
-
3
-
2
1
0
CIDL
WDTE
CPS1
CPS0
ECF
Bit
Bit
Number
Mnemonic Description
Counter Idle Control
7
6
CIDL
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
Watchdog Timer Enable
WDTE
Cleared to disable Watchdog Timer function on PCA Module 4.
Set to enable Watchdog Timer function on PCA Module 4.
Reserved
5
4
-
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
3
2
-
The value read from this bit is indeterminate. Do not set this bit.
CPS1
PCA Count Pulse Select
CPS1
0
CPS0 Selected PCA input
0
1
0
1
Internal clock fCLK PERIPH/6
0
1
1
Internal clock fCLK PERIPH/2
1
0
CPS0
ECF
Timer 0 Overflow
External clock at ECI/P1.2 pin (max rate = fCLK PERIPH/4
)
PCA Enable Counter Overflow Interrupt
Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
Reset Value = 00XX X000b
Not bit addressable
The CMOD register includes three additional bits associated with the PCA (see
Figure 11 and Table 11).
•
•
•
The CIDL bit which allows the PCA to stop during idle mode.
The WDTE bit which enables or disables the watchdog function on module 4.
The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in
the CCON SFR) to be set when the PCA timer overflows.
The CCON register contains the run control bit for the PCA and the flags for the PCA
timer (CF) and each module (see Table 12).
•
Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by
clearing this bit.
•
Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an
interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can
only be cleared by software.
•
Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,
etc.) and are set by hardware when either a match or a capture occurs. These flags
can only be cleared by software.
25
4113B–8051–03/05
Table 12. CCON Register
CCON - PCA Counter Control Register (D8h)
7
6
5
-
4
3
2
1
0
CF
CR
CCF4
CCF3
CCF2
CCF1
CCF0
Bit
Bit
Number
Mnemonic Description
PCA Counter Overflow flag
Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in
CMOD is set. CF may be set by either hardware or software but can only be
cleared by software.
7
CF
PCA Counter Run control bit
6
5
4
CR
-
Must be cleared by software to turn the PCA counter off.
Set by software to turn the PCA counter on.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
PCA Module 4 interrupt flag
CCF4
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 3 interrupt flag
3
2
1
0
CCF3
CCF2
CCF1
CCF0
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 2 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 1 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
PCA Module 0 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
Reset Value = 000X 0000b
Not bit addressable
The watchdog timer function is implemented in module 4 (see Figure 11).
The PCA interrupt system is shown in Figure 9.
26
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Figure 9. PCA Interrupt System
CCON
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
0xD8
PCA Timer/Counter
Module 0
Module 1
Module 2
Module 3
To Interrupt
Priority Decoder
Module 4
CMOD.0
IE.6
EC
IE.7
EA
CCAPMn.0
ECCFn
ECF
PCA Modules: each one of the five compare/capture modules has six possible func-
tions. It can perform:
•
•
•
•
•
•
16-bit Capture, positive-edge triggered
16-bit Capture, negative-edge triggered
16-bit Capture, both positive and negative-edge triggered
16-bit Software Timer
16-bit High-speed Output
8-bit Pulse Width Modulator
In addition, module 4 can be used as a Watchdog Timer.
Each module in the PCA has a special function register associated with it. These regis-
ters are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (see Table 13). The
registers contain the bits that control the mode that each module will operate in.
•
The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module)
enables the CCF flag in the CCON SFR to generate an interrupt when a match or
compare occurs in the associated module.
•
•
PWM (CCAPMn.1) enables the pulse width modulation mode.
The TOG bit (CCAPMn.2) when set causes the CEX output associated with the
module to toggle when there is a match between the PCA counter and the module's
capture/compare register.
•
•
The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON
register to be set when there is a match between the PCA counter and the module's
capture/compare register.
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge
that a capture input will be active on. The CAPN bit enables the negative edge, and
the CAPP bit enables the positive edge. If both bits are set both edges will be
enabled and a capture will occur for either transition.
•
The last bit in the register ECOM (CCAPMn.6) when set enables the comparator
function.
27
4113B–8051–03/05
Table 13 shows the CCAPMn settings for the various PCA functions.
Table 13. CCAPMn Registers (n = 0-4)
CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh)
CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh)
CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh)
CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh)
CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)
7
-
6
5
4
3
2
1
0
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
-
The value read from this bit is indeterminate. Do not set this bit.
Enable Comparator
ECOMn Cleared to disable the comparator function.
Set to enable the comparator function.
Capture Positive
5
4
CAPPn
CAPNn
Cleared to disable positive edge capture.
Set to enable positive edge capture.
Capture Negative
Cleared to disable negative edge capture.
Set to enable negative edge capture.
Match
When MATn = 1, a match of the PCA counter with this module's
compare/capture register causes the CCFn bit in CCON to be set, flagging an
interrupt.
3
MATn
Toggle
2
1
TOGn
When TOGn = 1, a match of the PCA counter with this module's
compare/capture register causes the CEXn pin to toggle.
Pulse Width Modulation Mode
PWMn
Cleared to disable the CEXn pin to be used as a pulse width modulated output.
Set to enable the CEXn pin to be used as a pulse width modulated output.
Enable CCF interrupt
Cleared to disable compare/capture flag CCFn in the CCON register to generate
an interrupt.
0
CCF0
Set to enable compare/capture flag CCFn in the CCON register to generate an
interrupt.
Reset Value = X000 0000b
Not bit addressable
28
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 14. PCA Module Modes (CCAPMn Registers)
ECOMn CAPPn CAPNn
MATn
TOGn
PWMm ECCFn Module Function
0
0
1
0
0
0
0
0
0
0
No Operation
16-bit capture by a positive-edge
trigger on CEXn
X
0
0
0
1
0
0
0
0
X
16-bit capture by a negative trigger
on CEXn
X
X
1
0
1
0
1
1
0
0
0
0
X
X
X
16-bit capture by a transition on
CEXn
16-bit Software Timer/Compare
mode.
1
1
1
0
0
0
0
0
0
1
0
1
1
0
X
0
1
0
X
0
16-bit High-speed Output
8-bit PWM
X
Watchdog Timer (module 4 only)
There are two additional registers associated with each of the PCA modules. They are
CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a
capture occurs or a compare should occur. When a module is used in the PWM mode
these registers are used to control the duty cycle of the output (see Table 15 and
Table 16).
Table 15. CCAPnH Registers (n = 0-4)
CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh)
CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh)
CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh)
CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh)
CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Bit
Number
Mnemonic Description
PCA Module n Compare/Capture Control
CCAPnH Value
7-0
-
Reset Value = 0000 0000b
Not bit addressable
29
4113B–8051–03/05
Table 16. CCAPnL Registers (n = 0-4)
CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh)
CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh)
CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh)
CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh)
CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Bit
Bit
Number
Mnemonic Description
PCA Module n Compare/Capture Control
CCAPnL Value
7-0
-
Reset Value = 0000 0000b
Not bit addressable
Table 17. CH Register
CH - PCA Counter Register High (0F9h)
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Bit
Bit
Number
Mnemonic Description
PCA counter
CH Value
7-0
-
Reset Value = 0000 0000b
Not bit addressable
Table 18. CL Register
CL - PCA Counter Register Low (0E9h)
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Bit
Bit
Number
Mnemonic Description
PCA Counter
CL Value
7-0
-
Reset Value = 0000 0000b
Not bit addressable
30
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
PCA Capture Mode
To use one of the PCA modules in the capture mode either one or both of the CCAPM
bits CAPN and CAPP for that module must be set. The external CEX input for the mod-
ule (on port 1) is sampled for a transition. When a valid transition occurs the PCA
hardware loads the value of the PCA counter registers (CH and CL) into the module's
capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON
SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated
(see Figure 10).
Figure 10. PCA Capture Mode
CCON
0xD8
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
PCA Counter/Timer
Cex.n
CH
CL
Capture
CCAP nH
CCA Pn L
CCAPMn, n= 0 to 4
0xDA to 0xDE
ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn
16-bit Software Timer/
Compare Mode
The PCA modules can be used as software timers by setting both the ECOM and MAT
bits in the modules CCAPMn register. The PCA timer will be compared to the module's
capture registers and when a match occurs an interrupt will occur if the CCFn (CCON
SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 11).
31
4113B–8051–03/05
Figure 11. PCA Compare Mode and PCA Watchdog Timer
CCON
0xD8
CF
CCF4 CCF3 CCF2 CCF1 CCF0
CR
Write to
CCAPnL Reset
PCA IT
Write to
CCAPnH
CCAP nH
CCA PnL
Enable
1
0
Match
16 bit comparator
RESET *
CH
CL
PCA counter/timer
CCA PMn, n = 0 to 4
0xDA to 0xDE
ECOMn CA PPn CAPNn MATn TOGn PWMn ECCFn
CMOD
0xD9
CIDL WDTE
CPS1 CPS0 ECF
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing to CCAPMn register.
High-speed Output Mode In this mode, the CEX output (on port 1) associated with the PCA module will toggle
each time a match occurs between the PCA counter and the module's capture registers.
To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR
must be set (see Figure 12).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
32
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Figure 12. PCA High-speed Output Mode
CCON
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
0xD8
Write to
CCAPnL
Reset
PCA IT
Write t
CCAPn
CCAPnH
CCAPnL
0
1
Enable
Match
16 bit comparator
CEXn
CH
CL
PCA counter/timer
CCAPMn, n = 0 to 4
0xDA to 0xDE
ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,
otherwise an unwanted match could occur.
Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t
occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this
reason, user software should write CCAPnL first, and then CCAPnH. Of course, the
ECOM bit can still be controlled by accessing the CCAPMn register.
Pulse Width Modulator
Mode
All of the PCA modules can be used as PWM outputs. Figure 13 shows the PWM func-
tion. The frequency of the output depends on the source for the PCA timer. All of the
modules will have the same frequency of output because they all share the PCA timer.
The duty cycle of each module is independently variable using the module's capture
register CCAPLn. When the value of the PCA CL SFR is less than the value in the mod-
ule's CCAPLn SFR the output will be low, when it is equal to or greater than the output
will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in
CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in
the module's CCAPMn register must be set to enable the PWM mode.
33
4113B–8051–03/05
Figure 13. PCA PWM Mode
CCAPnH
Overflow
CCAPnL
“0”
“1”
CEXn
Enable
8-Bit Comparator
CL
PCA Counter/Timer
CCAPMn, n= 0 to 4
0xDA to 0xDE
ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn
PCA Watchdog Timer
An on-board watchdog timer is available with the PCA to improve the reliability of the
system without increasing chip count. Watchdog timers are useful for systems that are
susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only
PCA module that can be programmed as a watchdog. However, this module can still be
used for other modes if the watchdog is not needed. Figure 11 shows a diagram of how
the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just
like the other compare modes, this 16-bit value is compared to the PCA timer value. If a
match is allowed to occur, an internal reset will be generated. This will not cause the
RST pin to be driven high.
In order to hold off the reset, the user has three options:
1. Periodically change the compare value so it will never match the PCA timer.
2. Periodically change the PCA timer value so it will never match the compare
values.
3. Disable the watchdog by clearing the WDTE bit before a match occurs and then
re-enable it.
The first two options are more reliable because the watchdog timer is never disabled as
in option #3. If the program counter ever goes astray, a match will eventually occur and
cause an internal reset. The second option is also not recommended if other PCA mod-
ules are being used. Remember, the PCA timer is the time base for all modules;
changing the time base for other modules would not be a good idea. Thus, in most appli-
cations the first solution is the best option.
This watchdog timer won’t generate a reset out on the reset pin.
34
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Serial I/O Port
The serial I/O port in the T8xc51Rx2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes
(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously
and at different baud rates
Serial I/O port includes the following enhancements:
•
•
Framing error detection
Automatic address recognition
Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-
ter (see Figure 14).
Figure 14. Framing Error Block diagram
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
SCO N (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UA RT mode control (SMOD0 = 0)
SMODSMOD0
-
PO F
GF1
GF0
PD
IDL
PCON (87h)
1
To UA RT framing error cont rol
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (see Table 22) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently, received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (see Figure 15 and Figure 16).
Figure 15. UART Timings in Mode 1
RXD
D0 D1
D2 D3 D4 D5 D6 D7
Data byte
Start
bit
Stop
bit
RI
SMOD0=X
FE
SMOD0=1
35
4113B–8051–03/05
Figure 16. UART Timings in Modes 2 and 3
RXD
D2
D0
D1
D3 D4 D5
D6
D7
D8
.Start
Bit
Data Byte
Ninth Stop
Bit Bit
RI
SMOD0 = 0
RI
SMOD0 = 1
FE
SMOD0 = 1
Automatic Address
Recognition
The automatic address recognition feature is enabled when the multiprocessor commu-
nication feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor
communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this
configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the
received command frame address matches the device’s address and is terminated by a
valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
Given Address
Each device has an individual address that is specified in SADDR register; the SADEN
register is a mask byte that contains don’t care bits (defined by zeros) to form the
device’s given address. The don’t care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0010b
SADEN1111 1101b
Given1111 00X1b
36
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com-
municate with slave A only, the master must send an address where bit 0 is clear (e.g.
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with
slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both
set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set,
bit 1 clear, and bit 2 clear (e.g. 1111 0001b).
Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t-care bits, e.g.:
SADDR 0101 0110b
SADEN 1111 1100b
Broadcast
= SADDR OR SADEN1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however
in most applications, a broadcast address is FFh. The following is an example of using
broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR = 1111 0010b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the slaves, the master must send an address FFh. To communicate with slaves A
and B, but not slave C, the master can send and address FBh.
Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and
broadcast addresses are XXXX XXXXb(all don’t-care bits). This ensures that the serial
port will reply to any address, and so, that it is backwards compatible with the 80C51
microcontrollers that do not support automatic address recognition.
Table 19. SADEN Register
SADEN - Slave Address Mask Register (B9h)
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
Not bit addressable
37
4113B–8051–03/05
Table 20. SADDR Register
SADDR - Slave Address Register (A9h)
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
Not bit addressable
Baud Rate Selection for
UART for Mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via
the T2CON and BDRCON registers.
Figure 17. Baud Rate selection
TIMER1
TI ME R_ BRG_ RX
0
1
0
1
TIMER2
/ 16
Rx Clock
RCLK
RB CK
INT_BRG
TIMER1
TI ME R2
TIMER_BRG_TX
0
1
0
1
/ 16
Tx Clock
TCLK
TB CK
INT_BRG
Table 21. Baud Rate Selection Table UART
TCLK
RCLK
TBCK
RBCK
Clock Source
UART Tx
Clock Source
(T2CON)
(T2CON)
(BDRCON)
(BDRCON)
UART Rx
0
1
0
1
X
X
0
1
X
0
0
1
1
0
1
X
X
X
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
1
1
1
Timer 1
Timer 2
Timer 1
Timer 1
Timer 1
Timer 2
Timer 2
Timer 2
INT_BRG
INT_BRG
Timer 1
Timer 1
Timer 2
INT_BRG
INT_BRG
INT_BRG
Timer 2
INT_BRG
38
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Internal Baud Rate Generator When the internal Baud Rate Generator is used, the Baud Rates are determined by the
(BRG)
BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode)
in BDRCON register and the value of the SMOD1 bit in PCON register.
Figure 18. Internal Baud Rate
Peripheral clock
/2
auto reload counter
overflow
0
1
/6
0
1
BRG
INT_BRG
BRL
SPD
BRR
•
The baud rate for UART is token by formula:
2SMOD × FCLKPERIPH
2 × 2 × 6〈1 – SPD〉 × 16 × [256 – (BRL)]
---------------------------------------------------------------------------------------------------------
BaudRate =
2SMOD1 × FCLKPERIPH
2 × 2 × 6(1 – SPD) × 16 × BaudRate
----------------------------------------------------------------------------------------
(BRL) = 256 –
39
4113B–8051–03/05
Table 22. SCON Register
SCON - Serial Control Register (98h)
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Bit
Number
Mnemonic Description
Framing Error bit (SMOD0 = 1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
7
FE
SMOD0 must be set to enable access to the FE bit
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SM0
SMOD0 must be cleared to enable access to the SM0 bit
Serial port Mode bit 1
SM1 Mode Description
Baud Rate
fCPU PERIPH/6
Variable
0
1
0
1
0
1
2
3
Shift Register
8-bit UART
9-bit UART
9-bit UART
6
5
SM1
SM2
fCPU PERIPH /32 or /16
Variable
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1. This bit should be cleared in mode 0.
Reception Enable bit
4
3
REN
TB8
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3
o transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
2
1
0
RB8
TI
In mode 1, if SM2=0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of
the stop bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 15. and
Figure 16. in the other modes.
RI
Reset Value = 0000 0000b
Bit addressable
40
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 23. Example of Computed Value when X2 = 1, SMOD1 = 1, SPD = 1
Baud Rates
FOSC=16.384 MHz
FOSC=24 MHz
Error (%)
BRL
Error (%)
1.23
BRL
243
230
217
204
178
100
-
115200
57600
38400
28800
19200
9600
247
238
229
220
203
149
43
0.16
0.16
0.16
0.16
0.16
0.16
-
1.23
1.23
1.23
0.63
0.31
4800
1.23
Table 24. Example of Computed Value when X2 = 0, SMOD1 = 0, SPD = 0
Baud Rates
FOSC=16.384 MHz
FOSC=24 MHz
Error (%)
BRL
Error (%)
1.23
BRL
243
230
202
152
4800
2400
1200
600
247
238
220
185
0.16
0.16
3.55
0.16
1.23
1.23
0.16
The baud rate generator can be used for mode 1 or 3 (see Figure 17.), but also for mode
0 for UART, thanks to the bit SRC located in BDRCON register (Table 31.)
41
4113B–8051–03/05
UART Registers
Table 25. SADEN Register
SADEN - Slave Address Mask Register for UART (B9h)
7
6
5
4
3
2
2
2
1
1
1
0
0
0
Reset Value = 0000 0000b
Table 26. SADDR Register
SADDR - Slave Address Register for UART (A9h)
7
6
5
4
3
Reset Value = 0000 0000b
Table 27. SBUF Register
SBUF - Serial Buffer Register for UART (99h)
7
6
5
4
3
Reset Value = XXXX XXXXb
Table 28. BRL Register
BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah)
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
42
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 29. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Bit
Number
Mnemonic Description
Timer 2 overflow Flag
7
6
TF2
Must be cleared by software.
Set by hardware on Timer 2 overflow, if RCLK=0 and TCLK=0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2 = 1.
When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2
interrupt is enabled.
EXF2
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN=1)
Receive Clock bit for UART
5
4
RCLK
TCLK
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit for UART
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if Timer 2 is not used to clock the serial port.
3
2
1
EXEN2
TR2
Timer 2 Run control bit
Cleared to turn off Timer 2.
Set to turn on Timer 2.
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be
0 for clock out mode.
C/T2#
Timer 2 Capture/Reload bit
If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload
on Timer 2 overflow.
Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin
if EXEN2 = 1.
0
CP/RL2#
Set to capture on negative transitions on T2EX pin if EXEN2 = 1.
Reset Value = 0000 0000b
Bit addressable
43
4113B–8051–03/05
Table 30. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit
Bit
Number
Mnemonic Description
Serial Port Mode bit 1 for UART
Set to select double baud rate in mode 1, 2 or 3.
7
6
5
SMOD1
SMOD0
-
Serial Port Mode bit 0 for UART
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set
by software.
4
POF
General purpose Flag
3
2
1
0
GF1
GF0
PD
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
IDL
Reset Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset
doesn’t affect the value of this bit.
44
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 31. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
7
-
6
-
5
-
4
3
2
1
0
BRR
TBCK
RBCK
SPD
SRC
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
-
The value read from this bit is indeterminate. Do not set this bit
Reserved
-
-
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Baud Rate Run Control bit
4
3
2
1
BRR
TBCK
RBCK
SPD
Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
Transmission Baud rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
Reception Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
Baud Rate Speed Control bit for UART
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
Baud Rate Source select bit in Mode 0 for UART
Cleared to select FOSC/12 as the Baud Rate Generator (FCLK PERIPH/6 in X2
mode).
0
SRC
Set to select the internal Baud Rate Generator for UARTs in mode 0.
Reset Value = XXX0 0000b
Not bit addressable
45
4113B–8051–03/05
Interrupt System
The T8xc51Rx2 have a total of 8 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, Keyboard inter-
rupt and the PCA global interrupt. These interrupts are shown in Figure 19.
Figure 19. Interrupt Control System
High Priority
IPH, IPL
Interrupt
3
INT0
IE0
0
3
0
TF0
Interrupt
3
INT1
IE1
Polling
0
3
Sequence, Decreasing from
High to Low Priority
TF1
0
3
PCA IT
0
3
0
RI
TI
3
TF2
EXF2
0
3
KBD IT
0
Individual Enable
Low Priority
Interrupt
Global Disable
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable register (Table 36 and Table 34). This register also
contains a global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source also can be individually programmed to one out of four priority lev-
els by setting or clearing a bit in the Interrupt Priority register (Table 37) and in the
Interrupt Priority High register (Table 35 and Table 36) shows the bit values and priority
levels associated with each combination.
46
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Registers
The PCA interrupt vector is located at address 0033H, the Keyboard interrupt vector is
located at address 004BH. All other vectors addresses are the same as standard C52
devices.
Table 32. Priority Level Bit Values
IPH.x
IPL.x
Interrupt Level Priority
0
0
1
1
0
1
0
1
0 (Lowest)
1
2
3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
47
4113B–8051–03/05
Table 33. IEO Register
IE0 - Interrupt Enable Register (A8h)
7
6
5
4
3
2
1
0
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
Bit
Bit
Number
Mnemonic Description
Enable All interrupt bit
7
6
EA
EC
Cleared to disable all interrupts.
Set to enable all interrupts.
PCA interrupt enable bit
Cleared to disable.
Set to enable.
Timer 2 overflow interrupt enable bit
5
4
3
2
1
0
ET2
ES
Cleared to disable Timer 2 overflow interrupt.
Set to enable Timer 2 overflow interrupt.
Serial port enable bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 1 overflow interrupt enable bit
Cleared to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
ET1
EX1
ET0
EX0
External interrupt 1 enable bit
Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
Timer 0 overflow interrupt enable bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
External interrupt 0 enable bit
Cleared to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0000 0000b
Bit addressable
48
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 34. IPL0 Register
IPL0 - Interrupt Priority Register (B8h)
7
-
6
5
4
3
2
1
0
PPCL
PT2L
PSL
PT1L
PX1L
PT0L
PX0L
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The value read from this bit is indeterminate. Do not set this bit.
PCA interrupt priority bit
Refer to PPCH for priority level.
PPCL
PT2L
PSL
Timer 2 overflow interrupt priority bit
Refer to PT2H for priority level.
Serial port priority bit
Refer to PSH for priority level.
Timer 1 overflow interrupt priority bit
Refer to PT1H for priority level.
PT1L
PX1L
PT0L
PX0L
External interrupt 1 priority bit
Refer to PX1H for priority level.
Timer 0 overflow interrupt priority bit
Refer to PT0H for priority level.
External interrupt 0 priority bit
Refer to PX0H for priority level.
Reset Value = X000 0000b
Bit addressable
49
4113B–8051–03/05
Table 35. IPH0 Register
IPH0 - Interrupt Priority High Register (B7h)
7
6
5
4
3
2
1
0
-
PPCH
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Bit
Bit
Number
Mnemonic Description
Reserved
7
-
The value read from this bit is indeterminate. Do not set this bit.
PCA interrupt priority high bit.
PPCH PPCL Priority Level
0
0
1
1
0
1
0
1
Lowest
6
PPCH
PT2H
PSH
Highest
Timer 2 overflow interrupt priority high bit
PT2H PT2L Priority Level
0
0
1
1
0
1
0
1
Lowest
5
4
3
2
1
0
Highest
Serial port priority high bit
PSH
0
0
1
1
PSL
0
1
0
1
Priority Level
Lowest
Highest
Timer 1 overflow interrupt priority high bit
PT1H PT1L Priority Level
0
0
1
1
0
1
0
1
Lowest
PT1H
PX1H
PT0H
PX0H
Highest
External interrupt 1 priority high bit
PX1H PX1L Priority Level
0
0
1
1
0
1
0
1
Lowest
Highest
Timer 0 overflow interrupt priority high bit
PT0H PT0L Priority Level
0
0
1
1
0
1
0
1
Lowest
Highest
External interrupt 0 priority high bit
PX0H PX0L Priority Level
0
0
1
1
0
1
0
1
Lowest
Highest
Reset Value = X000 0000b
Not bit addressable
50
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 36. IE1 Register
IE1 - Interrupt Enable Register (B1h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
KBD
Bit
Bit
Mnemonic Description
Number
7
6
5
4
3
2
1
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Keyboard interrupt Enable bit
0
KBD
Cleared to disable keyboard interrupt.
Set to enable keyboard interrupt.
Reset Value = XXXX XXX0b
Bit addressable
51
4113B–8051–03/05
Table 37. IPL1 Register
IPL1 - Interrupt Priority Register (B2h)
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
KBDL
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Keyboard Interrupt Priority bit
Refer to KBDH for priority level.
KBDL
Reset Value = XXXX XXX0b
Bit addressable
52
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 38. IPH1 Register
IPH1 - Interrupt Priority High Register (B3h)
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
KBDH
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
-
-
-
-
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Keyboard interrupt Priority High bit
KB DH KBDL Priority Level
0
0
1
1
0
1
0
1
Lowest
0
KBDH
Highest
Reset Value = XXXX XXX0b
Not bit addressable
53
4113B–8051–03/05
Interrupt Sources and
Vector Addresses
Table 39. Interrupt Sources and Vector Addresses
Vector
Interrupt
Request
Number
Polling Priority
Interrupt Source
Reset
Address
0
1
2
3
4
5
6
7
8
0
1
2
3
4
6
7
5
8
0000h
0003h
000Bh
0013h
001Bh
0023h
002Bh
0033h
003Bh
INT0
IE0
Timer 0
INT1
TF0
IE1
Timer 1
UART
IF1
RI+TI
Timer 2
PCA
TF2+EXF2
CF + CCFn (n = 0-4)
KBDIT
Keyboard
54
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Keyboard Interface
The T8xc51Rx2 implement a keyboard interface allowing the connection of a 8 x n
matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both
high or low level. These inputs are available as alternate function of P1 and allow to exit
from idle and power-down modes.
The keyboard interfaces with the C51 core through 3 special function registers: KBLS,
the Keyboard Level Selection register (Table 42), KBE, The Keyboard Interrupt Enable
register (Table 41), and KBF, the Keyboard Flag register (Table 40).
Interrupt
The keyboard inputs are considered as 8 independent interrupt sources sharing the
same interrupt vector. An interrupt enable bit (KBD in IE1) allows global enable or dis-
able of the keyboard interrupt (see Figure 20). As detailed in Figure 21 each keyboard
input has the capability to detect a programmable level according to KBLS.x bit value.
Level detection is then reported in interrupt flags KBF.x that can be masked by software
using KBE.x bits.
This structure allow keyboard arrangement from 1 x n to 8 x n matrix and allows usage
of P1 inputs for other purpose.
Figure 20. Keyboard Interface Block Diagram
VCC
0
P1:x
KBF.x
1
KBE.x
Internal Pull-up
KBLS.x
Figure 21. Keyboard Input Circuitry
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
KBDIT
Keyboard Interface
Interrupt Request
KBD
IE1
Power Reduction Mode
P1 inputs allow exit from idle and power-down modes as detailed in Section “Power-
down Mode”, page 59.
55
4113B–8051–03/05
Registers
Table 40. KBF Register
KBF - Keyboard Flag Register (9Eh)
7
6
5
4
3
2
1
0
KBF7
KBF6
KBF5
KBF4
KBF3
KBF2
KBF1
KBF0
Bit
Bit
Number
Mnemonic Description
Keyboard line 7 flag
Set by hardware when the Port line 7 detects a programmed level. It generates a
Keyboard interrupt request if the KBKBIE.7 bit in KBIE register is set.
Must be cleared by software.
7
6
5
4
3
2
1
0
KBF7
KBF6
KBF5
KBF4
KBF3
KBF2
KBF1
KBF0
Keyboard line 6 flag
Set by hardware when the Port line 6 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.6 bit in KBIE register is set.
Must be cleared by software.
Keyboard line 5 flag
Set by hardware when the Port line 5 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.5 bit in KBIE register is set.
Must be cleared by software.
Keyboard line 4 flag
Set by hardware when the Port line 4 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.4 bit in KBIE register is set.
Must be cleared by software.
Keyboard line 3 flag
Set by hardware when the Port line 3 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.3 bit in KBIE register is set.
Must be cleared by software.
Keyboard line 2 flag
Set by hardware when the Port line 2 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.2 bit in KBIE register is set.
Must be cleared by software.
Keyboard line 1 flag
Set by hardware when the Port line 1 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.1 bit in KBIE register is set.
Must be cleared by software.
Keyboard line 0 flag
Set by hardware when the Port line 0 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE.0 bit in KBIE register is set.
Must be cleared by software.
Reset Value = 0000 0000b
56
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 41. KBE Register
KBE - Keyboard Input Enable Register (9Dh)
7
6
5
4
3
2
1
0
KBE7
KBE6
KBE5
KBE4
KBE3
KBE2
KBE1
KBE0
Bit
Bit
Number
Mnemonic Description
Keyboard line 7 enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.7 bit in KBF register to generate an interrupt request.
7
6
5
4
3
2
1
0
KBE7
KBE6
KBE5
KBE4
KBE3
KBE2
KBE1
KBE0
Keyboard line 6 enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.6 bit in KBF register to generate an interrupt request.
Keyboard line 5 enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.5 bit in KBF register to generate an interrupt request.
Keyboard line 4 enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.4 bit in KBF register to generate an interrupt request.
Keyboard line 3 enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.3 bit in KBF register to generate an interrupt request.
Keyboard line 2 enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.2 bit in KBF register to generate an interrupt request.
Keyboard line 1 enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.1 bit in KBF register to generate an interrupt request.
Keyboard line 0 enable bit
Cleared to enable standard I/O pin.
Set to enable KBF.0 bit in KBF register to generate an interrupt request.
Reset Value = 0000 0000b
57
4113B–8051–03/05
Table 42. KBLS Register
KBLS - Keyboard Level Selector Register (9Ch)
7
6
5
4
3
2
1
0
KBLS7
KBLS6
KBLS5
KBLS4
KBLS3
KBLS2
KBLS1
KBLS0
Bit
Bit
Number
Mnemonic Description
Keyboard line 7 level selection bit
7
6
5
4
3
2
1
0
KBLS7
KBLS6
KBLS5
KBLS4
KBLS3
KBLS2
KBLS1
KBLS0
Cleared to enable a low level detection on Port line 7.
Set to enable a high level detection on Port line 7.
Keyboard line 6 level selection bit
Cleared to enable a low level detection on Port line 6.
Set to enable a high level detection on Port line 6.
Keyboard line 5 level selection bit
Cleared to enable a low level detection on Port line 5.
Set to enable a high level detection on Port line 5.
Keyboard line 4 level selection bit
Cleared to enable a low level detection on Port line 4.
Set to enable a high level detection on Port line 4.
Keyboard line 3 level selection bit
Cleared to enable a low level detection on Port line 3.
Set to enable a high level detection on Port line 3.
Keyboard line 2 level selection bit
Cleared to enable a low level detection on Port line 2.
Set to enable a high level detection on Port line 2.
Keyboard line 1 level selection bit
Cleared to enable a low level detection on Port line 1.
Set to enable a high level detection on Port line 1.
Keyboard line 0 level selection bit
Cleared to enable a low level detection on Port line 0.
Set to enable a high level detection on Port line 0.
Reset Value = 0000 0000b
58
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Power Management
Idle Mode
An instruction that sets PCON.0 indicates that it is the last instruction to be executed
before going into Idle mode. In Idle mode, the internal clock signal is gated off to the
CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is pre-
served in its entirety: the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during idle. The port pins hold the
logical states they had at the time Idle was activated. ALE and PSEN hold at logic high
level.
There are two ways to terminate the Idle mode. Activation of any enabled interrupt will
cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will
be serviced, and following RETI the next instruction to be executed will be the one fol-
lowing the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred dur-
ing normal operation or during idle. For example, an instruction that activates idle can
also set one or both flag bits. When idle is terminated by an interrupt, the interrupt ser-
vice routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
Power-down Mode
To save maximum power, a power-down mode can be invoked by software (refer to
Table 30, PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-
down mode is the last instruction executed. The internal RAM and SFRs retain their
value until the power-down mode is terminated. VCC can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from power-
down. To properly terminate power-down, the reset or external interrupt should not be
executed before VCC is restored to its normal operating level and must be held active
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0, INT1 and Keyboard Interrupts are useful to exit from
power-down. Thus, the interrupt must be enabled and configured as level - or edge -
sensitive interrupt input. When Keyboard Interrupt occurs after a power-down mode,
1024 clocks are necessary to exit to power-down mode and enter in operating mode.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as
detailed in Figure 22. When both interrupts are enabled, the oscillator restarts as soon
as one of the two inputs is held low and power-down exit will be completed when the first
input is released. In this case, the higher priority interrupt service routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put T8xc51Rx2 into power-down mode.
59
4113B–8051–03/05
Figure 22. Power-down Exit Waveform
INT0
INT1
XTAL
Active Phase
Power-down Phase
OscillatoR Restart Phase
Active Phase
Exit from power-down by reset redefines all the SFRs, exit from power-down by external
interrupt does no affect the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal
RAM content.
Note:
If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence
is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and
idle mode is not entered.
Table 43 shows the state of ports during idle and power-down modes.
Table 43. State of Ports
Mode
Program Memory
ALE
PSEN
PORT0
Port Data(1)
Floating
PORT1
PORT2
PORT3
Idle
Internal
External
Internal
External
1
1
0
0
1
1
0
0
Port Data
Port Data
Port Data
Port Data
Port Data
Address
Port Data
Port Data
Port Data
Port Data
Port Data
Port Data
Idle
Power-down
Power-down
Port Dat(1)
Floating
Note:
1. Port 0 can force a 0 level. A "one" will leave port floating.
60
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Hardware Watchdog
Timer
The WDT is intended as a recovery method in situations where the CPU may be sub-
jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer
Reset (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator
is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH
pulse at the RST-pin.
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. Therefore, the user must
reset the WDT at least every 16383 machine cycles. To reset the WDT the user must
write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse
at the RST-pin. The RESET pulse duration is 96 x TCLK PERIPH, where TCLK PERIPH= 1/FCLK
PERIPH. To make the best use of the WDT, it should be serviced in those sections of code
that will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 27 counter has been added to extend the Time-out
capability, ranking from 16 ms to 2s @ Fosc = 12 MHz. To manage this feature, refer to
WDTPRG register description, Table 44.
Table 44. WDTRST Register
WDTRST - Watchdog Reset Register (0A6h)
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Reset Value = XXXX XXXXb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
61
4113B–8051–03/05
Table 45. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
7
-
6
-
5
-
4
-
3
-
2
1
0
S2
S1
S0
Bit
Bit
Number
Mnemonic Description
7
6
5
4
3
2
1
0
-
-
Reserved
-
The value read from this bit is undetermined. Do not try to set this bit.
-
-
S2
S1
S0
WDT Time-out select bit 2
WDT Time-out select bit 1
WDT Time-out select bit 0
S2
0
0
0
0
1
1
1
1
S1 S0 Selected Time-out
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(214 - 1) machine cycles, 16. 3 ms @ Fosc =12 MHz
(215 - 1) machine cycles, 32.7 ms @ Fosc=12 MHz
(216 - 1) machine cycles, 65. 5 ms @ Fosc=12 MHz
(217 - 1) machine cycles, 131 ms @ Fosc=12 MHz
(218 - 1) machine cycles, 262 ms @ Fosc=12 MHz
(219 - 1) machine cycles, 542 ms @ Fosc=12 MHz
(220 - 1) machine cycles, 1.05 s @ Fosc=12 MHz
(221 - 1) machine cycles, 2.09 s @ Fosc=12 MHz
Reset Value = XXXX X000
WDT During Power-down In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode the user does not need to service the WDT. There are 2 methods of
and Idle
exiting Power-down mode: by a hardware reset or via a level activated external inter-
rupt which is enabled prior to entering Power-down mode. When Power-down is exited
with hardware reset, servicing the WDT should occur as normal, whenever the
T8xc51Rx2 is reset. Exiting Power-down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of power-down,
it is better to reset the WDT just before entering power-down.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
T8xc51Rx2 while in Idle mode, the user should always set up a timer that will periodi-
cally exit Idle, service the WDT, and re-enter Idle mode.
62
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
ROM
ROM Structure
The T89C51RB2/RC2 ROM memory is divided in two different arrays:
•
•
The code array:16/32K bytes.
The config byte: 1 byte.
Hardware Config Byte
The config byte sets the starting microcontroller options and the security levels.
The starting options are X2 mode, and XRAM.
7
6
-
5
-
4
-
3
2
-
1
0
X2
XRAM
LB1
LB0
Bit
Bit
Number
Mnemonic
Description
X2 Mode
Cleared to force X2 mode (6 clocks per instruction)
7
X2
Set to force X1 mode, Standard Mode.
6
5
4
-
-
-
Reserved
Reserved
Reserved
XRAM config bit
3
XRAM
Set this bit to enable XRAM.
Clear this bit to disable XRAM.
2
-
Reserved
User Program ROM Lock Bits
see Table 46.
1-0
LB0-1
ROM Lock System
The program Lock system, when programmed, protects the on-chip program against
software piracy.
Program ROM Lock Bits
Table 46. Program Lock bits
Program Lock Bits
Protection Description
Security
level
LB0
U
LB1
U
1
2
No program lock features enabled.
Reserved. Do not use.
P
U
MOVC instruction executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on reset.
Verify disable.
3
U
P
Notes: 1. U: unprogrammed
P: programmed
2. The lock bits when programmed according to Table 46 will provide different level of
protection for the on-chip code and data.
63
4113B–8051–03/05
Power-off Flag
The Power-off flag allows the user to distinguish between a “cold start” reset and a
“warm start” reset.
A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while
VCC is still applied to the device and could be generated for example by an exit from
power-down.
The Power-off flag (POF) is located in PCON register (Table 47). POF is set by hard-
ware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by
software allowing the user to determine the type of reset.
Table 47. PCON Register
PCON - Power Control Register (87h)
7
6
5
-
4
3
2
1
0
SMOD1
SMOD0
POF
GF1
GF0
PD
IDL
Bit
Bit
Number
Mnemonic Description
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
7
6
5
SMOD1
Serial port Mode bit 0
SMOD0 Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Power-off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by
software.
4
POF
General purpose Flag
3
2
1
0
GF1
GF0
PD
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
IDL
Reset Value = 00X1 0000b
Not bit addressable
64
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with
external program or data memory. Nevertheless, during internal code execution, ALE
signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting
AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no
longer output but remains active during MOVX and MOVC instructions and external
fetches. During ALE disabling, ALE pin is weakly pulled high.
Table 48. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
5
4
3
2
1
0
-
-
M0
-
XRS1
XRS0
EXTRAM
AO
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
-
The value read from this bit is indeterminate. Do not set this bit
Reserved
-
The value read from this bit is indeterminate. Do not set this bit
Pulse length
Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock
periods (default).
5
M0
Set to stretch MOVX control: the RD and the WR pulse length is 30 clock
periods.
Reserved
4
3
-
The value read from this bit is indeterminate. Do not set this bit
XRS1
XRAM Size
XRS1
0
XRS0 XRAM Size
0
1
0
1
256 bytes (default)
0
1
1
512 bytes
768 bytes
1024 bytes
2
XRS0
EXTRAM bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
EXTRAM Set to access external memory.
Programmed by hardware after Power-up regarding Hardware Security Byte
1
0
(HSB), default setting, XRAM selected.
ALE Output bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if
X2 mode is used) (default). Set, ALE is active only during a MOVX or MOVC
instructione is used.
AO
65
4113B–8051–03/05
Electrical Characteristics
Absolute Maximum Ratings
Note:
Stresses at or above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions may affect device
reliability.
C = commercial......................................................0°C to 70°C
I = industrial ........................................................-40°C to 85°C
Storage Temperature.................................... -65°C to + 150°C
Voltage on VCC to VSS (standard voltage).........-0.5V to + 6.5V
Voltage on VCC to VSS (low voltage)..................-0.5V to + 4.5V
Voltage on Any Pin to VSS..........................-0.5V to VCC + 0.5V
Power Dissipation.............................................................. 1 W
Power dissipation value is based on the maximum
allowable die temperature and the thermal resistance
of the package.
DC Parameters for
Standard Voltage
TA = 0°C to +70°C; VSS = 0V; VCC = 4.5V to 5.5V; F = 10 to 40 MHz
TA = -40°C to +85°C; VSS = 0V; VCC =4.5V to 5.5V; F = 10 to 40 MHz
Symbol
VIL
Parameter
Min
-0.5
Typ
Max
Unit
V
Test Conditions
Input Low Voltage
0.2 VCC - 0.1
VCC + 0.5
VCC + 0.5
VIH
Input High Voltage except RST, XTAL1
Input High Voltage RST, XTAL1
0.2 VCC + 0.9
0.7 VCC
V
VIH1
V
0.3
0.45
1.0
V
V
V
IOL = 100 µA(4)
IOL = 1.6 mA(4)
IOL = 3.5 mA(4)
VOL
Output Low Voltage, ports 1, 2, 3, 4 (6)
0.3
0.45
1.0
V
V
V
IOL = 200 µA(4)
IOL = 3.2 mA(4)
IOL = 7.0 mA(4)
VOL1
Output Low Voltage, port 0, ALE, PSEN (6)
I
I
I
OH = -10 µA
OH = -30 µA
OH = -60 µA
VCC - 0.3
V
V
V
VOH
Output High Voltage, ports 1, 2, 3, 4
V
V
CC - 0.7
CC - 1.5
V
CC = 5V 10%
I
I
I
OH = -200 µA
OH = -3.2 mA
OH = -7.0 mA
VCC - 0.3
V
V
V
VOH1
Output High Voltage, port 0, ALE, PSEN
V
V
CC - 0.7
CC - 1.5
V
CC = 5V 10%
RRST
IIL
RST Pull-down Resistor
50
200(5)
250
-50
kΩ
µA
µA
µA
Logical 0 Input Current ports 1, 2, 3, 4 and 5
Input Leakage Current
VIN = 0.45V
ILI
10
0.45V < VIN < VCC
VIN = 2.0 V
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3, 4
-650
Fc = 3 MHz
TA = 25°C
CIO
Capacitance of I/O Buffer
10
pF
IPD
Power-down Current
100
150
µA
4.5V < VCC < 5.5V(3)
ICCOP
ICCIDLE
Power Supply Current on normal mode
Power Supply Current on idle mode
0.29 x Frequency (MHz) + 4
0.16 x Frequency (MHz) + 4
mA VCC = 5.5V(1)
mA VCC = 5.5V(2)
66
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
DC Parameters for
Standard Voltage (2)
TA = 0°C to +70°C; VSS = 0 V; VCC = 2.7V to 5.5V; F = 10 to 40 MHz
TA = -40°C to +85°C; VSS = 0 V; VCC = 2.7V to 5.5V; F = 10 to 40 MHz
Symbol
VIL
Parameter
Min
-0.5
Typ(5)
Max
0.2 VCC - 0.1
VCC + 0.5
VCC + 0.5
0.45
Unit Test Conditions
Input Low Voltage
V
V
V
VIH
Input High Voltage except XTAL1, RST
Input High Voltage, XTAL1, RST
Output Low Voltage, ports 1, 2, 3, 4 and 5 (6)
Output Low Voltage, port 0, ALE, PSEN (6)
Output High Voltage, ports 1, 2, 3, 4 and 5
Output High Voltage, port 0, ALE, PSEN
Logical 0 Input Current ports 1, 2, 3, 4 and 5
Input Leakage Current
0.2 VCC + 0.9
0.7 VCC
VIH1
VOL
VOL1
VOH
VOH1
IIL
V
V
IOL = 0.8 mA(4)
IOL = 1.6 mA(4)
IOH = -10 µA
0.45
0.9 VCC
0.9 VCC
V
V
IOH = -40 µA
-50
10
µA
µA
VIN = 0.45V
ILI
0.45V < VIN < VCC
Logical 1 to 0 Transition Current, ports 1, 2, 3, 4
and 5
ITL
-650
250
10
µA
kΩ
pF
µA
VIN = 2.0V
RRST
CIO
RST Pulldown Resistor
Capacitance of I/O Buffer
50
200
120
Fc = 3 MHz
TA = 25°C
IPD
Power-down Current
150
VCC =2.7V to 5.5V(3)
ICCOP
ICCIDLE
Power Supply Current on normal mode
Power Supply Current on idle mode
0.29 x Frequency (MHz) + 4
0.16 x Frequency (MHz) + 4
mA VCC = 5.5V(1)
mA VCC = 5.5V(2)
67
4113B–8051–03/05
DC Parameters for Low
Voltage
TA = 0°C to +70°C; VSS = 0V; VCC = 2.7V to 3.6V; F = 10 to 40 MHz
TA = -40°C to +85°C; VSS = 0V; VCC = 2.7V to 3.6V; F = 10 to 40 MHz
Symbol
VIL
Parameter
Min
-0.5
Typ
Max
0.2 VCC - 0.1
VCC + 0.5
VCC + 0.5
0.45
Unit
V
Test Conditions
Input Low Voltage
VIH
Input High Voltage except RST, XTAL1
Input High Voltage, RST, XTAL1
Output Low Voltage, ports 1, 2, 3, 4(6)
Output Low Voltage, port 0, ALE, PSEN (6)
Output High Voltage, ports 1, 2, 3, 4
Output High Voltage, port 0, ALE, PSEN
Logical 0 Input Current ports 1, 2, 3, 4
Input Leakage Current
0.2 VCC + 0.9
0.7 VCC
V
VIH1
VOL
VOL1
VOH
VOH1
IIL
V
V
IOL = 0.8 mA(4)
IOL = 1.6 mA(4)
IOH = -10 µA
IOH = -40 µA
VIN = 0.45V
0.45
V
0.9 VCC
0.9 VCC
V
V
-50
10
µA
µA
µA
kΩ
ILI
0.45V < VIN < VCC
VIN = 2.0V
ITL
Logical 1 to 0 Transition Current, ports 1, 2, 3,
RST Pulldown Resistor
-650
250
RRST
50
200 (5)
Fc = 3 MHz
TA = 25°C
CIO
IPD
Capacitance of I/O Buffer
Power-down Current
10
50
pF
VCC = 2.7V to
3.6V(3)
10 (5)
µA
ICCOP
Power Supply Current on normal mode
Power Supply Current on idle mode
0.31 x Frequency (MHz) + 4
0.2 x Frequency (MHz) + 4
mA VCC = 3.6V(1)
mA VCC = 3.6V(2)
ICCIDLE
Notes: 1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 26.),
VIL = VSS + 0.5V,
VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure
23).
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V,
VIH = VCC - 0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 24).
3. Power-down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fig-
ure 25).
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1
and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7. For other values, please contact your sales office.
68
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Figure 23. ICC Test Condition, Active Mode
VCC
ICC
VCC
VCC
P0
EA
VCC
RST
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 24. ICC Test Condition, Idle Mode
VCC
ICC
VCC
VCC
P0
EA
RST
XTAL2
XTAL1
VSS
(NC)
CLOCK
SIGNAL
All other pins are disconnected.
Figure 25. ICC Test Condition, Power-down Mode
VCC
ICC
VCC
VCC
P0
EA
RST
XTAL2
XTAL1
VSS
(NC)
All other pins are disconnected.
Figure 26. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V
0.7VCC
0.2VCC-0.1
0.45V
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
69
4113B–8051–03/05
AC Parameters
Explanation of the AC
Symbols
Each timing symbol has 5 characters. The first character is always a “t” (stands for time).
The other characters, depending on their positions, stand for the name of a signal or the
logical status of that signal. The following is a list of all the characters and what they
stand for.
Example:TAVLL = Time for Address Valid to ALE Low.
T
LLPL = Time for ALE Low to PSEN Low.
(Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other
outputs = 80 pF.)
Table 49 Table 52, and Table 54 give the description of each AC symbols.
Table 51, Table 53 and Table 55 give for each range the AC parameter.
Table 50, Table 51 and Table 56 gives the frequency derating formula of the AC param-
eter for each speed range description. To calculate each AC symbols. take the x value
in the correponding column (-M or -L) and use this value in the formula.
Example: TLLIU for -M and 20 MHz, Standard clock.
x = 35 ns
T = 50 ns
T
CCIV = 4T - x = 165 ns
External Program Memory
Characteristics
Table 49. Symbol Description
Symbol
T
Parameter
Oscillator clock period
ALE pulse width
TLHLL
TAVLL
TLLAX
TLLIV
TLLPL
TPLPH
TPLIV
TPXIX
TPXIZ
TAVIV
TPLAZ
Address Valid to ALE
Address Hold After ALE
ALE to Valid Instruction In
ALE to PSEN
PSEN Pulse Width
PSEN to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction FloatAfter PSEN
Address to Valid Instruction In
PSEN Low to Address Float
70
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 50. AC Parameters for a Fix Clock
Symbol
-M
-L
Units
Min
25
35
5
Max
Min
25
35
5
Max
T
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TLHLL
TAVLL
TLLAX
TLLIV
TLLPL
TPLPH
TPLIV
TPXIX
TPXIZ
TAVIV
TPLAZ
5
5
65
30
65
30
5
5
50
50
0
0
10
80
10
10
80
10
Table 51. AC Parameters for a Variable Clock
Standard
X Parameter for - X Parameter for
Symbol
TLHLL
TAVLL
TLLAX
TLLIV
Type
Min
Clock
2 T - x
T - x
T - x
4 T - x
T - x
3 T - x
3 T - x
x
X2 Clock
T - x
M Range
-L Range
Units
15
20
20
35
15
25
45
0
15
20
20
35
15
25
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
0.5 T - x
0.5 T - x
2 T - x
0.5 T - x
1.5 T - x
1.5 T - x
x
Min
Max
Min
TLLPL
TPLPH
TPLIV
Min
Max
Min
TPXIX
TPXIZ
TAVIV
Max
Max
Max
T - x
5 T - x
x
0.5 T - x
2.5 T - x
x
15
45
10
15
45
10
TPLAZ
71
4113B–8051–03/05
External Program Memory
Read Cycle
12 TCLCL
TLHLL
TLLIV
TLLPL
ALE
TPLPH
PSEN
TPXAV
TPXIZ
TLLAX
TAVLL
TPLIV
TPLAZ
TPXIX
INSTR IN
PORT 0
PORT 2
INSTR IN
A0-A7
A0-A7
INSTR IN
TAVIV
ADDRESS A8 - A15
ADDRESS
OR SFR-P2
ADDRESS A8-A15
External Data Memory
Characteristics
Table 52. Symbol Description
Symbol
TRLRH
TWLWH
TRLDV
TRHDX
TRHDZ
TLLDV
Parameter
RD Pulse Width
WR Pulse Width
RD to Valid Data In
Data Hold After RD
Data Float After RD
ALE to Valid Data In
Address to Valid Data In
ALE to WR or RD
Address to WR or RD
TAVDV
TLLWL
TAVWL
TQVWX
TQVWH
TWHQX
TRLAZ
TWHLH
Data Valid to WR Transition
Data set-up to WR High
Data Hold After WR
RD Low to Address Float
RD or WR High to ALE high
72
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 53. AC Parameters for a Fix Clock
-M
-L
Symbol
TRLRH
TWLWH
TRLDV
TRHDX
TRHDZ
TLLDV
Min
125
125
Max
Min
125
125
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
95
95
0
0
25
25
155
160
105
155
160
105
TAVDV
TLLWL
45
70
5
45
70
5
TAVWL
TQVWX
TQVWH
TWHQX
TRLAZ
155
10
0
155
10
0
TWHLH
5
45
5
45
73
4113B–8051–03/05
Standard
Clock
X parameter for - X parameter for -
Symbol
TRLRH
TWLWH
TRLDV
TRHDX
TRHDZ
TLLDV
Type
Min
Min
Max
Min
Max
Max
Max
Min
Max
Min
Min
Min
Min
Max
Min
Max
X2 Clock
3 T - x
3 T - x
2.5 T - x
x
M range
25
25
30
0
L range
25
25
30
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6 T - x
6 T - x
5 T - x
x
2 T - x
8 T - x
9 T - x
3 T - x
3 T + x
4 T - x
T - x
T - x
25
45
65
30
30
30
20
20
15
0
25
45
65
30
30
30
20
20
15
0
4T -x
TAVDV
TLLWL
4.5 T - x
1.5 T - x
1.5 T + x
2 T - x
0.5 T - x
3.5 T - x
0.5 T - x
x
TLLWL
TAVWL
TQVWX
TQVWH
TWHQX
TRLAZ
TWHLH
TWHLH
7 T - x
T - x
x
T - x
0.5 T - x
0.5 T + x
20
20
20
20
T + x
External Data Memory Write
Cycle
TWHLH
ALE
PSEN
WR
TLLWL
TWLWH
TQVWX
TWHQX
TLLAX
A0-A7
TQVWH
DATA OUT
PORT 0
TAVWL
ADDRESS
OR SFR-P2
PORT 2
ADDRESS A8 - A15 OR SFR P2
74
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
External Data Memory Read Cycle
TWHLH
TLLDV
ALE
PSEN
RD
TLLWL
TRLRH
TRHDZ
TAVDV
TLLAX
TRHDX
PORT 0
A0-A7
DATA IN
TRLAZ
TAVWL
ADDRESS
OR SFR-P2
PORT 2
ADDRESS A8-A15 OR SFR P2
Serial Port Timing - Shift
Register Mode
Table 54. Symbol Description
Symbol
TXLXL
Parameter
Serial port clock cycle time
TQVHX
TXHQX
TXHDX
TXHDV
Output data set-up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
Table 55. AC Parameters for a Fix Clock
-M
-L
Symbol
TXLXL
Min
300
200
30
Max
Min
300
200
30
Max
Units
ns
TQVHX
TXHQX
TXHDX
TXHDV
ns
ns
0
0
ns
117
117
ns
Table 56. AC Parameters for a Variable Clock
Standard
Clock
X Parameter for - X Parameter for -L
Symbol
TXLXL
Type
Min
Min
Min
Min
Max
X2 Clock
6 T
M Range
Range
Units
12 T
10 T - x
2 T - x
x
ns
ns
ns
ns
ns
TQVHX
TXHQX
TXHDX
TXHDV
5 T - x
T - x
50
20
0
50
20
0
x
10 T - x
5 T- x
133
133
75
4113B–8051–03/05
Shift Register Timing Waveforms
0
1
2
3
4
5
6
7
8
INSTRUCTION
ALE
TXLXL
CLOCK
TXHQX
1
TQVXH
0
2
3
4
5
6
7
OUTPUT DATA
TXHDX
SET TI
TXHDV
WRITE to SBUF
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
CLEAR RI
External Clock Drive Waveforms
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCX
TCLCH
TCLCX
TCHCL
TCLCL
AC Testing Input/Output Waveforms
VCC -0.5V
0.45V
0.2 VCC + 0.9
0.2 VCC - 0.1
INPUT/OUTPUT
AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”.
Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.
Float Waveforms
FLOAT
VOH - 0.1 V
VOL + 0.1 V
VLOAD + 0.1 V
VLOAD - 0.1 V
VLOAD
For timing purposes as port pin is no longer floating when a 100 mV changes from load
voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level
occurs. IOL/IOH
≥
20 mA.
Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
76
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Figure 27. Internal Clock Signals
STATE4
INTERNAL
STATE5
P1 P2
STATE6
P1 P2
STATE1
STATE2
STATE3
P2
STATE4
STATE5
P2
CLOCK
P1
P2
P1
P2
P1 P2 P1
P1 P2 P1
XTAL2
ALE
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
EXTERNAL PROGRAM MEMORY FETCH
PSEN
P0
DATA
PCL OUT
DATA
PCL OUT
DATA
PCL OUT
SAMPLED
SAMPLED
SAMPLED
FLOAT
FLOAT
FLOAT
P2 (EXT)
INDICATES ADDRESS TRANSITIONS
READ CYCLE
RD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
DPL OR Rt OUT
DATA
SAMPLED
P0
FLOAT
P2
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WRITE CYCLE
WR
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
DPL OR Rt OUT
P0
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
DATA OUT
P2
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PORT OPERATION
MOV PORT SRC
OLD DATA
NEW DATA
P0 PINS SAMPLED
P0 PINS SAMPLED
MOV DEST P0
MOV DEST PORT (P1. P2. P3)
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
P1, P2, P3 PINS SAMPLED
(INCLUDES INTO. INT1. TO T1)
SERIAL PORT SHIFT CLOCK
RXD SAMPLED
TXD (MODE 0)
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however,
ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propaga-
tion also varies from output to output and component. Typically though (TA = 25°C fully loaded) RD and WR propagation
delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC
specifications.
77
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Ordering Information
Table 57. Ordering Information
Part Number
Memory Size
Supply Voltage
Package
PDIL40
Temperature Range
Commercial
Packing
Stick
Stick
Stick
Stick
Tray
AT80C51RD2-3CSCM
AT80C51RD2-3CSIM
AT80C51RD2-SLSCM
AT80C51RD2-SLSIM
AT80C51RD2-RLTIM
AT80C51RD2-3CSUM
AT80C51RD2-SLSUM
AT80C51RD2-RLTUM
AT80C51RD2-SLSIL
AT80C51RD2-RLTIL
AT80C51RD2-SLSUL
AT80C51RD2-RLTUL
PDIL40
Industrial
PLCC44
PLCC44
VQFP44
PDIL40
Commercial
Industrial
5V
Industrial
Industrial & Green
Industrial & Green
Industrial & Green
Industrial
Stick
Stick
Tray
ROMLess
PLCC44
VQFP44
PLCC44
VQFP44
PLCC44
VQFP44
Stick
Tray
Industrial
3V
Industrial & Green
Industrial & Green
Stick
Tray
78
4113B–8051–03/05
Table 57. Ordering Information (Continued)
Part Number
Memory Size
Supply Voltage
Package
PDIL40
Temperature Range
Commercial
Packing
Stick
Stick
Stick
Stick
Tray
AT83C51RB2xxx-3CSCM
AT83C51RB2xxx-3CSIM
AT83C51RB2xxx-SLSCM
AT83C51RB2xxx-SLSIM
AT83C51RB2xxx-RLTIM
AT83C51RB2xxx-3CSUM
AT83C51RB2xxx-SLSUM
AT83C51RB2xxx-RLTUM
AT83C51RC2xxx-3CSUM
AT83C51RC2xxx-SLSUM
AT83C51RC2xxx-RLTUM
AT83C51RB2xxx-SLSIL
AT83C51RB2xxx-RLTIL
AT83C51RB2xxx-SLSUL
AT83C51RB2xxx-RLTUL
PDIL40
Industrial
PLCC44
PLCC44
VQFP44
PDIL40
Commercial
Industrial
Industrial
5V
Industrial & Green
Industrial & Green
Industrial & Green
Industrial & Green
Industrial & Green
Industrial & Green
Industrial
Stick
Stick
Tray
PLCC44
VQFP44
PDIL40
16K bytes
Stick
Stick
Tray
PLCC44
VQFP44
PLCC44
VQFP44
PLCC44
VQFP44
Stick
Tray
Industrial
3V
Industrial & Green
Industrial & Green
Stick
Tray
Part Number
Memory Size
Supply Voltage
Package
PDIL40
Temperature Range
Commercial
Industrial
Packing
Stick
Stick
Stick
Stick
Tray
AT83C51RC2xxx-3CSCM
AT83C51RC2xxx-3CSIM
AT83C51RC2xxx-SLSCM
AT83C51RC2xxx-SLSIM
AT83C51RC2xxx-RLTIM
AT83C51RC2xxx-RLTIL
AT83C51RC2xxx-SLSIL
AT83C51RC2xxx-RLTUL
AT83C51RC2xxx-SLSUL
PDIL40
5V
PLCC44
PLCC44
VQFP44
VQFP44
PLCC44
VQFP44
PLCC44
Commercial
Industrial
32K bytes
Industrial
Industrial
Tray
Industrial
Stick
Tray
3V
Industrial & Green
Industrial & Green
Stick
79
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Package Information
PDIL40
80
4113B–8051–03/05
PLCC44
VQFP44
81
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
82
4113B–8051–03/05
Datasheet Change
Log
Changes from 4113A -
09/02 to 4113B -03/05
1. Added Green product ordering information.
83
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
Atmel Corporation
Atmel Operations
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Tel: 1(408) 441-0311
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Memory
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