AT80C51SND1C-ROTUL [ATMEL]
Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface; 单芯片闪存微控制器与MP3解码器和人机接口
| 型号： | AT80C51SND1C-ROTUL |
| 厂家： | 
ATMEL |
| 描述： | Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface |
| 文件： | 总42页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• MPEG I/II-Layer 3 Hardwired Decoder
– Stand-alone MP3 Decoder
– 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency
– Separated Digital Volume Control on Left and Right Channels (Software Control
using 31 Steps)
– Bass, Medium, and Treble Control (31 Steps)
– Bass Boost Sound Effect
– Ancillary Data Extraction
– CRC Error and MPEG Frame Synchronization Indicators
• Programmable Audio Output for Interfacing with Common Audio DAC
– PCM Format Compatible
Single-Chip
Flash
Microcontroller
with MP3
Decoder and
Human
Interface
– I2S Format Compatible
• 8-bit MCU C51 Core Based (FMAX = 20 MHz)
• 2304 Bytes of Internal RAM
• 64K Bytes of Code Memory
– AT89C51SND1C: Flash (100K Erase/Write Cycles)
– AT83SND1C: ROM
• 4K Bytes of Boot Flash Memory (AT89C51SND1C)
– ISP: Download from USB (standard) or UART (option)
• External Code Memory
– AT80C51SND1C: ROMless
• USB Rev 1.1 Controller
– Full Speed Data Transmission
• Built-in PLL
– MP3 Audio Clocks
– USB Clock
• MultiMedia Card® Interface Compatibility
• Atmel DataFlash® SPI Interface Compatibility
• IDE/ATAPI Interface
• 2 Channels 10-bit ADC, 8 kHz (8-true bit)
– Battery Voltage Monitoring
– Voice Recording Controlled by Software
• Up to 44 Bits of General-purpose I/Os
– 4-bit Interrupt Keyboard Port for a 4 x n Matrix
– SmartMedia® Software Interface
• 2 Standard 16-bit Timers/Counters
• Hardware Watchdog Timer
AT83SND1C
AT89C51SND1C
AT80C51SND1C
• Standard Full Duplex UART with Baud Rate Generator
• Two Wire Master and Slave Modes Controller
• SPI Master and Slave Modes Controller
• Power Management
– Power-on Reset
– Software Programmable MCU Clock
– Idle Mode, Power-down Mode
• Operating Conditions:
– 3V, 10%, 25 mA Typical Operating at 25°C
– Temperature Range: -40°C to +85°C
• Packages
– TQFP80, BGA81, PLCC84 (Development Board)
– Dice
4109JS–8051–10/06
1. Description
The AT8xC51SND1C are fully integrated stand-alone hardwired MPEG I/II-Layer 3 decoder with
a C51 microcontroller core handling data flow and MP3-player control.
The AT89C51SND1C includes 64K Bytes of Flash memory and allows In-System Programming
through an embedded 4K Bytes of Boot Flash memory.
The AT83SND1C includes 64K Bytes of ROM memory.
The AT80C51SND1C does not include any code memory.
The AT8xC51SND1C include 2304 Bytes of RAM memory.
The AT8xC51SND1C provides the necessary features for human interface like timers, keyboard
port, serial or parallel interface (USB, TWI, SPI, IDE), ADC input, I2S output, and all external
memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards).
2. Typical Applications
•
•
•
•
MP3-Player
PDA, Camera, Mobile Phone MP3
Car Audio/Multimedia MP3
Home Audio/Multimedia MP3
3. Block Diagram
Figure 3-1. AT8xC51SND1C Block Diagram
INT0
3
INT1
3
VDD VSS UVDD UVSS AVDD AVSS AREF AIN1:0 TXD RXD
T0
T1
SS MISO MOSI SCK SCL SDA
3
3
3
3
4
4
4
4
1
1
Interrupt
Handler Unit
Flash
ROM
UART
and
BRG
RAM
2304 Bytes
10-bit A to D
Converter
Timers 0/1
Watchdog
SPI/DataFlash
Controller
TWI
Controller
64 KBytes
Flash Boot
4 KBytes
8-Bit Internal Bus
C51 (X2 Core)
I/O
Ports
MP3 Decoder
Unit
I2S/PCM
Audio Interface
USB
Controller
Keyboard
Interface
MMC
Interface
IDE
Clock and PLL
Unit
Interface
1
FILT
X1 X2
RST
ISP
ALE
DOUT DCLK DSEL SCLK D+ D-
MCLK MDAT MCMD
KIN3:0
P0-P5
1 Alternate function of Port 1
3 Alternate function of Port 3
4 Alternate function of Port 4
2
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
4. Pin Description
4.1
Pinouts
Figure 4-1. AT8xC51SND1C 80-pin QFP Package
ALE
ISP1/PSEN2/NC
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P4.5
2
P4.4
3
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
VSS
4
5
6
7
P1.5
8
P1.6/SCL
P1.7/SDA
VDD
9
AT89C51SND1C-RO (FLASH)
AT83SND1C-RO (ROM)
AT80C51SND1C-RO (ROMLESS)
10
11
12
13
14
15
16
17
18
19
20
VDD
MCLK
MDAT
MCMD
RST
PVDD
FILT
PVSS
VSS
SCLK
X2
DSEL
X1
DCLK
DOUT
VSS
TST
UVDD
UVSS
VDD
Notes: 1. ISP pin is only available in AT89C51SND1C product.
Do not connect this pin on AT83SND1C product.
2. PSEN pin is only available in AT80C51SND1C product.
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4109JS–8051–10/06
Figure 4-2. AT8xC51SND1C 81-pin BGA Package
9
8
7
6
5
4
3
2
1
P2.0/
A8
P4.0/
MISO
P4.2/
SCK
P0.2/
AD2
P0.3/
AD3
P4.6
VDD
P5.0
ALE
A
ISP1/
PSEN2
NC
P4.1/
MOSI
P4.3/
SS
P0.1/
AD1
P0.4/
AD4
P0.0/
AD0
P4.4
P4.7
P1.1
B
C
P2.5/
A13
P2.2/
A10
P2.1/
A9
P1.0/
KIN0
P1.3/
KIN3
P1.2/
KIN2
P0.6
VSS
P5.1
P2.4/
A12
P2.6/
A14
P0.7/
AD7
P0.5/
AD5
P1.6/
SCL
P1.7/
SDA
P4.5
VSS
P1.5
X1
P1.4
VDD
X2
D
E
F
P2.3/
A11
P2.7/
A15
VDD
RST
FILT
PVDD
UVSS
VDD
P3.4/
T0
MCMD
SCLK
VSS
MCLK
DOUT
AIN1
MDAT
P5.3
AVDD
PVSS
TST
D-
P3.7/
RD
P3.5/
T1
DSEL
DCLK
VDD
VSS
UVDD
D+
G
H
J
P3.3/
INT1
P3.1/
TXD
AVSS
AREFN
AIN0
P3.6/
WR
P3.2/
INT0
P3.0/
RXD
P5.2
AREFP
VSS
Notes: 1. ISP pin is only available in AT89C51SND1C product.
Do not connect this pin on AT83SND1C and AT80C51SND1C product.
2. PSEN pin is only available in AT80C51SND1C product.
4
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
Figure 4-3. AT8xC51SND1C 84-pin PLCC Package
ALE 12
ISP 13
74 NC
73 P4.5
P1.0/KIN0 14
P1.1/KIN1 15
P1.2/KIN2 16
P1.3/KIN3 17
P1.4 18
72 P4.4
71 P2.2/A10
70 P2.3/A11
69 P2.4/A12
68 P2.5/A13
67 P2.6/A14
66 P2.7/A15
65 VSS
P1.5 19
P1.6/SCL 20
P1.7/SDA 21
AT89C51SND1C-SR (FLASH)
VDD 22
PAVDD 23
FILT 24
PAVSS 25
VSS 26
X2 27
64 VDD
63 MCLK
62 MDAT
61 MCMD
60 RST
59 SCLK
58 DSEL
57 DCLK
56 DOUT
55 VSS
NC 28
X1 29
TST 30
UVDD 31
UVSS 32
54 VDD
4.2
Signals
All the AT8xC51SND1C signals are detailed by functionality in Table 1 to Table 14.
Table 1. Ports Signal Description
Signal
Name
Alternate
Function
Type
Description
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. To
avoid any parasitic current consumption, floating P0 inputs must be
P0.7:0
I/O
AD7:0
polarized to VDD or VSS
.
KIN3:0
SCL
SDA
Port 1
P1.7:0
P2.7:0
I/O
I/O
P1 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 2
A15:8
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
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4109JS–8051–10/06
Signal
Name
Alternate
Function
Type
Description
RXD
TXD
INT0
INT1
T0
Port 3
P3.7:0
I/O
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
T1
WR
RD
MISO
MOSI
SCK
SS
Port 4
P4.7:0
P5.3:0
I/O
I/O
P4 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 5
-
P5 is a 4-bit bidirectional I/O port with internal pull-ups.
Table 2. Clock Signal Description
Signal
Name
Alternate
Function
Type
Description
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, its output is connected to this
pin. X1 is the clock source for internal timing.
X1
I
-
Output of the on-chip inverting oscillator amplifier
X2
O
I
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, leave X2 unconnected.
-
-
PLL Low Pass Filter input
FILT receives the RC network of the PLL low pass filter.
FILT
Table 3. Timer 0 and Timer 1 Signal Description
Signal
Name
Alternate
Function
Type
Description
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by
GATE0 bit in TCON register.
INT0
I
P3.2
External Interrupt 0
INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set,
bit IE0 is set by a falling edge on INT0. If bit IT0 is cleared, bit IE0 is set
by a low level on INT0.
Timer 1 Gate Input
INT1 serves as external run control for timer 1, when selected by
GATE1 bit in TCON register.
INT1
I
P3.3
External Interrupt 1
INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set,
bit IE1 is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set
by a low level on INT1.
6
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
Signal
Name
Alternate
Function
Type
Description
Timer 0 External Clock Input
T0
T1
I
When timer 0 operates as a counter, a falling edge on the T0 pin
increments the count.
P3.4
P3.5
Timer 1 External Clock Input
When timer 1 operates as a counter, a falling edge on the T1 pin
increments the count.
I
Table 4. Audio Interface Signal Description
Signal
Alternate
Function
Name
DCLK
DOUT
Type
O
Description
DAC Data Bit Clock
DAC Audio Data
-
-
O
DAC Channel Select Signal
DSEL is the sample rate clock output.
DSEL
SCLK
O
O
-
-
DAC System Clock
SCLK is the oversampling clock synchronized to the digital audio data
(DOUT) and the channel selection signal (DSEL).
Table 5. USB Controller Signal Description
Signal
Name
Alternate
Function
Type
I/O
Description
USB Positive Data Upstream Port
This pin requires an external 1.5 KΩ pull-up to VDD for full speed
operation.
D+
-
-
D-
I/O
USB Negative Data Upstream Port
Table 6. MutiMediaCard Interface Signal Description
Signal
Name
Alternate
Function
Type
Description
MMC Clock output
Data or command clock transfer.
MCLK
O
-
MMC Command line
Bidirectional command channel used for card initialization and data
transfer commands. To avoid any parasitic current consumption,
MCMD
MDAT
I/O
I/O
-
unused MCMD input must be polarized to VDD or VSS
.
MMC Data line
Bidirectional data channel. To avoid any parasitic current consumption,
unused MDAT input must be polarized to VDD or VSS
-
.
7
4109JS–8051–10/06
Table 7. UART Signal Description
Signal
Name
Alternate
Function
Type
Description
Receive Serial Data
RXD
I/O
RXD sends and receives data in serial I/O mode 0 and receives data in
serial I/O modes 1, 2 and 3.
P3.0
P3.1
Transmit Serial Data
TXD outputs the shift clock in serial I/O mode 0 and transmits data in
serial I/O modes 1, 2 and 3.
TXD
O
Table 8. SPI Controller Signal Description
Signal
Name
Alternate
Function
Type
Description
SPI Master Input Slave Output Data Line
MISO
I/O
When in master mode, MISO receives data from the slave peripheral.
When in slave mode, MISO outputs data to the master controller.
P4.0
P4.1
SPI Master Output Slave Input Data Line
When in master mode, MOSI outputs data to the slave peripheral.
When in slave mode, MOSI receives data from the master controller.
MOSI
I/O
SPI Clock Line
SCK
SS
I/O
I
When in master mode, SCK outputs clock to the slave peripheral. When
in slave mode, SCK receives clock from the master controller.
P4.2
P4.3
SPI Slave Select Line
When in controlled slave mode, SS enables the slave mode.
Table 9. TWI Controller Signal Description
Signal
Name
Alternate
Function
Type
Description
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to
the slave peripherals. When TWI controller is in slave mode, SCL
receives clock from the master controller.
SCL
I/O
P1.6
P1.7
TWI Serial Data
SDA is the bidirectional Two Wire data line.
SDA
I/O
Table 10. A/D Converter Signal Description
Signal
Alternate
Function
Name
AIN1:0
AREFP
Type
Description
I
I
A/D Converter Analog Inputs
Analog Positive Voltage Reference Input
-
-
Analog Negative Voltage Reference Input
This pin is internally connected to AVSS.
AREFN
I
-
8
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
Table 11. Keypad Interface Signal Description
Signal
Name
Alternate
Function
Type
Description
Keypad Input Lines
KIN3:0
I
Holding one of these pins high or low for 24 oscillator periods triggers a
keypad interrupt.
P1.3:0
Table 12. External Access Signal Description
Signal
Name
Alternate
Function
Type
Description
Address Lines
A15:8
I/O
Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
P2.7:0
P0.7:0
Address/Data Lines
Multiplexed lower address and data lines for the external memory or the
IDE interface.
AD7:0
ALE
I/O
O
Address Latch Enable Output
ALE signals the start of an external bus cycle and indicates that valid
address information is available on lines A7:0. An external latch is used
to demultiplex the address from address/data bus.
-
Program Store Enable Output (AT80C51SND1C Only)
This signal is active low during external code fetch or external code
read (MOVC instruction).
PSEN
ISP
I/O
I/O
-
-
ISP Enable Input (AT89C51SND1C Only)
This signal must be held to GND through a pull-down resistor at the
falling reset to force execution of the internal bootloader.
Read Signal
RD
O
O
P3.7
P3.6
Read signal asserted during external data memory read operation.
Write Signal
WR
Write signal asserted during external data memory write operation.
External Access Enable (Dice Only)
EA must be externally held low to enable the device to fetch code from
external program memory locations 0000h to FFFFh.
EA(1)(2)
I
-
Notes: 1. For ROM/Flash Dice product versions: pad EA must be connected to VCC.
2. For ROMless Dice product versions: pad EA must be connected to VSS.
Table 13. System Signal Description
Signal
Name
Alternate
Function
Type
Description
Reset Input
Holding this pin high for 64 oscillator periods while the oscillator is
running resets the device. The Port pins are driven to their reset
conditions when a voltage lower than VIL is applied, whether or not the
oscillator is running.
RST
I
-
This pin has an internal pull-down resistor which allows the device to be
reset by connecting a capacitor between this pin and VDD
.
Asserting RST when the chip is in Idle mode or Power-Down mode
returns the chip to normal operation.
Test Input
TST
I
-
Test mode entry signal. This pin must be set to VDD
.
9
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Table 14. Power Signal Description
Signal
Name
Alternate
Function
Type
Description
Digital Supply Voltage
Connect these pins to +3V supply voltage.
VDD
PWR
-
-
-
-
-
-
-
-
Circuit Ground
Connect these pins to ground.
VSS
GND
PWR
GND
PWR
GND
PWR
GND
Analog Supply Voltage
Connect this pin to +3V supply voltage.
AVDD
AVSS
PVDD
PVSS
UVDD
UVSS
Analog Ground
Connect this pin to ground.
PLL Supply voltage
Connect this pin to +3V supply voltage.
PLL Circuit Ground
Connect this pin to ground.
USB Supply Voltage
Connect this pin to +3V supply voltage.
USB Ground
Connect this pin to ground.
10
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
4.3
Internal Pin Structure
Table 15. Detailed Internal Pin Structure
Circuit(1)
Type
Pins
VDD
Input
TST
VDD
Watchdog Output
P
Input/Output
RST
VSS
VDD
VDD
VDD
2 osc
periods
P1(2)
P2(3)
P3
Latch Output
P1
P2
P3
Input/Output
P4
N
P53:0
VSS
VDD
P0
P
MCMD
MDAT
Input/Output
ISP
N
PSEN
VSS
VDD
ALE
SCLK
DCLK
P
Output
DOUT
DSEL
MCLK
N
VSS
D+
D-
Input/Output
D+
D-
Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to the
Section “DC Characteristics”, page 180.
2. When the Two Wire controller is enabled, P1, P2, and P3 transistors are disabled allowing
pseudo open-drain structure.
3. In Port 2, P1 transistor is continuously driven when outputting a high level bit address (A15:8).
11
4109JS–8051–10/06
5. Application Information
Figure 5-1. AT8xC51SND1C Typical Application with On-Board Atmel DataFlash and 2-wire
LCD
LCD
Ref.
P1.0/KIN0
MMC1
MMC2
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P0.0
MCLK
MDAT
MCMD
P0.1
P0.2
AT8xC51SND1C
P0.3
UVDD
X1
D+
D-
X2
USB PORT
UVSS
FILT
PVSS
DataFlash
Memories
Audio DAC
12
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
Figure 5-2. AT8xC51SND1C Typical Application with On-Board Atmel DataFlash and // LCD
LCD
Ref.
MMC1
P1.0/KIN0
MCLK
MMC2
P1.1/KIN1
P1.2/KIN2
MDAT
MCMD
P0.0
P0.1
P0.2
AT8xC51SND1C
UVDD
P0.3
D+
D-
X1
X2
USB PORT
UVSS
FILT
PVSS
DataFlash
Memories
Audio DAC
Figure 5-3. AT8xC51SND1C Typical Application with On-Board SSFDC Flash
LCD
Ref.
P1.0/KIN0
MMC1
MMC2
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
MCLK
MDAT
MCMD
P0.0
P0.1
P0.2
AT8xC51SND1C
UVDD
P0.3
D+
D-
X1
X2
USB PORT
UVSS
FILT
PVSS
Audio DAC
SSFDC Memories
or SmartMedia Cards
SmartMedia
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4109JS–8051–10/06
Figure 5-4. AT8xC51SND1C Typical Application with IDE CD-ROM Drive
LCD
Ref.
MMC1
MMC2
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
MCLK
MDAT
MCMD
P0.0
P0.1
P0.2
AT8xC51SND1C
P0.3
UVDD
X1
D+
D-
X2
USB PORT
UVSS
FILT
PVSS
Audio DAC
IDE CD-ROM
14
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
1. Peripherals
The AT8xC51SND1C peripherals are briefly described in the following sections. For fur-
ther details on how to interface (hardware and software) to these peripherals, please
refer to the AT8xC51SND1C design guide.
1.1 Clock Generator System
The AT8xC51SND1C internal clocks are extracted from an on-chip PLL fed by an on-
chip oscillator. Four clocks are generated respectively for the C51 core, the MP3
decoder, the audio interface, and the other peripherals. The C51 and peripheral clocks
are derived from the oscillator clock. The MP3 decoder clock is generated by dividing
the PLL output clock. The audio interface sample rates are also obtained by dividing the
PLL output clock.
1.2 Ports
The AT8xC51SND1C implements five 8-bit ports (P0 to P4) and one 4-bit port (P5). In
addition to performing general-purpose I/O, some ports are capable of external data
memory operations; others allow for alternate functions. All I/O Ports are bidirectional.
Each Port contains a latch, an output driver and an input buffer. Port 0 and Port 2 output
drivers and input buffers facilitate external memory operations. Some Port 1, Port 3 and
Port 4 pins serve for both general-purpose I/O and alternate functions.
1.3 Timers/Counters
The AT8xC51SND1C implements the two general-purpose, 16-bit Timers/Counters of a
standard C51. They are identified as Timer 0, Timer 1, and can independently be config-
ured each to operate in a variety of modes as a Timer or as an event Counter. When
operating as a Timer, a Timer/Counter runs for a programmed length of time, then
issues an interrupt request. When operating as a Counter, a Timer/Counter counts neg-
ative transitions on an external pin. After a preset number of counts, the Counter issues
an interrupt request.
1.4 Watchdog Timer
1.5 MP3 Decoder
The AT8xC51SND1C implements a hardware Watchdog Timer that automatically resets
the chip if it is allowed to time out. The WDT provides a means of recovering from rou-
tines that do not complete successfully due to software or hardware malfunctions.
The AT8xC51SND1C implements a MPEG I/II audio layer 3 decoder (known as MP3
decoder).
In MPEG I (ISO 11172-3) three layers of compression have been standardized support-
ing three sampling frequencies: 48, 44.1, and 32 KHz. Among these layers, layer 3
allows highest compression rate of about 12:1 while still maintaining CD audio quality.
For example, 3 minutes of CD audio (16-bit PCM, 44.1 KHz) data, which needs about 32
MBytes of storage, can be encoded into only 2.7 MBytes of MPEG I audio layer 3 data.
In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16
KHz are supported for low bit rates applications.
The AT8xC51SND1C can decode in real-time the MPEG I audio layer 3 encoded data
into a PCM audio data, and also supports MPEG II audio layer 3 additional frequencies.
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4109JS–8051–10/06
Additional features are supported by the AT8xC51SND1C MP3 decoder such as vol-
ume, bass, medium, and treble controls, bass boost effect and ancillary data extraction.
1.6 Audio Output Interface
The AT8xC51SND1C implements an audio output interface allowing the decoded audio
bitstream to be output in various formats. It is compatible with right and left justification
PCM and I2S formats and thanks to the on-chip PLL (see Section 1.1) allows connection
of almost all of the commercial audio DAC families available on the market.
1.7 Universal Serial Bus Interface
The AT8xC51SND1C implements a full speed Universal Serial Bus Interface. It can be
used for the following purposes:
•
•
Download of MP3 encoded audio files by supporting the USB mass storage class.
In System Programming by supporting the USB firmware upgrade class.
1.8 MultiMediaCard Interface
The AT8xC51SND1C implements a MultiMediaCard (MMC) interface compliant to the
V2.2 specification in MultiMediaCard Mode. The MMC allows storage of MP3 encoded
audio files in removable flash memory cards that can be easily plugged or removed from
the application. It can also be used for In System Programming.
1.9 IDE/ATAPI interface
1.10 Serial I/O Interface
The AT8xC51SND1C provides an IDE/ATAPI interface allowing connexion of devices
such as CD-ROM reader, CompactFlash cards, Hard Disk Drive… It consists in a 16-bit
bidirectional bus part of the low-level ANSI ATA/ATAPI specification. It is provided for
mass storage interface but could be used for In System Programming using CD-ROM.
The AT8xC51SND1C implements a serial port with its own baud rate generator provid-
ing one single synchronous communication mode and three full-duplex Universal
Asynchronous Receiver Transmitter (UART) communication modes. It is provided for
the following purposes:
•
•
In System Programming.
Remote control of the AT8xC51SND1C by a host.
1.11 Serial Peripheral Interface
The AT8xC51SND1C implements a Serial Peripheral Interface (SPI) supporting master
and slave modes. It is provided for the following purposes:
•
•
•
Interfacing DataFlash memory for MP3 encoded audio files storage.
Remote control of the AT8xC51SND1C by a host.
In System Programming.
16
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
1.12 2-wire Controller
The AT8xC51SND1C implements a 2-wire controller supporting the four standard mas-
ter and slave modes with multimaster capability. It is provided for the following
purposes:
•
•
•
Connection of slave devices like LCD controller, audio DAC…
Remote control of the AT8xC51SND1C by a host.
In System Programming.
1.13 A/D Controller
The AT8xC51SND1C implements a 2-channel 10-bit (8 true bits) analog to digital con-
verter (ADC). It is provided for the following purposes:
•
•
•
Battery monitoring.
Voice recording.
Corded remote control.
1.14 Keyboard Interface
The AT8xC51SND1C implements a keyboard interface allowing connection of 4 x n
matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both
high or low level. These inputs are available as alternate function of P1.3:0 and allow
exit from idle and power down modes.
17
4109JS–8051–10/06
22. Electrical Characteristics
22.1 Absolute Maximum Rating
*NOTICE:
Stressing the device beyond the “Absolute Maxi-
mum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond
the “operating conditions” is not recommended
and extended exposure beyond the “Operating
Conditions” may affect device reliability.
Storage Temperature......................................... -65 to +150°C
Voltage on any other Pin to VSS .................................... -0.3 to +4.0 V
IOL per I/O Pin ................................................................. 5 mA
Power Dissipation............................................................. 1 W
Operating Conditions
Ambient Temperature Under Bias........................ -40 to +85°C
VDD ........................................................................................................................4.0V
22.2 DC Characteristics
22.2.1
Table 143. Digital DC Characteristics
DD = 2.7 to 3.3 V, TA = -40 to +85°C
Digital Logic
V
Symbol
Parameter
Min
-0.5
Typ(1)
Max
0.2·VDD - 0.1
VDD
Units
Test Conditions
VIL
Input Low Voltage
V
V
V
(2)
VIH1
Input High Voltage (except RST, X1)
Input High Voltage (RST, X1)
0.2·VDD + 1.1
0.7·VDD
VIH2
VDD + 0.5
Output Low Voltage
VOL1
(except P0, ALE, MCMD, MDAT, MCLK,
SCLK, DCLK, DSEL, DOUT)
0.45
0.45
V
IOL= 1.6 mA
Output Low Voltage
(P0, ALE, MCMD, MDAT, MCLK, SCLK,
DCLK, DSEL, DOUT)
VOL2
V
V
IOL= 3.2 mA
Output High Voltage
(P1, P2, P3, P4 and P5)
VOH1
VDD - 0.7
IOH= -30 μA
Output High Voltage
(P0, P2 address mode, ALE, MCMD,
MDAT, MCLK, SCLK, DCLK, DSEL,
DOUT, D+, D-)
VOH2
VDD - 0.7
V
IOH= -3.2 mA
Logical 0 Input Current (P1, P2, P3, P4
and P5)
IIL
-50
10
μA
μA
μA
VIN= 0.45 V
0.45< VIN< VDD
VIN= 2.0 V
Input Leakage Current (P0, ALE, MCMD,
MDAT, MCLK, SCLK, DCLK, DSEL,
DOUT)
ILI
Logical 1 to 0 Transition Current
(P1, P2, P3, P4 and P5)
ITL
-650
200
RRST
CIO
Pull-Down Resistor
Pin Capacitance
50
90
10
kΩ
pF
V
TA= 25°C
VRET
VDD Data Retention Limit
1.8
180
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
Table 143. Digital DC Characteristics
DD = 2.7 to 3.3 V, TA = -40 to +85°C
V
Symbol
Parameter
Min
Typ(1)
Max
Units
Test Conditions
VDD < 3.3 V
X1 / X2 mode
6.5 / 10.5
8 / 13.5
AT89C51SND1C
Operating Current
12 MHz
16 MHz
20 MHz
(3)
mA
9.5 / 17
VDD < 3.3 V
X1 / X2 mode
6.5 / 10.5
8 / 13.5
AT83SND1C
Operating Current
12 MHz
16 MHz
20 MHz
IDD
mA
mA
mA
mA
mA
9.5 / 17
VDD < 3.3 V
X1 / X2 mode
6.5 / 10.5
8 / 13.5
AT80C51SND1C
Idle Mode Current
12 MHz
16 MHz
20 MHz
9.5 / 17
VDD < 3.3 V
X1 / X2 mode
5.3 / 8.1
6.4 / 10.3
7.5 / 13
AT89C51SND1C
Idle Mode Current
12 MHz
16 MHz
20 MHz
(3)
VDD < 3.3 V
X1 / X2 mode
5.3 / 8.1
6.4 / 10.3
7.5 / 13
AT83SND1C
Idle Mode Current
12 MHz
16 MHz
20 MHz
IDL
VDD < 3.3 V
X1 / X2 mode
5.3 / 8.1
6.4 / 10.3
7.5 / 13
AT80C51SND1C
Idle Mode Current
12 MHz
16 MHz
20 MHz
AT89C51SND1C
Power-Down Mode Current
20
20
20
500
500
500
15
μA
μA
μA
mA
VRET < VDD < 3.3 V
AT83SND1C
Power-Down Mode Current
IPD
VRET < VDD < 3.3 V
AT80C51SND1C
Power-Down Mode Current
V
RET < VDD < 3.3 V
AT89C51SND1C
Flash Programming Current
IFP
VDD < 3.3 V
Notes: 1. Typical values are obtained using VDD= 3 V and TA= 25°C. They are not tested and there is no
guarantee on these values.
2. Flash retention is guaranteed with the same formula for VDD min down to 0V.
3. See Table 144 for typical consumption in player mode.
Table 144. Typical Reference Design AT89C51SND1C Power Consumption
Player Mode
IDD
Test Conditions
AT89C51SND1C at 16 MHz, X2 mode, VDD= 3 V
No song playing
Stop
10 mA
AT89C51SND1C at 16 MHz, X2 mode, VDD= 3 V
MP3 Song with Fs= 44.1 KHz, at any bit rates (Variable Bit Rate)
Playing
30 mA
181
4109JS–8051–10/06
22.2.1.1
IDD, IDL and IPD Test Conditions
Figure 22-1. IDD Test Condition, Active Mode
VDD
VDD
VDD
PVDD
UVDD
AVDD
IDD
RST
(NC)
Clock Signal
X2
X1
VDD
P0
VSS
PVSS
UVSS
AVSS
TST
VSS
All other pins are unconnected
Figure 22-2. IDL Test Condition, Idle Mode
VDD
VDD
PVDD
UVDD
AVDD
IDL
RST
VSS
(NC)
Clock Signal
X2
X1
VDD
P0
VSS
PVSS
UVSS
AVSS
TST
VSS
All other pins are unconnected
Figure 22-3. IPD Test Condition, Power-Down Mode
VDD
VDD
PVDD
UVDD
AVDD
IPD
RST
VSS
(NC)
VDD
X2
X1
P0
MCMD
MDAT
TST
VSS
PVSS
UVSS
AVSS
VSS
All other pins are unconnected
182
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
22.2.2
A to D Converter
Table 145. A to D Converter DC Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Min
Typ
Max
Units
Test Conditions
AVDD
Analog Supply Voltage
2.7
3.3
V
AVDD= 3.3V
AIDD
Analog Operating Supply Current
600
μA
AIN1:0= 0 to AVDD
ADEN= 1
AVDD= 3.3V
ADEN= 0 or PD= 1
AIPD
AVIN
Analog Standby Current
Analog Input Voltage
2
μA
AVSS
AVDD
V
Reference Voltage
AREFN
AVREF
AVSS
2.4
V
AREFP
AVDD
30
RREF
CIA
AREF Input Resistance
Analog Input capacitance
10
KΩ
TA= 25°C
TA= 25°C
10
pF
22.2.3
Oscillator & Crystal
22.2.3.1
Schematic
Figure 22-4. Crystal Connection
X1
C1
C2
Q
VSS
X2
Note:
For operation with most standard crystals, no external components are needed on X1 and X2. It
may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10
pF). X1 and X2 may not be used to drive other circuits.
22.2.3.2
Parameters
Table 146. Oscillator & Crystal Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
CX1
CX2
CL
Parameter
Internal Capacitance (X1 - VSS)
Internal Capacitance (X2 - VSS)
Equivalent Load Capacitance (X1 - X2)
Drive Level
Min
Typ
10
10
5
Max
Unit
pF
pF
pF
DL
50
20
40
6
μW
MHz
Ω
F
Crystal Frequency
RS
Crystal Series Resistance
Crystal Shunt Capacitance
CS
pF
183
4109JS–8051–10/06
22.2.4
Phase Lock Loop
22.2.4.1
Schematic
Figure 22-5. PLL Filter Connection
FILT
R
C2
C1
VSS
VSS
22.2.4.2
Parameters
Table 147. PLL Filter Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Min
Typ
100
10
Max
Unit
Ω
R
Filter Resistor
C1
C2
Filter Capacitance 1
Filter Capacitance 2
nF
nF
2.2
22.2.5
USB Connection
22.2.5.1
Schematic
Figure 22-6. USB Connection
VDD
To Power
Supply
RFS
VBUS
D+
D-
D+
D-
RUSB
RUSB
GND
VSS
22.2.5.2
Parameters
Table 148. USB Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
RUSB
Parameter
USB Termination Resistor
USB Full Speed Resistor
Min
Typ
27
Max
Unit
Ω
RFS
1.5
KΩ
184
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
22.2.6
In System Programming
22.2.6.1
Schematic
Figure 22-7. ISP Pull-Down Connection
ISP
RISP
VSS
22.2.6.2
Parameters
Table 149. ISP Pull-Down Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
ISP Pull-Down Resistor
Min
Typ
Max
Unit
RISP
2.2
KΩ
185
4109JS–8051–10/06
22.3 AC Characteristics
22.3.1
External Program Bus Cycles
22.3.1.1
Definition of Symbols
Table 150. External Program Bus Cycles Timing Symbol Definitions
Signals
Address
Conditions
High
A
I
H
L
Instruction In
ALE
Low
L
P
V
X
Z
Valid
PSEN
No Longer Valid
Floating
22.3.1.2
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 151. External Program Bus Cycle - Read AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
Max
Unit
ns
TCLCL Clock Period
50
50
TLHLL
TAVLL
ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
4·TCLCL-35
3·TCLCL-25
TCLCL-15
ns
Address Valid to ALE Low
0.5·TCLCL-20
0.5·TCLCL-20
2·TCLCL-35
1.5·TCLCL-25
ns
TLLAX Address hold after ALE Low
TLLIV ALE Low to Valid Instruction
TPLPH PSEN Pulse Width
ns
ns
ns
TPLIV
TPXIX
TPXIZ
TAVIV
PSEN Low to Valid Instruction
3·TCLCL-35
1.5·TCLCL-35 ns
ns
Instruction Hold After PSEN High
Instruction Float After PSEN High
Address Valid to Valid Instruction
0
0
TCLCL-10
5·TCLCL-35
10
0.5·TCLCL-10 ns
2.5·TCLCL-35 ns
TPLAZ PSEN Low to Address Float
10
ns
186
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
22.3.1.3
Waveforms
Figure 22-8. External Program Bus Cycle - Read Waveforms
ALE
TLHLL
TPLPH
TLLPL
PSEN
TPLIV
TPXAV
TPXIZ
TPLAZ
TAVLL TLLAX
TPXIX
P0
P2
D7:0
A7:0
D7:0
Instruction In
A7:0
D7:0
Instruction In
A15:8
A15:8
22.3.2
External Data 8-bit Bus Cycles
22.3.2.1
Definition of Symbols
Table 152. External Data 8-bit Bus Cycles Timing Symbol Definitions
Signals
Conditions
High
A
D
L
Address
Data In
ALE
H
L
Low
V
X
Z
Valid
Q
R
W
Data Out
RD
No Longer Valid
Floating
WR
22.3.2.2
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 153. External Data 8-bit Bus Cycle - Read AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
Max
Unit
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
TCLCL-15
ns
TAVLL
Address Valid to ALE Low
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
ns
TLLAX Address hold after ALE Low
TLLRL ALE Low to RD Low
ns
ns
187
4109JS–8051–10/06
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
3·TCLCL-25
Max
Unit
TRLRH RD Pulse Width
6·TCLCL-25
TCLCL-20
ns
TRHLH RD high to ALE High
TAVDV Address Valid to Valid Data In
TAVRL Address Valid to RD Low
TRLDV RD Low to Valid Data
TRLAZ RD Low to Address Float
TRHDX Data Hold After RD High
TRHDZ Data Float After RD High
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20 ns
4.5·TCLCL-65 ns
9·TCLCL-65
4·TCLCL-30
2·TCLCL-30
ns
5·TCLCL-30
0
2.5·TCLCL-30 ns
0
ns
ns
ns
0
0
2·TCLCL-25
TCLCL-25
Table 154. External Data 8-bit Bus Cycle - Write AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
Max
Unit
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
4·TCLCL-30
7·TCLCL-20
TCLCL-15
TCLCL-15
ns
TAVLL
Address Valid to ALE Low
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
ns
TLLAX Address hold after ALE Low
TLLWL ALE Low to WR Low
TWLWH WR Pulse Width
ns
ns
ns
TWHLH WR High to ALE High
TAVWL Address Valid to WR Low
TQVWH Data Valid to WR High
TWHQX Data Hold after WR High
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20 ns
2·TCLCL-30
3.5·TCLCL-20
0.5·TCLCL-15
ns
ns
ns
188
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
22.3.2.3
Waveforms
Figure 22-9. External Data 8-bit Bus Cycle - Read Waveforms
ALE
TLHLL
TLLRL
TRLRH
TRHLH
RD
TRLDV
TRHDZ
TRHDX
TRLAZ
TLLAX
TAVLL
P0
P2
A7:0
TAVRL
TAVDV
D7:0
Data In
A15:8
Figure 22-10. External Data 8-bit Bus Cycle - Write Waveforms
ALE
TLHLL
TWHLH
TLLWL
TWLWH
WR
TAVWL
TLLAX
TAVLL
TQVWH
TWHQX
P0
P2
A7:0
D7:0
Data Out
A15:8
22.3.3
External IDE 16-bit Bus Cycles
22.3.3.1
Definition of Symbols
Table 155. External IDE 16-bit Bus Cycles Timing Symbol Definitions
Signals
Conditions
High
A
D
L
Address
Data In
ALE
H
L
Low
V
X
Z
Valid
Q
R
W
Data Out
RD
No Longer Valid
Floating
WR
189
4109JS–8051–10/06
22.3.3.2
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 156. External IDE 16-bit Bus Cycle - Data Read AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
Max
Unit
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
TCLCL-15
ns
TAVLL
Address Valid to ALE Low
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
ns
TLLAX Address hold after ALE Low
TLLRL ALE Low to RD Low
TRLRH RD Pulse Width
ns
ns
ns
TRHLH RD high to ALE High
TAVDV Address Valid to Valid Data In
TAVRL Address Valid to RD Low
TRLDV RD Low to Valid Data
TRLAZ RD Low to Address Float
TRHDX Data Hold After RD High
TRHDZ Data Float After RD High
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20 ns
4.5·TCLCL-65 ns
9·TCLCL-65
4·TCLCL-30
2·TCLCL-30
ns
5·TCLCL-30
0
2.5·TCLCL-30 ns
0
ns
ns
ns
0
0
2·TCLCL-25
TCLCL-25
Table 157. External IDE 16-bit Bus Cycle - Data Write AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol
Parameter
Min
Max
Min
Max
Unit
ns
TCLCL Clock Period
50
50
TLHLL ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
4·TCLCL-30
7·TCLCL-20
TCLCL-15
TCLCL-15
ns
TAVLL
Address Valid to ALE Low
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
ns
TLLAX Address hold after ALE Low
TLLWL ALE Low to WR Low
TWLWH WR Pulse Width
ns
ns
ns
TWHLH WR High to ALE High
TAVWL Address Valid to WR Low
TQVWH Data Valid to WR High
TWHQX Data Hold after WR High
TCLCL+20
0.5·TCLCL-20 0.5·TCLCL+20 ns
2·TCLCL-30
3.5·TCLCL-20
0.5·TCLCL-15
ns
ns
ns
190
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
22.3.3.3
Waveforms
Figure 22-11. External IDE 16-bit Bus Cycle - Data Read Waveforms
ALE
TLHLL
TLLRL
TRLRH
TRHLH
RD
TRLDV
TRHDZ
TRHDX
TRLAZ
TLLAX
TAVLL
P0
P2
A7:0
TAVRL
TAVDV
D7:0
Data In
A15:8
D15:8(1)
Data In
Note:
1. D15:8 is written in DAT16H SFR.
Figure 22-12. External IDE 16-bit Bus Cycle - Data Write Waveforms
ALE
TLHLL
TWHLH
TLLWL
TWLWH
WR
TAVWL
TLLAX
TAVLL
TQVWH
TWHQX
P0
P2
A7:0
D7:0
Data Out
A15:8
D15:8(1)
Data Out
Note:
1. D15:8 is the content of DAT16H SFR.
22.4 SPI Interface
22.4.0.4
Definition of Symbols
Table 158. SPI Interface Timing Symbol Definitions
Signals
Conditions
High
C
I
Clock
H
L
Data In
Data Out
Low
O
V
X
Z
Valid
No Longer Valid
Floating
191
4109JS–8051–10/06
22.4.0.5
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 159. SPI Interface Master AC Timing
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Slave Mode
Min
Max
Unit
TCHCH
Clock Period
2
TPER
TPER
TPER
ns
TCHCX
Clock High Time
Clock Low Time
0.8
0.8
100
40
TCLCX
TSLCH, TSLCL
SS Low to Clock edge
T
T
T
T
T
IVCL, TIVCH
CLIX, TCHIX
CLOV, TCHOV
CLOX, TCHOX
CLSH, TCHSH
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
SS High after Clock Edge
SS Low to Output Data Valid
Output Data Hold after SS High
SS High to SS Low
ns
40
ns
40
ns
0
0
ns
ns
TSLOV
TSHOX
TSHSL
TILIH
50
50
ns
ns
(1)
Input Rise Time
2
μs
μs
ns
ns
TIHIL
Input Fall Time
2
TOLOH
TOHOL
Output Rise time
100
100
Output Fall Time
Master Mode
TCHCH
Clock Period
2
TPER
TPER
TPER
ns
TCHCX
Clock High Time
0.8
0.8
20
20
TCLCX
Clock Low Time
TIVCL, TIVCH
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
Input Data Rise Time
T
T
CLIX, TCHIX
ns
CLOV, TCHOV
40
ns
TCLOX, TCHOX
TILIH
0
ns
2
2
μs
TIHIL
Input Data Fall Time
μs
TOLOH
Output Data Rise time
50
50
ns
TOHOL
Output Data Fall Time
ns
Note:
1. Value of this parameter depends on software.
192
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
22.4.0.6
Waveforms
Figure 22-13. SPI Slave Waveforms (SSCPHA= 0)
SS
(input)
TSLCH
TCLSH
TCHCH
TSHSL
TSLCL
TCHSH
TCLCH
SCK
(SSCPOL= 0)
(input)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(input)
TCLOX
TCHOX
TCLOV
TCHOV
TSLOV
SLAVE MSB OUT
TSHOX
MISO
(output)
(1)
BIT 6
SLAVE LSB OUT
TCHIX
TCLIX
TIVCH
TIVCL
MOSI
(input)
MSB IN
BIT 6
LSB IN
Note:
1. Not Defined but generally the MSB of the character which has just been received.
Figure 22-14. SPI Slave Waveforms (SSCPHA= 1)
SS
(input)
TSLCH
TCLSH
TCHSH
TSLCL
TCHCH
TSHSL
TCLCH
SCK
(SSCPOL= 0)
(input)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(input)
TCHOV
TCLOV
TCHOX
TCLOX
TSLOV
TSHOX
MISO
(output)
(1)
SLAVE MSB OUT
BIT 6
SLAVE LSB OUT
TIVCH
TIVCL
TCHIX
TCLIX
MOSI
(input)
MSB IN
BIT 6
LSB IN
Note:
1. Not Defined but generally the LSB of the character which has just been received.
193
4109JS–8051–10/06
Figure 22-15. SPI Master Waveforms (SSCPHA= 0)
SS
(output)
TCHCH
TCLCH
SCK
(SSCPOL= 0)
(output)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(output)
TIVCH
TCHIX
TIVCL TCLIX
MOSI
(input)
MSB IN
BIT 6
TCLOV
TCHOV
LSB IN
TCLOX
TCHOX
MISO
(output)
Port Data
MSB OUT
BIT 6
LSB OUT
Port Data
Note:
1. SS handled by software using general purpose port pin.
Figure 22-16. SPI Master Waveforms (SSCPHA= 1)
SS(1)
(output)
TCHCH
TCLCH
SCK
(SSCPOL= 0)
(output)
TCHCX
TCLCX
TCHCL
SCK
(SSCPOL= 1)
(output)
TIVCH
TCHIX
TIVCL TCLIX
MOSI
(input)
MSB IN
TCLOV
BIT 6
LSB IN
TCLOX
TCHOX
TCHOV
MISO
(output)
Port Data
MSB OUT
BIT 6
LSB OUT
Port Data
Note:
Two-wire Interface
Timings
1. SS handled by software using general purpose port pin.
22.4.1
22.4.1.1
Table 160. TWI Interface AC Timing
194
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
INPUT
Min
OUTPUT
Min
Symbol
Parameter
Start condition hold time
Max
Max
(4)
THD; STA
TLOW
14·TCLCL
16·TCLCL
14·TCLCL
1 μs
4.0 μs(1)
4.7 μs(1)
4.0 μs(1)
(4)
(4)
SCL low time
SCL high time
SCL rise time
SCL fall time
THIGH
(2)
TRC
-
TFC
0.3 μs
0.3 μs(3)
20·TCLCL(4)- TRD
1 μs(1)
TSU; DAT1
TSU; DAT2
TSU; DAT3
THD; DAT
TSU; STA
TSU; STO
TBUF
Data set-up time
250 ns
250 ns
250 ns
0 ns
SDA set-up time (before repeated START condition)
SDA set-up time (before STOP condition)
Data hold time
(4)
8·TCLCL
8·TCLCL(4) - TFC
4.7 μs(1)
(4)
Repeated START set-up time
STOP condition set-up time
Bus free time
14·TCLCL
14·TCLCL
14·TCLCL
1 μs
(4)
(4)
4.0 μs(1)
4.7 μs(1)
(2)
TRD
SDA rise time
-
TFD
SDA fall time
0.3 μs
0.3 μs(3)
Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this
must be < 1 μs.
3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered out. Maxi-
mum capacitance on bus-lines SDA and
SCL= 400 pF.
4. TCLCL= TOSC= one oscillator clock period.
22.4.1.2
Waveforms
Figure 22-17. Two Wire Waveforms
Repeated START condition
START or Repeated START condition
Trd
START condition
Tsu;STA
STOP condition
0.7 VDD
0.3 VDD
SDA
(INPUT/OUTPUT)
Tsu;STO
Tbuf
Tfd
Tsu;DAT3
Trc
Tfc
0.7 VDD
0.3 VDD
SCL
(INPUT/OUTPUT)
Thigh
Tsu;DAT2
Tlow
Thd;STA
Thd;DAT
Tsu;DAT1
195
4109JS–8051–10/06
22.4.2
MMC Interface
22.4.2.1
Definition of symbols
Table 161. MMC Interface Timing Symbol Definitions
Signals
Clock
Conditions
High
C
D
O
H
L
Data In
Low
Data Out
V
X
Valid
No Longer Valid
22.4.2.2
22.4.2.3
196
Timings
Table 162. MMC Interface AC timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C, CL ≤ 100pF (10 cards)
Symbol
TCHCH
Parameter
Min
50
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Period
TCHCX
TCLCX
TCLCH
TCHCL
TDVCH
TCHDX
TCHOX
TOVCH
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
10
10
10
10
Input Data Valid to Clock High
Input Data Hold after Clock High
Output Data Hold after Clock High
Output Data Valid to Clock High
3
3
5
5
Waveforms
Figure 22-18. MMC Input-Output Waveforms
TCHCH
TCHCX
TCLCX
MCLK
TCHCL
TCLCH
TIVCH
TCHIX
MCMD Input
MDAT Input
TCHOX
TOVCH
MCMD Output
MDAT Output
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
22.4.3
Audio Interface
22.4.3.1
Definition of symbols
Table 163. Audio Interface Timing Symbol Definitions
Signals
Clock
Conditions
High
C
O
S
H
L
Data Out
Low
Data Select
V
X
Valid
No Longer Valid
22.4.3.2
Timings
Table 164. Audio Interface AC timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C, CL≤ 30pF
Symbol
Parameter
Clock Period
Min
Max
Unit
ns
TCHCH
TCHCX
TCLCX
TCLCH
TCHCL
TCLSV
TCLOV
325.5(1)
Clock High Time
30
30
ns
Clock Low Time
ns
Clock Rise Time
10
10
10
10
ns
Clock Fall Time
ns
Clock Low to Select Valid
Clock Low to Data Valid
ns
ns
Note:
1. 32-bit format with Fs= 48 KHz.
22.4.3.3
Waveforms
Figure 22-19. Audio Interface Waveforms
TCHCH
TCHCX
TCLCX
DCLK
TCHCL
TCLCH
TCLSV
DSEL
DDAT
Right
Left
TCLOV
197
4109JS–8051–10/06
22.4.4
Analog to Digital Converter
22.4.4.1
Definition of symbols
Table 165. Analog to Digital Converter Timing Symbol Definitions
Signals
Clock
Conditions
High
C
E
H
L
Enable (ADEN bit)
Low
Start Conversion
(ADSST bit)
S
22.4.4.2
Characteristics
Table 166. Analog to Digital Converter AC Characteristics
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Clock Period
Min
Max
Unit
μs
TCLCL
TEHSH
TSHSL
4
Start-up Time
4
μs
Conversion Time
11·TCLCL
μs
Differential non-
linearity error(1)(2)
DLe
ILe
1
2
LSB
LSB
Integral non-
linearity errorss(1)(3)
OSe
Ge
Offset error(1)(4)
Gain error(1)(5)
4
4
LSB
LSB
Notes: 1. AVDD= AVREFP= 3.0 V, AVSS= AVREFN= 0 V. ADC is monotonic with no missing code.
2. The differential non-linearity is the difference between the actual step width and the ideal step
width (see Figure 22-21).
3. The integral non-linearity is the peak difference between the center of the actual step and the
ideal transfer curve after appropriate adjustment of gain and offset errors (see Figure 22-21).
4. The offset error is the absolute difference between the straight line which fits the actual trans-
fer curve (after removing of gain error), and the straight line which fits the ideal transfer curve
(see Figure 22-21).
5. The gain error is the relative difference in percent between the straight line which fits the actual
transfer curve (after removing of offset error), and the straight line which fits the ideal transfer
curve (see Figure 22-21).
198
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
22.4.4.3
Waveforms
Figure 22-20. Analog to Digital Converter Internal Waveforms
CLK
TCLCL
ADEN Bit
TEHSH
ADSST Bit
TSHSL
Figure 22-21. Analog to Digital Converter Characteristics
Offset Gain
Error Error
Code Out
OSe
Ge
1023
1022
1021
1020
1019
1018
Ideal Transfer curve
7
6
5
Example of an actual transfer curve
Center of a step
4
Integral non-linearity (ILe)
3
2
1
Differential non-linearity (DLe)
1 LSB
(ideal)
0
0
AVIN
(LSB ideal)
1
2
3
4
5
6
7
1018 1019 1020 1021 1022 1023 1024
Offset
Error OSe
199
4109JS–8051–10/06
22.4.5
Flash Memory
22.4.5.1
Definition of symbols
Table 167. Flash Memory Timing Symbol Definitions
Signals
ISP
Conditions
Low
S
R
B
L
RST
V
X
Valid
FBUSY flag
No Longer Valid
22.4.5.2
Timings
Table 168. Flash Memory AC Timing
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
TSVRL
Parameter
Min
Typ
Max
Unit
ns
Input ISP Valid to RST Edge
50
50
TRLSX
TBHBL
NFCY
TFDR
Input ISP Hold after RST Edge
FLASH Internal Busy (Programming) Time
Number of Flash Write Cycles
Flash Data Retention Time
ns
10
ms
100K
10
Cycle
Years
22.4.5.3
Waveforms
Figure 22-22. FLASH Memory - ISP Waveforms
RST
TSVRL
TRLSX
ISP(1)
Note:
1. ISP must be driven through a pull-down resistor (see Section “In System Programming”,
page 185).
Figure 22-23. FLASH Memory - Internal Busy Waveforms
FBUSY bit
TBHBL
200
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
22.4.6
External Clock Drive and Logic Level References
22.4.6.1
Definition of symbols
Table 169. External Clock Timing Symbol Definitions
Signals
Clock
Conditions
High
C
H
L
Low
X
No Longer Valid
22.4.6.2
Timings
External Clock AC Timings
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Symbol
Parameter
Min
50
10
10
3
Max
Unit
ns
ns
ns
ns
ns
%
TCLCL
TCHCX
TCLCX
TCLCH
TCHCL
TCR
Clock Period
High Time
Low Time
Rise Time
Fall Time
3
Cyclic Ratio in X2 mode
40
60
22.4.6.3
Waveforms
Figure 22-24. External Clock Waveform
TCLCH
TCHCX
VDD - 0.5
VIH1
TCLCX
VIL
0.45 V
TCHCL
TCLCL
Figure 22-25. AC Testing Input/Output Waveforms
INPUTS
OUTPUTS
VIH min
VIL max
VDD - 0.5
0.7 VDD
0.3 VDD
0.45 V
Note:
1. During AC testing, all inputs are driven at VDD -0.5 V for a logic 1 and 0.45 V for a logic 0.
2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0.
Figure 22-26. Float Waveforms
VLOAD + 0.1 V
LOAD - 0.1 V
VOH - 0.1 V
VOL + 0.1 V
VLOAD
Timing Reference Points
V
201
4109JS–8051–10/06
Note:
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with
I
OL/IOH= 20 mA.
202
AT8xC51SND1C
4109JS–8051–10/06
AT8xC51SND1C
24. Ordering Information
Temperature
Range
Memory
Size
Supply
Voltage
Max
Frequency
Product
Part Number
Package(2)
TQFP80
BGA81
Dice
Packing
Tray
Marking
89C51SND1C-IL
89C51SND1C-IL
-
AT89C51SND1C-ROTIL
AT89C51SND1C-7HTIL
AT89C51SND1C-DDV
AT83SND1Cxxx(1)-ROTIL
AT83SND1Cxxx(1)-7HTIL
AT83SND1Cxxx-DDV
AT80C51SND1C-ROTIL
AT80C51SND1C-7HTIL
AT80C51SND1C-DDV
64K Flash
64K Flash
64K Flash
64K ROM
64K ROM
64K ROM
ROMless
ROMless
ROMless
3V
3V
3V
3V
3V
3V
3V
3V
3V
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
40 MHz
40 MHz
40 MHz
40 MHz
40 MHz
40 MHz
40 MHz
40 MHz
40 MHz
Tray
Tray
TQFP80
BGA81
Dice
Tray
89C51SND1C-IL
89C51SND1C-IL
-
Tray
Tray
TQFP80
BGA81
Dice
Tray
89C51SND1C-IL
89C51SND1C-IL
-
Tray
Tray
Industrial &
Green
AT89C51SND1C-ROTUL
AT89C51SND1C-7HTJL
AT83SND1Cxxx(1)-ROTUL
64K Flash
64K Flash
64K ROM
3V
3V
3V
40 MHz
40 MHz
40 MHz
TQFP80
BGA81
Tray
Tray
Tray
89C51SND1C-IL
89C51SND1C-IL
89C51SND1C-IL
Industrial
Industrial &
Green
TQFP80
Industrial &
Green
AT83SND1Cxxx(1)-7HTJL
AT80C51SND1C-ROTUL
AT80C51SND1C-7HTJL
64K ROM
ROMless
ROMless
3V
3V
3V
40 MHz
40 MHz
40 MHz
BGA81
TQFP80
BGA81
Tray
Tray
Tray
89C51SND1C-IL
89C51SND1C-IL
89C51SND1C-IL
Industrial &
Green
Industrial &
Green
Notes: 1. Refers to ROM code.
2. PLCC84 package only available for development board.
203
4109JS–8051–10/06
Atmel Corporation
Atmel Operations
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Tel: 1(408) 441-0311
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Fax: 1(408) 436-4314
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