AT34C02-10TC-2.7 [ATMEL]
2-Wire Serial EEPROM with Permanent Software Write Protect; 2线串行EEPROM与常驻软件写保护
| 型号： | AT34C02-10TC-2.7 |
| 厂家： | 
ATMEL |
| 描述： | 2-Wire Serial EEPROM with Permanent Software Write Protect |
| 文件： | 总12页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Permanent Software Write Protection for the First-Half of the Array
– Software Procedure to Verify Write Protect Status
• Hardware Write Protection for the Entire Array
• Low Voltage and Standard Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized 256 x 8
• 2-Wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 100 KHz (1.8V and 2.7V) and 400 KHz (5.0V) Compatibility
• 16-Byte Page Write Modes
2-Wire Serial
EEPROM
• Partial Page Writes Are Allowed
with Permanent
Software Write
Protect
• Self-Timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: >3,000V
• Automotive Grade and Extended Temperature Devices Available
• 8-Pin PDIP, 8-Pin JEDEC SOIC and 8-Pin TSSOP Packages
2K (256 x 8)
Description
The AT34C02 provides 2048 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of
the device incorporates a software write protection feature while hardware write pro-
tection for the entire array is available via an external pin as well. Once the software
write protection is enabled, by sending a special command to the device, it cannot be
reversed. The hardware write protection is controlled with the WP pin and can be used
to protect the entire array, whether or not the software write protection has been
enabled. This allows the user to protect none, first-half, or all of the array depending
on the application. The device is optimized for use in many industrial and commercial
applications where low power and low voltage operations are essential. The AT34C02
is available in space saving 8-pin PDIP, 8-pin JEDEC SOIC, and 8-pin TSSOP pack-
ages and is accessed via a 2-wire serial interface. In addition, it is available in 5.0V
(4.5V to 5.5V), 2.7V (2.7V to 5.5V), and 1.8V (1.8V to 5.5V) versions.
AT34C02
2-Wire Serial
EEPROM with
Permanent
Software Write
Protec
Pin Configurations
8-Pin SOIC
Pin Name
A0 to A2
SDA
Function
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
Address Inputs
Serial Data
A2
SCL
SDA
GND
SCL
Serial Clock Input
Write Protect
WP
8-Pin TSSOP
8-Pin PDIP
A0
A1
1
8
7
6
5
VCC
WP
A0
1
8
VCC
2
3
4
A1
A2
2
3
4
7
6
5
WP
A2
SCL
SDA
SCL
SDA
GND
Rev. 0958D–07/98
GND
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage........................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
VCC
GND
WP
START
STOP
LOGIC
SCL
SDA
SERIAL
CONTROL
LOGIC
EN
H.V. PUMP/TIMING
DATA RECOVERY
WRITE PROTECT
CIRCUITRY
LOAD
COMP
DEVICE
ADDRESS
COMPARATOR
SOFTWARE WRITE
PROTECTED AREA
(00H - 7FH)
LOAD
INC
A2
A1
A0
R/W
DATA WORD
ADDR/COUNTER
E2PROM
Y DEC
SERIAL MUX
DIN
DOUT/ACK
LOGIC
DOUT
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive
edge clock data into each EEPROM device and negative
edge clock data out of each device.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1
and A0 pins are device address inputs that are hard wired
for the AT34C02. As many as eight 2K devices may be
addressed on a single bus system (device addressing is
discussed in detail under the Device Addressing section).
SERIAL DATA (SDA): The SDA pin is bidirectional for
serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open
collector devices.
WRITE PROTECT (WP): The AT34C02 has a Write Pro-
tect pin that provides hardware data protection. The Write
Protect pin allows normal read/write operations when con-
AT34C02
2
AT34C02
nected to ground (GND) or when left floating. When the
Write Protect pin is connected to VCC, the write protection
feature is enabled for the entire array. The write protection
modes are shown in the following table.
AT34C02 Write Protection Modes
WP Pin Status
Write Protect Register
Part of the Array Write Protected
Full Array (2K)
VCC
—
GND or Floating
Not Programmed
Normal Read/Write
First-Half of Array
(1K: 00H - 7FH)
GND or Floating
Programmed
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol Parameter
Test Condition
Min
1.8
2.7
4.5
Typ
Max
5.5
Units
V
VCC1
VCC2
VCC3
ICC
Supply Voltage
Supply Voltage
5.5
V
Supply Voltage
5.5
V
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Standby Current VCC = 1.8V
Standby Current VCC = 2.7V
Standby Current VCC = 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level(1)
READ at 100 KHz
WRITE at 100 KHz
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VOUT = VCC or VSS
0.4
2.0
1.0
mA
mA
µA
µA
µA
µA
µA
V
ICC
3.0
ISB1
ISB2
ISB3
ILI
0.6
3.0
1.6
4.0
8.0
18.0
3.0
0.10
0.05
ILO
3.0
VIL
-0.6
VCC x 0.3
VCC + 0.5
0.4
VIH
Input High Level(1)
VCC x 0.7
V
VOL2
Output Low Level VCC = 3.0V
Output Low Level VCC = 1.8V
IOL = 2.1 mA
V
VOL1
IOL = 0.15 mA
0.2
V
Note:
1. VIL min and VIH max are reference only and are not tested.
3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
1.8V, 2.7V
5.0V
Max
Symbol
fSCL
Parameter
Min
Max
Min
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(1)
Clock Low to Data Out Valid
Time the bus must be free before a new transmission can start(1)
Start Hold Time
100
400
tLOW
tHIGH
tI
4.7
4.0
1.2
0.6
µs
100
4.5
50
ns
tAA
0.1
4.7
4.0
4.7
0
0.1
1.2
0.6
0.6
0
0.9
µs
tBUF
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
µs
Start Set-up Time
µs
Data In Hold Time
µs
Data In Set-up Time
200
100
ns
Inputs Rise Time(1)
1.0
0.3
µs
tF
Inputs Fall Time(1)
300
300
ns
tSU.STO
tDH
Stop Set-up Time
4.7
0.6
50
µs
Data Out Hold Time
100
ns
tWR
Write Cycle Time
10
10
ms
Write
Cycles
Endurance(1)
5.0V, 25°C, Page Mode
1M
1M
Note:
1. This parameter is characterized and is not 100% tested.
Memory Organization
AT34C02, 2K Serial EEPROM: The 2K is internally orga-
nized with 256 pages of 1 byte each. Random word
addressing requires a 8-bit data word address.
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock
cycle.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as defined
below.
STANDBY MODE: The AT34C02 features a low power
standby mode which is enabled: (a) upon power-up or (b)
after the receipt of the STOP bit and the completion of any
internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps:
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle
while SCL is high and then (c) create a start condition as
SDA is high.
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
AT34C02
4
AT34C02
Bus Timing SCL: Serial Clock SDA: Serial Data I/O
Write Cycle Timing SCL: Serial Clock SDA: Serial Data I/O
(1)
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle.
5
Data Validity
Start and Stop Condition
Output Acknowledge
AT34C02
6
AT34C02
The data word address lower four bits are internally incre-
mented following the receipt of each data word. The higher
data word address bits are not incremented, retaining the
memory page row location. When the word address, inter-
nally generated, reaches the page boundary, the following
byte is placed at the beginning of the same page. If more
than sixteen data words are transmitted to the EEPROM,
the data word address will “roll over” and previous data will
be overwritten. The address “roll over” during write is from
the last byte of the current page to the first byte of the same
page.
Device Addressing
The 2K EEPROM device requires an 8-bit device address
word following a start condition to enable the chip for a read
or write operation (refer to Figure 2).
The device address word consists of a mandatory one-zero
sequence for the first four most-significant bits (1010) for
normal read and write operations and 0110 for writing to
the write protect register.
The next 3 bits are the A2, A1 and A0 device address bits
for the AT34C02 EEPROM. These 3 bits must compare to
their corresponding hard-wired input pins.
The device will acknowledge a write command, but not
write the data, if the software or hardware write protection
has been enabled. The write cycle time must be observed
even when the write protection is enabled.
The eighth bit of the device address is the read/write opera-
tion select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will
output a zero. If a compare is not made, the chip will return
to a standby state. The device will not acknowledge if the
write protect register has been programmed and the control
code is 0110.
ACKNOWLEDGE POLLING: Once the internally-timed
write cycle has started and the EEPROM inputs are dis-
abled, acknowledge polling can be initiated. This involves
sending a start condition followed by the device address
word. The read/write bit is representative of the operation
desired. Only if the internal write cycle has completed will
the EEPROM respond with a zero allowing the read or write
sequence to continue.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data
word address following the device address word and
acknowledgment. Upon receipt of this address, the
EEPROM will again respond with a zero and then clock in
the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write
sequence with a stop condition. At this time the EEPROM
enters an internally-timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and
the EEPROM will not respond until the write is complete
(refer to Figure 3).
Write Protection
The software write protection, once enabled, permanently
write protects only the first-half of the array (00H - 7FH)
while the hardware write protection, via the WP pin, is used
to protect the entire array.
SOFTWARE WRITE PROTECTION: The software write
protection is enabled by sending a command, similar to a
normal write command, to the device which programs the
write protect register. This must be done with the WP pin
low. The write protect register is programmed by sending a
write command with the device address of 0110 instead of
1010 with the address and data bit being don’t cares (refer
to Figure 1). Once the software write protection has been
enabled, the device will no longer acknowledge the 0110
control byte. The software write protection cannot be
reversed even if the device is powered down. The write
cycle time must be observed.
The device will acknowledge a write command, but not
write the data, if the software or hardware write protection
has been enabled. The write cycle time must be observed
even when the write protection is enabled.
PAGE WRITE: The 2K device is capable of 16-byte page
write.
A page write is initiated the same as a byte write, but the
microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcon-
troller can transmit up to fifteen more data words. The
EEPROM will respond with a zero after each data word
received. The microcontroller must terminate the page
write sequence with a stop condition (refer to Figure 4).
HARDWARE WRITE PROTECTION: The WP pin can be
connected to VCC, GND, or left floating. Connecting the WP
pin to VCC will write protect the entire array, regardless of
whether or not the software write protection has been
enabled. The software write protection register cannot be
programmed when the WP pin is connected to VCC. If the
WP pin is connected to GND or left floating, the write pro-
tection mode is determined by the status of the software
write protect register.
7
WP Connected to GND or Floating
Acknowledgment
from Device
Start R/W Bit Write Protect Register
Action from Device
1010
1010
1010
0110
0110
0110
0110
R
W
W
R
X
ACK
ACK
Read Array
Programmed
Not Programmed
Programmed
Not Programmed
Programmed
Not Programmed
Can Write to First Half Only
ACK
Can Write to Full Array
No ACK
ACK
Stop - Indicates Write Protect Register is Programmed
Read Out Data Don’t Care. Indicates WP Register is Not Prog
Stop - Indicates Write Protect Register is Programmed
Program Write Protect Register (irreversible)
R
W
W
No ACK
ACK
WP Connected to VCC
1010
1010
1010
0110
0110
0110
0110
R
W
W
R
X
ACK
ACK
Read Array
Programmed
Not Programmed
Programmed
Not Programmed
Programmed
Not Programmed
Device Write Protect
ACK
Device Write Protect
No ACK
ACK
Stop - Indicates Write Protect Register is Programmed
Read Out Data Don’t Care. Indicates WP Register is Not Prog
Stop - Indicates Write Protect Register is Programmed
Cannot Program Write Protect Register
R
W
W
No ACK
ACK
Figure 1. Setting Write Protect Register
S
T
A
R
T
CONTROL
BYTE
WORD
ADDRESS
S
T
O
P
DATA
SDA LINE
0 1 1 0
0
A
C
K
A
C
K
A
C
K
Read Operations
Read operations are initiated the same way as write opera-
tions with the exception that the read/write select bit in the
device address word is set to one. There are three read
operations: current address read, random address read
and sequential read.
the command, the microcontroller does not respond with an
input zero but does generate a following stop condition
(refer to Figure 5).
RANDOM READ: A random read requires a “dummy” byte
write sequence to load in the data word address. Once the
device address word and data word address are clocked in
and acknowledged by the EEPROM, the microcontroller
must generate another start condition. The microcontroller
now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM
acknowledges the device address and serially clocks out
the data word. To end the command, the microcontroller
does not respond with a zero but does generate a following
stop condition (refer to Figure 6).
CURRENT ADDRESS READ: The internal data word
address counter maintains the last address accessed dur-
ing the last read or write operation, incremented by one.
This address stays valid between operations as long as the
chip power is maintained. The address “roll over” during
read is from the last byte of the last memory page to the
first byte of the first page.
Once the device address with the read/write select bit set to
one is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. To end
AT34C02
8
AT34C02
SEQUENTIAL READ: Sequential reads are initiated by
either a current address read or a random address read.
After the microcontroller receives a data word, it responds
with an acknowledge. As long as the EEPROM receives an
acknowledge, it will continue to increment the data word
address and serially clock out sequential data words. When
the memory address limit is reached, the data word
address will “roll over” and the sequential read will con-
tinue. The sequential read operation is terminated when
the microcontroller does not respond with a zero but does
generate a following stop condition (refer to Figure 7).
WRITE PROTECT REGISTER STATUS: To find out if the
register has been programmed, the same procedure is
used as to program the register except that the R/W bit is
set to 1. If the device acknowledges, then the write protect
register has not been programmed. Otherwise, it has been
programmed and the device is permanently write protected
at the first half of the array.
Figure 2. Device Address
Figure 3. Byte Write
Figure 4. Page Write
Figure 5. Current Address Read
9
Figure 6. Random Read
Figure 7. Sequential Read
AT34C02
10
AT34C02
Ordering Information
tWR (max)
ICC (max)
ISB (max)
fMAX
(ms)
(µA)
(µA)
(kHz)
Ordering Code
Package
Operation Range
10
10
10
3000
3000
1500
1500
800
18
18
4
400
400
100
100
100
100
AT34C02-10PC
AT34C02N-10SC
AT34C02-10TC
8P3
8S1
8T
Commercial
(0°C to 70°C)
AT34C02-10PI
AT34C02N-10SI
AT34C02-10TI
8P3
8S1
8T
Industrial
(-40°C to 85°C)
AT34C02-10PC-2.7
AT34C02N-10SC-2.7
AT34C02-10TC-2.7
8P3
8S1
8T
Commercial
(0°C to 70°C)
4
AT34C02-10PI-2.7
AT34C02N-10SI-2.7
AT34C02-10TI-2.7
8P3
8S1
8T
Industrial
(-40°C to 85°C)
3
AT34C02-10PC-1.8
AT34C02N-10SC-1.8
AT34C02-10TC-1.8
8P3
8S1
8T
Commercial
(0°C to 70°C)
800
3
AT34C02-10PI-1.8
AT34C02N-10SI-1.8
AT34C02-10TI-1.8
8P3
8S1
8T
Industrial
(-40°C to 85°C)
Package Type
8P3
8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline Package(JEDEC SOIC)
8-Lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
8S1
8T
Blank
-2.7
Standard Operation (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
-1.8
Low Voltage (1.8V to 5.5V)
11
Packaging Information
8P3, 8-Lead, 0.300" Wide, Plastic Dual Inline
Package (PDIP)
8S1, 8-Lead, 0.150" Wide, Plastic Gull Wing Small
Outline (JEDEC SOIC)
Dimensions in Inches and (Millimeters)
Dimensions in Inches and (Millimeters)
.020 (.508)
.013 (.330)
.400 (10.16)
.355 (9.02)
PIN
1
.244 (6.20)
.228 (5.79)
.157 (3.99)
.150 (3.81)
.280 (7.11)
.240 (6.10)
PIN 1
.037 (.940)
.027 (.690)
.300 (7.62) REF
.210 (5.33) MAX
.050 (1.27) BSC
.100 (2.54) BSC
.196 (4.98)
.189 (4.80)
SEATING
PLANE
.068 (1.73)
.053 (1.35)
.015 (.380) MIN
.150 (3.81)
.115 (2.92)
.022 (.559)
.014 (.356)
.070 (1.78)
.045 (1.14)
.010 (.254)
.004 (.102)
.325 (8.26)
.300 (7.62)
0
8
REF
.010 (.254)
.007 (.203)
0
REF
15
.012 (.305)
.008 (.203)
.050 (1.27)
.016 (.406)
.430 (10.9) MAX
8T, 8-Lead, 0.170" Wide, Thin Shrink Small Outline
Package (TSSOP)
Dimensions in Millimeters and (Inches)
PIN 1
6.50 (.256)
6.25 (.246)
0.30 (.012)
0.19 (.008)
3.10 (.122)
2.90 (.114)
1.05 (.041)
0.80 (.033)
1.20 (.047) MAX
.65 (.026) BSC
0.15 (.006)
0.05 (.002)
4.5 (.177)
4.3 (.169)
0.20 (.008)
0.09 (.004)
0.75 (.030)
0.45 (.018)
0
8
REF
AT34C02
12
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