AV6532E-B [APLUS]
Speech Synthesizer, 65s, CMOS;
| 型号： | AV6532E-B |
| 厂家： | 
APLUS INTERGRATED CIRCUITS |
| 描述： | Speech Synthesizer, 65s, CMOS |
| 文件： | 总11页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A
PLUS MAKE YOUR PRODUCTION A-PLUS
AVXX32E-B SERIES
DATA SHEET
APLUS INTEGRATED CIRCUITS INC.
Address:
3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,
Sales E-mail:
Taiwan 115, R.O.C.
sales@aplusinc.com.tw
(115)台北市南港區成功路㆒段 32 號 3 樓之 10.
Technology E-mail:
service@aplusinc.com.tw
TEL: 886-2-2782-9266
FAX: 886-2-2782-9255
WEBSITE : http: //www.aplusinc.com.tw
AVXX32E-B SERIES
21, 32, 43, 65 and 87 Seconds Complicate Pure Speech
Features
yꢀ Operating voltage: 2.4V~5.0V
Ϋʳ OP_D Status0: Busy_high, DC_low
Status1: Busy_low, DC_high
yꢀ One single-key can implement play-all, play-next
and random function. Maximum play count is 32.
yꢀ 4-column inputs and 3-row outputs can
implement 4x4-matrix function.
yꢀ Each output can specify its initial state (High or
Low)
yꢀ Outputs can be set as constant current
regardless of the supply voltage varied.
yꢀ Two PWM playing ports. Drive speaker or
buzzer directly (For tone only).
yꢀ Each input can implement looping function.
yꢀ Single-key and 4-column inputs can be last-key
priority for stand-alone input or first-key priority.
yꢀ Each input trigger can select trigger mode: (For
OKY, TG0, TG1, TG2, TG3) Edge/Level,
Hold/Unhold, Retrigger/Irretrigger.
yꢀ Each input trigger can select its own debounce
time:
yꢀ One DAC playing port, together with external
bipolar to drive speaker. Ramp up/down is
automatic.
yꢀ For DAC, AVXX32E-B series supports 8
levels of current control to offer flexible choises
of corresponding BJT.
Fast debounce: < 200us;
Slow debounce: ~16ms (S.R.=6.0kHz)
yꢀ Support bouncing trigger solution for retrigger
application. (Second trigger force to retrigger
and slow debounce.)
yꢀ Four-level volume control is provided for DAC or
PWM output.
yꢀ Eight-pitch control is provided.
yꢀ Voice length: 21, 32, 43, 65 and 87 seconds.
(ROM capacity : 131072*5, 196608*5, 262144*5,
393216*5 and 524288*5 bits)
yꢀ Maximum table entries are 460*8.
yꢀ Word count is only limited by ROM capacity.
yꢀ 4 output ports for Status or Led application:
Ϋʳ OP_A Status:
yꢀ Voice algorithm: 5-bits LOG_PCM
yꢀ External resister or built-in resister for system
frequency by bonding option on the same pad.
yꢀ Sixteen default sampling frequencies are
supported. The default frequencies can be
changed by an external applying resistor.
yꢀ Support single key play on/off. (For OKY, TG0,
TG1)
Busy_high ,DC_low, Stop_high,DC_high
LED: +Fast,+Slow, Dyn(7/10), Off
Ϋʳ OP_B Status:
Busy_high, DC_low, Stop_high, DC_high
LED: -Fast, -Slow, Dyn(9/10), On
Ϋʳ OP_C Status: Busy_high, DC_low,
Busy_low, DC_high
yꢀ Programmable pull-high, pull-low or floating
input. (For OKY, TG0, TG1)
LED: +Fast, +Slow, On, Off
General Description
The AVXX32E-B is a series of single-chip
synthesizing CMOS VLSI which synthesizes voice
by LOG_PCM algorithm. Table programming and shared
multiple I/O pins make the applications flexible. Powerful
functions and pure speech architecture make the
AVXX32E-B series able to best fit most
speech applications and a best cost/performance ratio
as a result.
maximum 4*4 matrix plus one single-key inputs, but
less outputs; or 4 maximum outputs, but less inputs.
The AVXX32E-B series support DAC or
PWM audio output, the users can select both if
necessary.
The frequency stability in the AVXX32E-B
series is outstanding. The frequency variation by
voltage change is relatively small compared to the
competitor. Furthermore, volume option offers users
flexible selection for their applications. In addition, the
AVXX32E-B series support current control for
DAC output. Thus users can choose suitable current
output for their BJT component.
The programming of the AVXX32E-B
series is first to define words. Each word contains
voice data (or mute length), output method, pitch (if
pitch control enabled), and volume (if volume control
enabled). Assemble the words into sentences first,
and then the programmer can assign the sentences
to the keys corresponding to the user inputs.
The programming and the approval can be done in
the EV chip of the AVXX32E-B series. It
makes the programming and verification easy.
Please contact APLUS sales for the EV chip if
required.
The I/O pins of the AVXX32E-B series are
multiplexed. This means the users have flexible I/O
options for their applications in a minimum number of
pin counts, that is, lower cost. The users can use
10-1
Ver. 1.0
AVXX32E-B SERIES
Pin Description
Pin Name
VDD
I/O
Power
In
Pad Assign
Description
Positive power supply
Test enable pad, high-active, pull-low
TEST
With resister connected to VDD for system clock
generating or connected to VSS using internal resister
Trigger input, active-high
OSC
In
In
OKY
OKY_RW3
TG0,TG1
Out
In
ROW3
Row output for matrix function.
Column input or stand-alone input; active-high
Column input or stand-alone input; active-high
Status output
In
TG2
OP_D
TG3
TG2_OPD
TG3_OPC
RW1_OPB
RW2_OPA
Out
In
Column input or stand-alone input; active-high
Status output
Out
Out
Out
Out
Out
Out
OP_C
ROW1
OP_B
ROW2
OP_A
PWM1
OP_A
OP_C
PWM2
OP_B
OP_D
DAC
Row output for matrix function
Status output
Row output for matrix function
Status output
Voltage output to drive speaker or buzzer
PWM1
PWM2
Out
Out
Status output
Voltage output to drive speaker or buzzer
Out
Out
Status output
Current output for speaker application
OP_A
OP_B
OP_C
OP_D
DAC
VSS
Out
Status output
Power
Negative power supply
Absolute Maximum Rating
Symbol
Rating
-0.5 ~ +0.5
Unit
V
VDD~VSS
VIN (for input)
VSS-0.3 < VIN < VDD+0.3
VSS < VOUT < VDD
-10 ~ +60
V
VOUT (for all outputs)
V
к
T (operating)
T (storage)
-55 ~ +125
к
10-2
Ver. 1.0
AVXX32E-B SERIES
DC Characteristics
Symbol
Parameter
Min Typ. Max Unit
Condition
VDD
Isb
Iop
Iih
Operating Voltage
2.4 3.0 5.0
V
Ϋ
Ϋ
Ϋ
Ϋ
Ϋ
Ϋ
Ϋ
Ϋ
Ϋ
Ϋ
10
-5
ӴA
ӴA
ӴA
ӴA
Standby
Operating
1
400
-20
20
Ϋ
VDD=3.0V, I/O open
Supply
Current
VDD=3.0V, No loading
VDD=3.0V, VIP=0V
Input Current
Iil
VDD=3.0V, VIP=3.0V
Iol
Ioh
mA VDD=3.0V, VOP=0.8V
mA VDD=3.0V, VOP=2.5V
Output Current
Frequency Stability
Ϋ
(fOSC (4.5V)-fOSC(4.0))/
Ϋ
Ϋ
Ϋ
d F/F
%
r5
fOSC (4.5V)
Frequency
Variation
by
VDD=4.5V
Ϋ
d F/F
%
r10
difference lot
fOSC =384kHz
Function Diagram
Edge/Level mode (If sentence = word1+word2)
yꢀ Edge mode
Trigger length > Voice length
7*
$XGLR
ZRUGꢀ ZRUGꢁ
GHERXQFHꢂWLPH
Trigger length < Voice length
7*
ZRUGꢀ ZRUGꢁ
GHERXQFHꢂWLPH
yꢀ Level mode
Trigger length > Voice length (if sentence=word1+word2)
7*
$XGLR
ZRUGꢀ ZRUGꢁ ZRUGꢀ ZRUGꢁ
GHERXQFHꢂWLPH
10-3
Ver. 1.0
AVXX32E-B SERIES
Trigger length < Voice length (if sentence = word1+word2)
7*
$XGLR
ZRUGꢀ ZRUGꢁ
GHERXQFHꢂWLPH
Hold/Unhold mode (If sentence = word1+word2)
yꢀ Hold mode
7*
ZRUGꢁ
$XGLR
ZRUGꢀ
GHERXQFHꢂWLPH
yꢀ Unhold mode
7*
$XGLR
ZRUGꢀ ZRUGꢁ
GHERXQFHꢂWLPH
Retrigger/Irretrigger mode (If sentence = word1+word2)
yꢀ Retrigger mode (Edge Unhold mode)
7*
$XGLR
ZRUGꢀ ZRUGꢁ ZRUGꢀ ZRUGꢁ
GHERXQFHꢂWLPH
yꢀ Irretrigger mode (Edge, Unhold mode)
7*
$XGLR
ZRUGꢀ ZRUGꢁ
GHERXQFHꢂWLPH
10-4
Ver. 1.0
AVXX32E-B SERIES
Last key priority
yꢀ If TG1, TG2 are retrigger mode
7*ꢀ
7*ꢁ
$XGLR
7*ꢀꢃV 7*ꢁꢃV
7*ꢀꢃV
7*ꢁꢃV
Looping function
If sentence is set to looping mode (sentence1_sentence2)
yꢀ Unhold mode
7*
VHQWHQFH VHQWHQFH VHQWHQFH VHQWHQFH
$XGLR
ꢀ
ꢁ
ꢁ
ꢁ
yꢀ Hold mode
7*
VHQWHQFHꢁ
VHQWHQFH VHQWHQFH
$XGLR
ꢀ
ꢁ
Force to retrigger and slow debounce option
(Trigger mode set to Fast debounce and Irretrigger mode)
ꢀVWꢂ7*
)56%
'RQꢃWꢂFDUH
$XGLR
:ꢀꢀ :ꢀꢁ :ꢀꢄ :ꢀꢅ
7KLVꢂZRUGꢂPXVWꢂEHꢂODUJHUꢂWKDQꢂJOLWFKꢂSHULRGꢆ
ꢇ$ꢂPXWHꢂZRUGꢂFDQꢂEHꢂXVHGꢂEHUKDSVꢆꢈ
ꢁQGꢂ7*
)56%
$XGLR
:ꢁꢀ :ꢁꢁ :ꢁꢄ :ꢁꢅ
6ORZꢂGHERXQFHꢉ
6ORZꢂGHERXQFHꢉ
5HWULJJHUꢂPRGH
5HWULJJHUꢂPRGH
)DVWꢂGHERXQFHꢉ
,UUHWULJJHUꢂPRGH
)DVWꢂGHERXQFHꢉ
,UUHWULJJHUꢂPRGH
Busy=0, FRSB set to high;
Busy=1, depending on FRSB setting.
If FRSB=0, force to slow debounce and retrigger mode;
If FRSB=1, no change (fast debounce and irretrigger mode).
10-5
Ver. 1.0
AVXX32E-B SERIES
Stand-alone trigger inputs are enabled at the same time
OKY
COL0
COL1
COL2
COL3
Audio
This voice is enabled by COL3
Trigger input priority is COL3 > COL2 > COL1 > COL0 > OKY
Application circuit
yꢀ External resister, Driver speaker by PWM, driver LED
VDD
Rosc
OSC
OKY
OP_A
PWM1
PWM2
VSS
ROSC=200k: for frequency option 8
yꢀ Internal resister, driver speaker by PWM, driver LED
If OSC bonds to VSS, this chip uses internal resister automatically.
VDD
OKY
OSC
OP_A
PWM1
PWM2
VSS
10-6
Ver. 1.0
AVXX32E-B SERIES
yꢀ Power on play
Set the pull resisters of OKY, TG0 or TG1 to pull-high will cause the triggers to play immediately after
power on.
VDD
OSC
OP_A
PWM1
PWM2
VSS
yꢀ Matrix input
526&
9''
26&
2.<
7*ꢅ 7*ꢍ 7*ꢀꢁ
23B$
7*ꢏ
&2/ꢏ
23B%
23B&
7*ꢀ
&2/ꢀ
&2/ꢁ
&2/ꢄ
7*ꢁ
7*ꢄ
7*ꢎ 7*ꢀꢀ 7*ꢀꢌ
52:ꢄ
52:ꢁ
52:ꢀ
3:0ꢀ
3:0ꢁ
966
yꢀ Driver speaker by DAC and driver Motor application
ROSC
VDD
OSC
OKY
OP_A
OP_B
OP_C
-
+
Motor
C1
DAC
Cx
Rx
VSS
10-7
Ver. 1.0
AVXX32E-B SERIES
yꢀ Stand-alone trigger input
ROSC
VDD
OSC
OKY
OP_A
OP_B
OP_C
COL0
COL1
COL2
COL3
PWM1
PWM2
VSS
Output Definition
Option
0
BH
L
1
DL
L
2
3
DH
H
Status
SH
L
Standby state
OPA
LED
+Fast
H
+Slow
H
Dy07
H
OFF
H
Standby state
Status
BH
L
DL
L
SH
L
DH
H
Standby state
OPB
LED
-Fast
H
-Slow
H
Dy09
H
ON
H
Standby state
Status
BH
L
DL
L
BL
H
DH
H
Standby state
OPC
LED
+Fast
H
+Slow
H
ON
H
OFF
H
Standby state
Status1
BH
L
DL
L
Standby state
OPD
Satatus2
BH
H
DL
H
Standby state
10-8
Ver. 1.0
AVXX32E-B SERIES
Bonding Diagram
Y
PWM1
VSS
PWM2
VDD
TG0
TG1
DAC
OSC
RW2_OPA
TG3_OPC
TEST
OKY_RW3
RW1_OPB
TG2_OPD
X
Note: The IC substrate should be connect to VSS
(1) AV2132E
PIN Name
OKY_RW3
RW2_OPA
RW1_OPB
TG3_OPC
TG2_OPD
TEST
X(mm)
250.75
451.50
660.25
861.00
1069.75
1270.25
94.00
Y(mm)
94.00
94.25
94.25
94.25
94.25
94.25
OSC
271.25
TG1
1313.25
94.00
297.00
DAC
472.25
TG0
1313.25
410.75
631.00
1049.50
1331.00
501.00
VSS
1419.50
PWM2
1440.00
1440.00
PWM1
VDD
1440.00
DIE SIZE = 1510 * 1655 Pm^2 (X*Y)
(2) AV3232E
PIN Name
OKY_RW3
RW2_OPA
RW1_OPB
TG3_OPC
TG2_OPD
TEST
X(mm)
250.75
451.50
660.25
861.00
1069.75
1270.25
94.00
Y(mm)
94.00
94.25
94.25
94.25
94.25
94.25
OSC
271.25
TG1
1313.25
94.00
297.00
DAC
472.25
TG0
1313.25
410.75
631.00
1049.50
1331.00
501.00
VSS
1649.50
PWM2
1670.00
1670.00
PWM1
VDD
1670.00
DIE SIZE = 1510 * 1885 Pm^2 (X*Y)
10-9
Ver. 1.0
AVXX32E-B SERIES
(3) AV4332E
PIN Name
X(mm)
250.75
451.50
660.25
861.00
1069.75
1270.25
94.00
Y(mm)
OKY_RW3
RW2_OPA
RW1_OPB
TG3_OPC
TG2_OPD
TEST
94.00
94.25
94.25
94.25
94.25
94.25
OSC
271.25
TG1
1313.25
94.00
297.00
DAC
472.25
TG0
1313.25
410.75
631.00
1049.50
1331.00
501.00
VSS
1870.50
PWM2
PWM1
VDD
1890.25
1890.25
1890.25
DIE SIZE = 1510 * 2115 Pm^2 (X*Y)
(4) AV6532E
PIN Name
OKY_RW3
RW2_OPA
RW1_OPB
TG3_OPC
TG2_OPD
TEST
X(mm)
259.25
460.00
668.75
869.50
1078.25
1278.75
102.50
1321.75
102.50
1321.75
419.25
639.50
1058.00
1271.25
Y(mm)
94.00
94.25
94.25
94.25
94.25
94.25
OSC
271.25
TG1
297.00
DAC
472.25
TG0
501.00
VSS
2322.50
PWM2
2342.25
PWM1
2342.25
2364.25
VDD
DIE SIZE = 1427.25 * 2457.50 Pm^2 (X*Y)
(5) AV8732E
PIN Name
OKY_RW3
RW2_OPA
RW1_OPB
TG3_OPC
TG2_OPD
TEST
X(mm)
266.00
466.75
675.50
876.25
1085.00
1285.50
109.25
1328.50
109.25
1328.50
426.00
646.25
1064.75
1271.25
Y(mm)
94.00
94.25
94.25
94.25
94.25
94.25
OSC
271.25
TG1
297.00
DAC
472.25
TG0
501.00
VSS
2801.25
PWM2
PWM1
2821.00
2821.00
2815.00
VDD
DIE SIZE = 1427.25 * 2908.25 Pm^2 (X*Y)
10-10
Ver. 1.0
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