AV80576GH0676MG/SLGEL [INTEL]
RISC Microprocessor, 64-Bit, 2660MHz, PBGA479;型号: | AV80576GH0676MG/SLGEL |
厂家: | INTEL |
描述: | RISC Microprocessor, 64-Bit, 2660MHz, PBGA479 |
文件: | 总113页 (文件大小:2115K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Intel® Core™2 Duo Mobile
Processor, Intel® Core™2 Solo
Mobile Processor and Intel® Core™2
Extreme Mobile Processor on 45-nm
Process
Datasheet
For platforms based on Mobile Intel® 4 Series Express Chipset Family
March 2009
Document Number: 320120-004
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MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics
of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with
this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Φ 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications
enabled for IntelÆ 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for
more information.
Enhanced Intel SpeedStep® Technology for specified units of this processor are available. See the Processor Spec Finder at http://
processorfinder.intel.com or contact your Intel representative for more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check
with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Φ
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some
uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations
and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.
Intel, Pentium, Centrino, Intel Core Duo, Intel SpeedStep, MMX and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2008-2009, Intel Corporation. All rights reserved.
2
Datasheet
Contents
1
Introduction..............................................................................................................7
1.1
1.2
Terminology .......................................................................................................8
References .........................................................................................................9
2
Low Power Features................................................................................................ 11
2.1
Clock Control and Low-Power States .................................................................... 11
2.1.1 Core Low-Power State Descriptions........................................................... 13
2.1.1.1 Core C0 State........................................................................... 13
2.1.1.2 Core C1/AutoHALT Powerdown State........................................... 13
2.1.1.3 Core C1/MWAIT Powerdown State............................................... 14
2.1.1.4 Core C2 State........................................................................... 14
2.1.1.5 Core C3 State........................................................................... 14
2.1.1.6 Core C4 State........................................................................... 14
2.1.1.7 Core Deep Power Down Technology (Code Name C6) State ............ 15
2.1.2 Package Low-power State Descriptions...................................................... 15
2.1.2.1 Normal State............................................................................ 15
2.1.2.2 Stop-Grant State ...................................................................... 15
2.1.2.3 Stop-Grant Snoop State............................................................. 16
2.1.2.4 Sleep State.............................................................................. 16
2.1.2.5 Deep Sleep State...................................................................... 16
2.1.2.6 Deeper Sleep State................................................................... 17
Enhanced Intel SpeedStep® Technology .............................................................. 19
Extended Low-Power States................................................................................ 20
FSB Low Power Enhancements............................................................................ 21
2.4.1 Dynamic FSB Frequency Switching ........................................................... 21
2.4.2 Enhanced Intel® Dynamic Acceleration Technology .................................... 22
VID-x .............................................................................................................. 23
Processor Power Status Indicator (PSI-2) Signal.................................................... 23
2.2
2.3
2.4
2.5
2.6
3
Electrical Specifications........................................................................................... 25
3.1
3.2
Power and Ground Pins ...................................................................................... 25
Decoupling Guidelines........................................................................................ 25
3.2.1 VCC Decoupling...................................................................................... 25
3.2.2 FSB AGTL+ Decoupling ........................................................................... 25
3.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking........................................... 25
Voltage Identification and Power Sequencing ........................................................ 26
Catastrophic Thermal Protection.......................................................................... 29
Reserved and Unused Pins.................................................................................. 29
FSB Frequency Select Signals (BSEL[2:0])............................................................ 29
FSB Signal Groups............................................................................................. 30
CMOS Signals ................................................................................................... 31
Maximum Ratings.............................................................................................. 31
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10 Processor DC Specifications ................................................................................ 32
4
5
Package Mechanical Specifications and Pin Information.......................................... 51
4.1
4.2
4.3
Package Mechanical Specifications....................................................................... 51
Processor Pinout and Pin List .............................................................................. 59
Alphabetical Signals Reference............................................................................ 93
Thermal Specifications and Design Considerations ................................................ 101
5.1
Monitoring Die Temperature ............................................................................. 108
5.1.1 Thermal Diode ..................................................................................... 108
5.1.2 Intel® Thermal Monitor......................................................................... 109
Datasheet
3
5.1.3 Digital Thermal Sensor ..........................................................................111
Out of Specification Detection............................................................................112
PROCHOT# Signal Pin ......................................................................................112
5.2
5.3
Figures
1
2
3
4
Core Low-Power States .............................................................................................12
Package Low-Power States ........................................................................................13
Dynamic FSB Frequency Switching Protocol..................................................................22
Active VCC and ICC Loadline for Standard Voltage, Low-Power SV (25 W) and Dual-Core,
Extreme Edition Processors........................................................................................43
Deeper Sleep VCC and ICC Loadline for Standard-Voltage, Low-Power SV (25 W) and Dual-
Core Extreme Edition Processors ................................................................................44
Deeper Sleep VCC and ICC Loadline for Low-Power Standard-Voltage Processors ..............45
Active VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and Power Optimized
Performance Processor..............................................................................................46
Deeper Sleep VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and Power Optimized
Performance Processor..............................................................................................47
6-MB and 3-MB on 6-MB Die Micro-FCPGA Package Drawing (Sheet 1 of 2) ......................52
5
6
7
8
9
10 3-MB die Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) ...................................53
11 3-MB Die Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)...................................54
12 3-MB Die Micro-FCBGA Processor Package Drawing (Sheet 1 of 2) ..................................55
13 3-MB Die Micro-FCBGA Processor Package Drawing (Sheet 2 of 2) ..................................56
14 Intel Core 2 Duo Mobile Processor (POP and LV) Die Micro-FCBGA Processor Package
Drawing..................................................................................................................57
15 Intel Core 2 Duo Mobile Processor (ULV SC and ULV DC) Die Micro-FCBGA Processor Package
Drawing..................................................................................................................58
16 Processor Pinout (Top Package View, Left Side) ............................................................59
17 Processor Pinout (Top Package View, Right Side) ..........................................................60
18 Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Left Side.....................80
19 Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Right Side...................81
20 Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Left Side.....................82
21 Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Right Side...................83
Tables
1
Coordination of Core Low-Power States at the Package Level..........................................13
2
3
4
5
6
7
8
Voltage Identification Definition..................................................................................26
BSEL[2:0] Encoding for BCLK Frequency......................................................................29
FSB Pin Groups ........................................................................................................30
Processor Absolute Maximum Ratings..........................................................................31
Voltage and Current Specifications for the Dual-Core, Extreme Edition Processors .............32
Voltage and Current Specifications for the Dual-Core, Standard-Voltage Processors...........34
Voltage and Current Specifications for the Dual-Core, Low-Power Standard-Voltage Processors
(25 W) in Standard Package ......................................................................................35
Voltage and Current Specifications for the Dual-Core, Power Optimized Performance (25 W)
SFF Processors.........................................................................................................37
9
10 Voltage and Current Specifications for the Dual-Core, Low-Voltage SFF Processor .............38
11 Voltage and Current Specifications for the Dual-Core, Ultra-Low-Voltage SFF Processor .....40
12 Voltage and Current Specifications for the Ultra-Low-Voltage, Single-Core
(5.5 W) SFF Processor...............................................................................................41
13 AGTL+ Signal Group DC Specifications ........................................................................48
14 CMOS Signal Group DC Specifications..........................................................................49
15 Open Drain Signal Group DC Specifications ..................................................................49
4
Datasheet
16 Pin Name Listing...................................................................................................... 61
17 Pin # Listing............................................................................................................ 72
18 Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name........................... 84
19 Signal Description .................................................................................................... 93
20 Power Specifications for the Dual-Core Extreme Edition Processor................................. 101
21 Power Specifications for the Dual-Core Standard Voltage Processor............................... 102
22 Power Specifications for the Dual-Core Low Power Standard Voltage Processors (25 W) in
Standard Package .................................................................................................. 103
23 Power Specifications for the Dual-Core Power Optimized Performance (25 W) SFF
Processors ............................................................................................................ 104
24 Power Specifications fro the Dual-Core Low Voltage (LV) SFF Processors ....................... 105
25 Power Specifications for the Dual-Core Ultra-Low-Voltage (ULV) Processors ................... 106
26 Power Specifications for the Single-Core Ultra-Low-Voltage (5.5 W) SFF Processors ........ 107
27 Thermal Diode Interface ......................................................................................... 108
28 Thermal Diode Parameters Using Transistor Model...................................................... 109
Datasheet
5
Revision History
Document Revision
Description
Date
Number
Number
320120
-001
Initial Release
July 2008
• Chapter Update
— Chapter 1: Added introduction to the Intel Core 2 Duo
Processor in SFF Package
— Section 4.1: Added the package coplanarity information for
the processors in SFF Package
• Figure Update
— Added Figure 7
— Added Figure 8
— Added Figure 14
— Added Figure 15
— Added Figure 18 through Figure 21
• Table Update
320120
-002
August 2008
— Added Table 9
— Added Table 10
— Added Table 11
— Added Table 12
— Updated Table 16: Added Intel Core 2 Duo SFF Package
Processor Ball listing by Pin name
— Added Table 18
— Added Table 23
— Added Table 24
— Added Table 25
• Added information for Intel Core 2 Duo T9800, T9550, P9600,
P8700
320120
320120
-003
-004
January 2009
March 2009
• Added information for Intel Core 2 Duo processor skus below:
— Updated Table 7 and 21 with T9900
— Updated Table 9 and 23 with SP9600
— Updated Table 10 and 24 with SL9600
— Updataed Table 11 and 25 with SU9600
— Updated Table 12 and 26 with SU3500
§
6
Datasheet
Introduction
1
Introduction
The Intel® Core™2 Duo mobile processor, Intel® Core™2 Duo mobile processor low-
voltage (LV), ultra low-voltage (ULV) in small form factor (SFF) package and Intel®
Core™2 Extreme mobile are high-performance, low-power mobile processor based on
the Intel Core microarchitecture for Intel® Centrino® 2 processor technology.
This document contains electrical, mechanical and thermal specifications for the
following processors:
• The Intel Core 2 Duo processors and Intel Core 2 Extreme processors support the
Mobile Intel® 4 Series Express Chipset and Intel® ICH9M I/O controller.
— Dual-core extreme edition (DC-XE)
— Standard voltage (SV)
— 25-W processor in standard package (Power Optimized Performance-POP)
• The Intel Core 2 Duo processor in SFF package supports the Mobile Intel® GS45
Express Chipset and Intel® ICH9M SFF I/O controller.
This document contains electrical, mechanical and thermal specifications for:
— Power Optimized Performance (POP) in SFF package
— Low-voltage (LV) Processor in SFF package
— Ultra-low voltage (ULV) dual-core (DC) and single-core (SC) Processors in SFF
package
Notes:
In this document
1. Intel Core 2 Duo processor, and the Intel Core 2 Extreme processor are referred to
as the processor
2. Intel Core 2 Duo LV/ULV/POP processors are referred to as SFF processor
3. Mobile Intel 4 Series Express Chipset is referred as the GMCH.
Key features include:
• Dual-core processor for mobile with enhanced performance
• Supports Intel architecture with Intel® Wide Dynamic Execution
• Supports L1 cache-to-cache (C2C) transfer
• On-die, primary 32-KB instruction cache and 32-KB, write-back data cache in each
core
• The processor in DC-XE, standard voltage (SV) and LV have an on-die, up to 6-MB
second-level, shared cache with Advanced Transfer Cache architecture
• The processor in ULV single-core and dual-core have an on-die, up to 3-MB
second-level, shared cache with Advanced Transfer Cache architecture
• Streaming SIMD extensions 2 (SSE2), streaming SIMD extensions 3 (SSE3),
supplemental streaming SIMD extensions 3 (SSSE3) and SSE4.1 instruction sets
• The processor in DC-XE, SV and LV are offered at 1066-MHz, source-synchronous
front side bus (FSB)
• The processor in ULV are offered at 800-MHz, source-synchronous FSB
• Advanced power management features including Enhanced Intel SpeedStep®
Technology and dynamic FSB frequency switching
Datasheet
7
Introduction
• Digital thermal sensor (DTS)
• Intel® 64 architecture
• Supports enhanced Intel® Virtualization Technology
• Enhanced Intel® Dynamic Acceleration Technology and Enhanced Multi-Threaded
Thermal Management (EMTTM)
• Supports PSI2 functionality
• SV processor offered in Micro-FCPGA and Micro-FCBGA packaging technologies
• Processor in POP, LV and ULV are offered in Micro-FCBGA packaging technologies
only
• Execute Disable Bit support for enhanced security
• Intel® Deep Power Down low-power state with P_LVL6 I/O support
• Support for Intel® Trusted Execution Technology
• Half ratio support (N/2) for core to bus ratio
1.1
Terminology
Term
Definition
A “#” symbol after a signal name refers to an active low signal, indicating a
signal is in the active state when driven to a low level. For example, when
RESET# is low, a reset has been requested. Conversely, when NMI is high,
a nonmaskable interrupt has occurred. In the case of signals where the
name does not imply an active state but describes part of a binary
sequence (such as address or data), the “#” symbol implies that the signal
is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#
= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
#
Front Side Bus
(FSB)
Refers to the interface between the processor and system core logic (also
known as the chipset components).
Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+
signaling technology on some Intel processors.
AGTL+
Refers to a non-operational state. The processor may be installed in a
platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor landings should not
be connected to any supply voltages, have any I/Os biased or receive any
clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device
removed from packaging material) the processor must be handled in
accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
Storage
Conditions
Enhanced Intel
SpeedStep®
Technology
Technology that provides power management capabilities to laptops.
Processor core die with integrated L1 and L2 cache. All AC timing and signal
integrity specifications are at the pads of the processor core.
Processor Core
8
Datasheet
Introduction
Term
Definition
The Execute Disable bit allows memory to be marked as executable or non-
executable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to
the operating system. This feature can prevent some classes of viruses or
worms that exploit buffer overrun vulnerabilities and can thus help improve
the overall security of the system. See the Intel® 64 and IA-32
Execute Disable
Bit
Architectures Software Developer's Manuals for more detailed information.
Intel® 64
Technology
64-bit memory extensions to the IA-32 architecture.
Intel®
Virtualization
Technology
Processor virtualization that, when used in conjunction with Virtual Machine
Monitor software, enables multiple, robust independent software
environments inside a single platform.
Half ratio support
(N/2) for Core to
Bus ratio
Intel Core 2 Duo processors and Intel Core 2 Extreme processors support
the N/2 feature that allows having fractional core-to-bus ratios. This feature
provides the flexibility of having more frequency options and being able to
have products with smaller frequency steps.
TDP
VCC
VSS
Thermal Design Power.
The processor core power supply.
The processor ground.
Low-voltage
LV
ULV
DC-XE
Ultra-Low-Voltage
Dual-core Extreme Edition
1.2
References
Material and concepts available in the following documents may be beneficial when
reading this document.
Document
Document
Number
Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile
Processor, Intel® Core™2 Extreme Processor on 45-nm Technology
320121
Specification Update
Mobile Intel® 4 Series Express Chipset Family Datasheet
320122
320123
Mobile Intel® 4 Series Express Chipset Family Specification Update
Intel® I/O Controller Hub 9 (ICH9)/ I/O Controller Hub 9M (ICH9M)
Datasheet
316972
316973
Intel® I/O Controller Hub 9 (ICH9)/ I/O Controller Hub 9M (ICH9M)
Specification Update
Intel® 64 and IA-32 Architectures Software Developer's Manuals
Volume 1: Basic Architecture
253665
253666
Volume 2A: Instruction Set Reference, A-M
Datasheet
9
Introduction
Document
Number
Document
Volume 2B: Instruction Set Reference, N-Z
Volume 3A: System Programming Guide
Volume 3B: System Programming Guide
253667
253668
253669
NOTE: Contact your Intel representative for the latest revision of this document.
§
10
Datasheet
Low Power Features
2
Low Power Features
2.1
Clock Control and Low-Power States
The processor supports low-power states both at the individual core level and the
package level for optimal power management.
A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, C4, Intel®
Enhanced Deeper Sleep and Intel® Deep Power Down Technology low-power states.
When both cores coincide in a common core low-power state, the central power
management logic ensures the entire processor enters the respective package low-
power state by initiating a P_LVLx (P_LVL2, P_LVL3, P_LVL4, P_LVL5,P_LVL6) I/O read
to the GMCH.
The processor implements two software interfaces for requesting low-power states:
MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK
register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are
converted to equivalent MWAIT C-state requests inside the processor and do not
directly result in I/O reads on the processor FSB. The P_LVLx I/O Monitor address does
not need to be set up before using the P_LVLx I/O read interface. The sub-state hints
used for each P_LVLx read can be configured through the IA32_MISC_ENABLES model
specific register (MSR).
If a core encounters a GMCH break event while STPCLK# is asserted, it asserts the
PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system
logic that individual cores should return to the C0 state and the processor should return
to the Normal state.
Figure 1 shows the core low-power states and Figure 2 shows the package low-power
states for the processor. Table 1 maps the core low-power states to package low-power
states.
Datasheet
11
Low Power Features
Figure 1.
Core Low-Power States
Stop
Grant
STPCLK#
asserted
STPCLK#
deasserted
STPCLK#
deasserted
STPCLK#
asserted
STPCLK#
deasserted
STPCLK#
asserted
C1/Auto
Halt
C1/MWAIT
Core state
break
HLT instruction
MWAIT(C1)
Halt break
C0
P_LVL2 or
MWAIT(C2)
Core State
break
Core state
break
P_LVL3 or
C2†
P_LVL4 or
P_LVL5/P_LVL6ø
MWAIT(C4/C6)
Core
state
MWAIT(C3)
C4† ‡/C6
break
C3†
halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
† — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4.
‡ — Core C4 state supports the package level Deep C4 sub-state.
Ø — P_LVL5/P_LVL6 read is issued once the L2 cache is reduced to zero.
12
Datasheet
Low Power Features
Figure 2.
Package Low-Power States
SLP# asserted
DPSLP# asserted
DPRSTP# asserted
STPCLK# asserted
Stop
Grant
Deep
Sleep
Deeper
Sleep†
Normal
Sleep
STPCLK# deasserted
SLP# deasserted
DPSLP# deasserted
DPRSTP# deasserted
Snoop Snoop
serviced occurs
Stop Grant
Snoop
† — Deeper Sleep includes the Deeper Sleep state, Deep C4 sub-state, and C6
Table 1.
Coordination of Core Low-Power States at the Package Level
Package State
Core1 State
C4/Deep Power Down
Technology State
Core0 State
C0
C11
C2
C3
(Code Named C6 State)
C0
C11
C2
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal Stop-Grant Stop-Grant
Normal Stop-Grant Deep Sleep
Stop-Grant
Deep Sleep
C3
Deeper Sleep /Intel®
Enhanced Deeper Sleep/
Intel® Deep Power Down
C4/Deep Power
Down Technology
Normal
Normal Stop-Grant Deep Sleep
NOTE:
1.
AutoHALT or MWAIT/C1.
2.1.1
Core Low-Power State Descriptions
2.1.1.1
Core C0 State
This is the normal operating state for cores in the processor.
2.1.1.2
Core C1/AutoHALT Powerdown State
C1/AutoHALT is a low-power state entered when a core executes the HALT instruction.
The processor core will transition to the C0 state upon occurrence of SMI#, INIT#,
LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to
immediately initialize itself.
A System Management Interrupt (SMI) handler will return execution to either Normal
state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures
Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more
information.
Datasheet
13
Low Power Features
The system can generate a STPCLK# while the processor is in the AutoHALT
Powerdown state. When the system deasserts the STPCLK# interrupt, the processor
will return execution to the HALT state.
While in AutoHALT Powerdown state, the dual-core processor will process bus snoops
and snoops from the other core. The processor core will enter a snoopable sub-state
(not shown in Figure 1) to process the snoop and then return to the AutoHALT
Powerdown state.
2.1.1.3
2.1.1.4
Core C1/MWAIT Powerdown State
C1/MWAIT is a low-power state entered when the processor core executes the
MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the
AutoHALT state except that Monitor events can cause the processor core to return to
the C0 state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals,
Volume 2A: Instruction Set Reference, A-M and Volume 2B: Instruction Set Reference,
N-Z, for more information.
Core C2 State
Individual cores of the dual-core processor can enter the C2 state by initiating a P_LVL2
I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a
Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted.
While in the C2 state, the dual-core processor will process bus snoops and snoops from
the other core. The processor core will enter a snoopable sub-state (not shown in
Figure 1) to process the snoop and then return to the C2 state.
2.1.1.5
Core C3 State
Individual cores of the dual-core processor can enter the C3 state by initiating a P_LVL3
I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering C3, the processor
core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the
caches, the processor core maintains all its architectural states in the C3 state. The
Monitor remains armed if it is configured. All of the clocks in the processor core are
stopped in the C3 state.
Because the core’s caches are flushed the processor keeps the core in the C3 state
when the processor detects a snoop on the FSB or when the other core of the dual-core
processor accesses cacheable memory. The processor core will transition to the C0
state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB
interrupt message. RESET# will cause the processor core to immediately initialize itself.
2.1.1.6
Core C4 State
Individual cores of the dual-core processor can enter the C4 state by initiating a P_LVL4
or P_LVL5 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor core
behavior in the C4 state is nearly identical to the behavior in the C3 state. The only
difference is that if both processor cores are in C4, the central power management logic
will request that the entire processor enter the Deeper Sleep package low-power state
(see Section 2.1.2.6).
To enable the package-level Intel Enhanced Deeper Sleep state, Dynamic Cache Sizing
and Intel Enhanced Deeper Sleep state fields must be configured in the
PMG_CST_CONFIG_CONTROL MSR. Refer to Section 2.1.2.6 for further details on Intel
Enhanced Deeper Sleep state.
14
Datasheet
Low Power Features
2.1.1.7
Core Deep Power Down Technology (Code Name C6) State
Deep Power Down Technology state is a new, power-saving state which is being
implemented on the processor. In Deep Power Down Technology the processor saves its
entire architectural state onto an on-die SRAM hence allowing it to lower its main core
voltage to any value, even as low as 0-V.
When the core enters Deep Power Down Technology state, it saves the processor state
that is relevant to the processor context in an on-die SRAM that resides on a separate
power plane VCCP (I/O power supply). This allows the main core Vcc to be lowered to
any arbitrary voltage including 0-V. The on-die storage for saving the processor state is
implemented as a per-core SRAM.
2.1.2
Package Low-power State Descriptions
2.1.2.1
Normal State
This is the normal operating state for the processor. The processor remains in the
Normal state when at least one of its cores is in the C0, C1/AutoHALT, or C1/MWAIT
state.
2.1.2.2
Stop-Grant State
When the STPCLK# pin is asserted, each core of the dual-core processor enters the
Stop-Grant state within 20 bus clocks after the response phase of the processor-issued
Stop-Grant Acknowledge special bus cycle. Processor cores that are already in the C2,
C3, or C4 state remain in their current low-power state. When the STPCLK# pin is
deasserted, each core returns to its previous core low-power state.
Since the AGTL+ signal pins receive power from the FSB, these pins should not be
driven (allowing the level to return to VCCP) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the FSB should be
driven to the inactive state.
RESET# causes the processor to immediately initialize itself, but the processor will stay
in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#, SLP#,
DPSLP#, and DPRSTP# pins must be deasserted prior to RESET# deassertion as per AC
Specification T45. When re-entering the Stop-Grant state from the Sleep state,
STPCLK# should be deasserted after the deassertion of SLP# as per AC Specification
T75.
While in Stop-Grant state, the processor will service snoops and latch interrupts
delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts
and will service only one of each upon return to the Normal state.
The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be
asserted if there is any pending interrupt or Monitor event latched within the processor.
Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause
assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor
should return to the Normal state.
A transition to the Stop-Grant Snoop state occurs when the processor detects a snoop
on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4)
occurs with the assertion of the SLP# signal.
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2.1.2.3
2.1.2.4
Stop-Grant Snoop State
The processor responds to snoop or interrupt transactions on the FSB while in Stop-
Grant state by entering the Stop-Grant Snoop state. The processor will stay in this
state until the snoop on the FSB has been serviced (whether by the processor or
another agent on the FSB) or the interrupt has been latched. The processor returns to
the Stop-Grant state once the snoop has been serviced or the interrupt has been
latched.
Sleep State
The Sleep state is a low-power state in which the processor maintains its context,
maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is
entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP#
pin should only be asserted when the processor is in the Stop-Grant state. SLP#
assertions while the processor is not in the Stop-Grant state is out of specification and
may result in unapproved operation.
In the Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals (with the exception of
SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep
state. Snoop events that occur while in Sleep state or during a transition into or out of
Sleep state will cause unpredictable behavior. Any transition on an input signal before
the processor has returned to the Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as
specified in the RESET# pin specification, then the processor will reset itself, ignoring
the transition through the Stop-Grant state. If RESET# is driven active while the
processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted
immediately after RESET# is asserted to ensure the processor correctly executes the
Reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power
state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 2.1.2.5). While
the processor is in the Sleep state, the SLP# pin must be deasserted if another
asynchronous FSB event needs to occur.
2.1.2.5
Deep Sleep State
The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep
state. BCLK may be stopped during the Deep Sleep state for additional platform-level
power savings. BCLK stop/restart timings on appropriate GMCH-based platforms with
the CK505 clock chip are as follows:
• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs
of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels
within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK
periods.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-
started after DPSLP# deassertion as described above. A period of 15 microseconds (to
allow for PLL stabilization) must occur before the processor can be considered to be in
the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter
the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop
transactions or latching interrupt signals. No transitions of signals are allowed on the
FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep
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state, it will not respond to interrupts or snoop transactions. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable
behavior.
2.1.2.6
Deeper Sleep State
The Deeper Sleep state is similar to the Deep Sleep state but further reduces core
voltage levels. One of the potential lower core voltage levels is achieved by entering the
base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the
DPRSTP# pin while in the Deep Sleep state. The following lower core voltage level is
achieved by entering the Intel Enhanced Deeper Sleep state which is a sub-state of
Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of
the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely
shut down. Refer to Section 2.1.2.6.1 and Section 2.1.2.6.3 for further details on
reducing the L2 cache and entering Intel Enhanced Deeper Sleep state.
In response to entering Deeper Sleep, the processor drives the VID code corresponding
to the Deeper Sleep core voltage on the VID[6:0] pins.
Exit from Deeper Sleep or Intel Enhanced Deeper Sleep state is initiated by DPRSTP#
deassertion when either core requests a core state other than C4 or either core
requests a processor performance state other than the lowest operating point.
2.1.2.6.1
Intel® Enhanced Deeper Sleep State
Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power-
saving capabilities by allowing the processor to further reduce core voltage once the L2
cache has been reduced to zero ways and completely shut down. The following events
occur when the processor enters Intel Enhanced Deeper Sleep state:
• The last core entering C4 issues a P_LVL4 or P_LVL5 I/O read or an MWAIT(C4)
instruction and then progressively reduces the L2 cache to zero
• Once the L2 cache has been reduced to zero, the processor triggers a special
chipset sequence to notify the chipset to redirect all FSB traffic, except APIC
messages, to memory. The snoops are replied as misses by the chipset and are
directed to main memory instead of the L2 cache. This allows for higher residency
of the processor’s Intel Enhanced Deeper Sleep state.
• The processor drives the VID code corresponding to the Intel Enhanced Deeper
Sleep state core voltage on the VID[6:0] pins.
2.1.2.6.2
Deep Power Down State Technology (Code Named C6) State
When both cores have entered the CC6 state and the L2 cache has been shrunk down
to zero ways, the processor will enter the Deep Power Down Technology state. To do so
both cores save their architectural states in the on-die SRAM that resides in the VCCP
domain. At this point, the core VCC will be dropped to the lowest core voltage closer to
0-V. The processor is now in an extremely low-power state.
In Intel Deep Power Down Technology state, the processor does not need to be
snooped as all the caches are flushed before entering this state.
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2.1.2.6.3
Dynamic Cache Sizing
Dynamic Cache Sizing allows the processor to flush and disable a programmable
number of L2 cache ways upon each Deeper Sleep entry under the following
conditions:
• The second core is already in C4 and Intel Enhanced Deeper Sleep state or Deep
Power Down Technology state (C6) is enabled (as specified in Section 2.1.1.6).
• The C0 timer that tracks continuous residency in the Normal package state has not
expired. This timer is cleared during the first entry into Deeper Sleep to allow
consecutive Deeper Sleep entries to shrink the L2 cache as needed.
• The FSB speed to processor core speed ratio is below the predefined L2 shrink
threshold.
The number of L2 cache ways disabled upon each Deeper Sleep entry is configured in
the BBL_CR_CTL3 MSR. The C0 timer is referenced through the
CLOCK_CORE_CST_CONTROL_STT MSR. The shrink threshold under which the L2
cache size is reduced is configured in the PMG_CST_CONFIG_CONTROL MSR. If the
FSB speed to processor core speed ratio is above the predefined L2 shrink threshold,
then L2 cache expansion will be requested. If the ratio is zero, then the ratio will not be
taken into account for Dynamic Cache Sizing decisions.
Upon STPCLK# deassertion, the first core exiting Intel Enhanced Deeper Sleep state or
Deep Power Down Technology state will expand the L2 cache to two ways and
invalidate previously disabled cache ways. If the L2 cache reduction conditions stated
above still exist when the last core returns to C4 and the package enters Intel
Enhanced Deeper Sleep state or Deep Power Down Technology state (C6), then the L2
will be shrunk to zero again. If a core requests a processor performance state resulting
in a higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the
second core (not the one currently entering the interrupt routine) requests the C1, C2,
or C3 states, then the whole L2 will be expanded upon the next interrupt event.
In addition, the processor supports Full Shrink on L2 cache. When the MWAIT Deep
Power Down Technology state instruction is executed with a hint=0x2 in ECX[3:0], the
micro code will shrink all the active ways of the L2 cache in one step. This ensures that
the package enters Deep Power Down Technology immediately when both cores are in
CC6 instead of iterating till the cache is reduced to zero. The operating system (OS) is
expected to use this hint when it wants to enter the lowest power state and can
tolerate the longer entry latency.
L2 cache shrink prevention may be enabled as needed on occasion through an
MWAIT(C4) sub-state field. If shrink prevention is enabled, the processor does not
enter Intel Enhanced Deeper Sleep state or Intel Deep Power Down state since the L2
cache remains valid and in full size.
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2.2
Enhanced Intel SpeedStep® Technology
The processor features Enhanced Intel SpeedStep Technology. Following are the key
features of Enhanced Intel SpeedStep Technology:
• Multiple voltage and frequency operating points provide optimal performance at the
lowest power.
• Voltage and frequency selection is software-controlled by writing to processor
MSRs:
— If the target frequency is higher than the current frequency, VCC is ramped up
in steps by placing new values on the VID pins, and the PLL then locks to the
new frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
new frequency and the VCC is changed through the VID pin mechanism.
— Software transitions are accepted at any time. If a previous transition is in
progress, the new transition is deferred until the previous transition completes.
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
• Low transition latency and large number of transitions possible per second:
— Processor core (including L2 cache) is unavailable for up to 10 μs during the
frequency transition.
— The bus protocol (BNR# mechanism) is used to block snooping.
• Improved Intel® Thermal Monitor mode:
— When the on-die thermal sensor indicates that the die temperature is too high
the processor can automatically perform a transition to a lower frequency and
voltage specified in a software-programmable MSR.
— The processor waits for a fixed time period. If the die temperature is down to
acceptable levels, an up-transition to the previous frequency and voltage point
occurs.
— An interrupt is generated for the up and down Intel Thermal Monitor transitions
enabling better system-level thermal management.
• Enhanced thermal management features:
— Digital Thermal Sensor and Out of Specification detection.
— Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in
case of unsuccessful TM2 transition.
— Dual-core thermal management synchronization.
Each core in the dual-core processor implements an independent MSR for controlling
Enhanced Intel SpeedStep Technology, but both cores must operate at the same
frequency and voltage. The processor has performance state coordination logic to
resolve frequency and voltage requests from the two cores into a single frequency and
voltage request for the package as a whole. If both cores request the same frequency
and voltage, then the processor will transition to the requested common frequency and
voltage. If the two cores have different frequency and voltage requests, then the
processor will take the highest of the two frequencies and voltages as the resolved
request and transition to that frequency and voltage.
The processor also supports Dynamic FSB Frequency Switching and Intel Dynamic
Acceleration Technology mode on select SKUs. The operating system can take
advantage of these features and request a lower operating point called SuperLFM (due
to Dynamic FSB Frequency Switching) and a higher operating point Intel Dynamic
Acceleration Technology mode.
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Low Power Features
2.3
Extended Low-Power States
Extended low-power states (CXE) optimize for power by forcibly reducing the
performance state of the processor when it enters a package low-power state. Instead
of directly transitioning into the package low-power state, the enhanced package low-
power state first reduces the performance state of the processor by performing an
Enhanced Intel SpeedStep Technology transition down to the lowest operating point.
Upon receiving a break event from the package low-power state, control will be
returned to software while an Enhanced Intel SpeedStep Technology transition up to
the initial operating point occurs. The advantage of this feature is that it significantly
reduces leakage while in the Stop-Grant and Deeper Sleep states.
Deep Power Down Technology is always enabled in the extended low power state as
described above.
Note:
Long-term reliability cannot be assured unless all the Extended Low Power States are
enabled.
The processor implements two software interfaces for requesting enhanced package
low-power states: MWAIT instruction extensions with sub-state hints and via BIOS by
configuring IA32_MISC_ENABLES MSR bits to automatically promote package low-
power states to enhanced package low-power states.
Caution:
Caution:
Extended Stop-Grant and Enhanced Deeper Sleep must be enabled via the
BIOS for the processor to remain within specification. As processor technology
changes, enabling the extended low power states becomes increasingly crucial when
building computer systems. Maintaining the proper BIOS configuration is key to
reliable, long-term system operation. Not complying to this guideline may affect the
long-term reliability of the processor.
Enhanced Intel SpeedStep Technology transitions are multistep processes
that require clocked control. These transitions cannot occur when the processor is in
the Sleep or Deep Sleep package low-power states since processor clocks are not
active in these states. Extended Deeper Sleep is an exception to this rule when the
Hard C4E configuration is enabled in the IA32_MISC_ENABLES MSR. This Extended
Deeper Sleep state configuration will lower core voltage to the Deeper Sleep level while
in Deeper Sleep and, upon exit, will automatically transition to the lowest operating
voltage and frequency to reduce snoop service latency. The transition to the lowest
operating point or back to the original software-requested point may not be
instantaneous. Furthermore, upon very frequent transitions between active and idle
states, the transitions may lag behind the idle state entry resulting in the processor
either executing for a longer time at the lowest operating point or running idle at a high
operating point. Observations and analyses show this behavior should not significantly
impact total power savings or performance score while providing power benefits in
most other cases.
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2.4
FSB Low Power Enhancements
The processor incorporates FSB low power enhancements:
• Dynamic FSB Power Down
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On-Die Termination disabling
• Low VCCP (I/O termination voltage)
• Dynamic FSB frequency switching
The processor incorporates the DPWR# signal that controls the data bus input buffers
on the processor. The DPWR# signal disables the buffers when not used and activates
them only when data bus activity occurs, resulting in significant power savings with no
performance impact. BPRI# control also allows the processor address and control input
buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows
a reciprocal power reduction in GMCH address and control input buffers when the
processor deasserts its BR0# pin. The On-Die Termination on the processor FSB buffers
is disabled when the signals are driven low, resulting in additional power savings. The
low I/O termination voltage is on a dedicated voltage plane independent of the core
voltage, enabling low I/O switching power at all times.
2.4.1
Dynamic FSB Frequency Switching
Dynamic FSB frequency switching effectively reduces the internal bus clock frequency
in half to further decrease the minimum processor operating frequency from the
Enhanced Intel SpeedStep Technology performance states and achieve the Super Low
Frequency Mode (Super LFM). This feature is supported at FSB frequencies of
1066 MHz, 800 MHz and 667 MHz and does not entail a change in the external bus
signal (BCLK) frequency. Instead, both the processor and GMCH internally lower their
BCLK reference frequency to 50% of the externally visible frequency. Both the
processor and GMCH maintain a virtual BCLK signal (VBCLK) that is aligned to the
external BCLK but at half the frequency. After a downward shift, it would appear
externally as if the bus is running with a 133-MHz base clock in all aspects, except that
the actual external BCLK remains at 266 MHz. See Figure 3 for details. The transition
into Super LFM, a “down-shift,” is done following a handshake between the processor
and GMCH. A similar handshake is used to indicate an “up-shift,” a change back to
normal operating mode. Please ensure this feature is enabled and supported in the
BIOS.
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21
Low Power Features
Figure 3.
Dynamic FSB Frequency Switching Protocol
NOTES:
1.
2.
All common clock signals will be active for two BCLKs instead of one (e.g., ADS#, HIT#).
The double-pumped signal strobes will have only one transition per BCLK when active,
instead of two.
3.
The quad-pumped signal strobes will have only two transitions per BCLK when active,
instead of four.
4.
5.
6.
7.
Same setup and hold times apply, but relative to every second rising BCLK.
Following a RESET#, the bus will be in the legacy full-frequency mode.
There will not be a down-shift right after RESET# deassertion.
There is no backing out of a transition into or out of half-frequency mode. Once the
sequence starts it must be completed.
2.4.2
Enhanced Intel® Dynamic Acceleration Technology
The processor supports Intel Dynamic Acceleration Technology mode. The Intel
Dynamic Acceleration Technology feature allows one core of the processor to operate at
a higher frequency point when the other core is inactive and the operating system
requests increased performance. This higher frequency is called the opportunistic
frequency and the maximum rated operating frequency is the ensured frequency.
The processor includes a hysteresis mechanism that improves overall Intel Dynamic
Acceleration Technology performance by decreasing unnecessary transitions of the
cores in and out of Intel Dynamic Acceleration Technology mode. Normally, the
processor would exit Intel Dynamic Acceleration Technology as soon as two cores are
active. This can become an issue if the idle core is frequently awakened for a short
periods (i.e., high timer tick rates). The hysteresis mechanism allows two cores to be
active for a limited time before it transitions out of Intel Dynamic Acceleration
Technology mode.
Intel Dynamic Acceleration Technology mode enabling requires:
• Exposure, via BIOS, of the opportunistic frequency as the highest ACPI P state
• Enhanced Multi-Threaded Thermal Management (EMTTM)
• Intel Dynamic Acceleration Technology mode and EMTTM MSR configuration via
BIOS.
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When in Intel Dynamic Acceleration Technology mode, it is possible for both cores to be
active under certain internal conditions. In such a scenario the processor may draw a
Instantaneous current (ICC_CORE_INST) for a short duration of tINST; however, the
average ICC current will be lesser than or equal to ICCDES current specification. Please
refer to the Processor DC Specifications section for more details.
2.5
VID-x
The processor implements the VID-x feature for improved control of core voltage levels
when the processor enters a reduced power consumption state. VID-x applies only
when the processor is in the Intel Dynamic Acceleration Technology performance state
and one or more cores are in low-power state (i.e., CC3/CC4/CC6). VID-x provides the
ability for the processor to request core voltage level reductions greater than one VID
tick. The amount of VID tick reduction is fixed and only occurs while the processor is in
Intel Dynamic Acceleration Technology mode. This improved voltage regulator
efficiency during periods of reduced power consumption allows for leakage current
reduction which results in platform power savings and extended battery life.
When in Intel Dynamic Acceleration Technology mode, it is possible for both cores to be
active under certain internal conditions. In such a scenario the processor may draw a
Instantaneous current (ICC_CORE_INST) for a short duration of tINST; however, the
average ICC current will be lesser than or equal to ICCDES current specification. Please
refer to the Processor DC Specifications section for more details.
2.6
Processor Power Status Indicator (PSI-2) Signal
The processor incorporates the PSI# signal that is asserted when the processor is in a
reduced power consumption state. PSI# can be used to improve intermediate and light
load efficiency of the voltage regulator, resulting in platform power savings and
extended battery life. The algorithm that the processor uses for determining when to
assert PSI# is different from the algorithm used in previous mobile processors. PSI-2
functionality is expanded further to support three processor states:
• Both cores are in idle state
• Only one core active state
• Both cores are in active state
PSI-2 functionality improves overall voltage regulator efficiency over a wide power
range based on the C-state and P-state of the two cores. The combined C-state and P-
state of both cores are used to dynamically predict processor power.
The real-time power prediction is compared against a set of predefined and configured
values of CHH and CHL. CHH is indicative of the active C-state of both the cores and
CHL is indicative that only one core is in active C-state and the other core is in low
power core state. PSI-2# output is asserted upon crossing these thresholds indicating
that the processor requires lower power. The voltage regulator will adapt its power
output accordingly. Additionally the voltage regulator may switch to a single phase and/
or asynchronous mode when the processor is idle and fused leakage limit is less than or
equal to the BIOS threshold value.
§
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24
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Electrical Specifications
3
Electrical Specifications
3.1
Power and Ground Pins
For clean, on-chip power distribution, the processor will have a large number of VCC
(power) and VSS (ground) inputs. All power pins must be connected to VCC power
planes while all VSS pins must be connected to system ground planes. Use of multiple
power and ground planes is recommended to reduce I*R drop. The processor VCC pins
must be supplied the voltage determined by the VID (Voltage ID) pins.
3.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large average current swings between low and full power states.
This may cause voltages on power planes to sag below their minimum values if bulk
decoupling is not adequate. Larger bulk storage, such as electrolytic capacitors, supply
current during longer lasting changes in current demand by the component, such as
coming out of an idle condition. Similarly, they act as a storage well for current when
entering an idle condition from a running condition. Care must be taken in the board
design to ensure that the voltage provided to the processor remains within the
specifications listed in the tables in Section 3.10. Failure to do so can result in timing
violations or reduced lifetime of the component.
3.2.1
V Decoupling
CC
VCC regulator solutions need to provide bulk capacitance with a low Effective Series
Resistance (ESR) and keep a low interconnect resistance from the regulator to the
socket. Bulk decoupling for the large current swings when the part is powering on, or
entering/exiting low-power states, should be provided by the voltage regulator solution
depending on the specific system design.
3.2.2
3.2.3
FSB AGTL+ Decoupling
The processors integrate signal termination on the die as well as incorporate high
frequency decoupling capacitance on the processor package. Decoupling must also be
provided by the system motherboard for proper AGTL+ bus operation.
FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous-generation processors, the processor core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio at manufacturing. The processor uses a differential clocking
implementation.
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25
Electrical Specifications
3.3
Voltage Identification and Power Sequencing
The processor uses seven voltage identification pins,VID[6:0], to support automatic
selection of power supply voltages. The VID pins for the processor are CMOS outputs
driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding
to the state of VID[6:0]. A 1 in the table refers to a high-voltage level and a 0 refers to
a low-voltage level.
Table 2.
Voltage Identification Definition (Sheet 1 of 3)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCC (V)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.5000
1.4875
1.4750
1.4625
1.4500
1.4375
1.4250
1.4125
1.4000
1.3875
1.3750
1.3625
1.3500
1.3375
1.3250
1.3125
1.3000
1.2875
1.2750
1.2625
1.2500
1.2375
1.2250
1.2125
1.2000
1.1875
1.1750
1.1625
1.1500
1.1375
1.1250
1.1125
1.1000
1.0875
1.0750
1.0625
1.0500
1.0375
1.0250
1.0125
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Electrical Specifications
Table 2.
Voltage Identification Definition (Sheet 2 of 3)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCC (V)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.0000
0.9875
0.9750
0.9625
0.9500
0.9375
0.9250
0.9125
0.9000
0.8875
0.8750
0.8625
0.8500
0.8375
0.8250
0.8125
0.8000
0.7875
0.7750
0.7625
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
Datasheet
27
Electrical Specifications
Table 2.
Voltage Identification Definition (Sheet 3 of 3)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCC (V)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.4125
0.4000
0.3875
0.3750
0.3625
0.3500
0.3375
0.3250
0.3125
0.3000
0.2875
0.2750
0.2625
0.2500
0.2375
0.2250
0.2125
0.2000
0.1875
0.1750
0.1625
0.1500
0.1375
0.1250
0.1125
0.1000
0.0875
0.0750
0.0625
0.0500
0.0375
0.0250
0.0125
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
28
Datasheet
Electrical Specifications
3.4
Catastrophic Thermal Protection
The processor supports the THERMTRIP# signal for catastrophic thermal protection. An
external thermal sensor should also be used to protect the processor and the system
against excessive temperatures. Even with the activation of THERMTRIP#, which halts
all processor internal clocks and activity, leakage current can be high enough that the
processor cannot be protected in all conditions without the removal of power to the
processor. If the external thermal sensor detects a catastrophic processor temperature
of approximately 125°C (maximum), or if the THERMTRIP# signal is asserted, the VCC
supply to the processor must be turned off within 500 ms to prevent permanent silicon
damage due to thermal runaway of the processor. THERMTRIP# functionality is not
ensured if the PWRGOOD signal is not asserted, and during Deep Power Down
Technology State (C6).
3.5
Reserved and Unused Pins
All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to VCC,
VSS, or to any other signal (including each other) can result in component malfunction
or incompatibility with future processors. See Section 4.2 for a pin listing of the
processor and the location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active low AGTL+ inputs may be left as no-connects if
AGTL+ termination is provided on the processor silicon. Unused active high inputs
should be connected through a resistor to ground (VSS). Unused outputs can be left
unconnected. The TEST1,TEST2,TEST3,TEST4,TEST5,TEST6,TEST7 pins are used for
test purposes internally and can be left as “No Connects”.
3.6
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). These signals should be connected to the clock chip and the appropriate
chipset on the platform. The BSEL encoding for BCLK[1:0] is shown in Table 3.
Table 3.
BSEL[2:0] Encoding for BCLK Frequency
BSEL[2]
BSEL[1] BSEL[0]
BCLK Frequency
L
L
L
L
L
H
H
L
266 MHz
RESERVED
RESERVED
200 MHz
L
H
H
H
H
L
L
H
H
H
H
L
RESERVED
RESERVED
RESERVED
RESERVED
H
H
L
L
Datasheet
29
Electrical Specifications
3.7
FSB Signal Groups
The FSB signals have been combined into groups by buffer type in the following
sections. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as
well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the
AGTL+ output group as well as the AGTL+ I/O group when driving.
With the implementation of a source-synchronous data bus, two sets of timing
parameters are specified. One set is for common clock signals, which are dependent
upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.), and the second set is for
the source-synchronous signals which are relative to their respective strobe lines (data
and address) as well as the rising edge of BCLK0. Asychronous signals are still present
(A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle.
Table 4 identifies which signals are common clock, source synchronous, and
asynchronous.
Table 4.
FSB Pin Groups
Signal Group
Type
Signals1
AGTL+ Common Synchronous to
Clock Input BCLK[1:0]
BPRI#, DEFER#, PREQ#5, RESET#, RS[2:0]#, TRDY#
AGTL+ Common Synchronous to
ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#, DRDY#,
HIT#, HITM#, LOCK#, PRDY#3, DPWR#
Clock I/O
BCLK[1:0]
Signals
Associated Strobe
REQ[4:0]#, A[16:3]# ADSTB[0]#
A[35:17]#
ADSTB[1]#
AGTL+ Source
Synchronous
I/O
Synchronous to
assoc. strobe
D[15:0]#, DINV0#
D[31:16]#, DINV1#
D[47:32]#, DINV2#
D[63:48]#, DINV3#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
Synchronous to
BCLK[1:0]
AGTL+ Strobes
CMOS Input
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK#
Asynchronous
Asynchronous
Open Drain
Output
FERR#, IERR#, THERMTRIP#
Open Drain I/O
CMOS Output
CMOS Input
Asynchronous
Asynchronous
PROCHOT#4
PSI#, VID[6:0], BSEL[2:0]
Synchronous to TCK TCK, TDI, TMS, TRST#
Synchronous to TCK TDO
Open Drain
Output
FSB Clock
Clock
BCLK[1:0]
COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1,
Power/Other
THERMDA, THERMDC, VCC, VCCA, VCCP, VCC_SENSE
SS, VSS_SENSE
,
V
NOTES:See next page
30
Datasheet
Electrical Specifications
1.
2.
Refer to Chapter 4 for signal descriptions and termination requirements.
In processor systems where there is no debug port implemented on the system board,
these signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
BPM[2:1]# and PRDY# are AGTL+ output-only signals.
PROCHOT# signal type is open drain output and CMOS input.
On-die termination differs from other AGTL+ signals.
3.
4.
5.
3.8
3.9
CMOS Signals
CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other non-
AGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers. These
signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,
all of the CMOS signals are required to be asserted for more than four BCLKs for the
processor to recognize them. See Section 3.10 for the DC specifications for the CMOS
signal groups.
Maximum Ratings
Table 5 specifies absolute maximum and minimum ratings only, which lie outside the
functional limits of the processor. Only within specified operation limits, can
functionality and long-term reliability be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function, or its reliability will be
severely degraded.
Caution:
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.
Table 5.
Processor Absolute Maximum Ratings
Symbol
TSTORAGE
TSTORAGE
Parameter
Min
Max
Unit
Notes1,2
Processor Storage Temperature
Processor Storage Temperature
-40
-25
85
°C
°C
3,4,5
6
Any Processor Supply Voltage with
Respect to VSS
VCC
-0.3
-0.1
-0.1
1.45
1.45
1.45
V
V
V
AGTL+ Buffer DC Input Voltage with
Respect to VSS
VinAGTL+
CMOS Buffer DC Input Voltage with
Respect to VSS
VinAsynch_CMOS
NOTES:
1.
For functional operation, all processor electrical, signal quality, mechanical and thermal
specifications must be satisfied.
Datasheet
31
Electrical Specifications
2.
3.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to
the processor.
Storage temperature is applicable to storage conditions only. In this scenario, the
processor must not receive a clock, and no lands can be connected to a voltage bias.
Storage within these limits will not affect the long-term reliability of the device. For
functional operation, please refer to the processor case temperature specifications.
This rating applies to the processor and does not include any tray or packaging.
Failure to adhere to this specification can affect the long-term reliability of the processor.
For Intel® Core™2 Duo mobile processors in 22x22 mm package.
4.
5.
6.
3.10
Processor DC Specifications
The processor DC specifications in this section are defined at the processor
core (pads) unless noted otherwise.
The tables list the DC specifications for the processor and are valid only while meeting
specifications for junction temperature, clock frequency, and input voltages. The
Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer to the highest
and lowest core operating frequencies supported on the processor. Active mode load
line specifications apply in all states except in the Deep Sleep and Deeper Sleep states.
V
CC,BOOT is the default voltage driven by the voltage regulator at power up in order to
set the VID values. Unless specified otherwise, all specifications for the processor are at
TJ = 105 °C. Read all notes associated with each parameter.
Table 6.
Voltage and Current Specifications for the Dual-Core, Extreme Edition
Processors (Sheet 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VCC in Enhanced Intel® Dynamic Acceleration
Technology Mode
VCCDAM
1.0
1.325
V
1, 2
VCCHFM
VCCLFM
VCC at Highest Frequency Mode (HFM)
VCC at Lowest Frequency Mode (LFM)
1.0
—
—
1.275
1.1
V
V
1, 2
1, 2
0.85
VCC at Super Low Frequency Mode
(Super LFM)
VCCSLFM
0.8
—
1.0
V
1, 2
2, 6
VCC,BOOT
VCCP
Default VCC Voltage for Initial Power Up
AGTL+ Termination Voltage
PLL Supply Voltage
—
1.20
1.05
1.5
—
V
V
V
V
V
1.00
1.425
0.65
0.6
1.10
1.575
0.85
VCCA
VCCDPRSLP
VDC4
VCC at Deeper Sleep
1, 2
1, 2
VCC at Intel® Enhanced Deeper Sleep State
—
0.85
VCC at Deep Power Down Technology State
(C6)
VCCDPPWDN
ICCDES
0.35
—
0.7
V
A
ICC for Processors Recommended Design
Target
—
—
—
—
—
—
60
—
—
12
ICC for Processors
Processor
Core Frequency/Voltage
Number
ICC
X9100
3.06 GHz & VCCHFM
1.6 GHz & VCCLFM
0.8 GHz & VCCSLFM
59
34
24
—
—
A
3, 4, 10
32
Datasheet
Electrical Specifications
Table 6.
Symbol
Voltage and Current Specifications for the Dual-Core, Extreme Edition
Processors (Sheet 2 of 2)
Parameter
Min
Typ
Max
Unit
Notes
ICC Auto-Halt & Stop-Grant
HFM
SuperLFM
IAH,
ISGNT
—
—
29.7
16.7
A
3, 4, 10
ICC Sleep
HFM
SuperLFM
ISLP
—
—
—
—
28.8
16.5
A
A
3, 4, 10
3, 4, 10
ICC Deep Sleep
HFM
SuperLFM
IDSLP
26.8
16.0
IDPRSLP
IDC4
ICC Deeper Sleep (C4)
—
—
—
—
—
—
12.2
11.7
11.0
A
A
A
3, 4
3, 4
3, 4
ICC Intel Enhanced Deeper Sleep State
ICC Deep Power Down Technology State (C6)
IPPWDN
VCC Power Supply Current Slew Rate at
Processor Package Pin
dICC/DT
ICCA
—
—
—
—
—
—
600
130
mA/µs
mA
5, 7
ICC for VCCA Supply
8
9
ICC for VCCP Supply before VCC Stable
4.5
2.5
A
A
ICCP
I
CC for VCCP Supply after VCC Stable
NOTES:
1.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Intel Thermal
Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).
2.
The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3.
4.
5.
6.
7.
Specified at 105 °C TJ.
Specified at the nominal VCC
Measured at the bulk capacitors on the motherboard.
CC,BOOT tolerance shown in Figure 4 and Figure 5.
.
V
Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
8.
9.
10.
This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low.
This is a steady-state ICC current specification, which is applicable when both VCCP and VCC_CORE are high.
The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or
equal to 300 mV.
11.
The ICCDES (max) specification of 60 A is for Intel® Core™2 Extreme processors only.
Datasheet
33
Electrical Specifications
Table 7.
Voltage and Current Specifications for the Dual-Core, Standard-Voltage
Processors
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VCC in Enhanced Intel® Dynamic Acceleration
Technology Mode
VCCDAM
1.0
1.3
V
1, 2
VCCHFM
VCCLFM
VCCSLFM
VCC,BOOT
VCCP
VCC at Highest Frequency Mode (HFM)
VCC at Lowest Frequency Mode (LFM)
VCC at Super Low Frequency Mode (Super LFM)
Default VCC Voltage for Initial Power Up
AGTL+ Termination Voltage
1.0
0.85
0.75
—
1.25
1.1
V
V
V
V
V
V
V
V
V
A
1, 2
1, 2
1, 2
2, 6
—
—
0.95
—
1.2
1.05
1.5
—
1.0
1.1
VCCA
PLL Supply Voltage
1.425
0.65
0.6
1.575
0.85
0.85
0.7
VCCDPRSLP
VDC4
VCC at Deeper Sleep
1, 2
1, 2
1, 2
12
VCC at Intel® Enhanced Deeper Sleep State
—
VCCDPPWDN VCC at Deep Power Down Technology State (C6)
0.35
—
—
ICCDES
ICC for Processors Recommended Design Target
ICC for Processors
—
47
—
—
—
Processor
Core Frequency/Voltage
Number
—
—
—
—
T9900
T9800
T9600
T9550
T9400
3.06 GHz & VCCHFM
2.93 GHz & VCCHFM
2.80 GHz & VCCHFM
2.66 GHz & VCCHFM
2.53 GHz & VCCHFM
1.6 GHz & VCCLFM
0.8 GHz & VCCSLFM
47
47
47
47
47
ICC
—
A
3, 4, 10
31.4
22.4
ICC Auto-Halt & Stop-Grant
HFM
SuperLFM
IAH,
ISGNT
—
—
—
—
—
—
25.4
13.7
A
A
A
3, 4, 10
3, 4, 10
3, 4, 10
ICC Sleep
HFM
SuperLFM
ISLP
24.7
13.5
ICC Deep Sleep
HFM
SuperLFM
IDSLP
22.9
13.0
IDPRSLP
IDC4
ICC Deeper Sleep (C4)
—
—
—
—
—
—
11.7
10.5
5.7
A
A
A
3, 4
3, 4
3, 4
ICC Intel Enhanced Deeper Sleep
ICC Deep Power Down Technology State (C6)
IPPWDN
VCC Power Supply Current Slew Rate at Processor
Package Pin
dICC/DT
ICCA
—
—
—
—
—
—
600
130
mA/µs
mA
5, 7
ICC for VCCA Supply
8
9
ICCC for VCCP Supply before VCC Stable
ICC for VCCP Supply after VCC Stable
4.5
2.5
A
A
ICCP
NOTES:See next page.
34
Datasheet
Electrical Specifications
1.
2.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Intel Thermal
Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).
The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3.
4.
5.
6.
7.
Specified at 105 °C TJ.
Specified at the nominal VCC
Measured at the bulk capacitors on the motherboard.
CC,BOOT tolerance shown in Figure 7 and Figure 8.
.
V
Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
8.
9.
10.
11.
This is a power-up peak current specification that is applicable when VCCP is high and VCC_CORE is low.
This is a steady-state ICCcurrent specification that is applicable when both VCCP and VCC_CORE are high.
Processor ICC requirements in Intel Dynamic Acceleration Technology mode are lesser than ICC in HFM
The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or
equal to 300 mV.
12.
Instantaneous current ICC_CORE_INST of 57 A has to be sustained for short time (tINST) of 35 µs. Average
current will be less than maximum specified ICCDES. VR OCP threshold should be high enough to support
current levels described herein.
Table 8.
Voltage and Current Specifications for the Dual-Core, Low-Power
Standard-Voltage Processors (25 W) in Standard Package
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VCC in Enhanced Intel® Dynamic Acceleration
Technology Mode
VCCDAM
0.9
1.3
V
1, 2
VCCHFM
VCCLFM
VCCSLFM
VCC,BOOT
VCCP
VCC at Highest Frequency Mode (HFM)
VCC at Lowest Frequency Mode (LFM)
VCC at Super Low Frequency Mode (Super LFM)
Default VCC Voltage for Initial Power Up
AGTL+ Termination Voltage
0.9
0.85
0.75
—
1.25
1.025
0.95
—
V
V
V
V
V
V
V
V
V
A
1, 2
1, 2
1, 2
2, 6
—
—
1.2
1.05
1.5
—
1.0
1.1
VCCA
PLL Supply Voltage
1.425
0.65
0.6
1.575
0.85
0.85
0.7
VCCDPRSLP
VDC4
VCC at Deeper Sleep
1, 2
1, 2
1, 2
12
VCC at Intel® Enhanced Deeper Sleep State
—
VCCDPPWDN VCC at Deep Power Down Technology State (C6)
0.35
—
—
ICCDES
ICC for Processors Recommended Design Target
ICC for Processors
—
38
—
—
—
Processor
Core Frequency/Voltage
Number
—
—
—
P9700
P9600
P8800
P9500
P8700
P8600
P8400
2.8 GHz & VCCHFM
2.667 GHz & VCCHFM
2.667 GHz & VCCHFM
2.53 GHz & VCCHFM
2.53 GHz & VCCHFM
2.4 GHz & VCCHFM
2.267 GHz & VCCHFM
1.6 GHz & VCCLFM
0.8 GHz & VCCSLFM
38
38
38
38
38
38
38
27.7
17.5
ICC
—
—
A
3, 4, 10
Datasheet
35
Electrical Specifications
Table 8.
Symbol
Voltage and Current Specifications for the Dual-Core, Low-Power
Standard-Voltage Processors (25 W) in Standard Package
Parameter
Min
Typ
Max
Unit
Notes
ICC Auto-Halt & Stop-Grant
HFM
SuperLFM
IAH,
ISGNT
—
—
15.3
10.5
A
3, 4, 10
ICC Sleep
HFM
SuperLFM
ISLP
—
—
—
—
14.6
10.3
A
A
3, 4, 10
3, 4, 10
ICC Deep Sleep
HFM
SuperLFM
IDSLP
12.9
9.8
IDPRSLP
IDC4
ICC Deeper Sleep
—
—
—
—
—
—
7.3
6.7
4.3
A
A
A
3, 4
3, 4
3, 4
ICC Intel Enhanced Deeper Sleep
ICC Deep Power Down Technology State (C6)
IPPWDN
VCC Power Supply Current Slew Rate at Processor
Package Pin
dICC/DT
ICCA
—
—
—
—
—
—
600
130
mA/µs
mA
5, 7
ICC for VCCA Supply
8
9
ICCC for VCCP Supply before VCC Stable
4.5
2.5
A
A
ICCP
I
CC for VCCP Supply after VCC Stable
NOTES:.
1.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Intel Thermal
Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).
2.
The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3.
4.
5.
6.
7.
Specified at 105 °C TJ.
Specified at the nominal VCC
Measured at the bulk capacitors on the motherboard.
CC,BOOT tolerance shown in Figure 4 and Figure 5.
.
V
Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
8.
9.
10.
11.
This is a power-up peak current specification that is applicable when VCCP is high and VCC_CORE is low.
This is a steady-state ICCcurrent specification that is applicable when both VCCP and VCC_CORE are high.
Processor ICC requirements in Intel Dynamic Acceleration Technology mode are lesser than ICC in HFM
The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or
equal to 300 mV.
12.
Instantaneous current ICC_CORE_INST of 49 A has to be sustained for short time (tINST) of 35 µs. Average
current will be less than maximum specified ICCDES. VR OCP threshold should be high enough to support
current levels described herein.
36
Datasheet
Electrical Specifications
Table 9.
Voltage and Current Specifications for the Dual-Core, Power Optimized
Performance (25 W) SFF Processors
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VCC in Enhanced Intel® Dynamic Acceleration
Technology Mode
VCCDAM
0.9
—
1.275
V
1, 2
VCCHFM
VCCLFM
VCCSLFM
VCC,BOOT
VCCP
VCC at Highest Frequency Mode (HFM)
VCC at Lowest Frequency Mode (LFM)
VCC at Super Low Frequency Mode (Super LFM)
Default VCC Voltage for Initial Power Up
AGTL+ Termination Voltage
0.9
0.85
0.75
—
—
—
1.2125
1.025
0.95
—
V
V
V
V
V
V
V
V
V
A
1, 2
1, 2
—
1, 2
1.20
1.05
1.5
—
2, 6, 8
1.00
1.425
0.65
0.6
1.10
1.575
0.85
0.85
0.7
VCCA
PLL Supply Voltage
VCCDPRSLP
VDC4
VCC at Deeper Sleep
1, 2
1, 2
1, 2
5
VCC at Intel® Enhanced Deeper Sleep State
—
VCCDPPWDN VCC at Deep Power Down Technology State (C6)
0.35
—
—
ICCDES
ICC for Processors Recommended Design Target
—
37
Processor
Core Frequency/Voltage
Number
—
—
—
—
SP9600
SP9400
SP9300
2.53 GHz & VCCHFM
2.4 GHz & VCCHFM
2.26 GHz & VCCHFM
1.2 GHz & VCCLFM
0.8 GHz & VCCSLFM
37
37
37
28
17
ICC
—
A
3, 4, 12
ICC Auto-Halt & Stop-Grant
HFM
SuperLFM
IAH,
ISGNT
14.8
8.8
—
—
—
—
—
—
A
A
A
3, 4, 12
3, 4, 12
3, 4, 12
ICC Sleep
HFM
SuperLFM
ISLP
14.2
8.6
ICC Deep Sleep
HFM
SuperLFM
IDSLP
12.5
8.1
IDPRSLP
IDC4
ICC Deeper Sleep
—
—
—
—
—
—
6.9
5.9
3.5
A
A
A
3, 4
3, 4
3, 4
ICC Intel Enhanced Deeper Sleep State
ICC Deep Power Down Technology State (C6)
IDPWDN
VCC Power Supply Current Slew Rate at Processor
Package Pin
dICC/DT
ICCA
—
—
—
—
—
—
600
130
mA/µs
mA
7, 9
ICC for VCCA Supply
10
11
ICC for VCCP Supply before VCC Stable
ICC for VCCPSupply after VCC Stable
4.5
2.5
A
A
ICCP
NOTES:
1.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
Datasheet
37
Electrical Specifications
that this differs from the VID employed by the processor during a power management event (Intel Thermal
Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).
The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
2.
3.
4.
5.
6.
7.
Specified at 105 °C TJ.
Specified at the nominal VCC
Measured at the bulk capacitors on the motherboard.
CC,BOOT tolerance shown in Figure 7 and Figure 8.
.
V
Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
8.
9.
10.
11.
This is a power-up peak current specification that is applicable when VCCP is high and VCC_CORE is low.
This is a steady-state ICC current specification that is applicable when both VCCP and VCC_CORE are high.
Processor ICC requirements in Intel Dynamic Acceleration Technology mode are lesser than ICC in HFM
The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or
equal to 300 mV.
12.
Instantaneous current ICC_CORE_INST of 44 A has to be sustained for short time (tINST) of 35 µs. Average
current will be less than maximum specified ICCDES. VR OCP threshold should be high enough to support
current levels described herein.
Table 10.
Voltage and Current Specifications for the Dual-Core, Low-Voltage SFF
Processor
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VCC in Enhanced Intel® Dynamic Acceleration
Technology Mode
VCCDAM
0.9
—
1.25
V
1, 2
VCCHFM
VCCLFM
VCCSLFM
VCC,BOOT
VCCP
VCC at Highest Frequency Mode (HFM)
VCC at Lowest Frequency Mode (LFM)
VCC at Super Low Frequency Mode (Super LFM)
Default VCC Voltage for Initial Power Up
AGTL+ Termination Voltage
0.9
0.85
0.75
—
—
—
1.175
1.025
0.95
—
V
V
V
V
V
V
V
V
V
A
1, 2
1, 2
—
1, 2
1.20
1.05
1.5
—
2, 6, 8
1.00
1.425
0.65
0.6
1.10
1.575
0.85
0.85
0.7
VCCA
PLL Supply Voltage
VCCDPRSLP
VDC4
VCC at Deeper Sleep
1, 2
1, 2
1, 2
5
VCC at Intel® Enhanced Deeper Sleep State
—
VCCDPPWDN VCC at Deep Power Down Technology State (C6)
0.35
—
—
ICCDES
ICC for Processors Recommended Design Target
—
27
Processor
Core Frequency/Voltage
Number
—
—
—
—
SL9600
SL9400
SL9300
2.13 GHz & VCCHFM
1.86 GHz & VCCHFM
1.6 GHz & VCCHFM
1.6 GHz & VCCLFM
0.8 GHz & VCCSLFM
27
27
27
25.5
15
ICC
—
A
3, 4, 12
ICC Auto-Halt & Stop-Grant
HFM
SuperLFM
IAH,
ISGNT
—
—
—
—
12.3
8.2
A
A
3, 4, 12
3, 4, 12
ICC Sleep
HFM
SuperLFM
ISLP
11.8
8.0
38
Datasheet
Electrical Specifications
Table 10.
Symbol
IDSLP
Voltage and Current Specifications for the Dual-Core, Low-Voltage SFF
Processor
Parameter
Min
Typ
Max
Unit
Notes
ICC Deep Sleep
HFM
SuperLFM
—
—
10.5
7.5
A
3, 4, 12
IDPRSLP
IDC4
ICC Deeper Sleep
—
—
—
—
—
—
6.5
5.6
3.2
A
A
A
3, 4
3, 4
3, 4
ICC Intel Enhanced Deeper Sleep
IDPWDN
ICC Deep Power Down Technology State (C6)
VCC Power Supply Current Slew Rate at Processor
Package Pin
dICC/DT
ICCA
—
—
—
—
—
—
600
130
mA/µs
mA
7, 9
ICC for VCCA Supply
10
11
ICC for VCCP Supply before VCC Stable
ICC for VCCP Supply after VCC Stable
4.5
2.5
A
A
ICCP
NOTES:
1.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Intel Thermal
Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).
2.
The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3.
4.
5.
6.
7.
Specified at 105 °C TJ.
Specified at the nominal VCC
Measured at the bulk capacitors on the motherboard.
CC,BOOT tolerance shown in Figure 7 and Figure 8.
.
V
Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
8.
9.
10.
11.
This is a power-up peak current specification that is applicable when VCCP is high and VCC_CORE is low.
This is a steady-state ICC current specification that is applicable when both VCCP and VCC_CORE are high.
Processor ICC requirements in Intel Dynamic Acceleration Technology mode are lesser than ICC in HFM
The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or
equal to 300 mV.
12.
Instantaneous current ICC_CORE_INST of 36 A has to be sustained for short time (tINST) of 35 µs. Average
current will be less than maximum specified ICCDES. VR OCP threshold should be high enough to support
current levels described herein.
Datasheet
39
Electrical Specifications
Table 11.
Voltage and Current Specifications for the Dual-Core, Ultra-Low-Voltage SFF
Processor
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VCC in Enhanced Intel® Dynamic Acceleration
Technology Mode
VCCDAM
0.8
—
1.1625
V
1, 2
VCCHFM
VCCLFM
VCCSLFM
VCC,BOOT
VCCP
VCC at Highest Frequency Mode (HFM)
VCC at Lowest Frequency Mode (LFM)
VCC at Super Low Frequency Mode (Super LFM)
Default VCC Voltage for Initial Power Up
AGTL+ Termination Voltage
0.775
0.8
—
—
1.1
0.975
0.925
—
V
V
V
V
V
V
V
V
V
A
1, 2
1, 2
0.725
—
—
1, 2
1.20
1.05
1.5
—
2, 6, 8
1.00
1.425
0.65
0.6
1.10
1.575
0.8
VCCA
PLL Supply Voltage
VCCDPRSLP
VDC4
VCC at Deeper Sleep
1, 2
1, 2
1, 2
5
VCC at Intel® Enhanced Deeper Sleep State
—
0.8
VCCDPPWDN VCC at Deep Power Down Technology State (C6)
0.35
—
—
0.6
ICCDES
ICC for Processors Recommended Design Target
—
18
Processor
Core Frequency/Voltage
Number
—
—
—
—
SU9600
SU9400
SU9300
1.6 GHz & VCCHFM
1.4 GHz & VCCHFM
1.2 GHz & VCCHFM
1.2 GHz & VCCLFM
0.8 GHz & VCCSLFM
18
18
18
18
13
ICC
—
A
3, 4, 12
ICC Auto-Halt & Stop-Grant
HFM
SuperLFM
IAH,
ISGNT
—
—
—
—
—
—
6.3
4.4
A
A
A
3, 4, 12
3, 4, 12
3, 4, 12
ICC Sleep
HFM
SuperLFM
ISLP
5.9
4.2
ICC Deep Sleep
HFM
SuperLFM
IDSLP
5.0
3.7
IDPRSLP
IDC4
ICC Deeper Sleep
—
—
—
—
—
—
3.2
2.8
2.4
A
A
A
3, 4
3, 4
3, 4
ICC Intel Enhanced Deeper Sleep State
ICC Deep Power Down Technology State (C6)
IDPWDN
VCC Power Supply Current Slew Rate at Processor
Package Pin
dICC/DT
ICCA
—
—
—
—
—
—
600
130
mA/µs
mA
7, 9
ICC for VCCA Supply
10
11
ICC for VCCP Supply before VCC Stable
4.5
2.5
A
A
ICCP
I
CC for VCCPSupply after VCC Stable
NOTES:See next page.
40
Datasheet
Electrical Specifications
1.
2.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Intel Thermal
Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).
The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3.
4.
5.
6.
7.
Specified at 105 °C TJ.
Specified at the nominal VCC
Measured at the bulk capacitors on the motherboard.
CC,BOOT tolerance shown in Figure 7 and Figure 8.
.
V
Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
8.
9.
10.
11.
This is a power-up peak current specification that is applicable when VCCP is high and VCC_CORE is low.
This is a steady-state ICC current specification that is applicable when both VCCP and VCC_CORE are high.
Processor ICC requirements in Intel Dynamic Acceleration Technology mode are lesser than ICC in HFM
The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or
equal to 300 mV.
12.
Instantaneous current ICC_CORE_INST of 24 A has to be sustained for short time (tINST) of 35µs. Average
current will be less than maximum specified ICCDES. VR OCP threshold should be high enough to support
current levels described herein.
Table 12.
Symbol
Voltage and Current Specifications for the Ultra-Low-Voltage, Single-Core
(5.5 W) SFF Processor
Parameter
Min
Typ
Max
Unit
Notes
VCCHFM
VCCLFM
VCCSLFM
VCC,BOOT
VCCP
VCC at Highest Frequency Mode (HFM)
VCC at Lowest Frequency Mode (LFM)
VCC at Super Low Frequency Mode (Super LFM)
Default VCC Voltage for Initial Power Up
AGTL+ Termination Voltage
0.775
0.8
—
—
1.1
0.975
0.925
—
V
V
V
V
V
V
V
V
V
A
1, 2
1, 2
0.725
—
—
1, 2
1.20
1.05
1.5
—
2, 6, 8
1.00
1.425
0.65
0.6
1.10
1.575
0.8
VCCA
PLL Supply Voltage
VCCDPRSLP
VDC4
VCC at Deeper Sleep
1, 2
1, 2
1, 2
5
VCC at Intel® Enhanced Deeper Sleep State
—
0.8
VCCDPPWDN VCC at Deep Power Down Technology State (C6)
0.35
—
—
0.6
ICCDES
ICC for Processors Recommended Design Target
—
9
Processor
Core Frequency/Voltage
Number
—
—
—
—
SU3500
SU3300
1.4 GHz & VCCHFM
1.2 GHz & VCCHFM
1.2 GHz & VCCLFM
0.8 GHz & VCCSLFM
9
9
9
7
ICC
—
A
3, 4, 12
ICC Auto-Halt & Stop-Grant
HFM
SuperLFM
IAH,
ISGNT
—
—
—
—
4.4
3.7
A
A
3, 4, 12
3, 4, 12
ICC Sleep
HFM
SuperLFM
ISLP
4.1
3.5
Datasheet
41
Electrical Specifications
Table 12.
Symbol
IDSLP
Voltage and Current Specifications for the Ultra-Low-Voltage, Single-Core
(5.5 W) SFF Processor
Parameter
Min
Typ
Max
Unit
Notes
ICC Deep Sleep
HFM
SuperLFM
—
—
3.3
3.0
A
3, 4, 12
IDPRSLP
IDC4
ICC Deeper Sleep
—
—
—
—
—
—
2.1
1.9
1.7
A
A
A
3, 4
3, 4
3, 4
ICC Intel Enhanced Deeper Sleep State
IDPWDN
ICC Deep Power Down Technology State (C6)
VCC Power Supply Current Slew Rate at Processor
Package Pin
dICC/DT
ICCA
—
—
—
—
—
—
600
130
mA/µs
mA
7, 9
ICC for VCCA Supply
10
11
ICC for VCCP Supply before VCC Stable
ICC for VCCPSupply after VCC Stable
4.5
2.5
A
A
ICCP
NOTES:
1.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Intel Thermal
Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State).
2.
The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3.
4.
5.
6.
7.
Specified at 100 °C TJ.
Specified at the nominal VCC
Measured at the bulk capacitors on the motherboard.
CC,BOOT tolerance shown in Figure 4 and Figure 5.
.
V
Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
8.
9.
10.
11.
This is a power-up peak current specification that is applicable when VCCP is high and VCC_CORE is low.
This is a steady-state ICC current specification that is applicable when both VCCP and VCC_CORE are high.
Processor ICC requirements in Intel Dynamic Acceleration Technology mode are lesser than ICC in HFM
The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or
equal to 300 mV.
42
Datasheet
Electrical Specifications
Figure 4.
Active VCC and ICC Loadline for Standard Voltage, Low-Power SV (25 W) and
Dual-Core, Extreme Edition Processors
VCC-CORE [V]
Slope = -2.1 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
VCC-CORE max {HFM|LFM}
VCC-CORE, DC max {HFM|LFM}
10mV= RIPPLE
VCC-CORE nom {HFM|LFM}
VCC-CORE, DC min {HFM|LFM}
VCC-CORE min {HFM|LFM}
+/-VCC-CORE Tolerance
= VR St. Pt. Error 1/
ICC-CORE
[A]
0
ICC-CORE max
{HFM|LFM}
Note 1/ VCC-CORE Set Point Error Tolerance is per below :
Tolerance VCC-CORE VID Voltage Range
--------------- --------------------------------------------------------
+/-1.5% VCC-CORE > 0.7500V
+/-11.5mV 0.5000V </= Vcc_core </= 0.75000V
Datasheet
43
Electrical Specifications
Figure 5.
Deeper Sleep VCC and ICC Loadline for Standard-Voltage, Low-Power SV
(25 W) and Dual-Core Extreme Edition Processors
VCC-CORE [V]
Slope = -2.1 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
VCC-CORE max {HFM|LFM}
VCC-CORE, DC max {HFM|LFM}
13mV= RIPPLE
VCC-CORE nom {HFM|LFM}
VCC-CORE, DC min {HFM|LFM}
VCC-CORE min {HFM|LFM}
+/-VCC-CORE Tolerance
= VR St. Pt. Error 1/
ICC-CORE
[A]
0
ICC-CORE max
{HFM|LFM}
Note 1/ VCC-CORE Set Point Error Tolerance is per below:
Tolerance VCC-CORE VID Voltage Range
--------------- --------------------------------------------------------
+/-[(VID*1.5%)-3mV]
VCC-CORE > 0.7500V
+/-(11.5mV-3mV)
0.5000V </= VCC-CORE </= 0.7500V
Total tolerance window
including ripple is +/-35mV for C6
0.3000V </= VCC-CORE < 0.5000V
NOTE: Deeper Sleep mode tolerance depends on VID value.
44
Datasheet
Electrical Specifications
Figure 6.
Deeper Sleep VCC and ICC Loadline for Low-Power Standard-Voltage
Processors
VCC-CORE [V]
Slope = -4.0 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
VCC-CORE max {HFM|LFM}
VCC-CORE, DC max {HFM|LFM}
10mV= RIPPLE
VCC-CORE nom
{HFM|LFM}
VCC-CORE, DC min
{HFM|LFM}
+/-VCC-CORE Tolerance
= VR St. Pt. Error 1/
VCC-CORE min {HFM|LFM}
ICC-CORE
[A]
ICC-CORE max
{HFM|LFM}
0
Note 1/ VCC-CORE Set Point Error Tolerance is per below:
Tolerance VCC-CORE VID Voltage Range
--------------- --------------------------------------------------------
+/-[(VID*1.5%)-3mV]
VCC-CORE > 0.7500V
+/-(11.5mV-3mV)
0.5000V </= VCC-CORE </= 0.7500V
Total tolerance window
including ripple is +/-35mV for C6
0.3000V </= VCC-CORE < 0.5000V
NOTES:
1.
2.
Applies to low-power standard-voltage 22-mm (dual-core) processors.
Deeper Sleep mode tolerance depends on VID value.
Datasheet
45
Electrical Specifications
Figure 7.
Active VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and Power
Optimized Performance Processor
VCC-CORE [V]
Slope = -4.0 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
VCC-CORE max {HFM|LFM}
VCC-CORE, DC max {HFM|LFM}
10mV= RIPPLE
VCC-CORE nom {HFM|LFM}
VCC-CORE, DC min {HFM|LFM}
VCC-CORE min {HFM|LFM}
+/-VCC-CORE Tolerance
= VR St. Pt. Error 1/
ICC-CORE
[A]
0
ICC-CORE max
{HFM|LFM}
Note 1/ VCC-CORE Set Point Error Tolerance is per below:
Tolerance VCC-CORE VID Voltage Range
--------------- --------------------------------------------------------
+/-1.5%
+/-11.5mV
+/-25mV
VCC-CORE > 0.7500V
0.5000V </= VCC-CORE </= 0.7500V
0.3000V </= VCC-CORE < 0.5000V
NOTES:
1.
Applies to Low-Voltage, Ultra-Low-Voltage and Power Optimised Performance processors in
22 mmx22 mm package.
2.
Active mode tolerance depends on VID value
46
Datasheet
Electrical Specifications
Figure 8.
Deeper Sleep VCC and ICC Loadline for Low-Voltage, Ultra-Low-Voltage and
Power Optimized Performance Processor
VCC-CORE [V]
Slope = -4.0 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
VCC-CORE max {HFM|LFM}
VCC-CORE, DC max {HFM|LFM}
10mV= RIPPLE
VCC-CORE nom
{HFM|LFM}
VCC-CORE, DC min
{HFM|LFM}
+/-VCC-CORE Tolerance
= VR St. Pt. Error 1/
VCC-CORE min {HFM|LFM}
ICC-CORE
[A]
ICC-CORE max
{HFM|LFM}
0
Note 1/ VCC-CORE Set Point Error Tolerance is per below:
Tolerance VCC-CORE VID Voltage Range
--------------- --------------------------------------------------------
+/-[(VID*1.5%)-3mV]
VCC-CORE > 0.7500V
+/-(11.5mV-3mV)
0.5000V </= VCC-CORE </= 0.7500V
Total tolerance window
including ripple is +/-35mV for C6
0.3000V </= VCC-CORE < 0.5000V
NOTES:
1.
Applies to Low-Voltage, Ultra-Low-Voltage and Power Optimised Performance processors in
22 mmx22 mm package.
2.
Deeper Sleep mode tolerance depends on VID value.
Datasheet
47
Electrical Specifications
Table 13.
Symbol
AGTL+ Signal Group DC Specifications
Parameter
I/O Voltage
Min
Typ
Max
Unit
Notes1
V
1.00
0.65
27.23
49
1.05
0.70
27.5
55
1.10
0.72
27.78
63
V
V
CCP
GTLREF
Reference Voltage
6
10
R
Compensation Resistor
Termination Resistor Address
Termination Resistor Data
Termination Resistor Control
Input High Voltage
Ω
Ω
Ω
Ω
V
COMP
ODT/A
ODT/D
R
R
11, 12
11, 13
11, 14
3,6
49
55
63
R
49
55
63
ODT/Cntrl
V
0.82
-0.10
0.90
50
1.05
0
1.20
0.55
1.10
61
IH
V
Input Low Voltage
V
2,4
IL
V
Output High Voltage
V
V
6
OH
CCP
R
Termination Resistance Address
Termination Resistance Data
Termination Resistance Control
Buffer On Resistance Address
Buffer On Resistance Data
Buffer On Resistance Control
Input Leakage Current
Pad Capacitance
55
55
Ω
Ω
Ω
Ω
Ω
Ω
µA
pF
7, 12
7, 13
7, 14
5, 12
5, 13
5, 14
8
TT/A
TT/D
R
50
61
R
50
55
61
TT/Cntrl
R
R
23
25
29
ON/A
ON/D
23
25
29
R
23
25
29
ON/Cntrl
I
—
—
± 100
2.75
LI
Cpad
1.80
2.30
9
NOTES:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
V
IL
value.
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
3.
4.
5.
V
IH
value.
and V
V
may experience excursions above V . However, input signal drivers must comply with the
CCP
IH
OH
signal quality specifications.
This is the pulldown driver resistance. Measured at 0.31*V . R
(min) = 0.418*R , R (typ) =
ON
CCP
ON
TT
0.455*R ,
TT
R
(max) = 0.527*R . R typical value of 55 Ω is used for R
typ/min/max calculations.
ON
TT
TT
ON
6.
7.
GTLREF should be generated from V
specifications is the instantaneous V
with a 1% tolerance resistor divider. The V
referred to in these
CCP
CCP
.
CCP
R
is the on-die termination resistance measured at V of the AGTL+ output driver. Measured at
TT
OL
0.31*V . R is connected to V on die. Refer to processor I/O buffer models for I/V characteristics.
CCP
TT
CCP
8.
Specified with on-die R and R
turned off. Vin between 0 and V
.
TT
ON
CCP
9.
Cpad includes die capacitance only. No package parasitics are included.
This is the external resistor on the comp pins.
10.
11.
12.
13.
14.
On-die termination resistance, measured at 0.33*V
Applies to Signals A[35:3].
.
CCP
Applies to Signals D[63:0].
Applies to Signals BPRI#, DEFER#, PREQ#, PREST#, RS[2:0]#, TRDY#, ADS#, BNR#, BPM[3:0], BR0#,
DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#, DPWR#, DSTB[1:0]#, DSTBP[3:0] and DSTBN[3:0]#.
48
Datasheet
Electrical Specifications
Table 14.
Symbol
CMOS Signal Group DC Specifications
Parameter
Min
Typ
Max
Unit
Notes1
V
I/O Voltage
1.00
1.05
0.00
1.10
V
V
CCP
V
Input Low Voltage CMOS
Input High Voltage
-0.10
0.3*V
2
2
2
2
3
4
5
6
7
IL
IH
CCP
V
0.7*V
V
V +0.1
CCP
V
CCP
CCP
V
Output Low Voltage
-0.10
0.9*V
0
0.1*V
V
OL
OH
OL
OH
CCP
V
Output High Voltage
Output Low Current
Output High Current
Input Leakage Current
Pad Capacitance
V
V +0.1
CCP
V
CCP
CCP
I
1.5
1.5
—
—
4.1
mA
mA
µA
pF
pF
I
4.1
±100
2.75
1.45
I
—
—
LI
Cpad1
Cpad2
1.80
0.95
2.30
1.2
Pad Capacitance for CMOS Input
NOTES:
1.
2.
3.
4.
5.
6.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
The V referred to in these specifications refers to instantaneous V
.
CCP
CCP
Measured at 0.1 *V
Measured at 0.9 *V
.
CCP
.
CCP
For Vin between 0 V and V . Measured when the driver is tristated.
CCP
Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package parasitics are
included.
7.
Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included.
Table 15.
Symbol
Open Drain Signal Group DC Specifications
Parameter
Output High Voltage
Min
–5%
Typ
Max
V +5%
CCP
Unit
Notes1
V
V
V
V
V
3
OH
CCP
CCP
V
Output Low Voltage
Output Low Current
Output Leakage Current
Pad Capacitance
0
16
—
—
0.20
50
OL
OL
LO
I
I
mA
µA
pF
2
4
5
—
—
±200
2.75
Cpad
1.80
2.30
NOTES:
1.
2.
3.
4.
5.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Measured at 0.2 V.
V
is determined by value of the external pull-up resistor to V
.
OH
CCP
For Vin between 0 V and V
.
OH
Cpad includes die capacitance only. No package parasitics are included.
§
Datasheet
49
Electrical Specifications
50
Datasheet
Package Mechanical Specifications and Pin Information
4
Package Mechanical
Specifications and Pin
Information
4.1
Package Mechanical Specifications
The processor (XE and SV) is available in 478-pin Micro-FCPGA packages as well as
479-ball Micro-FCBGA packages. The package mechanical dimensions are shown in
Figure 9 through Figure 13.
The processor (POP, LV, ULV DC and ULV SC) is available 956-ball Micro-FCBGA
packages. The package mechanical dimensions are shown in Figure 14 and Figure 15.
The maximum outgoing co-planarity is 0.2 mm (8 mils) for SFF processors.
The mechanical package pressure specifications are in a direction normal to the surface
of the processor. This protects the processor die from fracture risk due to uneven die
pressure distribution under tilt, stack-up tolerances and other similar conditions. These
specifications assume that a mechanical attach is designed specifically to load one type
of processor.
A 15-lbf load limit should not be exceeded on BGA packages so as to not impact solder
joint reliability after reflow. This load limit ensures that impact to the package solder
joints due to transient bend, shock, or tensile loading is minimized. The 15-lbf metric
should be used in parallel with the 689-kPa (100 psi) pressure limit as long as neither
limits are exceeded. In some cases, designing to 15 lbf will exceed the pressure
specification of 689 kPa (100 psi) and therefore should be reduced to ensure both limits
are maintained.
Moreover, the processor package substrate should not be used as a mechanical
reference or load-bearing surface for the thermal or mechanical solution.
Caution:
The Micro-FCBGA package incorporates land-side capacitors. The land-side capacitors
are electrically conductive so care should be taken to avoid contacting the capacitors
with other electrically conductive materials on the motherboard. Doing so may short
the capacitors and possibly damage the device or render it inactive.
Datasheet
51
Package Mechanical Specifications and Pin Information
Figure 9.
6-MB and 3-MB on 6-MB Die Micro-FCPGA Package Drawing (Sheet 1 of 2)
52
Datasheet
Package Mechanical Specifications and Pin Information
Figure 10.
3-MB die Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)
Datasheet
53
Package Mechanical Specifications and Pin Information
Figure 11.
3-MB Die Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)
54
Datasheet
Package Mechanical Specifications and Pin Information
Figure 12.
3-MB Die Micro-FCBGA Processor Package Drawing (Sheet 1 of 2)
Datasheet
55
Package Mechanical Specifications and Pin Information
Figure 13.
3-MB Die Micro-FCBGA Processor Package Drawing (Sheet 2 of 2)
56
Datasheet
Package Mechanical Specifications and Pin Information
Figure 14.
Intel Core 2 Duo Mobile Processor (POP and LV) Die Micro-FCBGA Processor
Package Drawing
Datasheet
57
Package Mechanical Specifications and Pin Information
Figure 15.
Intel Core 2 Duo Mobile Processor (ULV SC and ULV DC) Die Micro-FCBGA
Processor Package Drawing
58
Datasheet
Package Mechanical Specifications and Pin Information
4.2
Processor Pinout and Pin List
Figure 16 and Figure 17 show the processor (SV and XE) pinout as viewed from the top
of the package. Table 16 provides the pin list, arranged numerically by pin number.
Figure 16 through Figure 18 show the top view of the LV and ULV processor package.
Table 18 lists the SFF processor ballout alphabetically by signal name. For signal
descriptions, refer to Section 4.3.
Figure 16.
Processor Pinout (Top Package View, Left Side)
1
2
3
4
5
6
7
8
9
10
11
12
13
1
A
VSS
RSVD
SMI#
INIT#
VSS
FERR#
DPSLP#
A20M#
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
A
B
1
B
LINT1
IGNNE
#
THERM
TRIP#
C
D
E
RESET#
VSS
VSS
TEST7
RSVD
VSS
VSS
LINT0
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
C
D
E
STPCLK
#
PWRGO
OD
RSVD
BNR#
VSS
SLP#
DPRSTP
#
DBSY#
HITM#
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
F
BR0#
VSS
VSS
RS[0]#
RS[2]#
RS[1]#
VSS
VSS
RSVD
HIT#
F
G
TRDY#
BPRI#
G
REQ[1]
#
H
J
ADS#
A[9]#
VSS
LOCK#
A[3]#
DEFER#
VSS
VSS
H
J
REQ[3]
#
VSS
VCCP
REQ[2]
#
REQ[0]
#
K
L
VSS
VSS
A[6]#
A[4]#
VSS
VCCP
VSS
K
L
REQ[4]#
A[13]#
VSS
VSS
A[5]#
RSVD
ADSTB[0]
#
M
A[7]#
VCCP
M
N
P
R
T
VSS
A[8]#
A[12]#
VSS
A[10]#
VSS
VSS
RSVD
A[11]#
VSS
VCCP
VSS
N
P
R
T
A[15]#
A[16]#
VSS
A[14]#
A[24]#
VSS
A[19]#
A[26]#
VSS
VCCP
VCCP
VSS
RSVD
A[25]#
A[18]#
U
A[23]#
A[30]#
A[21]#
U
ADSTB[1]
#
V
VSS
RSVD
A[31]#
VSS
VCCP
V
W
Y
VSS
A[27]#
A[17]#
A[32]#
VSS
VSS
A[28]#
A[22]#
A[20]#
VSS
W
Y
COMP[3]
A[29]#
A
A
AA
AB
AC
AD
AE
AF
COMP[2]
VSS
VSS
A[34]#
PRDY#
VSS
A[35]#
TDO
A[33]#
VSS
VSS
TMS
TDI
TRST#
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VCC
A
B
BPM[3]
#
A
C
PREQ#
BPM[2]#
VSS
VSS
TCK
BPM[1]
#
BPM[0]
#
A
D
VSS
VID[0]
PSI#
VSS
SENSE
A
E
VID[6]
VID[4]
VSS
VID[2]
VCC
SENSE
A
F
TEST5
VSS
VID[5]
VID[3]
VID[1]
VSS
VSS
VCC
VCC
VSS
VCC
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
NOTES:
1.
2.
Keying option for Micro-FCPGA, A1 and B1 are de-populated.
Keying option for Micro-FCBGA, A1 is de-populated and B1 is VSS.
Datasheet
59
Package Mechanical Specifications and Pin Information
Figure 17.
Processor Pinout (Top Package View, Right Side)
14
15
16
17
18
19
20
21
22
23
24
THRMDA
VSS
25
VSS
26
A
B
C
VSS
VCC
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VCC
BCLK[1]
VSS
BCLK[0]
BSEL[0]
VSS
VSS
TEST6
VCCA
VCCA
A
B
C
VCC
BSEL[1]
TEST1
THRMDC
VSS
DBR#
BSEL[2]
TEST3
PROCHOT
#
D
VCC
VCC
VSS
VCC
VCC
VSS
IERR#
RSVD
VSS
DPWR#
TEST2
VSS
D
E
F
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
DRDY#
VCCP
D[0]#
VSS
D[7]#
D[4]#
VSS
VSS
D[6]#
VSS
D[2]#
D[13]#
VSS
E
F
D[1]#
D[9]#
G
D[3]#
D[5]#
G
DSTBP[
0]#
H
VSS
D[12]#
D[15]#
VSS
DINV[0]#
H
DSTBN[
0]#
J
K
L
VCCP
VCCP
VSS
VSS
D[11]#
VSS
D[10]#
D[8]#
VSS
VSS
J
K
L
D[14]#
D[22]#
D[17]#
D[29]#
VSS
DSTBN[
1]#
D[20]#
DSTBP[
1]#
M
VCCP
VSS
D[23]#
D[21]#
VSS
M
N
P
VCCP
VSS
D[16]#
D[26]#
VSS
DINV[1]#
VSS
D[31]#
D[24]#
VSS
N
P
D[25]#
D[18]#
COMP[0
]
R
T
VCCP
VCCP
VSS
VSS
D[19]#
VSS
D[28]#
D[27]#
VSS
VSS
R
T
D[37]#
DINV[2]#
D[30]#
D[38]#
VSS
COMP[1
]
U
D[39]#
U
V
VCCP
VCCP
VSS
D[36]#
VSS
D[34]#
D[43]#
VSS
D[35]#
VSS
V
W
D[41]#
D[44]#
W
DSTBN[
2]#
Y
VSS
D[32]#
VSS
D[42]#
D[45]#
VSS
D[40]#
VSS
Y
DSTBP[
2]#
A
A
AA
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
VCC
D[50]#
D[46]#
A
B
AB
AC
D[52]#
VSS
D[51]#
D[60]#
VSS
VSS
D[63]#
D[61]#
VSS
D[33]#
VSS
D[47]#
D[57]#
VSS
VSS
D[53]#
GTLREF
VSS
DINV[3
]#
A
C
A
D
A
D
D[54]#
VCC
D[59]#
D[58]#
D[49]#
D[48]#
DSTBN[3]
#
A
E
AE
AF
D[55]#
DSTBP[3]
#
A
F
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
D[62]#
D[56]#
VSS
TEST4
14
15
16
17
18
19
20
21
22
23
24
25
26
60
Datasheet
Package Mechanical Specifications and Pin Information
Table 16.
Pin Name Listing
Signal
Table 16.
Pin Name Listing
Signal
Pin Name Pin #
Buffer
Type
Direction
Pin Name Pin #
Buffer
Type
Direction
Source
Synch
Input/
Output
Source
Synch
Input/
Output
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
R4
T5
A[3]#
A[4]#
J4
L5
L4
K5
M3
N2
J1
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
T3
A[5]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
W2
W5
Y4
A[6]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
A[7]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
A[8]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
U2
A[9]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
V4
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
N3
P5
P2
L2
P4
P1
R1
Y2
U5
R3
W6
U4
Y5
U1
Source
Synch
Input/
Output
Source
Synch
Input/
Output
W3
AA4
AB2
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
A[35]#
A20M#
ADS#
AA3
A6
CMOS
Input
Source
Synch
Input/
Output
Common Input/
Clock
H1
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
ADSTB[0]#
ADSTB[1]#
M1
V1
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
BCLK[0]
BCLK[1]
A22
A21
Bus Clock Input
Bus Clock Input
Common Input/
Source
Synch
Input/
Output
BNR#
E2
Source
Synch
Input/
Output
Clock
Output
Common Input/
Clock
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
AD4
AD3
AD1
AC4
Source
Synch
Input/
Output
Output
Output
Common
Clock
Source
Synch
Input/
Output
Common
Clock
Output
Source
Synch
Input/
Output
Common Input/
Clock Output
Datasheet
61
Package Mechanical Specifications and Pin Information
Table 16.
Pin Name Listing
Signal
Table 16.
Pin Name Listing
Signal
Pin Name Pin #
Buffer
Type
Direction
Pin Name Pin #
Buffer
Type
Direction
Common
Clock
Source
Synch
Input/
Output
BPRI#
BR0#
G5
F1
Input
D[14]#
D[15]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
D[32]#
D[33]#
D[34]#
D[35]#
K22
H23
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
Y22
AB24
V24
V26
Common Input/
Source
Synch
Input/
Output
Clock
CMOS
CMOS
CMOS
Output
Output
Output
Output
BSEL[0]
BSEL[1]
BSEL[2]
B22
B23
C21
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Power/
Other
Input/
Output
COMP[0]
COMP[1]
COMP[2]
COMP[3]
D[0]#
R26
U26
AA1
Y1
Source
Synch
Input/
Output
Power/
Other
Input/
Output
Source
Synch
Input/
Output
Power/
Other
Input/
Output
Source
Synch
Input/
Output
Power/
Other
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
Source
Synch
Input/
Output
Source
Synch
Input/
Output
D[1]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
D[2]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
D[3]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
D[4]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
D[5]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
D[6]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
D[7]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
D[8]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
D[9]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
D[10]#
D[11]#
D[12]#
D[13]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
62
Datasheet
Package Mechanical Specifications and Pin Information
Table 16.
Pin Name Listing
Signal
Table 16.
Pin Name Listing
Signal
Pin Name Pin #
Buffer
Type
Direction
Pin Name Pin #
Buffer
Type
Direction
Source
Synch
Input/
Output
Source
Synch
Input/
Output
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
V23
T22
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
AE21
AD21
AC22
AD23
AF22
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
U25
Source
Synch
Input/
Output
Source
Synch
Input/
Output
U23
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Y25
Source
Synch
Input/
Output
Source
Synch
Input/
Output
W22
Y23
D[63]#
DBR#
AC23
C20
E1
Source
Synch
Input/
Output
CMOS
Output
Common Input/
Clock
DBSY#
Source
Synch
Input/
Output
Output
W24
W25
AA23
AA24
AB25
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
Common
Clock
DEFER#
DINV[0]#
DINV[1]#
DINV[2]#
DINV[3]#
H5
H25
N24
U22
AC20
Input
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
DPRSTP#
DPSLP#
E5
B5
CMOS
CMOS
Input
Input
Source
Synch
Input/
Output
Common Input/
Clock Output
Source
Synch
Input/
Output
DPWR#
DRDY#
D24
F21
J26
L26
Y26
Common Input/
Clock
Source
Synch
Input/
Output
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
DSTBN[0]#
DSTBN[1]#
DSTBN[2]#
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Source
Synch
Input/
Output
DSTBN[3]# AE25
Source
Synch
Input/
Output
Source
Synch
Input/
Output
DSTBP[0]#
DSTBP[1]#
H26
M26
Source
Synch
Input/
Output
Source
Synch
Input/
Output
Datasheet
63
Package Mechanical Specifications and Pin Information
Table 16.
Pin Name Listing
Signal
Table 16.
Pin Name Listing
Signal
Pin Name Pin #
Buffer
Type
Direction
Pin Name Pin #
Buffer
Type
Direction
Source
Synch
Input/
Output
Common
Clock
DSTBP[2]# AA26
DSTBP[3]# AF24
RS[1]#
RS[2]#
F4
Input
Input
Source
Synch
Input/
Output
Common
Clock
G3
Open
Drain
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
SLP#
SMI#
STPCLK#
TCK
B2
D2
D3
D22
F6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CMOS
FERR#
GTLREF
HIT#
A5
AD26
G6
Output
Input
Power/
Other
Common Input/
Clock Output
Common Input/
Clock
M4
N5
HITM#
IERR#
E4
Output
Open
Drain
D20
Output
T2
V3
IGNNE#
INIT#
LINT0
C4
B3
C6
B4
CMOS
CMOS
CMOS
CMOS
Input
Input
Input
Input
D7
A3
Input
Input
Input
Input
Input
CMOS
D5
AC5
AA6
CMOS
LINT1
CMOS
Common Input/
Clock
LOCK#
PRDY#
H4
Output
TDI
CMOS
Common
Clock
Open
Drain
AC2
AC1
D21
Output
TDO
AB3
Output
Common
Clock
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
C23
D25
C24
AF26
AF1
A26
C3
Test
Test
Test
Test
Test
Test
Test
PREQ#
Input
Open
Drain
Input/
Output
PROCHOT#
PSI#
AE6
D6
CMOS
CMOS
Output
Input
PWRGOOD
Source
Synch
Input/
Output
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
RESET#
RS[0]#
K3
H2
K2
J3
Source
Synch
Input/
Output
THERMTRIP
#
Open
Drain
C7
Output
Source
Synch
Input/
Output
Power/
Other
THRMDA
A24
Source
Synch
Input/
Output
Power/
Other
THRMDC
TMS
B25
AB5
G2
Source
Synch
Input/
Output
CMOS
Input
Input
Input
L1
C1
F3
Common
Clock
TRDY#
TRST#
VCC
Common
Clock
Input
Input
AB6
A7
CMOS
Common
Clock
Power/
Other
64
Datasheet
Package Mechanical Specifications and Pin Information
Table 16.
Pin Name Listing
Signal
Table 16.
Pin Name Listing
Signal
Pin Name Pin #
Buffer
Type
Direction
Pin Name Pin #
Buffer
Type
Direction
Power/
Other
Power/
Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
A9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB15
AB17
AB18
AB20
AC7
Power/
Other
Power/
Other
A10
Power/
Other
Power/
Other
A12
Power/
Other
Power/
Other
A13
Power/
Other
Power/
Other
A15
Power/
Other
Power/
Other
A17
AC9
Power/
Other
Power/
Other
A18
AC10
AC12
AC13
AC15
AC17
AC18
AD7
Power/
Other
Power/
Other
A20
Power/
Other
Power/
Other
AA7
Power/
Other
Power/
Other
AA9
Power/
Other
Power/
Other
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB7
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AD9
Power/
Other
Power/
Other
AD10
AD12
AD14
AD15
AD17
AD18
AE9
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AB9
Power/
Other
Power/
Other
AB10
AB12
AB14
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AE10
Datasheet
65
Package Mechanical Specifications and Pin Information
Table 16.
Pin Name Listing
Signal
Table 16.
Pin Name Listing
Signal
Pin Name Pin #
Buffer
Type
Direction
Pin Name Pin #
Buffer
Type
Direction
Power/
Other
Power/
Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AE12
AE13
AE15
AE17
AE18
AE20
AF9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
B20
C9
Power/
Other
Power/
Other
Power/
Other
Power/
Other
C10
C12
C13
C15
C17
C18
D9
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AF10
AF12
AF14
AF15
AF17
AF18
AF20
B7
Power/
Other
Power/
Other
Power/
Other
Power/
Other
D10
D12
D14
D15
D17
D18
E7
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
B9
Power/
Other
Power/
Other
B10
E9
Power/
Other
Power/
Other
B12
E10
E12
E13
E15
E17
Power/
Other
Power/
Other
B14
Power/
Other
Power/
Other
B15
Power/
Other
Power/
Other
B17
Power/
Other
Power/
Other
B18
66
Datasheet
Package Mechanical Specifications and Pin Information
Table 16.
Pin Name Listing
Signal
Table 16.
Pin Name Listing
Signal
Pin Name Pin #
Buffer
Type
Direction
Pin Name Pin #
Buffer
Type
Direction
Power/
Other
Power/
Other
VCC
VCC
E18
E20
F7
VCCP
VCCP
R6
R21
T6
Power/
Other
Power/
Other
Power/
Other
Power/
Other
VCC
VCCP
Power/
Other
Power/
Other
VCC
F9
VCCP
T21
V6
Power/
Other
Power/
Other
VCC
F10
F12
F14
F15
F17
F18
F20
B26
C26
G21
J6
VCCP
Power/
Other
Power/
Other
VCC
VCCP
V21
W21
AF7
Power/
Other
Power/
Other
VCC
VCCP
Power/
Other
Power/
Other
VCC
VCCSENSE
Power/
Other
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AD6
AF5
AE5
AF4
AE3
AF3
AE2
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Output
Output
Output
Output
Output
Output
Output
VCC
Power/
Other
VCC
Power/
Other
VCC
Power/
Other
VCCA
VCCA
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
Power/
Other
Power/
Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A2
A4
Power/
Other
Power/
Other
Power/
Other
Power/
Other
A8
Power/
Other
J21
K6
Power/
Other
A11
A14
A16
A19
A23
A25
Power/
Other
Power/
Other
Power/
Other
K21
M6
Power/
Other
Power/
Other
Power/
Other
Power/
Other
M21
N6
Power/
Other
Power/
Other
Power/
Other
Power/
Other
N21
Datasheet
67
Package Mechanical Specifications and Pin Information
Table 16.
Pin Name Listing
Signal
Table 16.
Pin Name Listing
Signal
Pin Name Pin #
Buffer
Type
Direction
Pin Name Pin #
Buffer
Type
Direction
Power/
Other
Power/
Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA2
AA5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AC14
AC16
AC19
AC21
AC24
AD2
Power/
Other
Power/
Other
Power/
other
Power/
Other
AA8
Power/
Other
Power/
Other
AA11
AA14
AA16
AA19
AA22
AA25
AB1
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AD5
Power/
Other
Power/
Other
AD8
Power/
Other
Power/
Other
AD11
AD13
AD16
AD19
AD22
AD25
AE1
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AB4
Power/
Other
Power/
Other
AB8
Power/
Other
Power/
Other
AB11
AB13
AB16
AB19
AB23
AB26
AC3
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AE4
Power/
Other
Power/
Other
AE8
Power/
Other
Power/
Other
AE11
AE14
AE16
AE19
AE23
Power/
Other
Power/
Other
Power/
Other
Power/
Other
AC6
Power/
Other
Power/
Other
AC8
Power/
Other
Power/
Other
AC11
68
Datasheet
Package Mechanical Specifications and Pin Information
Table 16.
Pin Name Listing
Signal
Table 16.
Pin Name Listing
Signal
Pin Name Pin #
Buffer
Type
Direction
Pin Name Pin #
Buffer
Type
Direction
Power/
Other
Power/
Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE26
AF2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF25
B6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C14
C16
C19
C22
C25
D1
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
D4
Power/
Other
Power/
Other
D8
Power/
Other
Power/
Other
D11
D13
D16
D19
D23
D26
E3
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
B8
Power/
Other
Power/
Other
B11
B13
B16
B19
B21
B24
C2
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
E6
Power/
Other
Power/
Other
E8
Power/
Other
Power/
Other
E11
E14
E16
E19
E21
Power/
Other
Power/
Other
Power/
Other
Power/
Other
C5
Power/
Other
Power/
Other
C8
Power/
Other
Power/
Other
C11
Datasheet
69
Package Mechanical Specifications and Pin Information
Table 16.
Pin Name Listing
Signal
Table 16.
Pin Name Listing
Signal
Pin Name Pin #
Buffer
Type
Direction
Pin Name Pin #
Buffer
Type
Direction
Power/
Other
Power/
Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E24
F2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K1
K4
Power/
Other
Power/
Other
Power/
Other
Power/
Other
F5
K23
K26
L3
Power/
Other
Power/
Other
F8
Power/
Other
Power/
Other
F11
F13
F16
F19
F22
F25
G1
Power/
Other
Power/
Other
L6
Power/
Other
Power/
Other
L21
L24
M2
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
M5
Power/
Other
Power/
Other
M22
M25
N1
Power/
Other
Power/
Other
G4
Power/
Other
Power/
Other
G23
G26
H3
Power/
Other
Power/
Other
N4
Power/
Other
Power/
Other
N23
N26
P3
Power/
Other
Power/
Other
H6
Power/
Other
Power/
Other
H21
H24
J2
Power/
Other
Power/
Other
P6
Power/
Other
Power/
Other
P21
P24
R2
Power/
Other
Power/
Other
J5
Power/
Other
Power/
Other
J22
J25
Power/
Other
Power/
Other
R5
70
Datasheet
Package Mechanical Specifications and Pin Information
Table 16.
Pin Name Listing
Signal
Table 16.
Pin Name Listing
Signal
Pin Name Pin #
Buffer
Type
Direction
Pin Name Pin #
Buffer
Type
Direction
Power/
Other
Power/
Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R22
R25
T1
VSS
VSS
Y21
Y24
AE7
Power/
Other
Power/
Other
Power/
Other
Power/
Other
VSSSENSE
Output
Power/
Other
T4
Power/
Other
T23
T26
U3
Power/
Other
Power/
Other
Power/
Other
U6
Power/
Other
U21
U24
V2
Power/
Other
Power/
Other
Power/
Other
V5
Power/
Other
V22
V25
W1
W4
W23
W26
Y3
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Power/
Other
Y6
Datasheet
71
Package Mechanical Specifications and Pin Information
Table 17.
Pin # Listing
Table 17.
Pin # Listing
Signal Buffer Directi
Signal Buffer Directi
Pin # Pin Name
Pin # Pin Name
Type
on
Type
on
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
A2
A3
VSS
SMI#
VSS
Power/Other
CMOS
Input
A4
Power/Other
Open Drain
CMOS
A5
FERR#
A20M#
VCC
Output
Input
A6
A7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Bus Clock
A8
VSS
A9
VCC
Input/
Output
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
VCC
AA21
AA22
AA23
D[50]#
VSS
Source Synch
Power/Other
Source Synch
VSS
VCC
Input/
Output
D[45]#
VCC
VSS
Input/
Output
AA24
AA25
AA26
AB1
D[46]#
VSS
Source Synch
Power/Other
Source Synch
Power/Other
Source Synch
VCC
VSS
DSTBP[2]
#
Input/
Output
VCC
VCC
VSS
VSS
Input/
Output
AB2
A[34]#
VCC
BCLK[1]
BCLK[0]
VSS
Input
Input
AB3
AB4
TDO
VSS
TMS
TRST#
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
Open Drain
Power/Other
CMOS
Output
Bus Clock
Power/Other
Power/Other
Power/Other
Test
AB5
Input
Input
THRMDA
VSS
AB6
CMOS
AB7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TEST6
AB8
Input/
Output
AB9
AA1
AA2
AA3
COMP[2]
VSS
Power/Other
Power/Other
Source Synch
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
Input/
Output
A[35]#
Input/
Output
AA4
A[33]#
Source Synch
AA5
AA6
VSS
TDI
Power/Other
CMOS
Input
AA7
VCC
VSS
VCC
VCC
VSS
VCC
Power/Other
Power/other
Power/Other
Power/Other
Power/Other
Power/Other
AA8
AA9
AA10
AA11
AA12
Input/
Output
AB21
D[52]#
Source Synch
72
Datasheet
Package Mechanical Specifications and Pin Information
Table 17.
Pin # Listing
Table 17.
Pin # Listing
Signal Buffer Directi
Signal Buffer Directi
Pin # Pin Name
Pin # Pin Name
Type
on
Type
on
Input/
Output
AD3
AD4
BPM[1]# Common Clock Output
AB22
AB23
AB24
D[51]#
VSS
Source Synch
Power/Other
Source Synch
Input/
BPM[0]# Common Clock
Output
Input/
Output
AD5
AD6
VSS
VID[0]
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
Power/Other
CMOS
D[33]#
Output
Input/
Output
AD7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AB25
D[47]#
Source Synch
Power/Other
AD8
AB26
AC1
AC2
AC3
VSS
PREQ#
PRDY#
VSS
AD9
Common Clock Input
Common Clock Output
Power/Other
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
Input/
Output
AC4
BPM[3]# Common Clock
AC5
AC6
TCK
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VSS
CMOS
Input
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
Input/
Output
AD20
D[54]#
Source Synch
Input/
Output
AD21
AD22
AD23
D[59]#
VSS
Source Synch
Power/Other
Source Synch
Input/
Output
D[61]#
Input/
Output
AD24
D[49]#
Source Synch
AD25
AD26
AE1
VSS
GTLREF
VSS
Power/Other
Power/Other
Power/Other
CMOS
Input
Input/
Output
AC20
AC21
AC22
DINV[3]# Source Synch
VSS
Power/Other
Source Synch
AE2
VID[6]
VID[4]
VSS
Output
Output
Input/
Output
AE3
CMOS
D[60]#
AE4
Power/Other
CMOS
Input/
Output
AE5
VID[2]
PSI#
Output
Output
Output
AC23
AC24
AC25
D[63]#
VSS
Source Synch
Power/Other
Source Synch
AE6
CMOS
AE7
VSSSENSE Power/Other
Input/
Output
D[57]#
AE8
VSS
VCC
VCC
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AE9
Input/
Output
AC26
D[53]#
Source Synch
AE10
AE11
AE12
AD1
AD2
BPM[2]# Common Clock Output
VSS Power/Other
73
Datasheet
Package Mechanical Specifications and Pin Information
Table 17.
Pin # Listing
Table 17.
Pin # Listing
Signal Buffer Directi
Signal Buffer Directi
Pin # Pin Name
Pin # Pin Name
Type
on
Type
on
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input/
Output
AF22
AF23
AF24
D[62]#
D[56]#
Source Synch
Input/
Output
Source Synch
Source Synch
DSTBP[3]
#
Input/
Output
AF25
AF26
B2
VSS
TEST4
RSVD
INIT#
LINT1
DPSLP#
VSS
Power/Other
Test
Reserved
Input/
Output
B3
CMOS
Input
Input
Input
AE21
D[58]#
Source Synch
B4
CMOS
Input/
Output
AE22
AE23
AE24
D[55]#
VSS
Source Synch
Power/Other
Source Synch
B5
CMOS
B6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
CMOS
B7
VCC
Input/
Output
D[48]#
B8
VSS
DSTBN[3]
#
Input/
Output
B9
VCC
AE25
Source Synch
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
VCC
AE26
AF1
AF2
AF3
AF4
AF5
AF6
VSS
TEST5
VSS
Power/Other
Test
VSS
VCC
Power/Other
CMOS
VSS
VID[5]
VID[3]
VID[1]
VSS
Output
Output
Output
VCC
CMOS
VCC
CMOS
VSS
Power/Other
VCC
VCCSENS
E
VCC
AF7
Power/Other
VSS
AF8
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
AF9
VSS
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
BSEL[0]
BSEL[1]
VSS
Output
Output
CMOS
Power/Other
Power/Other
Power/Other
THRMDC
VCCA
RESET# Common Clock Input
C2
VSS
TEST7
IGNNE#
VSS
Power/Other
Test
C3
C4
CMOS
Input
C5
Power/Other
CMOS
C6
LINT0
Input
THERMTRI
P#
C7
Open Drain
Output
Datasheet
74
Package Mechanical Specifications and Pin Information
Table 17.
Pin # Listing
Table 17.
Pin # Listing
Signal Buffer Directi
Signal Buffer Directi
Pin # Pin Name
Pin # Pin Name
Type
on
Type
on
C8
C9
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
CMOS
PROCHOT
Input/
Output
D21
#
Open Drain
D22
D23
RSVD
VSS
Reserved
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
VCC
Power/Other
VSS
Input/
Output
VCC
D24
DPWR#
Common Clock
VCC
D25
D26
TEST2
VSS
Test
VSS
Power/Other
VCC
Input/
Output
E1
DBSY#
Common Clock
VSS
VCC
Input/
Output
E2
E3
E4
BNR#
VSS
Common Clock
Power/Other
VCC
VSS
Input/
Output
DBR#
BSEL[2]
VSS
Output
Output
HITM#
Common Clock
CMOS
E5
E6
DPRSTP#
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
CMOS
Input
Power/Other
Test
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TEST1
TEST3
VSS
E7
Test
E8
Power/Other
Power/Other
Power/Other
Reserved
E9
VCCA
VSS
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
D2
RSVD
RSVD
VSS
D3
Reserved
D4
Power/Other
CMOS
D5
STPCLK#
PWRGOOD
SLP#
VSS
Input
Input
Input
D6
CMOS
D7
CMOS
D8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Open Drain
D9
VCC
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
VCC
VSS
VCC
Input/
Output
E22
D[0]#
Source Synch
VSS
VCC
Input/
Output
E23
E24
E25
D[7]#
VSS
Source Synch
Power/Other
Source Synch
VCC
VSS
VCC
Input/
Output
D[6]#
VCC
Input/
Output
VSS
E26
F1
D[2]#
BR0#
Source Synch
Common Clock
IERR#
Output
Input/
Output
Datasheet
75
Package Mechanical Specifications and Pin Information
Table 17.
Pin # Listing
Table 17.
Pin # Listing
Signal Buffer Directi
Signal Buffer Directi
Pin # Pin Name
Pin # Pin Name
Type
on
Type
on
F2
F3
VSS
RS[0]#
RS[1]#
VSS
Power/Other
Input/
Output
G25
G26
H1
D[5]#
VSS
Source Synch
Power/Other
Common Clock Input
Common Clock Input
Power/Other
Reserved
F4
Input/
Output
F5
ADS#
Common Clock
F6
RSVD
VCC
Input/
Output
H2
H3
H4
REQ[1]#
VSS
Source Synch
Power/Other
F7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
F8
VSS
F9
VCC
Input/
Output
LOCK#
Common Clock
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
VCC
H5
H6
DEFER# Common Clock Input
VSS
VSS
VSS
Power/Other
Power/Other
VCC
H21
VSS
Input/
Output
VCC
H22
D[12]#
Source Synch
VCC
Input/
Output
H23
H24
H25
D[15]#
VSS
Source Synch
Power/Other
VSS
VCC
VCC
Input/
Output
DINV[0]# Source Synch
VSS
VCC
DSTBP[0]
Source Synch
#
Input/
Output
H26
Input/
Common Clock
Output
F21
F22
F23
DRDY#
VSS
Input/
Output
J1
J2
J3
A[9]#
VSS
Source Synch
Power/Other
Source Synch
Power/Other
Input/
Source Synch
Output
D[4]#
Input/
Output
REQ[3]#
Input/
Source Synch
Output
F24
F25
F26
D[1]#
VSS
Input/
Output
J4
A[3]#
Source Synch
Power/Other
J5
J6
VSS
VCCP
VCCP
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Input/
Source Synch
Output
D[13]#
G1
G2
G3
G4
G5
VSS
TRDY#
RS[2]#
VSS
Power/Other
J21
J22
Common Clock Input
Common Clock Input
Power/Other
Input/
Output
J23
D[11]#
Source Synch
Input/
Output
BPRI#
Common Clock Input
J24
J25
J26
K1
D[10]#
VSS
Source Synch
Power/Other
Source Synch
Power/Other
Source Synch
Input/
Common Clock
Output
G6
HIT#
VCCP
D[3]#
VSS
DSTBN[0]
#
Input/
Output
G21
G22
G23
G24
Power/Other
Input/
Source Synch
Output
VSS
Input/
Output
Power/Other
K2
REQ[2]#
Input/
Source Synch
Output
D[9]#
76
Datasheet
Package Mechanical Specifications and Pin Information
Table 17.
Pin # Listing
Table 17.
Pin # Listing
Signal Buffer Directi
Signal Buffer Directi
Pin # Pin Name
Pin # Pin Name
Type
on
Type
on
Input/
Output
M22
M23
VSS
Power/Other
K3
K4
K5
REQ[0]#
VSS
Source Synch
Power/Other
Source Synch
Input/
Output
D[23]#
Source Synch
Input/
Output
Input/
Output
A[6]#
M24
M25
M26
N1
D[21]#
VSS
Source Synch
Power/Other
Source Synch
Power/Other
Source Synch
K6
VCCP
VCCP
Power/Other
Power/Other
K21
DSTBP[1]
#
Input/
Output
Input/
Output
K22
K23
K24
D[14]#
VSS
Source Synch
Power/Other
Source Synch
VSS
Input/
Output
N2
A[8]#
Input/
Output
D[8]#
Input/
Output
N3
A[10]#
Source Synch
Input/
Output
K25
K26
L1
D[17]#
VSS
Source Synch
Power/Other
Source Synch
N4
N5
VSS
RSVD
VCCP
VCCP
Power/Other
Reserved
Input/
Output
N6
Power/Other
Power/Other
REQ[4]#
N21
Input/
Output
Input/
Output
L2
L3
L4
A[13]#
VSS
Source Synch
Power/Other
Source Synch
N22
N23
N24
D[16]#
VSS
Source Synch
Power/Other
Input/
Output
Input/
Output
A[5]#
DINV[1]# Source Synch
Input/
Output
Input/
Output
L5
A[4]#
Source Synch
N25
N26
P1
D[31]#
VSS
Source Synch
Power/Other
Source Synch
L6
VSS
VSS
Power/Other
Power/Other
L21
Input/
Output
A[15]#
Input/
Output
L22
D[22]#
Source Synch
Input/
Output
P2
P3
P4
A[12]#
VSS
Source Synch
Power/Other
Source Synch
Input/
Output
L23
L24
L25
D[20]#
VSS
Source Synch
Power/Other
Source Synch
Input/
Output
A[14]#
Input/
Output
D[29]#
Input/
Output
P5
A[11]#
Source Synch
DSTBN[1]
#
Input/
Output
L26
Source Synch
P6
VSS
VSS
Power/Other
Power/Other
ADSTB[0]
#
Input/
Output
P21
M1
M2
M3
Source Synch
Power/Other
Source Synch
Input/
Output
P22
D[26]#
Source Synch
VSS
Input/
Output
Input/
Output
A[7]#
P23
P24
P25
D[25]#
VSS
Source Synch
Power/Other
Source Synch
M4
M5
RSVD
VSS
Reserved
Power/Other
Power/Other
Power/Other
Input/
Output
D[24]#
M6
VCCP
VCCP
M21
Datasheet
77
Package Mechanical Specifications and Pin Information
Table 17.
Pin # Listing
Table 17.
Pin # Listing
Signal Buffer Directi
Signal Buffer Directi
Pin # Pin Name
Pin # Pin Name
Type
on
Type
on
Input/
Output
Input/
Output
P26
D[18]#
Source Synch
U5
A[18]#
Source Synch
Input/
Output
U6
VSS
VSS
Power/Other
Power/Other
R1
R2
R3
A[16]#
VSS
Source Synch
Power/Other
Source Synch
U21
Input/
Output
U22
DINV[2]# Source Synch
Input/
Output
A[19]#
Input/
Output
U23
U24
U25
D[39]#
VSS
Source Synch
Power/Other
Source Synch
Input/
Output
R4
A[24]#
Source Synch
R5
R6
VSS
VCCP
VCCP
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Input/
Output
D[38]#
R21
R22
Input/
Output
U26
V1
COMP[1]
Power/Other
Source Synch
ADSTB[1]
#
Input/
Output
Input/
Output
R23
D[19]#
Source Synch
V2
V3
VSS
Power/Other
Reserved
Input/
Output
R24
R25
R26
D[28]#
VSS
Source Synch
Power/Other
Power/Other
RSVD
Input/
Output
V4
A[31]#
Source Synch
Input/
Output
COMP[0]
V5
V6
VSS
VCCP
VCCP
VSS
Power/Other
Power/Other
Power/Other
Power/Other
T1
T2
VSS
Power/Other
Reserved
RSVD
V21
V22
Input/
Output
T3
T4
T5
A[26]#
VSS
Source Synch
Power/Other
Source Synch
Input/
Output
V23
D[36]#
Source Synch
Input/
Output
Input/
Output
A[25]#
V24
V25
V26
W1
D[34]#
VSS
Source Synch
Power/Other
Source Synch
Power/Other
Source Synch
T6
VCCP
VCCP
Power/Other
Power/Other
T21
Input/
Output
D[35]#
VSS
Input/
Output
T22
T23
T24
D[37]#
VSS
Source Synch
Power/Other
Source Synch
Input/
Output
W2
A[27]#
Input/
Output
D[27]#
Input/
Output
W3
W4
W5
A[32]#
VSS
Source Synch
Power/Other
Source Synch
Input/
Output
T25
T26
U1
D[30]#
VSS
Source Synch
Power/Other
Source Synch
Input/
Output
A[28]#
Input/
Output
A[23]#
Input/
Output
W6
A[20]#
VCCP
Source Synch
Power/Other
Source Synch
Power/Other
Input/
Output
U2
U3
U4
A[30]#
VSS
Source Synch
Power/Other
Source Synch
W21
W22
W23
Input/
Output
D[41]#
VSS
Input/
Output
A[21]#
78
Datasheet
Package Mechanical Specifications and Pin Information
Table 17.
Pin # Listing
Signal Buffer Directi
Pin # Pin Name
Type
on
Input/
Output
W24
D[43]#
Source Synch
Input/
Output
W25
W26
Y1
D[44]#
VSS
Source Synch
Power/Other
Power/Other
Input/
Output
COMP[3]
Input/
Output
Y2
Y3
Y4
A[17]#
VSS
Source Synch
Power/Other
Source Synch
Input/
Output
A[29]#
Input/
Output
Y5
A[22]#
Source Synch
Y6
VSS
VSS
Power/Other
Power/Other
Y21
Input/
Output
Y22
D[32]#
Source Synch
Input/
Output
Y23
Y24
Y25
D[42]#
VSS
Source Synch
Power/Other
Source Synch
Input/
Output
D[40]#
DSTBN[2]
#
Input/
Output
Y26
Source Synch
Datasheet
79
Package Mechanical Specifications and Pin Information
Figure 18.
Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Left Side
BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC
COMP[
2]
VSS
VSS
VSS
TMS
TDI
TDO
A[35]#
A[17]#
A[31]#
A[30]#
A[19]#
A[16]#
1
BPM[3]
#
COMP[
3]
VSS
VID[5]
VSS
PREQ#
TCK
A[22]#
A[20]#
VSS
A[34]#
A[28]#
VSS
A[32]#
A[27]#
VSS
A[21]#
A[18]#
VSS
A[23]#
A[26]#
VSS
A[11]#
A[12]#
VSS
2
VSS
VID[4]
VID[1]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
VSS
VSS
VID[6]
VSS
A[24]#
VSS
4
BPM[2]
#
ADSTB
[1]#
RSVD0
4
RSVD0
3
A[33]#
VSS
A[29]#
VCCP
VCCP
VCCP
VCCP
VSS
A[25]#
VCCP
VCCP
VCCP
VCCP
VSS
A[14]#
VCCP
VCCP
VCCP
VCCP
VSS
A[10]#
VCCP
VCCP
VCCP
VCCP
VSS
5
VSS
6
BPM[1]
#
VCCP
VCCP
VCCP
VCCP
VSS
VCCP
VCCP
VCCP
VCCP
VSS
VCCP
VCCP
VCCP
VCCP
VSS
7
BPM[0]
#
VID[0]
PSI#
VID[3]
VID[2]
VSS
TRST#
PRDY#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
9
TEST5
VSS
VSS
VCCP
VCCP
VCC
VSS
VCCP
VCCP
VCCP
VCC
VSS
VCCP
VCCP
VCCP
VCC
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
VSS
VCCP
VCCP
VSS
VCCS
ENSE
VSS
VSS
VSS
VSS
VSSSE
NSE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCP
VCC
VCC
VCC
VCC
VCCP
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
80
Datasheet
Package Mechanical Specifications and Pin Information
Figure 19.
Intel Core 2 Duo Mobile Processor in SFF Package Top View Upper Right Side
AB AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
REQ[2]
#
REQ[0]
#
A[7]#
A[5]#
LOCK#
TRDY#
DBSY#
VSS
VSS
1
RSVD0
2
RSVD0
1
A[15]#
A[8]#
VSS
A[9]#
A[3]#
BR0#
RS[0]#
HIT#
HITM#
VSS
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BPRI#
VCCP
VCCP
VCCP
VCCP
VSS
VSS
BNR#
DBR#
VSS
VSS
VSS
LINT1
A20M#
LINT0
VSS
3
ADSTB
[0]#
REQ[3]
#
RSVD0
6
A[4]#
VSS
A[6]#
VSS
VSS
VSS
VSS
VCCP
VCC
VCC
VCC
VCC
ADS#
VSS
VSS
VSS
VSS
VCCP
VCC
VCC
VCC
VCC
RS[2]#
VSS
RS[1]#
VSS
FERR#
VSS
VSS
VSS
4
REQ[4]
#
REQ[1]
#
DEFER
#
RESET
#
A[13]#
VCCP
VCCP
VCCP
VCCP
VSS
SMI#
VSS
VSS
VSS
VSS
VCCP
VSS
VSS
VSS
VSS
5
VSS
VSS
VSS
VSS
VCCP
VCC
VCC
VCC
VCC
VSS
VSS
VSS
6
DPRST
P#
PWRG
OOD
VCCP
VCCP
VCCP
VCCP
VSS
VCCP
VCCP
VCCP
VCCP
VSS
VCCP
VCCP
VCCP
VCCP
VSS
VCCP
VCCP
VCCP
VCCP
VSS
7
RSVD0
7
STPCL
K#
DPSLP
#
VSS
VSS
VSS
INIT#
SLP#
VCCP
VCCP
VCC
8
RSVD0
5
VSS
VCCP
VCCP
VSS
VSS
VCCP
VCCP
VSS
9
THER
MTRIP
IGNNE
#
VCCP
VCCP
VCCP
VCC
VCCP
VCCP
VCCP
VCC
VCC
VCC
VCC
VCCP
VCCP
VCCP
VCC
VCCP
VCCP
VCCP
VCC
VSS
VCCP
VCCP
VCC
VCC
VCC
VCC
10
11
12
13
14
15
16
17
18
19
20
21
22
VCCP
VCCP
VSS
VCCP
VCCP
VCC
VCC
VCC
VCC
VCCP
VCCP
VCC
VCC
VCC
VCC
VCCP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
Datasheet
81
Package Mechanical Specifications and Pin Information
Figure 20.
Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Left Side
BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC
VSS
VSS
VSS
VSS
VSS
VSS
D[58]#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D[52]#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
D[26]#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VCC
VCCP
VCCP
VSS
VCC
VCCP
VCCP
VSS
VCC
VCC
VCCP
VCCP
VSS
VCC
THRM
DC
THRM
DA
VSS
VSS
VSS
D[62]#
D[54]#
VSS
VCCP
VCCP
VSS
VCCP
VCCP
VSS
VCCP
VCCP
VSS
VSS
VSS
VSS
VSS
D[55]#
D[61]#
VSS
D[56]#
VSS
VCCP
VCCP
D[45]#
VSS
VSS
VCCP
VCCP
D[43]#
VSS
VSS
VCCP
VCCP
D[35]#
VSS
DINV[3
]#
VSS
VSS
DSTBP
[3]#
D[48]#
D[50]#
VSS
VSS
VSS
VSS
D[59]#
VSS
VSS
VSS
DSTBN
[3]#
D[57]#
VSS
D[42]#
VSS
D[34]#
VSS
DINV[2
]#
D[60]#
VSS
D[51]#
D[63]#
D[53]#
D[33]#
D[46]#
D[41]#
D[47]#
D[37]#
D[44]#
TEST4
D[27]#
TEST6
VSS
VSS
GTLRE
F
DSTBP
[2]#
COMP[
0]
D[36]#
DSTBN
[2]#
COMP[
1]
VSS
D[49]#
D[32]#
D[40]#
D[39]#
D[38]#
82
Datasheet
Package Mechanical Specifications and Pin Information
Figure 21.
Intel Core 2 Duo Mobile Processor in SFF Package Top View Lower Right Side
AB AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCCP
VCCA
VSS
VCCP
VCCA
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCP
VCCP
VSS
VCC
VCCP
VSS
VCCP
VCCP
TEST1
VSS
VCCP
VCCP
VSS
VSS
VSS
VSS
VCCP
VCCP
DRDY#
D[0]#
VSS
BCLK[
1]
BCLK[
0]
VCCP
VCCP
VSS
VCCP
VCCP
VSS
VCCP
VCCP
VSS
VCCP
VCCP
VSS
VCCP
VCCP
VSS
VCCP
VCCP
VSS
VCCP
VCCP
D[25]#
VSS
VSS
VCCP
VCCP
D[17]#
VSS
VSS
VCCP
VCCP
VSS
VCCP
VCCP
VCCP
VSS
BSEL[1
]
BSEL[0
]
PROC
HOT#
BSEL[2
]
VSS
VSS
VSS
D[6]#
D[13]#
D[1]#
VSS
VSS
VSS
DINV[0
]#
DSTBN
[0]#
D[29]#
VSS
D[11]#
VSS
D[12]#
VSS
D[4]#
VSS
TEST2
VSS
IERR#
VSS
DSTBP
[0]#
DPWR
#
D[24]#
D[28]#
D[21]#
D[23]#
D[20]#
D[10]#
D[22]#
D[8]#
D[15]#
D[7]#
D[2]#
VSS
VSS
DSTBP
[1]#
DSTBN
[1]#
DINV[1
]#
D[3]#
TEST3
D[19]#
D[30]#
D[18]#
D[31]#
D[16]#
D[14]#
D[9]#
D[5]#
VSS
VSS
Datasheet
83
Package Mechanical Specifications and Pin Information
Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name
Signal
Name
Ball
Number
Ball
Number
Signal
Name
Ball
Number
Signal Name
A[3]#
A[4]#
P2
V4
BCLK[0]
BCLK[1]
BNR#
AN5
A35
C35
J5
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
R41
W41
A[5]#
W1
N43
A[6]#
T4
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
BPRI#
U41
A[7]#
AA1
AB4
T2
AY8
BA7
BA5
AY2
L5
AA41
AB40
AD40
AC41
AA43
Y40
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADS#
AC5
AD2
AD4
AA5
AE5
AB2
AC1
AN1
AK4
AG1
AT4
AK2
AT2
AH2
AF4
AJ5
AH4
AM4
AP4
AR5
AJ1
AL1
AM2
AU5
AP2
AR1
C7
BR0#
BSEL[0]
BSEL[1]
BSEL[2]
COMP[0]
COMP[1]
COMP[2]
COMP[3]
D[0]#
M2
A37
C37
B38
AE43
AD44
AE1
AF2
F40
G43
E43
J43
Y44
T44
AP44
AR43
AH40
AF40
AJ43
AG41
AF44
AH44
AM44
AN43
AM40
AK40
AG43
AP40
AN41
AL41
AV38
AT44
AV40
AU41
AW41
AR41
BA37
BB38
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
H40
H44
G39
E41
L41
K44
N41
T40
M40
M44
L43
P44
V40
V44
AB44
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
D[16]#
D[17]#
D[18]#
D[19]#
ADSTB[0]#
ADSTB[1]#
M4
Y4
84
Datasheet
Package Mechanical Specifications and Pin Information
Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name
Signal
Name
Ball
Number
Ball
Number
Signal
Name
Ball
Number
Signal Name
D[56]#
D[57]#
AY36
AT40
BC35
BC39
BA41
BB40
BA35
AU43
J7
PRDY#
PREQ#
AV10
AV2
D38
BD10
E7
TMS
TRDY#
TRST#
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AW5
L1
D[58]#
PROCHOT#
PSI#
AV8
D[59]#
AA33
AB16
AB18
AB20
AB22
AB24
AB26
AB28
AB30
AB32
AC33
AD16
AD18
AD20
AD22
AD24
AD26
AD28
AD30
AD32
AE33
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AF30
AF32
AG33
AH16
AH18
AH20
D[60]#
PWRGOOD
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
RESET#
RS[0]#
RS[1]#
RS[2]#
RSVD01
RSVD02
RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
SLP#
D[61]#
R1
D[62]#
R5
D[63]#
U1
DBR#
P4
DBSY#
J1
W5
DEFER#
DINV[0]#
DINV[1]#
DINV[2]#
DINV[3]#
DPRSTP#
DPSLP#
DPWR#
N5
G5
P40
R43
AJ41
BC37
G7
K2
H4
K4
V2
Y2
B8
AG5
AL5
J9
C41
F38
K40
U43
AK44
AY40
J41
DRDY#
DSTBN[0]#
DSTBN[1]#
DSTBN[2]#
DSTBN[3]#
DSTBP[0]#
DSTBP[1]#
DSTBP[2]#
DSTBP[3]#
FERR#
F4
H8
D10
E5
SMI#
STPCLK#
TCK
F8
W43
AL43
AY38
D4
AV4
AW7
AU1
E37
D40
C43
AE41
AY10
AC43
B10
BB34
BD34
B10
TDI
TDO
TEST1
GTLREF
AW43
H2
TEST2
HIT#
TEST3
HITM#
F2
TEST4
IERR#
B40
F10
D8
TEST5
IGNNE#
INIT#
TEST6
THERMTRIP#
THRMDA
THRMDC
THERMTRIP#
LINT0
C9
LINT1
C5
LOCK#
N1
Datasheet
85
Package Mechanical Specifications and Pin Information
Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name
Signal
Name
Ball
Number
Ball
Number
Signal
Name
Ball
Number
Signal Name
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AH22
AH24
AH26
AH28
AH30
AH32
AJ33
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AP32
AR33
AT14
AT16
AT18
AT20
AT22
AT24
AT26
AT28
AT30
AT32
AT34
AU33
AV14
AV16
AV18
AV20
AV22
AV24
AV26
AV28
AV30
AV32
AY14
AY16
AY18
AY20
AY22
AY24
AY26
AY28
AY30
AY32
B16
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
B22
B24
B26
B28
B30
BB14
BB16
BB18
BB20
BB22
BB24
BB26
BB28
BB30
BB32
BD14
BD16
BD18
BD20
BD22
BD24
BD26
BD28
BD30
BD32
D16
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK30
AK32
AL33
AM14
AM16
AM18
AM20
AM22
AM24
AM26
AM28
AM30
AM32
AN33
AP14
AP16
AP18
AP20
AP22
AP24
AP26
AP28
AP30
D18
D20
D22
D24
D26
D28
D30
F16
F18
B18
F20
B20
F22
86
Datasheet
Package Mechanical Specifications and Pin Information
Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name
Signal
Name
Ball
Number
Ball
Number
Signal
Name
Ball
Number
Signal Name
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
F24
F26
F28
F30
F32
G33
H16
H18
H20
H22
H24
H26
H28
H30
H32
J33
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
P18
P20
P22
P24
P26
P28
P30
P32
R33
T16
T18
T20
T22
T24
T26
T28
T30
T32
U33
V16
V18
V20
V22
V24
V26
V28
V30
V32
W33
Y16
Y18
Y20
Y22
Y24
Y26
Y28
Y30
VCC
Y32
B34
VCCA
VCCA
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
D34
A13
A33
AA7
AA9
AA11
AA13
AA35
AA37
AB10
AB12
AB14
AB36
AB38
AC7
K16
K18
K20
K22
K24
K26
K28
K30
K32
L33
M16
M18
M20
M22
M24
M26
M28
M30
M32
N33
P16
AC9
AC11
AC13
AC35
AC37
AD14
AE7
AE9
AE11
AE13
AE35
AE37
AF10
AF12
AF14
AF36
AF38
AG7
AG9
AG11
Datasheet
87
Package Mechanical Specifications and Pin Information
Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name
Signal
Name
Ball
Number
Ball
Number
Signal
Name
Ball
Number
Signal Name
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
AG13
AG35
AG37
AH14
AJ7
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
B12
B14
B32
C13
C33
D12
D14
D32
E11
E13
E33
E35
F12
F14
F34
F36
G11
G13
G35
H12
H14
H36
J11
J13
J35
J37
K10
K12
K14
K36
K38
L7
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
M14
N7
N9
N11
N13
N35
N37
P10
P12
P14
P36
P38
R7
AJ9
AJ11
AJ13
AJ35
AJ37
AK10
AK12
AK14
AK36
AK38
AL7
R9
R11
R13
R35
R37
T14
U7
AL9
AL11
AL13
AL35
AL37
AN7
U9
U11
U13
U35
U37
V10
V12
V14
V36
V38
W7
AN9
AN11
AN13
AN35
AN37
AP10
AP12
AP36
AP38
AR7
W9
AR9
L9
W11
W13
W35
W37
Y14
AR11
AR13
AU11
AU13
L11
L13
L35
L37
88
Datasheet
Package Mechanical Specifications and Pin Information
Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name
Signal
Name
Ball
Number
Ball
Number
Signal
Name
Ball
Number
Signal Name
VCCSENSE
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VSS
BD12
BD8
BC7
BB10
BB8
BC5
BB4
AY4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB42
AC3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AG17
AG19
AG21
AG23
AG25
AG27
AG29
AG31
AG39
AH6
AC15
AC17
AC19
AC21
AC23
AC25
AC27
AC29
AC31
AC39
AD6
A5
VSS
A7
VSS
A9
AH8
VSS
A11
AH10
AH12
AH34
AH36
AH38
AH42
AJ3
VSS
A15
VSS
A17
AD8
VSS
A19
AD10
AD12
AD34
AD36
AD38
AD42
AE3
VSS
A21
VSS
A23
VSS
A25
VSS
A27
AJ15
AJ17
AJ19
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AJ39
AK6
VSS
A29
VSS
A31
VSS
A39
AE15
AE17
AE19
AE21
AE23
AE25
AE27
AE29
AE31
AE39
AF6
VSS
A41
VSS
AA3
AA15
AA17
AA19
AA21
AA23
AA25
AA27
AA29
AA31
AA39
AB6
AB8
AB34
VSS
VSS
VSS
VSS
VSS
VSS
AK8
VSS
AK34
AK42
AL3
VSS
VSS
AF8
VSS
AF34
AF42
AG3
AL15
AL17
AL19
AL21
VSS
VSS
VSS
AG15
Datasheet
89
Package Mechanical Specifications and Pin Information
Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name
Signal
Name
Ball
Number
Ball
Number
Signal
Name
Ball
Number
Signal Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL23
AL25
AL27
AL29
AL31
AL39
AM6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AR29
AR31
AR35
AR37
AR39
AT6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AW13
AW15
AW17
AW19
AW21
AW23
AW25
AW27
AW29
AW31
AW33
AW35
AW37
AW39
AY6
AT8
AM8
AT10
AT12
AT36
AT38
AT42
AU3
AM10
AM12
AM34
AM36
AM38
AM42
AN3
AU7
AU9
AN15
AN17
AN19
AN21
AN23
AN25
AN27
AN29
AN31
AN39
AP6
AU15
AU17
AU19
AU21
AU23
AU25
AU27
AU29
AU31
AU35
AU37
AU39
AV6
AY12
AY34
AY42
AY44
B4
B6
B36
B42
BA1
BA3
BA9
AP8
BA11
BA13
BA15
BA17
BA19
BA21
BA23
BA25
BA27
BA29
BA31
AP34
AP42
AR3
AV12
AV34
AV36
AV42
AV44
AW1
AW3
AW9
AW11
AR15
AR17
AR19
AR21
AR23
AR25
AR27
90
Datasheet
Package Mechanical Specifications and Pin Information
Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name
Signal
Name
Ball
Number
Ball
Number
Signal
Name
Ball
Number
Signal Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BA33
BA39
BA43
BB2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C31
C39
D2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H10
H34
H38
H42
J3
D6
BB6
D36
D42
D44
E1
BB12
BB36
BB42
BC3
J15
J17
J19
J21
J23
J25
J27
J29
J31
J39
K6
E3
BC9
E9
BC11
BC15
BC17
BC19
BC21
BC23
BC25
BC27
BC29
BC31
BC33
BC41
BD4
E15
E17
E19
E21
E23
E25
E27
E29
E31
E39
F6
K8
K34
K42
L3
L15
L17
L19
L21
L23
L25
L27
L29
L31
L39
M6
F42
F44
G1
BD6
BD36
BD38
BD40
C3
G3
G9
G15
G17
G19
G21
G23
G25
G27
G29
G31
G37
H6
C11
C15
C17
C19
M8
C21
M10
M12
M34
M36
M38
C23
C25
C27
C29
Datasheet
91
Package Mechanical Specifications and Pin Information
Table 18.Intel Core 2 Duo Mobile Processor in SFF Package Listing by Ball Name
Signal
Name
Ball
Number
Ball
Number
Signal
Name
Ball
Number
Signal Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M42
N3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSSENSE
U15
U17
U19
U21
U23
U25
U27
U29
U31
U39
V6
N15
N17
N19
N21
N23
N25
N27
N29
N31
N39
P6
V8
V34
V42
W3
P8
P34
P42
R3
W15
W17
W19
W21
W23
W25
W27
W29
W31
W39
Y6
R15
R17
R19
R21
R23
R25
R27
R29
R31
R39
T6
Y8
Y10
Y12
Y34
Y36
Y38
Y42
BC13
T8
T10
T12
T34
T36
T38
T42
U3
U5
92
Datasheet
Package Mechanical Specifications and Pin Information
4.3
Alphabetical Signals Reference
Table 19.
Signal Description (Sheet 1 of 8)
Name
Type
Description
36
A[35:3]# (Address) define a 2 -byte physical memory address
space. In sub-phase 1 of the address phase, these pins transmit the
address of a transaction. In sub-phase 2, these pins transmit
transaction type information. These signals must connect the
appropriate pins of both agents on the processor FSB. A[35:3]# are
source-synchronous signals and are latched into the receiving
buffers by ADSTB[1:0]#. Address signals are used as straps, which
are sampled before RESET# is deasserted.
Input/
Output
A[35:3]#
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address
wrap-around at the 1-MB boundary. Assertion of A20M# is only
supported in real mode.
A20M#
Input
A20M# is an asynchronous signal. However, to ensure recognition
of this signal following an input/output write instruction, it must be
valid along with the TRDY# assertion of the corresponding input/
output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# and REQ[4:0]# pins. All bus
agents observe the ADS# activation to begin parity checking,
protocol checking, address decode, internal snoop, or deferred
reply ID match operations associated with the new transaction.
Input/
Output
ADS#
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their
rising and falling edges. Strobes are associated with signals as
shown below.
Input/
Output
ADSTB[1:0]#
Signals
REQ[4:0]#, A[16:3]# ADSTB[0]#
A[35:17]# ADSTB[1]#
Associated Strobe
The differential pair BCLK (Bus Clock) determines the FSB
frequency. All FSB agents must receive these signals to drive their
outputs and latch their inputs.
BCLK[1:0]
BNR#
Input
All external timing parameters are specified with respect to the
rising edge of BCLK0 crossing V
.
CROSS
BNR# (Block Next Request) is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus
stall, the current bus owner cannot issue any new transactions.
Input/
Output
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor that indicate
the status of breakpoints and programmable counters used for
monitoring processor performance. BPM[3:0]# should connect the
appropriate pins of all processor FSB agents.This includes debug or
performance monitoring tools.
Output
BPM[2:1]#
BPM[3,0]#
Input/
Output
Datasheet
93
Package Mechanical Specifications and Pin Information
Table 19.
Signal Description (Sheet 2 of 8)
Name
Type
Description
BPRI# (Bus Priority Request) is used to arbitrate for ownership of
the FSB. It must connect the appropriate pins of both FSB agents.
Observing BPRI# active (as asserted by the priority agent) causes
the other agent to stop issuing new requests, unless such requests
are part of an ongoing locked operation. The priority agent keeps
BPRI# asserted until all of its requests are completed, then releases
the bus by deasserting BPRI#.
BPRI#
Input
BR0# is used by the processor to request the bus. The arbitration is
done between the processor (Symmetric Agent) and GMCH (High
Priority Agent).
Input/
Output
BR0#
BSEL[2:0] (Bus Select) are used to select the processor input clock
frequency. Table 3 defines the possible combinations of the signals
and the frequency associated with each combination. The required
frequency is determined by the processor, chipset and clock
synthesizer. All agents must operate at the same frequency.
BSEL[2:0]
COMP[3:0]
Output
Analog
COMP[3:0] must be terminated on the system board using
precision (1% tolerance) resistors.
D[63:0]# (Data) are the data signals. These signals provide a
64-bit data path between the FSB agents, and must connect the
appropriate pins on both agents. The data driver asserts DRDY# to
indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four
times in a common clock period. D[63:0]# are latched off the
falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of
16 data signals correspond to a pair of one DSTBP# and one
DSTBN#. The following table shows the grouping of data signals to
data strobes and DINV#.
Quad-Pumped Signal Groups
DSTBN#/
Input/
Output
D[63:0]#
Data Group
DINV#
DSTBP#
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
0
1
2
3
0
1
2
3
Furthermore, the DINV# pins determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DINV#
signal. When the DINV# signal is active, the corresponding data
group is inverted and therefore sampled active high.
DBR# (Data Bus Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by a
debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no
connect in the system. DBR# is not a processor signal.
DBR#
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the FSB to indicate that the data bus is in use. The
data bus is released after DBSY# is deasserted. This signal must
connect the appropriate pins on both FSB agents.
Input/
Output
DBSY#
94
Datasheet
Package Mechanical Specifications and Pin Information
Table 19.
Signal Description (Sheet 3 of 8)
Name
Type
Description
DEFER# is asserted by an agent to indicate that a transaction
cannot be ensured in-order completion. Assertion of DEFER# is
normally the responsibility of the addressed memory or input/
output agent. This signal must connect the appropriate pins of both
FSB agents.
DEFER#
Input
DINV[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals. The DINV[3:0]#
signals are activated when the data on the data bus is inverted. The
bus agent will invert the data bus signals if more than half the bits,
within the covered group, would change level in the next cycle.
DINV[3:0]# Assignment To Data Bus
Input/
Output
Bus Signal
Data Bus Signals
DINV[3:0]#
DINV[3]#
DINV[2]#
DINV[1]#
DINV[0]#
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
DPRSTP#, when asserted on the platform, causes the processor to
transition from the Deep Sleep State to the Deeper Sleep state or
Deep Power Down Technology (C6) state. To return to the Deep
Sleep State, DPRSTP# must be deasserted. DPRSTP# is driven by
the ICH9M.
DPRSTP#
Input
Input
DPSLP# when asserted on the platform causes the processor to
transition from the Sleep State to the Deep Sleep state. To return to
the Sleep State, DPSLP# must be deasserted. DPSLP# is driven by
the ICH9M.
DPSLP#
DPWR#
DRDY#
DPWR# is a control signal used by the chipset to reduce power on
the processor data bus input buffers. The processor drives this pin
during dynamic FSB frequency switching.
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be deasserted to insert idle clocks.
This signal must connect the appropriate pins of both FSB agents.
Input/
Output
Data strobe used to latch in D[63:0]#.
Signals
Associated Strobe
Input/
Output
D[15:0]#, DINV[0]#
D[31:16]#, DINV[1]#
D[47:32]#, DINV[2]#
D[63:48]#, DINV[3]#
DSTBN[0]#
DSTBN[1]#
DSTBN[2]#
DSTBN[3]#
DSTBN[3:0]#
Datasheet
95
Package Mechanical Specifications and Pin Information
Table 19.
Signal Description (Sheet 4 of 8)
Name
Type
Description
Data strobe used to latch in D[63:0]#.
Signals
Associated Strobe
Input/
Output
D[15:0]#, DINV[0]#
D[31:16]#, DINV[1]#
D[47:32]#, DINV[2]#
D[63:48]#, DINV[3]#
DSTBP[0]#
DSTBP[1]#
DSTBP[2]#
DSTBP[3]#
DSTBP[3:0]#
FERR# (Floating-point Error)/PBE# (Pending Break Event) is a
multiplexed signal and its meaning is qualified with STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating point
when the processor detects an unmasked floating-point error.
FERR# is similar to the ERROR# signal on the Intel® 387
coprocessor, and is included for compatibility with systems using
Microsoft MS-DOS*-type floating-point error reporting. When
STPCLK# is asserted, an assertion of FERR#/PBE# indicates that
the processor has a pending break event waiting for service. The
assertion of FERR#/PBE# indicates that the processor should be
returned to the Normal state. When FERR#/PBE# is asserted,
indicating a break event, it will remain asserted until STPCLK# is
deasserted. Assertion of PREQ# when STPCLK# is active will also
cause an FERR# break event.
FERR#/PBE#
Output
For additional information on the pending break event functionality,
including identification of support of the feature and enable/disable
information, refer to Volumes 3A and 3B of the Intel® 64 and IA-32
Architectures Software Developer's Manuals and the Intel®
Processor Identification and CPUID Instruction application note.
GTLREF determines the signal reference level for AGTL+ input pins.
GTLREF should be set at 2/3 VCCP. GTLREF is used by the AGTL+
receivers to determine if a signal is a logical 0 or logical 1.
GTLREF
Input
Input/
Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Either FSB agent may assert both HIT#
and HITM# together to indicate that it requires a snoop stall that
can be continued by reasserting HIT# and HITM# together.
HIT#
Input/
Output
HITM#
IERR# (Internal Error) is asserted by the processor as the result of
an internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the FSB. This transaction may optionally
be converted to an external error signal (e.g., NMI) by system core
logic. The processor will keep IERR# asserted until the assertion of
RESET#, BINIT#, or INIT#.
IERR#
Output
IGNNE# (Ignore Numeric Error) is asserted to force the processor
to ignore a numeric error and continue to execute non-control
floating-point instructions. If IGNNE# is deasserted, the processor
generates an exception on a non-control floating-point instruction if
a previous floating-point instruction caused an error. IGNNE# has
no effect when the NE bit in control register 0 (CR0) is set.
IGNNE#
Input
IGNNE# is an asynchronous signal. However, to ensure recognition
of this signal following an input/output write instruction, it must be
valid along with the TRDY# assertion of the corresponding input/
output Write bus transaction.
96
Datasheet
Package Mechanical Specifications and Pin Information
Table 19.
Signal Description (Sheet 5 of 8)
Name
Type
Description
INIT# (Initialization), when asserted, resets integer registers inside
the processor without affecting its internal caches or floating-point
registers. The processor then begins execution at the power-on
Reset vector configured during power-on configuration. The
processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal. However, to ensure
recognition of this signal following an input/output write instruction,
it must be valid along with the TRDY# assertion of the
INIT#
Input
corresponding input/output write bus transaction. INIT# must
connect the appropriate pins of both FSB agents.
If INIT# is sampled active on the active-to-inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST)
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins
of all APIC Bus agents. When the APIC is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1
becomes NMI, a nonmaskable interrupt. INTR and NMI are
backward-compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
LINT[1:0]
Input
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins of both
FSB agents. For a locked sequence of transactions, LOCK# is
asserted from the beginning of the first transaction to the end of
the last transaction.
Input/
Output
LOCK#
When the priority agent asserts BPRI# to arbitrate for ownership of
the FSB, it will wait until it observes LOCK# deasserted. This
enables symmetric agents to retain ownership of the FSB
throughout the bus locked operation and ensure the atomicity of
lock.
Probe Ready signal used by debug tools to determine processor
debug readiness.
PRDY#
PREQ#
Output
Input
Probe Request signal used by debug tools to request debug
operation of the processor.
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the
processor has reached its maximum safe operating temperature.
This indicates that the processor Thermal Control Circuit (TCC) has
been activated, if enabled. As an input, assertion of PROCHOT# by
the system will activate the TCC, if enabled. The TCC will remain
active until the system deasserts PROCHOT#.
Input/
Output
PROCHOT#
By default PROCHOT# is configured as an output. The processor
must be enabled via the BIOS for PROCHOT# to be configured as
bidirectional.
This signal may require voltage translation on the motherboard.
Processor Power Status Indicator signal. This signal is asserted
when the processor is both in the normal state (HFM to LFM) and in
lower power states (Deep Sleep and Deeper Sleep).
PSI#
Output
Datasheet
97
Package Mechanical Specifications and Pin Information
Table 19.
Signal Description (Sheet 6 of 8)
Name
Type
Description
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and
power supplies are stable and within their specifications. ‘Clean’
implies that the signal remains low (capable of sinking leakage
current), without glitches, from the time that the power supplies
are turned on until they come within specification. The signal must
then transition monotonically to a high state.
PWRGOOD
Input
The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It
should be driven high throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins
of both FSB agents. They are asserted by the current bus owner to
define the currently active transaction type. These signals are
source synchronous to ADSTB[0]#.
Input/
Output
REQ[4:0]#
RESET#
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at
least two milliseconds after V and BCLK have reached their
CC
proper specifications. On observing active RESET#, both FSB
agents will deassert their outputs within two clocks. All processor
straps must be valid within the specified setup time before RESET#
is deasserted.
Input
There is a 55 Ω (nominal) on die pull-up resistor on this signal.
RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
must connect the appropriate pins of both FSB agents.
RS[2:0]#
RSVD
Input
Reserved/ These pins are RESERVED and must be left unconnected on the
No
Connect
board. However, it is recommended that routing channels to these
pins on the board be kept open for possible future use.
SLP# (Sleep), when asserted in Stop-Grant state, causes the
processor to enter the Sleep state. During Sleep state, the
processor stops providing internal clock signals to all units, leaving
only the Phase-Locked Loop (PLL) still operating. Processors in this
state will not recognize snoops or interrupts. The processor will
recognize only assertion of the RESET# signal, deassertion of SLP#,
and removal of the BCLK input while in Sleep state. If SLP# is
deasserted, the processor exits Sleep state and returns to Stop-
Grant state, restarting its internal clock signals to the bus and
processor core units. If DPSLP# is asserted while in the Sleep state,
the processor will exit the Sleep state and transition to the Deep
Sleep state.
SLP#
Input
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt, the
processor saves the current state and enters System Management
Mode (SMM). An SMI Acknowledge transaction is issued and the
processor begins program execution from the SMM handler.
SMI#
Input
If an SMI# is asserted during the deassertion of RESET#, then the
processor will tristate its outputs.
98
Datasheet
Package Mechanical Specifications and Pin Information
Table 19.
Signal Description (Sheet 7 of 8)
Name
Type
Description
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is deasserted,
the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus
clock; STPCLK# is an asynchronous input.
STPCLK#
Input
TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TCK
TDI
Input
Input
TDI (Test Data In) transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor.
TDO provides the serial output needed for JTAG specification
support.
TDO
Output
TEST1,
TEST2,
TEST3,
TEST4,
TEST5,
TEST6
TEST7
Refer to the appropriate platform design guide for further TEST1,
TEST2, TEST3, TEST4, TEST5, TEST6 and TEST7 termination
requirements and implementation details.
Input
THRMDA
THRMDC
Other
Other
Thermal Diode Anode.
Thermal Diode Cathode.
The processor protects itself from catastrophic overheating by use
of an internal thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there are no false
trips. The processor will stop all execution when the junction
temperature exceeds approximately 125 °C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
THERMTRIP#
Output
TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
TMS
Input
Input
Input
TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both FSB agents.
TRDY#
TRST#
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
VCC
Input
Input
Input
Input
Processor core power supply.
Processor core ground node.
VSS
VCCA
VCCP
VCCA provides isolated power for the internal processor core PLLs
.
Processor I/O Power Supply.
Datasheet
99
Package Mechanical Specifications and Pin Information
Table 19.
Signal Description (Sheet 8 of 8)
Name
Type
Description
VCCSENSE together with VSSSENSE are voltage feedback signals
that control the 2.1 mΩ loadline at the processor die. It should be
used to sense voltage near the silicon with little noise.
VCCSENSE
Output
VID[6:0] (Voltage ID) pins are used to support automatic selection
of power supply voltages (V ). Unlike some previous generations
CC
of processors, these are CMOS signals that are driven by the
processor. The voltage supply for these pins must be valid before
the VR can supply V to the processor. Conversely, the VR output
CC
VID[6:0]
Output
Output
must be disabled until the voltage supply for the VID pins becomes
valid. The VID pins are needed to support the processor voltage
specification variations. See Table 2 for definitions of these pins.
The VR must supply the voltage that is requested by the pins, or
disable itself.
VSSSENSE together with VCCSENSE are voltage feedback signals
that control the 2.1-mΩ loadline at the processor die. It should be
used to sense ground near the silicon with little noise.
VSSSENSE
§
100
Datasheet
Thermal Specifications and Design Considerations
5
Thermal Specifications and
Design Considerations
A complete thermal solution includes both component and system-level thermal
management features. To allow for the optimal operation and long-term reliability of
Intel processor-based systems, the system/processor thermal solution should be
designed so the processor remains within the minimum and maximum junction
temperature (TJ) specifications at the corresponding thermal design power (TDP) value
listed in the tables below
Caution:
Operating the processor outside these operating limits may result in permanent
damage to the processor and potentially other components in the system.
Table 20.
Power Specifications for the Dual-Core Extreme Edition Processor
Processor
Number
Thermal Design
Power
Symbol
Core Frequency & Voltage
Unit Notes
44
29
20
3.06 GHz & V
1.6 GHz & V
CCHFM
1, 4,
5, 6
TDP
X9100
W
CCLFM
0.8 GHz & V
CCSLFM
Symbol
Parameter
Auto Halt, Stop Grant Power
Min Typ Max
Unit Notes
P
P
AH,
at V
at V
—
—
—
—
—
—
18.8
6.7
W
W
W
2, 5, 7
2, 5, 7
2, 5, 8
CCHFM
SGNT
CCSLFM
Sleep Power
P
P
at V
at V
17.8
6.4
SLP
CCHFM
CCSLFM
Deep Sleep Power
at V
at V
8.2
3.8
DSLP
CCHFM
CCSLFM
P
P
P
T
Deeper Sleep Power
—
—
—
0
—
—
—
—
1.9
1.7
1.3
105
W
W
W
°C
2, 8
2, 8
2, 8
3, 4
DPRSLP
Intel® Enhanced Deeper Sleep state Power
Intel® Deep Power Down Power
Junction Temperature
DC4
C6
J
NOTES:
1.
The TDP specification should be used to design the processor thermal solution. The TDP is
not the maximum theoretical power the processor can generate.
2.
Not 100% tested. These power specifications are determined by characterization of the
processor currents at higher temperatures and extrapolating the values for the
temperature indicated.
3.
4.
5.
As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal
Monitor’s automatic mode is used to indicate that the maximum T has been reached.
J
The Intel Thermal Monitor automatic mode must be enabled for the processor to operate
within specifications.
Processor TDP requirements in Intel Dynamic Acceleration Technology mode are lesser
than TDP in HFM.
o
6.
7.
8.
At Tj of 105 C
o
At Tj of 50 C
o
At Tj of 35 C
Datasheet
101
Thermal Specifications and Design Considerations
Table 21.
Power Specifications for the Dual-Core Standard Voltage Processor
Processor
Number
Thermal Design
Power
Symbol
Core Frequency & Voltage
Unit Notes
35
35
35
35
35
22
12
3.06 GHz & V
T9900
CCHFM
2.93 GHz & V
T9800
T9600
T9550
T9400
CCHFM
2.80 GHz & V
CCHFM
1, 4,
5, 6
2.66 GHz & V
TDP
W
CCHFM
2.53 GHz & V
CCHFM
1.6 GHz & V
0.8 GHz & V
CCLFM
CCSLFM
Symbol
Parameter
Auto Halt, Stop Grant Power
Min Typ Max
Unit Notes
P
P
AH,
at V
at V
—
—
—
—
—
—
13.9
5.0
W
W
W
2, 5, 7
2, 5, 7
2, 5, 8
CCHFM
SGNT
CCSLFM
Sleep Power
P
at V
at V
13.1
4.8
SLP
CCHFM
CCSLFM
Deep Sleep Power
P
at V
at V
5.5
2.2
DSLP
CCHFM
CCSLFM
P
P
P
T
Deeper Sleep Power
—
—
—
0
—
—
—
—
1.7
1.3
0.3
105
W
W
W
°C
2, 8
2, 8
2, 8
3, 4
DPRSLP
Intel® Enhanced Deeper Sleep state Power
Intel® Deep Power Down Power
Junction Temperature
DC4
C6
J
NOTES:
1.
The TDP specification should be used to design the processor thermal solution. The TDP is
not the maximum theoretical power the processor can generate.
2.
Not 100% tested. These power specifications are determined by characterization of the
processor currents at higher temperatures and extrapolating the values for the
temperature indicated.
3.
4.
5.
As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal
Monitor’s automatic mode is used to indicate that the maximum T has been reached.
J
The Intel Thermal Monitor automatic mode must be enabled for the processor to operate
within specifications.
Processor TDP requirements in Intel Dynamic Acceleration Technology mode are lesser
than TDP in HFM.
o
6.
7.
8.
At Tj of 105 C
o
At Tj of 50 C
o
At Tj of 35 C
102
Datasheet
Thermal Specifications and Design Considerations
Table 22.
Power Specifications for the Dual-Core Low Power Standard Voltage
Processors (25W) in Standard Package
Processor
Thermal Design
Power
Symbol
Core Frequency & Voltage
Unit Notes
Number
P9700
P9600
P8800
P9500
P8700
P8600
P8400
25
25
25
25
25
25
25
20
11
2.8 GHz & V
CCHFM
2.667 GHz & V
2.667 GHz & V
CCHFM
CCHFM
CCHFM
CCHFM
2.53 GHz & V
2.53 GHz & V
2.4 GHz & V
1, 4,
TDP
W
5, 6
CCHFM
2.267 GHz & V
CCHFM
CCLFM
CCSLFM
1.6 GHz & V
0.8 GHz & V
Symbol
Parameter
Auto Halt, Stop Grant Power
Min Typ Max
Unit Notes
P
P
AH,
—
—
—
—
—
—
8.1
3.7
W
W
W
2, 5, 7
2, 5, 7
2, 5, 8
at V
at V
CCHFM
SGNT
CCSLFM
Sleep Power
P
P
7.3
3.5
at V
SLP
CCHFM
at V
CCSLFM
Deep Sleep Power
2.9
2.1
at V
DSLP
CCHFM
at V
CCSLFM
P
P
P
T
Deeper Sleep Power
—
—
—
0
—
—
—
—
1.0
0.9
0.3
105
W
W
W
°C
2, 8
2, 8
2, 8
3, 4
DPRSLP
Intel® Enhanced Deeper Sleep State Power
Intel® Deep Power Down Power
Junction Temperature
DC4
C6
J
NOTES:
1.
The TDP specification should be used to design the processor thermal solution. The TDP is
not the maximum theoretical power the processor can generate.
2.
Not 100% tested. These power specifications are determined by characterization of the
processor currents at higher temperatures and extrapolating the values for the
temperature indicated.
3.
As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal
Monitor’s automatic mode is used to indicate that the maximum T has been reached.
J
Refer to Section 6.1 for more details.
4.
5.
The Intel Thermal Monitor automatic mode must be enabled for the processor to operate
within specifications.
Processor TDP requirements in Intel Dynamic Acceleration Technology mode are lesser
than TDP in HFM.
o
6.
7.
8.
At Tj of 105 C
o
At Tj of 50 C
o
At Tj of 35 C
Datasheet
103
Thermal Specifications and Design Considerations
Table 23.
Symbol
Power Specifications for the Dual-Core Power Optimized Performance (25 W)
SFF Processors
Processor
Number
Thermal Design
Power
Core Frequency & Voltage
Unit
Notes
SP9600
2.53 GHz & HFM V
25
25
25
20
11
CC
SP9400
SP9300
2.4 GHz & HFM V
CC
1, 4, 5,
6
TDP
2.26 GHz & HFM V
W
CC
1.6 GHz & Super LFM V
0.8 GHz & Super LFM V
CC
CC
Symbol
Parameter
Min
Typ
Max
Unit
Notes
Auto Halt, Stop Grant Power
P
P
AH,
at V
at V
—
—
8.3
3.3
W
2, 5, 7
CCHFM
SGNT
CCSLFM
Sleep Power
P
at V
at V
—
—
—
—
7.5
3.1
W
W
2, 5, 7
2, 5, 8
SLP
CCHFM
CCSLFM
Deep Sleep Power
P
at V
at V
2.9
1.8
DSLP
CCHFM
CCSLFM
P
P
P
T
Deeper Sleep Power
—
—
—
0
—
—
—
—
1.0
0.9
0.3
105
W
W
W
°C
2, 8
2, 8
2, 8
3, 4
DPRSLP
Intel® Enhanced Deeper Sleep State Power
Intel® Deep Power Down Power
Junction Temperature
DC4
C6
J
NOTES:
1.
2.
3.
4.
The TDP specification should be used to design the processor thermal solution. The TDP is not the
maximum theoretical power the processor can generate.
Not 100% tested. These power specifications are determined by characterization of the processor currents
at higher temperatures and extrapolating the values for the temperature indicated.
As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic
mode is used to indicate that the maximum T has been reached.
J
The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within
specifications.
5.
6.
7.
8.
Processor TDP requirements in Intel Dynamic Acceleration Technology mode are lesser than TDP in HFM.
At Tj of 105 C
o
At Tj of 50 °C
o
At Tj of 35 C
104
Datasheet
Thermal Specifications and Design Considerations
Table 24.
Symbol
Power Specifications fro the Dual-Core Low Voltage (LV) SFF Processors
Processor
Number
Thermal Design
Power
Core Frequency & Voltage
Unit
Notes
SL9600
17
17
2.13 GHz & HFM VCC
1.86 GHz & HFM VCC
1.6 GHz & HFM VCC
1.6 GHz & Super LFM VCC
0.8 GHz & Super LFM VCC
SL9400
SL9300
1, 4, 5,
6
TDP
17
W
16.7
10
Symbol
Parameter
Min
Typ Max
Unit
Notes
Auto Halt, Stop Grant Power
P
P
AH,
—
—
—
—
6.3
3.0
W
2, 5, 7
at V
at V
CCHFM
SGNT
CCSLFM
Sleep Power
P
—
—
5.7
2.8
W
W
2, 5, 7
2, 5, 8
at V
SLP
CCHFM
at V
CCSLFM
Deep Sleep Power
P
2.6
1.3
at V
DSLP
CCHFM
at V
CCSLFM
P
P
P
T
Deeper Sleep Power
—
—
—
0
—
—
—
—
0.9
0.8
0.3
105
W
W
W
°C
2, 8
2, 8
2, 8
3, 4
DPRSLP
Intel® Enhanced Deeper Sleep State Power
Intel® Deep Power Down Power
Junction Temperature
DC4
C6
J
NOTES:
1.
2.
3.
4.
The TDP specification should be used to design the processor thermal solution. The TDP is not the
maximum theoretical power the processor can generate.
Not 100% tested. These power specifications are determined by characterization of the processor currents
at higher temperatures and extrapolating the values for the temperature indicated.
As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic
mode is used to indicate that the maximum T has been reached.
J
The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within
specifications.
5.
6.
7.
8.
Processor TDP requirements in Intel Dynamic Acceleration Technology mode are lesser than TDP in HFM.
At Tj of 105 C
o
At Tj of 50 °C
o
At Tj of 35 C
Datasheet
105
Thermal Specifications and Design Considerations
Table 25.
Symbol
Power Specifications for the Dual-Core Ultra-Low-Voltage (ULV) Processors
Processor
Number
Thermal Design
Power
Core Frequency & Voltage
Unit
Notes
1.4 GHz & HFM V
10
10
10
10
8
SU9600
SU9400
SU9300
CC
CC
1.4 GHz & HFM V
1.2GHz & HFM V
1, 4, 5,
6
TDP
W
CC
1.2 GHz & Super LFM V
0.8 GHz & Super LFM V
CC
CC
Symbol
Parameter
Min
Typ
Max
Unit
Notes
Auto Halt, Stop Grant Power
P
P
AH,
at V
at V
—
—
2.9
1.6
W
2, 5, 7
CCHFM
SGNT
CCSLFM
Sleep Power
2.5
1.4
P
P
at V
at V
—
—
—
—
W
W
2, 5, 7
2, 5, 8
SLP
CCHFM
CCSLFM
Deep Sleep Power
at V
at V
1.3
0.9
DSLP
CCHFM
CCSLFM
P
P
P
T
Deeper Sleep Power
—
—
—
0
—
—
—
—
0.6
0.4
W
W
W
°C
2, 8
2, 8
2, 8
3, 4
DPRSLP
Intel® Enhanced Deeper Sleep state Power
Intel® Deep Power Down Power
Junction Temperature
DC4
C6
J
0.25
105
NOTES:
1.
2.
3.
4.
The TDP specification should be used to design the processor thermal solution. The TDP is not the
maximum theoretical power the processor can generate.
Not 100% tested. These power specifications are determined by characterization of the processor currents
at higher temperatures and extrapolating the values for the temperature indicated.
As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic
mode is used to indicate that the maximum T has been reached.
J
The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within
specifications.
5.
6.
7.
8.
Processor TDP requirements in Intel Dynamic Acceleration Technology mode are lesser than TDP in HFM.
At Tj of 105 C
o
At Tj of 50 °C
o
At Tj of 35 C
106
Datasheet
Thermal Specifications and Design Considerations
Table 26.
Symbol
Power Specifications for the Single-Core Ultra-Low-Voltage (5.5 W) SFF
Processors
Processor
Number
Thermal Design
Power
Core Frequency & Voltage
Unit
Notes
SU3500
SU3300
1.4 GHz & HFM V
5.5
5.5
5.5
5
CC
CC
1.2 GHz & HFM V
1, 4, 5,
6
TDP
W
1.2 GHz & Super LFM V
0.8 GHz & Super LFM V
CC
CC
Symbol
Parameter
Min
Typ
Max
Unit
Notes
Auto Halt, Stop Grant Power
P
P
AH,
at V
at V
—
—
2.1
1.4
W
2, 5, 7
CCHFM
SGNT
CCSLFM
Sleep Power
P
P
at V
at V
—
—
—
—
1.8
1.2
W
W
2, 5, 7
2, 5, 8
SLP
CCHFM
CCSLFM
Deep Sleep Power
at V
at V
0.7
0.6
DSLP
CCHFM
CCSLFM
P
P
P
T
Deeper Sleep Power
—
—
—
0
—
—
—
—
0.4
0.3
0.2
100
W
W
W
°C
2, 8
2, 8
2, 8
3, 4
DPRSLP
Intel® Enhanced Deeper Sleep state Power
Intel® Deep Power Down Power
Junction Temperature
DC4
C6
J
NOTES:
1.
2.
3.
4.
The TDP specification should be used to design the processor thermal solution. The TDP is not the
maximum theoretical power the processor can generate.
Not 100% tested. These power specifications are determined by characterization of the processor currents
at higher temperatures and extrapolating the values for the temperature indicated.
As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic
mode is used to indicate that the maximum T has been reached.
J
The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within
specifications.
5.
6.
7.
8.
Processor TDP requirements in Intel Dynamic Acceleration Technology mode are lesser than TDP in HFM.
At Tj of 100 C
At Tj of 50 °C
At Tj of 35 °C
o
Datasheet
107
Thermal Specifications and Design Considerations
5.1
Monitoring Die Temperature
The processor incorporates three methods of monitoring die temperature:
• Thermal Diode
• Intel® Thermal Monitor
• Digital Thermal Sensor
5.1.1
Thermal Diode
Intel’s processors utilize an SMBus thermal sensor to read back the voltage/current
characteristics of a substrate PNP transistor. Since these characteristics are a function
of temperature, these parameters can be used to calculate silicon temperature values.
For older silicon process technologies, it is possible to simplify the voltage/current and
temperature relationships by treating the substrate transistor as though it were a
simple diffusion diode. In this case, the assumption is that the beta of the transistor
does not impact the calculated temperature values. The resultant “diode” model
essentially predicts a quasi linear relationship between the base/emitter voltage
differential of the PNP transistor and the applied temperature (one of the
proportionality constants in this relationship is processor specific, and is known as the
diode ideality factor). Realization of this relationship is accomplished with the SMBus
thermal sensor that is connected to the transistor.
The processor, however, is built on Intel’s advanced 45-nm processor technology. Due
to this new processor technology, it is no longer possible to model the substrate
transistor as a simple diode. To accurately calculate silicon temperature use a full bi-
polar junction transistor-type model. In this model, the voltage/current and
temperature characteristics include an additional process dependant parameter which
is known as the transistor “beta”. System designers should be aware that the current
thermal sensors may not be configured to account for “beta” and should work with their
SMB thermal sensor vendors to ensure they have a part capable of reading the thermal
diode in BJT model.
Offset between the thermal diode-based temperature reading and the Intel Thermal
Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic
mode activation of the thermal control circuit. This temperature offset must be
considered when using the processor thermal diode to implement power management
events. This offset is different than the diode Toffset value programmed into the
processor Model-Specific Register (MSR).
Table 27 and Table 28 provide the diode interface and transistor model specifications.
Table 27.
Thermal Diode Interface
Signal Name
Pin/Ball Number
Signal Description
THERMDA
THERMDC
A24
A25
Thermal diode anode
Thermal diode cathode
108
Datasheet
Thermal Specifications and Design Considerations
Table 28.
Thermal Diode Parameters Using Transistor Model
Symbol
Parameter
Min
Typ
Max
Unit
Notes
I
Forward Bias Current
Emitter Current
5
5
—
—
200
200
μA
μA
1
1
FW
E
I
n
Transistor Ideality
0.997
0.1
3.0
1.001
0.4
1.008
0.5
2, 3, 4
2, 3
2
Q
Beta
R
Series Resistance
4.5
7.0
Ω
T
NOTES:
1.
2.
3.
4.
Intel does not support or recommend operation of the thermal diode under reverse bias.
Characterized across a temperature range of 50-105°C.
Not 100% tested. Specified by design characterization.
The ideality factor, nQ, represents the deviation from ideal transistor model behavior as
exemplified by the equation for the collector current:
qV /n kT
I
= I * (e BE
Q
–1)
C
S
where I = saturation current, q = electronic charge, V = voltage across the transistor
S
BE
base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute
temperature (Kelvin).
5.1.2
Intel® Thermal Monitor
The Intel Thermal Monitor helps control the processor temperature by activating the
TCC (Thermal Control Circuit) when the processor silicon reaches its maximum
operating temperature. The temperature at which the Intel Thermal Monitor activates
the TCC is not user configurable. Bus traffic is snooped in the normal manner and
interrupt requests are latched (and serviced during the time that the clocks are on)
while the TCC is active.
With a properly designed and characterized thermal solution, the TCC would only be
activated for very short periods of time when running the most power-intensive
applications. The processor performance impact due to these brief periods of TCC
activation is expected to be minor and hence not detectable. An under-designed
thermal solution that is not able to prevent excessive activation of the TCC in the
anticipated ambient environment may cause a noticeable performance loss and may
affect the long-term reliability of the processor. In addition, a thermal solution that is
significantly under designed may not be capable of cooling the processor even when
the TCC is active continuously.
The Intel Thermal Monitor controls the processor temperature by modulating (starting
and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep
Technology transition when the processor silicon reaches its maximum operating
temperature. The Intel Thermal Monitor uses two modes to activate the TCC: automatic
mode and on-demand mode. If both modes are activated, automatic mode takes
precedence.
There are two automatic modes called Intel Thermal Monitor 1 (TM1) and Intel Thermal
Monitor 2 (TM2). These modes are selected by writing values to the MSRs of the
processor. After automatic mode is enabled, the TCC will activate only when the
internal die temperature reaches the maximum allowed value for operation.
When TM1 is enabled and a high temperature situation exists, the clocks will be
modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times
are processor speed-dependent and will decrease linearly as processor core frequencies
increase. Once the temperature has returned to a non-critical level, modulation ceases
and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid
Datasheet
109
Thermal Specifications and Design Considerations
active/inactive transitions of the TCC when the processor temperature is near the trip
point. The duty cycle is factory configured and cannot be modified. Also, automatic
mode does not require any additional hardware, software drivers, or interrupt handling
routines. Processor performance will be decreased by the same amount as the duty
cycle when the TCC is active.
When TM2 is enabled and a high temperature situation exists, the processor will
perform an Enhanced Intel SpeedStep Technology transition to the LFM. When the
processor temperature drops below the critical level, the processor will make an
Enhanced Intel SpeedStep Technology transition to the last requested operating point.
The processor also supports Enhanced Multi-Threaded Thermal Monitoring (EMTTM).
EMTTM is a processor feature that enhances TM2 with a processor throttling algorithm
known as Adaptive TM2. Adaptive TM2 transitions to intermediate operating points,
rather than directly to the LFM, once the processor has reached its thermal limit and
subsequently searches for the highest possible operating point. Please ensure this
feature is enabled and supported in the BIOS. Also with EMTTM enabled, the operating
system can request the processor to throttling to any point between Intel
Dynamic Acceleration Technology frequency and SuperLFM frequency as long
as these features are enabled in the BIOS and supported by the processor.
The Intel Thermal Monitor automatic mode and Enhanced Multi-Threaded
Thermal Monitoring must be enabled through BIOS for the processor to be
operating within specifications. Intel recommends TM1 and TM2 be enabled on the
processors.
TM1, TM2 and EMTTM features are collectively referred to as Adaptive Thermal
Monitoring features.
TM1 and TM2 can co-exist within the processor. If both TM1 and TM2 bits are enabled in
the auto-throttle MSR, TM2 takes precedence over TM1. However, if Force TM1 over
TM2 is enabled in MSRs via BIOS and TM2 is not sufficient to cool the processor below
the maximum operating temperature, then TM1 will also activate to help cool down the
processor.
If a processor load-based Enhanced Intel SpeedStep Technology transition (through
MSR write) is initiated when a TM2 period is active, there are two possible results:
1. If the processor load-based Enhanced Intel SpeedStep Technology transition target
frequency is higher than the TM2 transition-based target frequency, the processor
load-based transition will be deferred until the TM2 event has been completed.
2. If the processor load-based Enhanced Intel SpeedStep Technology transition target
frequency is lower than the TM2 transition-based target frequency, the processor
will transition to the processor load-based Enhanced Intel SpeedStep Technology
target frequency point.
The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal
Monitor control register is written to a 1, the TCC will be activated immediately
independent of the processor temperature. When using on-demand mode to activate
the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the
same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is
fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be
programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments.
On-demand mode may be used at the same time automatic mode is enabled, however,
if the system tries to enable the TCC via on-demand mode at the same time automatic
mode is enabled and a high temperature condition exists, automatic mode will take
precedence.
An external signal, PROCHOT# (processor hot) is asserted when the processor detects
that its temperature is above the thermal trip point. Bus snooping and interrupt
latching are also active while the TCC is active.
110
Datasheet
Thermal Specifications and Design Considerations
Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also
includes one ACPI register, one performance counter register, three MSR, and one I/O
pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal
Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt
upon the assertion or deassertion of PROCHOT#.
PROCHOT# will not be asserted when the processor is in the Stop Grant,
Sleep, Deep Sleep, and Deeper Sleep low-power states, hence the thermal
diode reading must be used as a safeguard to maintain the processor junction
temperature within maximum specification. If the platform thermal solution is not
able to maintain the processor junction temperature within the maximum specification,
the system must initiate an orderly shutdown to prevent damage. If the processor
enters one of the above low-power states with PROCHOT# already asserted,
PROCHOT# will remain asserted until the processor exits the low-power state and the
processor junction temperature drops below the thermal trip point. However,
PROCHOT# will de-assert for the duration of Deep Power Down Technology state (C6)
residency.
If Thermal Monitor automatic mode is disabled, the processor will be operating out of
specification. Regardless of enabling the automatic or on-demand modes, in the event
of a catastrophic cooling failure, the processor will automatically shut down when the
silicon has reached a temperature of approximately 125 °C. At this point the
THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor
activity and does not generate any bus cycles. When THERMTRIP# is asserted, the
processor core voltage must be shut down within the time specified in Chapter 3.
In all cases the Intel Thermal Monitor feature must be enabled for the processor to
remain within specification.
5.1.3
Digital Thermal Sensor
The processor also contains an on-die Digital Thermal Sensor (DTS) that can be read
via an MSR (no I/O interface). Each core of the processor will have a unique digital
thermal sensor whose temperature is accessible via the processor MSRs. The DTS is the
preferred method of reading the processor die temperature since it can be located
much closer to the hottest portions of the die and can thus more accurately track the
die temperature and potential activation of processor core clock modulation via the
Thermal Monitor. The DTS is only valid while the processor is in the normal operating
state (the Normal package level low-power state).
Unlike traditional thermal devices, the DTS outputs a temperature relative to the
maximum supported operating temperature of the processor (TJ,max). It is the
responsibility of software to convert the relative temperature to an absolute
temperature. The temperature returned by the DTS will always be at or below TJ,max
.
Catastrophic temperature conditions are detectable via an Out Of Specification status
bit. This bit is also part of the DTS MSR. When this bit is set, the processor is operating
out of specification and immediate shutdown of the system should occur. The processor
operation and code execution is not ensured once the activation of the Out of
Specification status bit is set.
The DTS-relative temperature readout corresponds to the Thermal Monitor (TM1/TM2)
trigger point. When the DTS indicates maximum processor core temperature has been
reached, the TM1 or TM2 hardware thermal control mechanism will activate. The DTS
and TM1/TM2 temperature may not correspond to the thermal diode reading since the
thermal diode is located in a separate portion of the die and thermal gradient between
the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode
can vary substantially due to changes in processor power, mechanical and thermal
attach, and software application. The system designer is required to use the DTS to
ensure proper operation of the processor within its temperature operating
specifications.
Datasheet
111
Thermal Specifications and Design Considerations
Changes to the temperature can be detected via two programmable thresholds located
in the processor MSRs. These thresholds have the capability of generating interrupts
via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures Software
Developer's Manuals for specific register and programming details.
5.2
5.3
Out of Specification Detection
Overheat detection is performed by monitoring the processor temperature and
temperature gradient. This feature is intended for graceful shutdown before the
THERMTRIP# is activated. If the processor’s TM1 or TM2 are triggered and the
temperature remains high, an Out Of Spec status and sticky bit are latched in the
status MSR register and generates a thermal interrupt.
PROCHOT# Signal Pin
An external signal, PROCHOT# (processor hot), is asserted when the processor die
temperature has reached its maximum operating temperature. If TM1 or TM2 is
enabled, then the TCC will be active when PROCHOT# is asserted. The processor can
be configured to generate an interrupt upon the assertion or deassertion of
PROCHOT#. Refer to the an interrupt upon the assertion or deassertion of PROCHOT#.
Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for
specific register and programming details.
The processor implements a bi-directional PROCHOT# capability to allow system
designs to protect various components from overheating situations. The PROCHOT#
signal is bi-directional in that it can either signal when the processor has reached its
maximum operating temperature or be driven from an external source to activate the
TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal
protection of system components.
Only a single PROCHOT# pin exists at a package level of the processor. When either
core's thermal sensor trips, PROCHOT# signal will be driven by the processor package.
If only TM1 is enabled, PROCHOT# will be asserted regardless of which core is above its
TCC temperature trip point, and both cores will have their core clocks modulated. If
TM2 is enabled then, regardless of which core(s) are above the TCC temperature trip
point, both cores will enter the lowest programmed TM2 performance state. It is
important to note that Intel recommends both TM1 and TM2 to be enabled.
When PROCHOT# is driven by an external agent, if only TM1 is enabled on both cores,
then both processor cores will have their core clocks modulated. If TM2 is enabled on
both cores, then both processor cores will enter the lowest programmed TM2
performance state. It should be noted that Force TM1 on TM2, enabled via BIOS, does
not have any effect on external PROCHOT#. If PROCHOT# is driven by an external
agent when TM1, TM2, and Force TM1 on TM2 are all enabled, then the processor will
still apply only TM2.
PROCHOT# may be used for thermal protection of voltage regulators (VR). System
designers can create a circuit to monitor the VR temperature and activate the TCC
when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low)
and activating the TCC, the VR will cool down as a result of reduced processor power
consumption. Bi-directional PROCHOT# can allow VR thermal designs to target
maximum sustained current instead of maximum current. Systems should still provide
proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case
of system cooling failure. The system thermal design should allow the power delivery
circuitry to operate within its temperature specification even while the processor is
operating at its TDP. With a properly designed and characterized thermal solution, it is
anticipated that bi-directional PROCHOT# would only be asserted for very short periods
112
Datasheet
Thermal Specifications and Design Considerations
of time when running the most power-intensive applications. An under-designed
thermal solution that is not able to prevent excessive assertion of PROCHOT# in the
anticipated ambient environment may cause a noticeable performance loss.
§
Datasheet
113
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