AAT1160 [ANALOGICTECH]
12V, 3A Step-Down DC/DC Converter; 12V ， 3A降压型DC / DC转换器
| 型号： | AAT1160 |
| 厂家： | 
ADVANCED ANALOGIC TECHNOLOGIES |
| 描述： | 12V, 3A Step-Down DC/DC Converter |
| 文件： | 总17页 (文件大小：656K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
General Description
Features
The AAT1160 is an 800kHz high efficiency step-down
DC/DC converter. With a wide input voltage range of
4.0V to 13.2V, the AAT1160 is an ideal choice for dual-
cell Lithium-ion battery-powered devices and mid-pow-
er-range regulated 12V-powered industrial applications.
The internal power switches are capable of delivering up
to 3A to the load.
• Input Voltage Range: 4.0V to 13.2V
• Up to 3A Load Current
• Fixed or Adjustable Output:
Output Voltage: 0.6V to VIN
▪
• Low 150μA No-Load Operating Current
• Less than 1μA Shutdown Current
• Up to 96% Efficiency
• Integrated Power Switches
• 800kHz Switching Frequency
The AAT1160 is a highly integrated device, simplifying
system-level design. Minimum external components are
required for the converter.
Synchronizable to External Clock
Forced PWM or Light Load Mode
• Soft Start Function
▪
▪
The AAT1160 optimizes efficiency throughout the entire
load range. It operates in a combination PWM/Light Load
mode for improved light-load efficiency. It can also
operate in a forced Pulse Width Modulation (PWM) mode
for easy control of the switching noise as well as faster
transient response. The high switching frequency allows
the use of small external components. The low current
shutdown feature disconnects the load from VIN and
drops shutdown current to less than 1μA.
• Short-Circuit and Over-Temperature Protection
• Minimum External Components
• TDFN34-16 Package
• Temperature Range: -40°C to +85°C
Applications
• Distributed Power Systems
• Industrial Applications
• Laptop Computers
• Portable DVD Players
• Portable Media Players
• Set-Top Boxes
The AAT1160 is available in a Pb-free, space-saving,
thermally-enhanced 16-pin TDFN34 package and is rated
over an operating temperature range of -40°C to
+85°C.
• TFT LCD Monitors and HDTVs
Typical Application
Output:
L
0.94 x Input max
Input:
4.0V ~ 13.2V
IN
LX
FB
2.2 to 3.8μH
C6
22μF
EN
R4
10
R3
C2
0.1μF
432k
DGND
AIN
C3, C4
2x22μF
AAT1160
C8
1μF
R6
59k
SYNC
PGND
AGND
COMP
LDO
R5
50k
C7
150pF
C9
1μF
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1160.2007.11.1.1
1
PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
Pin Descriptions
Pin #
Symbol Function
Power switching node. LX is the drain of the internal P-channel switch and N-channel synchronous recti-
fier. Connect the output inductor to the two LX pins and to EP2. A large exposed copper pad under the
package should be used for EP2.
1, 2, EP2
3, 12
LX
N/C
IN
Not connected.
Power source input. Connect IN to the input power source. Bypass IN to DGND with a 10μF or greater
capacitor. Connect both IN pins together as close to the IC as possible. An additional 100nF ceramic ca-
pacitor should also be connected between the two IN pins and DGND, pin 6
4, 5
Exposed Pad 1 Digital Ground, DGND. The exposed thermal pad (EP1) should be connected to board
ground plane and pins 6 and 13. The ground plane should include a large exposed copper pad under the
package for thermal dissipation (see package outline).
Internal analog bias input. AIN supplies internal power to the AAT1160. Connect AIN to the input source
voltage and bypass to AGND with a 0.1μF or greater capacitor. For additional noise rejection, connect to
the input power source through a 10Ω or lower value resistor.
Internal LDO bypass node. The output voltage of the internal LDO is bypassed at LDO. The internal cir-
cuitry of the AAT1160 is powered from LDO. Do not draw external power from LDO. Bypass LDO to AGND
with a 1μF or greater capacitor.
Output voltage feedback input. FB senses the output voltage for regulation control. For fixed output
versions, connect FB to the output voltage. For adjustable versions, drive FB from the output voltage
through a resistive voltage divider. The FB regulation threshold is 0.6V.
6, 13, EP1
DGND
AIN
7
8
9
LDO
FB
10
11
COMP
AGND
Control compensation node. Connect a series RC network from COMP to AGND, R = 50k and C = 150pF.
Analog signal ground. Connect AGND to PGND at a single point as close to the IC as possible.
Frequency select and synchronization input. Drive SYNC with a 500kHz to 1.6MHz signal to synchronize
the AAT1160 switching frequency to that signal. The Sync pin is also a mode select input. Drive SYNC
high or connect to the LDO pin for low-noise forced PWM mode. Drive SYNC low for high-efficiency PWM/
Light Load mode.
14
SYNC
Active high enable input. Drive EN high to turn on the AAT1160; drive it low to turn it off. For automatic
startup, connect EN to IN through a 4.7kΩ resistor. EN must be biased high, biased low, or driven to a
logic level by an external source. Do not let the EN pin float when the device is powered.
15
16
EN
PGND
Power ground. Connect AGND to PGND at a single point as close to the IC as possible.
Pin Configuration
TDFN34-16
(Top View)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PGND
EN
LX
LX
EP2
EP1
N/C
IN
SYNC
DGND
N/C
IN
AGND
DGND
AIN
LDO
COMP
FB
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1160.2007.11.1.1
PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
Absolute Maximum Ratings1
Symbol
Description
Value
Units
VIN, VAIN
VLX
VFB
VEN
VSYNC
TJ
Input Voltage
LX to GND Voltage
FB to GND Voltage
EN to GND Voltage
SYNC to GND Voltage
Operating Junction Temperature Range
-0.3 to 14
-0.3 to VIN + 0.3
-0.3 to VIN + 0.3
-0.3 to VIN + 0.3
-0.3 to 6.5
V
V
V
V
V
-40 to 150
°C
Thermal Information2
Symbol
Description
Maximum Power Dissipation3
Thermal Resistance
Value
Units
PD
θJA
2.7
37
W
°C/W
1. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions
specified is not implied. Only one Absolute Maximum Rating should be applied at any one time.
2. Mounted on an FR4 board.
3. Derate 2.7mW/°C above 25°C.
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1160.2007.11.1.1
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PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
Electrical Characteristics1
4.0V < VIN < 13.2V. CIN = COUT = 22μF; L = 2.2μH or 3.8μH, TA = -40°C to +85°C, unless otherwise noted. Typical
values are at TA = 25°C.
Symbol Description
Conditions
Min
Typ
Max
Units
VIN
Input Voltage Range
4.0
13.2
4.0
V
Rising
VUVLO
Input Under-Voltage Lockout
V
Hysteresis
No Load
VEN = GND
0.3
150
IQ
ISHDN
Supply Current
Shutdown Current
300
1
μA
μA
0.94
VIN
2.5
VOUT
Output Voltage Range
Output Voltage Accuracy
Line Regulation
0.6
V
%
VOUT
ΔVLINEREG
ΔVIN
IOUT = 0A to 3A
-2.5
/
VIN = 4.5V to 13.2V
0.023 0.100
0.4
%/V
%
ΔVLOADREG
Load Regulation
Feedback Reference Voltage (adjustable
version)
VIN = 12V, VOUT = 5V, IOUT = 0A to 3A
No Load, TA = 25°C
VFB
0.59
0.60
0.61
0.2
V
Adjustable Version
VOUT = 1.2V
IFBLEAK
FB Leakage Current
μA
Fixed Version
2
FOSC
FSYNC
TS
PWM Oscillator Frequency
External Clock Frequency Range
Start-Up Time
0.6
0.5
0.8
1
1.6
MHz
MHz
ms
kHz
%
CMOS Logic Clock Signal on SYNC Pin
IOUT = 3A, VOUT = 5V
2
200
Foldback Frequency
DC
TON
TSS
Maximum Duty Cycle
Minimum Turn-On Time
Soft-Start Time
94
100
2
ns
ms
VIN = 12V
VIN = 6V
VIN = 12V
VIN = 6V
0.12
0.15
0.06
0.08
90
RDS(ON)H
RDS(ON)L
P-Channel On Resistance
N-Channel On Resistance
Ω
Ω
η
ILIM
ILXLEAK
TSD
THYS
VILEN
VIHEN
VILSYNC
VIHSYNC
IEN
Efficiency
PMOS Current Limit
LX Leakage Current
Over-Temperature Shutdown Threshold
Over-Temperature Shutdown Hysteresis
EN Logic Low Input Threshold
EN Logic High Input Threshold
SYNC Logic Low Input Threshold
SYNC Logic High Input Threshold
EN Input Current
VIN = 12V, VOUT = 5V, IOUT = 3A
%
A
μA
°C
°C
V
V
V
V
μA
4.0
1.4
6.0
VIN = 13.2V, VLX = 0 to VIN
1
140
25
0.4
0.4
1.0
1.62
-1.0
VEN = 0V, VEN = 13.2V
1. The AAT1160 is guaranteed to meet performance specifications over the -40°C to +85°C operating temperature range and is assured by design, characterization, and correla-
tion with statistical process controls.
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1160.2007.11.1.1
PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
Typical Characteristics
Efficiency vs. Load Current
(VOUT = 5V)
Load Regulation
(VOUT = 5V)
100
90
0.5
0.4
6V
0.3
80
70
0.2
8.4V
60
0.1
13.2V
50
0
8.4V
10V
40
30
20
10
0
-0.1
12V
-0.2
10V
12V
6V
-0.3
-0.4
13.2V
-0.5
0.0001
0.001
0.01
0.1
1
10
0.0001
0.001
0.01
0.1
1
10
Output Current (A)
Output Current (A)
Efficiency vs. Load Current
(VOUT = 5V; PWM Mode)
Load Regulation
(VOUT = 5V; PWM Mode)
0.5
0.4
0.3
100
90
80
70
60
50
40
30
20
10
0
13.2V
6V
0.2 10V 12V
8.4V
0.1
0
8.4V
-0.1
-0.2
-0.3
-0.4
-0.5
12V
6V
13.2V
10V
0.0001
0.001
0.01
0.1
1
10
0.0001
0.001
0.01
0.1
1
10
Output Current (A)
Output Current (A)
Efficiency vs. Load Current
(VOUT = 3.3V)
Load Regulation
(VOUT = 3.3V)
0.6
100
90
80
70
60
50
40
30
20
10
0
8.4V
0.4
0.2
12V
5V
10V
0.0
13.2V
-0.2
-0.4
-0.6
5V
13.2V
10V
8.4V
1
10
100
1000
10000
0.0001
0.001
0.01
0.1
1
10
Output Current (A)
Output Current (mA)
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PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
Typical Characteristics
Efficiency vs. Load Current
(VOUT = 3.3V; PWM Mode)
Load Regulation
(VOUT = 3.3V; PWM Mode)
0.6
0.4
100
8.4V
90
80
70
60
50
40
30
20
10
0
5V
0.2
5V
13.2V
0.0
13.2V
12V
10V
-0.2
8.4V
10V
12V
-0.4
-0.6
1
10
100
1000
10000
1
10
100
1000
10000
Output Current (A)
Output Current (mA)
Line Regulation
(VOUT = 5V)
Line Regulation
(VOUT = 3.3V)
0.5
0.3
0.05
0.04
0.03
0.02
0.01
0
3A
10mA
100mA
0.1
1mA
1.5A
100mA
1mA
-0.1
-0.3
-0.5
-0.01
-0.02
-0.03
-0.04
1.5A
10mA
3A
6
7
8
9
10
11
12
5
6
7
8
9
10
11
12
Input Voltage (V)
Input Voltage (V)
Switching Current vs. Input Voltage
(VOUT = 5V)
Switching Current vs. Temperature
170
160
150
140
130
120
110
170
160
150
140
130
120
85°C
85°C
25°C
-40°C
-40°C
110
-40
-15
10
35
60
85
6
7
8
9
10
11
12
Input Voltage (V)
Temperature (°C)
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1160.2007.11.1.1
PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
Typical Characteristics
N-Channel RDS(ON) vs. Temperature
P-Channel RDS(ON) vs. Temperature
(VIN = 6V)
120
100
200
180
160
140
6V
6V
80
120
60
100
80 12V
40
12V
60
40
20
0
20
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
Switching Frequency vs. Temperature
Line Transient
(VOUT = 5.0V; CFF = 100pF; VIN = 7.6V to 11V;
IOUT = 3A; CIN = 10µF; COUT = 22µF; L = 3.8µH)
810
805
800
795
790
785
780
775
770
12
11
10
9
5.30
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
6V
8
12V
7
6
5
4
-40
-15
10
35
60
85
Temperature (°C)
Time (100µs/div)
Start-Up Time
(VOUT = 5.0V; CFF = 100pF; RLOAD = 1.67Ω;
CIN = 10µF; COUT = 22µF; L = 3.8µH)
Load Transient
(VOUT = 5.0V; CFF = 100pF; IOUT = 1A to 3A;
CIN = 10µF; COUT = 22µF; L = 3.8µH)
6
5
4
3
2
1
0
6
5
4
3
2
1
0
5.5
5
9
8
7
6
5
4
3
2
1
VEN
4.5
4
VOUT
ILOAD
3.5
3
ILX
ILOAD
Time (500µs/div)
Time (100µs/div)
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1160.2007.11.1.1
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PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
Typical Characteristics
Load Transient
(VOUT = 5.0V; CFF = 100pF; IOUT = 10mA to 3A;
CIN = 10µF; COUT = 22µF; L = 3.8µH)
SYNC Mode
(VOUT = 5.0V; CFF = 100pF; SYNC = 1.4MHz;
IOUT = 3A; CIN = 10µF; COUT = 22µF; L = 3.8µH)
6
5
4
3
2
1
0
6
5
4
3
2
1
0
8
6
4
2
0
40
30
20
10
0
ILOAD
ILX
Time (100µs/div)
Time (200ns/div)
SYNC Mode
(VOUT = 5.0V; CFF = 100pF; SYNC = 500kHz;
IOUT = 3A; CIN = 10µF; COUT = 2x22µF; L = 3.8µH)
VOUT vs. Temperature
(VOUT = 3.3V; ILOAD = 1.5A)
1
8
40
0.8
0.6
0.4
0.2
0
6
4
2
0
30
20
10
0
-0.2
-0.4
-0.6
-0.8
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (°C)
Time (500ns/div)
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1160.2007.11.1.1
PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
Functional Block Diagram
LDO
AIN
IN
Note1
FB
Internal
Power
LDO
Current
Sense Amp
+
-
+
-
+
Error
Amp
Control
Logic
Current
Mode
-
LX
Comparator
Reference
PGND
AGND
EN
SYNC
DGND
COMP
.
Note1: For fixed output voltage versions, FB is connected to the
error amplifier through the resistive voltage divider shown.
Control Loop
Functional Description
The AAT1160 regulates the output voltage using con-
stant frequency current mode control. The AAT1160
monitors current through the high-side P-channel
MOSFET and uses that signal to regulate the output volt-
age. This provides improved transient response and
eases compensation. Internal slope compensation is
included to ensure the current “inside loop” stability.
The AAT1160 is a current-mode step-down DC/DC con-
verter that operates over a wide 4V to 13.2V input volt-
age range and is capable of supplying up to 3A to the
load with the output voltage regulated as low as 0.6V.
Both the P-channel power switch and N-channel syn-
chronous rectifier are internal, reducing the number of
external components required. The output voltage is
adjusted by an external resistor divider; fixed output
voltage versions are available upon request. The regula-
tion system is externally compensated, allowing the
circuit to be optimized for each application. The AAT1160
includes cycle-by-cycle current limiting, frequency fold-
back for improved short-circuit performance, and ther-
mal overload protection to prevent damage in the event
of an external fault condition.
High efficiency is maintained under light load conditions
by automatically switching to variable frequency Light
Load control. In this condition, transition losses are
reduced by operating at a lower frequency at light loads.
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9
PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
Short-Circuit Protection
Applications Information
The AAT1160 uses a cycle-by-cycle current limit to pro-
tect itself and the load from an external fault condition.
When the inductor current reaches the internally set
6.0A current limit, the P-channel MOSFET switch turns
off and the N-channel synchronous rectifier is turned on,
limiting the inductor and the load current.
Setting the Output Voltage
Figure 1 shows the basic application circuit for the
AAT1160 and output setting resistors. Resistors R3 and
R6 program the output to regulate at a voltage higher
than 0.6V. To limit the bias current required for the
external feedback resistor string while maintaining good
noise immunity, the minimum suggested value for R6 is
5.9kΩ. Although a larger value will further reduce quies-
cent current, it will also increase the impedance of the
feedback node, making it more sensitive to external
noise and interference. Table 1 summarizes the resistor
values for various output voltages with R6 set to either
5.9kΩ for good noise immunity or 59kΩ for reduced no
load input current.
During an overload condition, when the output voltage
drops below 25% of the regulation voltage (0.15V at
FB), the AAT1160 switching frequency drops by a factor
of 4. This gives the inductor current ample time to reset
during the off time to prevent the inductor current from
rising uncontrolled in a short-circuit condition.
Thermal Protection
The AAT1160 includes thermal protection that disables
the regulator when the die temperature reaches 140ºC.
It automatically restarts when the temperature decreas-
es by 25ºC or more.
L1
EP2
VOUT
5V, 2A
VIN 4.5V -13 .2V
R4
3.8μH
LX
3
4
1
2
LX
LX
FB
EN
IN
C3, C4
2x22μF
C1
R3
10Ω
5
7
C6
22μF
100pF
43.2kΩ
C2
0.1μF
IN
9
AAT1160
R6
AIN
10
11
C8
1μF
COMP
Frequency Synchronization
5.9kΩ
6
13
16
AGND
DGND
R5
50kΩ
The AAT1160 operates at a fixed 800kHz switching fre-
quency, or it can be synchronized to an external signal.
Synchronize switching to an external signal between
500kHz and 1.6MHz by driving SYNC with that signal. In
this mode, the rising edge of the signal at SYNC turns on
the P-channel switch. When changing switching frequen-
cy, the external components CIN, COUT and L must be
changed according to the component equations. The
external clock duty cycle is limited to a 30% to 90%
range.
14
8
DGND
PGND
SYNC
LDO
DGND
EP1
C7
150pF
C9
1μF
Figure 1: Typical Application Circuit.
The adjustable feedback resistors, combined with an
external feed forward capacitor (C1 in Figure 1), deliver
enhanced transient response for extreme pulsed load
applications. The addition of the feed forward capacitor
typically requires a larger output capacitor C3/C4 for
stability. Larger C3/C4 values reduce overshoot and
undershoot during startup and load changes. However,
do not exceed 470pF to maintain stable operation.
PWM or Light Load Mode
The device can be set to operate in forced Pulse Width
Modulation (PWM) mode to filter or set the switching
noise to a desired frequency by connecting the SYNC to
a high logic level. Alternately, a combination PWM/LL
(Light Load) mode for improved light load efficiency can
be set by connecting the SYNC pin to GND or a low logic
level. When connecting SYNC to an external clock sig-
nal, the device is always in forced PWM mode.
The external resistors set the output voltage according
to the following equation:
⎛
⎝
R3⎞
R6⎠
V
OUT = 0.6V 1 +
or
V
⎛
⎝
⎞
-1 · R6
⎠
OUT
R3 =
V
REF
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1160.2007.11.1.1
PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
Table 1 shows the resistor selection for different output
voltage settings.
mum recommended inductor is 3.8μH. For 3.3V and
below, use a 2 to 2.2μH inductor. For optimum voltage-
positioning load transients, choose an inductor with DC
series resistance in the 15mꢀ to 20mꢀ range. For
higher efficiency at heavy loads (above 1A), or minimal
load regulation (but some transient overshoot), the
resistance should be kept below 18mꢀ. The DC current
rating of the inductor should be at least equal to the
maximum load current plus half the ripple current to
prevent core saturation (3A + 526mA). Table 2 lists
some typical surface mount inductors that meet target
applications for the AAT1160.
R6 = 5.9kΩ
R3 (kΩ)
R6 = 59kΩ
R3 (kΩ)
VOUT (V)
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.8
1.85
2.0
2.5
3.3
5.0
1.96
2.94
3.92
4.99
5.90
6.81
7.87
8.87
11.8
12.4
13.7
18.7
26.7
43.2
19.6
29.4
39.2
49.9
59.0
68.1
78.7
88.7
118
124
137
187
267
Manufacturer’s specifications list both the inductor DC
current rating, which is a thermal limitation, and the
peak current rating, which is determined by the satura-
tion characteristics. The inductor should not show any
appreciable saturation under normal load conditions.
Some inductors may meet the peak and average current
ratings yet result in excessive losses due to a high DCR.
Always consider the losses associated with the DCR and
its effect on the total converter efficiency when selecting
an inductor. For example, the 3.7ꢁH CDR7D43 series
inductor selected from Sumida has an 18.9mΩ DCR and
a 4.3ADC current rating. At full load, the inductor DC
loss is 170mW which gives only a 1.13% loss in effi-
ciency for a 3A, 5V output.
432
Table 1: Resistor Selection for Different Output
Voltage Settings. Standard 1% Resistors are
Substituted for Calculated Values.
Inductor Selection
For most designs, the AAT1160 operates with inductors
of 2μH to 4.7μH. Low inductance values are physically
smaller, but require faster switching, which results in
some efficiency loss. The inductor value can be derived
from the following equation:
Input Capacitor Selection
The input capacitor reduces the surge current drawn
from the input and switching noise from the device. The
input capacitor impedance at the switching frequency
shall be less than the input source impedance to prevent
high frequency switching current passing to the input. A
low ESR input capacitor sized for maximum RMS current
must be used. Ceramic capacitors with X5R or X7R
dielectrics are highly recommended because of their low
ESR and small temperature coefficients. A 22μF ceramic
capacitor is sufficient for most applications.
VOUT · (VIN
-
VOUT
)
L1 =
VIN · ΔIL · FOSC
Where ∆IL is inductor ripple current. Large value induc-
tors lower ripple current and small value inductors result
in high ripple currents. Choose inductor ripple current
approximately 32% of the maximum load current 3A, or
∆IL = 959mA. For output voltages above 3.3V, the mini-
Max DCR
(mΩ)
Rated DC
Current (A)
Size WxLxH
(mm)
Manufacturer
Part Number
L (μH)
Sumida
Sumida
Coilcraft
CDRH103RNP-2R2N
CDR7D43MNNP-3R7NC
MSS1038-382NL
2.2
3.7
3.8
16.9
18.9
13
5.10
4.3
4.25
10.3x10.5x3.1
7.6x7.6x4.5
10.2x7.7x3.8
Table 2: Typical Surface Mount Inductors.
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1160.2007.11.1.1
11
PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
To estimate the required input capacitor size, determine
the acceptable input ripple level (VPP) and solve for C.
The calculated value varies with input voltage and is a
maximum when VIN is double the output voltage.
high frequency content of the input current localized,
minimizing EMI and input voltage ripple. The proper
placement of the input capacitor (C6) can be seen in the
evaluation board layout in Figure 3. Additional noise fil-
tering for proper operation is accomplished by adding a
small 0.1μF capacitor on the IN pins (C2).
VO
⎛
VO ⎞
VIN ⎠
· 1 -
⎝
VIN
CIN =
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the evalu-
ation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result. Since the inductance of a
short PCB trace feeding the input voltage is significantly
lower than the power leads from the bench power sup-
ply, most applications do not exhibit this problem. In
applications where the input power source lead induc-
tance cannot be reduced to a level that does not affect
the converter performance, a high ESR tantalum or alu-
minum electrolytic should be placed in parallel with the
low ESR, ESL bypass ceramic. This dampens the high Q
network and stabilizes the system.
⎛ VPP
⎝ IO
⎞
- ESR ·FOSC
⎠
VO
⎛
VO ⎞
VIN ⎠
1
· 1 -
⎝
=
for VIN = 2 · VO
VIN
4
1
CIN(MIN)
=
⎛ VPP
⎝ IO
⎞
- ESR · 4 · FOSC
⎠
Always examine the ceramic capacitor DC voltage coef-
ficient characteristics when selecting the proper value.
For example, the capacitance of a 10ꢁF, 16V, X5R ceram-
ic capacitor with 12V DC applied is actually about 8.5ꢁF.
The maximum input capacitor RMS current is:
VO
⎛
VO ⎞
VIN ⎠
IRMS = IO ·
· 1 -
⎝
Output Capacitor Selection
VIN
The output capacitor is required to keep the output volt-
age ripple small and to ensure regulation loop stability.
The output capacitor must have low impedance at the
switching frequency. Ceramic capacitors with X5R or X7R
dielectrics are recommended due to their low ESR and
high ripple current. The output ripple VOUT is determined
by:
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current:
VO
⎛
VO ⎞
VIN ⎠
1
· 1 -
⎝
=
D · (1 - D) = 0.52 =
VIN
2
VOUT · (VIN - VOUT
)
⎛
1
⎞
for VIN = 2 · VO
ΔVOUT
≤
· ESR +
VIN · FOSC · L
⎝
8 · FOSC · COUT
⎠
IO
IRMS(MAX)
=
2
The output capacitor limits the output ripple and pro-
vides holdup during large load transitions. A 10ꢁF to
47ꢁF X5R or X7R ceramic capacitor typically provides
sufficient bulk capacitance to stabilize the output during
large load transitions and has the ESR and ESL charac-
teristics necessary for low output ripple. The output volt-
age droop due to a load transient is dominated by the
capacitance of the ceramic output capacitor. During a
step increase in load current, the ceramic output capac-
itor alone supplies the load current until the loop
responds. Within two or three switching cycles, the loop
responds and the inductor current increases to match
VO
⎛
VO
1 -
⎞
⎠
·
VIN
⎝
VIN
The term
appears in both the input voltage
ripple and input capacitor RMS current equations and is
at maximum when VO is twice VIN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle. The input capacitor
provides a low impedance loop for the edges of pulsed
current drawn by the AAT1160. Low ESR/ESL X7R and
X5R ceramic capacitors are ideal for this function. To
minimize stray inductance, the capacitor should be
placed as closely as possible to the IC. This keeps the
w w w . a n a l o g i c t e c h . c o m
12
1160.2007.11.1.1
PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
the load current demand. The relationship of the output
voltage droop during the three switching cycles to the
output capacitance can be estimated by:
FOSC is the switching frequency and COUT is based on the
output capacitor calculation. The CCOMP value can be
determined from the following equation:
4
CCOMP (C7) =
3 · ΔILOAD
DROOP · FOSC
COUT
=
⎛FOSC
⎞
V
2πRCOMP (R5) ·
⎝ 10 ⎠
Layout Guidance
Once the average inductor current increases to the DC
load level, the output voltage recovers. The above equa-
tion establishes a limit on the minimum value for the
output capacitor with respect to load transients. The
internal voltage loop compensation also limits the mini-
mum output capacitor value to 22ꢁF. This is due to its
effect on the loop crossover frequency (bandwidth),
phase margin, and gain margin. Increased output capac-
itance will reduce the crossover frequency with greater
phase margin.
Figure 2 is the schematic for the evaluation board. When
laying out the PC board, the following layout guideline
should be followed to ensure proper operation of the
AAT1160:
1. Exposed pad EP1 must be reliably soldered to PGND/
DGND/AGND. The exposed thermal pad should be
connected to board ground plane and pins 6, 11, 13,
and 16. The ground plane should include a large
exposed copper pad under the package for thermal
dissipation.
2. The power traces, including GND traces, the LX
traces and the VIN trace should be kept short, direct
and wide to allow large current flow. The L1 connec-
tion to the LX pins should be as short as possible.
Use several via pads when routing between layers.
3. Exposed pad pin EP2 must be reliably soldered to
the LX pins 1 and 2. The exposed thermal pad
should be connected to the board LX connection and
the inductor L1 and also pins 1 and 2. The LX plane
should include a large exposed copper pad under the
package for thermal dissipation.
The maximum output capacitor RMS ripple current is
given by:
1
V
OUT · (VIN(MAX) - VOUT
)
IRMS(MAX)
=
·
L · FOSC · VIN(MAX)
2 · 3
Dissipation due to the RMS current in the ceramic output
capacitor ESR is typically minimal, resulting in less than
a few degrees rise in hot-spot temperature.
Compensation
4. The input capacitors (C2 and C6) should be con-
nected as close as possible to IN (Pins 4 and 5) and
DGND (Pin 6) to get good power filtering.
5. Keep the switching node LX away from the sensitive
FB node.
6. The feedback trace for the FB pin should be separate
from any power trace and connected as closely as
possible to the load point. Sensing along a high-
current load trace will degrade DC load regulation.
The feedback resistors should be placed as close as
possible to the FB pin (Pin 9) to minimize the length
of the high impedance feedback trace.
7. The output capacitors C3, 4, and 5 and L1 should be
connected as close as possible and there should not
be any signal lines under the inductor.
The AAT1160 step-down converter uses peak current
mode control with slope compensation scheme to main-
tain stability with lower value inductors for duty cycles
greater than 50%. The regulation feedback loop in the
IC is stabilized by the components connected to the
COMP pin, as shown in Figure 1.
To optimize the compensation components, the following
equations can be used. The compensation resistor RCOMP
(R5) is calculated using the following equation:
2πVOUT · COUT
10GEA · GCOMP · VFB
·
FOSC
RCOMP (R5)=
Where VFB = 0.6V, GCOMP = 40.1734 and GEA = 9.091 ·
10-5.
8. The resistance of the trace from the load return to
the PGND (Pin 16) should be kept to a minimum.
This will help to minimize any error in DC regulation
due to differences in the potential of the internal
signal ground and the power ground.
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1160.2007.11.1.1
13
PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
JP1
Enable
TP1
GND
TP14
GND
R1
4.75K
R2
4.75K
TP2
LX
DGND
TP3
Enable
AAT1160
U1
EP2
VOUT
L1
LX
TP4
VIN
15
4
1
2
EN
IN
LX
LX
TP5
VIN
VOUT
3.8μH
C1
100pF
R3
5
3
9
10
IN
FB
C2
0.1μF
432K
R4
10
TP6
VOUT
N/C
AIN
COMP
TP7
VIN
7
11
12
C3
22μF
C4
22μF
C5
NP
R5
AGND
N/C
50K
6
13
C6
R6
59K
DGND
DGND
14
8
TB2
VOUT
10μF
SYNC
LDO
TB1
VIN
C7
150pF
16
PGND
C8
1μF
EP1
TP8
GND
C9
1μF
DGND
TP9
GND
TP10
TP12
GND
TP11
GND
TP13
GND
*
SYNC
DGND
*Note: Connect GND, DGND, and AGND at IC
Inductor -Sumida CDRH103RNP-3R3NC-B
JP2
SYNC
Figure 2: AAT1160 Evaluation Board Schematic.
Figure 3: AAT1160 Evaluation Board
Component Side Layout.
Figure 4: AAT1160 Evaluation Board
Solder Side Layout.
w w w . a n a l o g i c t e c h . c o m
14
1160.2007.11.1.1
PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
Design Example
Specifications
VOUT
VIN
5V @ 3A, Pulsed Load ΔILOAD = 3A
12V nominal
FOSC
TAMB
800kHz
85°C in TDFN34-16 Package
Output Inductor
VOUT · (VIN VOUT
L1 =
-
)
= 3.8µH; see Table 2.
VIN · ΔIL · FOSC
ΔIL = 0.32 · ILOAD
For Coilcraft inductor MSS1038 3.8μH DCR = 13mΩ max.
⎛
⎞
⎠
VOUT
VO1
5
V
5V
⎛
⎞
⎠
ΔI1 =
⋅ 1 -
⎝
=
⋅ 1 -
= 959mA
⎝
L1 ⋅ FOSC
VIN
3.8µH ⋅ 800kHz
12V
ΔI1
2
IPK1 = ILOAD
+
= 3A + 0.479A = 3.48A
2
PL1 = ILOAD ⋅ DCR = 3A2 ⋅ 13mΩ = 117mW
Output Capacitor
VDROOP = 0.2V
3 · ΔILOAD
VDROOP · FOSC
3 · 3A
COUT
=
=
= 56µF; use two 22µF
0.2V · 800kHz
(VOUT) · (VIN(MAX) - VOUT
)
1
5V · (12V - 5V)
1
·
= 277mArms
IRMS(MAX)
=
·
=
3.8µH · 800kHz · 12V
L · FOSC · VIN(MAX)
2· 3
2· 3
Pesr = esr · IRMS2 = 5mΩ · (277mA)2 = 384µW
Input Capacitor
Input Ripple VPP = 50mV
1
1
CIN =
=
= 26µF; use 22µF
⎛ VPP
⎝ ILOAD
⎞
⎛ 50mV
⎞
⎠
- ESR · 4 · FOSC
- 5mΩ · 4 · 800kHz
⎠
⎝
3A
ILOAD
IRMS(MAX)
=
= 1.5Arms
2
P = esr · IRMS2 = 5mΩ · (1.5A)2 = 11.25mW
w w w . a n a l o g i c t e c h . c o m
1160.2007.11.1.1
15
PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
AAT1160 Losses
Total losses can be estimated by calculating the dropout (VIN = VO) losses where the power MOSFET RDS(ON) will be at
the maximum value. All values assume an 85°C ambient temperature and a 140°C junction temperature with the TDFN
37°C/W package.
PLOSS = ILOAD2 · RDS(ON)H = 3A2 · 0.12Ω = 1.08W
TJ(MAX) = TAMB + ΘJA · PLOSS = 85°C + (37°C/W) · 1.08W = 125°C
The total losses are also investigated at the nominal input voltage (12V). The simplified version of the RDS(ON) losses
assumes that the N-channel and P-channel RDS(ON) are equal.
PTOTAL = ILOAD2 · RDS(ON) + [(tsw · FOSC · ILOAD + IQ) · VIN]
= 3A2 · 100mΩ + [(5ns · 800kHz · 3A + 150µA) · 12V] = 1.0458W
TJ(MAX) = TAMB + ΘJA · PLOSS = 85°C + (37°C/W) · 1.0458W = 124°C
w w w . a n a l o g i c t e c h . c o m
16
1160.2007.11.1.1
PRODUCT DATASHEET
AAT1160
SwitchRegTM
12V, 3A Step-Down DC/DC Converter
Ordering Information
Package
Marking1
Part Number (Tape and Reel)2
AAT1160IRN-0.6-T1
TDFN34-16
XAXYY
All AnalogicTech products are offered in Pb-free packaging. The term “Pb-free” means semiconductor
products that are in compliance with current RoHS standards, including the requirement that lead not
exceed 0.1% by weight in homogeneous materials. For more information, please visit our website at
http://www.analogictech.com/pbfree.
Package Information
TDFN34-16
1.600 0.050
3.000 0.050
Index Area
0.25 REF
0.430 0.050
1.600 0.050
Top View
Bottom View
0.050 0.050
0.230 0.050
Side View
All dimensions in millimeters.
1. XYY = assembly and date code.
2. Sample stock is generally held on part numbers listed in BOLD.
3. The leadless package family, which includes QFN, TQFN, DFN, TDFN and STDFN, has exposed copper (unplated) at the end of the lead terminals due to the manufacturing
process. A solder fillet at the exposed copper edge cannot be guaranteed and is not required to ensure a proper bottom solder connection.
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Phone (408) 737-4600
Fax (408) 737-4611
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AnalogicTech cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an AnalogicTech product. No circuit patent licenses, copyrights, mask work rights, or other intellectual
property rights are implied. AnalogicTech reserves the right to make changes to their products or specifications or to discontinue any product or service without notice. Except as provided in AnalogicTech’s terms and
conditions of sale, AnalogicTech assumes no liability whatsoever, and AnalogicTech disclaims any express or implied warranty relating to the sale and/or use of AnalogicTech products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. In order to minimize risks associated with the customer’s applications, adequate
design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. Testing and other quality control techniques are utilized to the extent AnalogicTech deems necessary to
support this warranty. Specific testing of all parameters of each device is not necessarily performed. AnalogicTech and the AnalogicTech logo are trademarks of Advanced Analogic Technologies Incorporated. All other
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w w w . a n a l o g i c t e c h . c o m
1160.2007.11.1.1
17
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