FQV243L7.5PFI [AMICC]

FIFO, 2KX18, 5ns, Synchronous, CMOS, PQFP80;
FQV243L7.5PFI
型号: FQV243L7.5PFI
厂家: AMIC TECHNOLOGY    AMIC TECHNOLOGY
描述:

FIFO, 2KX18, 5ns, Synchronous, CMOS, PQFP80

时钟 先进先出芯片 内存集成电路
文件: 总43页 (文件大小:399K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
3.3 Volt Synchronous x9/x18 First-In/First-Out Queue  
Memory Organization  
262,144 x 18 / 524,288 x 9  
131,072 x 18 / 262,144 x 9  
65,536 x 18 / 131,072 x 9  
32,768 x 18 / 65,536 x 9  
Device  
FQV2113  
FQV2103  
FQV293  
FQV283  
Memory Organization  
16,384 x 18 / 32,768 x 9  
8,192 x 18 / 16,384 x 9  
4,096 x 18 / 8,192 x 9  
2,048 x 18 / 4,096 x 9  
Device  
FQV273  
FQV263  
FQV253  
FQV243  
Key Features  
Industry leading First-In/First-Out Queues (up to 166MHz)  
Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns)  
Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns)  
User selectable input and output port bus-sizing  
Big Endian/Little Endian user selectable byte representation  
3.3V power supply  
5V input tolerant on all control and data input pins  
5V output tolerant on all flags and data output pins  
Master Reset clears all previously programmed configurations including Write and Read pointers  
Partial Reset clears Write and Read pointers but maintains all previously programmed configurations  
First Word Fall Through (FWFT) and Standard Timing modes  
Presets for eight different Almost Full and Almost Empty offset values  
Parallel/Serial programming of PRAF and PRAE offset values  
Programmable 8-bit or 9-bit parallel programming modes for offset values  
Full, Empty, Almost Full, Almost Empty, and Half Full indicators  
PRAF and PRAE operates in either synchronous or asynchronous modes  
Asynchronous output enable tri-state data output drivers  
Data retransmission with programmable zero or normal latency modes  
Available package: 80 - pin Plastic Thin Quad Flat Pack (TQFP)  
(0°C to 70°C) Commercial operating temperature available for cycle time of 6.0ns and above  
(-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above  
Product Description  
HBA’s FlexQ™ III offers industry leading FIFO queuing bandwidth (up to 3.0 Gbps), with a wide range of memory  
configurations (from 2,048 x 18 to 262,144 x 18 or 4,096 x 9 to 524,286 x 9). System designer has full flexibility of  
implementing deeper and wider queues using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators  
allow easy handshaking between transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial)  
indicators allow implementation of virtual queue depths.  
5V tolerant on all input and output pins allows easy interfacing with devices operating at higher voltage levels. Asynchronous  
Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching  
capability.  
Master Reset clears all previously programmed configurations by providing a low pulse on MRST pin. In addition, Write and  
Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will  
initialize Write and Read pointers to zero.  
In FWFT mode, the first data written into the queue appears on output data bus after the specified latency period at the low to  
high transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when  
implementing depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and  
EMPTY respectively.  
JANUARY 2003  
3F30918C  
Page 1 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Product Description (Continued)  
In Standard mode, always assert REN whenever a read operation. FULL and EMPTY are used instead of DRDY and  
QRDY respectively.  
Bus matching feature is available with the following configurations:  
Input Bus Width  
Output Bus Width  
x9  
x9  
x9  
x18  
x9  
x18  
x18  
x18  
In addition, Endian Select is available for implementing byte re-ordering on data outputs.  
Eight different default offset values are available for Almost Full ( PRAF ) and Almost Empty ( PRAE ) flags. Parallel and Serial  
programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 9-bit  
parallel programming modes for offset values can be selected for convenience.  
PRAF , PRAE , and HALF are available in either FWFT or Standard mode. PRAF and PRAE can operate in either  
synchronous or asynchronous modes.  
At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of  
RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the  
physical 0th (Read pointer = zero) location of the queue. Both zero and normal latency timing modes are available for retransmit  
operation.  
These FlexQ™ III devices have low power consumption, hence minimizing system power requirements. In addition, industry  
standard 80 - pin Plastic TQFP is offered to save system board space.  
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test  
equipment, network switching, etc.  
.
JANUARY 2003  
3F30918C  
Page 2 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Block Diagram of Single Synchronous Queue  
262,144 x 18 / 131,072 x 18 / 65,536 x 18 / 32,768 x 18 / 16,384 x 18 / 8,192 x 18 / 4,096 x 18 / 2,048 x 18 /  
524,288 x 9 / 262,144 x 9 / 131,072 X 9 / 65,536 X 9 / 32,768 X 9 / 16,384 X 9 / 8,192 x 9 / 4,096 x 9  
PRST  
MRST  
)
PARTIAL RESET (  
)
MASTER RESET (  
READ CLOCK (RCLK)  
REN  
WRTIE CLOCK (WCLK)  
WEN  
READ ENABLE (  
)
WRITE ENABLE (  
)
OE  
OUTPUT ENABLE (  
)
FQV2113  
FQV2103  
FQV293  
FQV283  
FQV273  
FQV263  
FQV253  
FQV243  
LOAD ( LOAD)  
x18 or x9 DATA IN (D 17 - 0  
x18 or x9 DATA OUT (Q 17 - 0  
)
)
RETRANSMIT (  
)
RET  
EMPTY FLAG / OUTPUT READY  
EMPTY /QRDY  
SERIAL DATA ENABLE  
( SDEN)  
(
)
FIRST WORD FALL THROUGH/  
SERIAL DATA INPUT (FWFT/SDI)  
FULL FLAG / INPUT READY  
PROGRAMMABLE ALMOST-  
EMPTY (  
)
PRAE  
HALF-FULL FLAG (  
)
(
)
HALF  
FULL/ DRDY  
PROGRAMMABLE  
ALMOST-FULL (  
BIG-ENDIAN / LITTLE-ENDIAN (  
INTERSPERSED /  
NON-INTERSPERSED PARITY (IPAR)  
)
ES  
)
PRAF  
BUS MATCHING 1  
(BM1)  
BUS MATCHING 0  
(BM0)  
Figure 1. Single Device Configuration Signal Flow Diagram  
JANUARY 2003  
3F30918C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 3 of 43  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
WCLK WEN  
IPAR LOAD SDEN FWFT/SDI  
/ DRDY  
FULL  
PRAF  
Write Control  
Logic  
EMPTY/QRDY  
PRAE  
HALF  
FWFT/SDI  
Offset Register  
Flag Logic  
SFM  
PFS1  
PFS0  
Write Pointer  
Output  
Buffer  
Input Register  
Output Register  
SRAM  
Q 17-0  
x18, x9  
D17-0  
x18, x9  
OE  
Read Pointer  
Bus  
Configuration  
Read Control  
Logic  
Reset  
RETZL RET RCLK REN  
MRST PRST  
ES BM1 BM0  
Figure 2. Device Architecture  
JANUARY 2003  
3F30918C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 4 of 43  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Index  
WEN  
SDEN  
DNC1  
Vcc  
RET  
OE  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
Vcc  
Q17  
Q16  
GND  
DNC1  
BM1  
GND  
D17  
Vcc  
GND  
Q15  
Q14  
Vcc  
D16  
D15  
D14  
D13  
GND  
D12  
D11  
D10  
D9  
Q13  
Q12  
GND  
Q11  
GND  
Q10  
Vcc  
Q9  
Q8  
Q7  
D8  
Vcc  
TQFP - 80 (Drw No: PF-01A; Order code: PF)  
Top View  
NOTES:  
1.  
DNC = Do Not Connect.  
Figure 3. Device Pin Out  
JANUARY 2003  
3F30918C  
Page 5 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Description  
Pin #  
Pin Name  
Pin Symbol  
Input/Output  
Master Reset is required to initialize Write and Read  
pointers to the first position of the queue by setting  
MRST low. In Standard mode, FULL and PRAF will  
go high; EMPTY and PRAE will go low. In FWFT  
mode, DRDY will go low and QRDY will go high.  
PRAF and PRAE will go to the same state as Standard  
mode. In both modes, all data outputs will go low.  
Previous programmed configurations will not be  
maintained.  
78  
Master Reset  
Input  
MRST  
Partial Reset is required to initialize Write and Read  
pointers to the first position of the queue by setting  
PRST low. In Standard mode, FULL and PRAF will  
go high; EMPTY and PRAE will go low. In FWFT  
mode, DRDY will go low and QRDY will go high.  
PRAF and PRAE will go to the same state as Standard  
mode. In both modes, all data outputs will go low.  
Previous programmed configurations will be  
maintained.  
79  
Partial Reset  
Input  
PRST  
Writes data into queue during low to high transitions of  
WCLK if WEN is set to low.  
80  
01  
Write Clock  
Write Enable  
WCLK  
WEN  
Input  
Input  
Controls write operation into queue or offset registers  
during low to high transition of WCLK.  
During Master Reset, set LOAD low to select parallel  
programming and one of eight default-offset values.  
Set LOAD high to select serial programming and one  
of eight default offset values. After Master Reset,  
LOAD controls write/read, to/from offset registers  
during low to high transition of WCLK/RCLK  
77  
Load Enable  
Input  
LOAD  
respectively. Use in conjunction with WEN / REN .  
Default  
During Master Reset, select one of eight default-offset  
values. Use in conjunction with LOAD and PFS0.  
70  
72  
PFS1  
PFS0  
Input  
Input  
Programming 1  
Default  
During Master Reset, select one of eight default-offset  
values. Use in conjunction with LOAD and PFS1.  
Programming 0  
08,10,11,  
12,13,15,  
16,17,18  
19,21,22,  
24,25,26,  
27,28,29  
Data Inputs  
D17-0  
Input  
18 - bit wide input data bus.  
Reads data from queue during low to high transitions of  
RCLK if REN is set to low.  
62  
61  
Read Clock  
Read Enable  
RCLK  
REN  
Input  
Input  
Controls read operation from queue or offset registers  
during low to high transition of RCLK.  
Setting OE low activates the data output drivers.  
Setting OE high deactivates the data output drivers  
(High-Z).  
59  
Output Enable  
Input  
OE  
Table 1. Pin Descriptions  
JANUARY 2003  
3F30918C  
Page 6 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Description  
Pin #  
Pin Name  
Pin Symbol  
Input/Output  
57,56,53,  
52,50,49,  
47,45,43,  
42,41,40,  
38,37,35,  
34,32,31  
Data Outputs  
Q17-0  
Output  
18 - bit wide output data bus.  
Selects FWFT timing or Standard timing mode during  
Master Reset. After Master Reset, if serial  
programming is selected ( LOAD = high), FWFT/SDI  
is used as the serial data input for the offset registers.  
Serial data is written during the low to high transition  
of WCLK. Use in conjunction with SDEN .  
First Word Fall  
Through/Serial  
Data Input  
76  
02  
FWFT/SDI  
SDEN  
Input  
Input  
If serial programming is selected, setting SDEN low  
and LOAD low enables serial data input to be written  
into offset registers during the low to high transition of  
WCLK.  
Serial Data  
Input Enable  
Bus Matching  
1
During Master Reset, set BM1 low to select x18 input  
bus width or BM1 high to select x9 input bus width.  
06  
73  
BM1  
BM0  
Input  
Input  
During Master Reset, set BM0 low to select x18  
output bus width or BM0 high to select x9 output bus  
width.  
Bus Matching  
0
During Master Reset, set ES high to select byte re-  
ordering on data outputs or ES low to select no byte  
re-ordering on data outputs.  
69  
60  
63  
75  
Endian Select  
ES  
Input  
Input  
Data previously read from the queue can be  
retransmitted by asserting RET pin at the low to high  
transition of RCLK for a retransmit operation.  
Retransmit initializes the Read pointer to zero. Hence,  
all re-reads will always start from the physical 0th  
(Read pointer = zero) location of the queue.  
Retransmit  
RET  
RETZL  
During Master Reset, set RETZL low to select zero  
latency retransmit or RETZL high to select normal  
latency retransmit.  
Zero Latency  
Retransmit  
Input  
Queue is full when FULL goes low during the low to  
high transition of WCLK. This prohibits further  
writes into the queue. In FWFT mode, queue is full  
when DRDY goes high during low to high transition  
of WCLK. This prohibits further writes into the  
queue.  
Full/Data Input  
Ready Flag  
Output  
FULL / DRDY  
Queue is empty when EMPTY goes low during the  
low to high transition of RCLK. This prohibits further  
reads from the queue. In FWFT mode, queue is empty  
when QRDY goes high during the low to high  
transition of RCLK. This prohibits further reads from  
the queue.  
Empty/Data  
Output Ready  
Flag  
64  
EMPTY / QRDY  
IPAR  
Output  
Input  
During Master Reset, set IPAR low to select 9-bit  
parallel programming mode or IPAR high to select 8-  
bit parallel programming mode.  
Interspersed  
Parity  
68  
Table 1. Pin Descriptions (Continued)  
JANUARY 2003  
3F30918C  
Page 7 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Description  
Pin #  
Pin Name  
Pin Symbol Input/Output  
During Master Reset, set SFM high to select  
Synchronous Partial Flag mode or SFM low to select  
Asynchronous Partial Flag mode.  
Synchronous  
65  
SFM  
Input  
Partial Flag Mode  
Queue is almost full when PRAF goes low during the  
low to high transition of WCLK. Default (Full-offset)  
or programmed offset values determine the status of  
PRAF .  
Queue is almost empty when PRAE goes low during  
the low to high transition of RCLK. Default (Empty  
+offset) or programmed offset values determine the  
status of PRAE .  
74  
66  
Almost Full  
Output  
PRAF  
Almost Empty  
Output  
PRAE  
Queue is more than half full when HALF goes low.  
Triggered by both WCLK and RCLK.  
71  
Half Full  
Output  
N/A  
HALF  
DNC  
03, 05  
Do Not Connect  
Do not connect.  
04,09,20  
36,44,51,  
58,67  
Power  
VCC  
N/A  
N/A  
3.3V power supply.  
07,14,23,  
30,33,39,  
Ground  
GND  
0V Ground.  
46,48,54,55,  
Table 1. Pin Descriptions (Continued)  
JANUARY 2003  
3F30918C  
Page 8 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Symbol  
Rating  
Com’l & Ind’l  
Unit  
NOTES:  
Terminal Voltage with  
respect to GND  
Absolute Max Ratings are for reference only. Permanent damage to the device may  
VTERM  
-0.5 to + 4.5  
V
occur if extended period of operation is outside this range. Standard operation should  
fall within the Recommended Operating Conditions.  
TSTG  
IOUT  
Storage Temperature  
DC Output Current  
-55 to +125  
-50 to +50  
°C  
mA  
Table 2. Absolute Maximum Ratings  
FQV2113, FQV2103FQV293, FQV283  
FQV273, FQV263, FQV253, FQV243  
Commercial  
Industrial  
Clock = 6ns, 7.5ns, 10ns,  
Clock = 7.5ns, 10ns, 15ns  
15ns  
Symbol  
Parameter  
Min.  
Typ.  
Max. Min.  
Typ.  
Max.  
Unit  
Recommended Operating Conditions  
Vcc  
Supply Voltage Com’l / Ind’l  
3.15  
3.3  
3.45  
3.15  
3.3  
3.45  
V
GND  
VIH  
VIL  
TA  
Supply Voltage  
0
2.0  
-
0
-
0
0
2.0  
-
0
-
0
V
V
Input High Voltage Com’l /  
Ind’l  
Input Low Voltage Com’l /  
Ind’l  
Operating Temperature  
Commercial  
Operating Temperature  
Industrial  
5.5  
0.8  
70  
85  
5.5  
0.8  
70  
85  
-
-
V
0
-
0
-
°C  
°C  
TA  
-40  
-
-40  
-
DC Electrical Characteristics  
Input Leakage Current (any  
ILI(1)  
-1  
-10  
2.4  
-
-
-
-
-
1
10  
-
-1  
-10  
2.4  
-
-
-
-
-
1
10  
-
µA  
µA  
V
input)  
ILO  
Output Leakage Current  
Output Logic “1” Voltage,  
IOH=-2mA  
VOH  
Output Logic “0” Voltage, IOL  
VOL  
0.4  
0.4  
V
= 8mA  
Power Consumption  
ICC1(2,3)  
Active Power Supply Current  
(x9 Input to x9 Output)  
-
-
-
-
-
-
30  
35  
15  
-
-
-
-
-
-
30  
35  
15  
mA  
mA  
mA  
Active Power Supply Current  
ICC1(2,3)  
ICC2(4)  
(x18 Input to x18 Output)  
Standby Current  
Table 3. DC Specifications  
JANUARY 2003  
3F30918C  
Page 9 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Capacitance at 1.0MHz Ambient Temperature (25°C)  
Symbol  
Parameter  
Conditions  
Max.  
Unit  
CIN(2)  
Input Capacitance  
VIN= 0V  
10  
pF  
COUT(2,4)  
Output Capacitance  
VOUT= 0V  
10  
pF  
NOTES:  
1.  
2.  
3.  
4.  
Measurement with 0.4<=VIN<=Vcc.  
With output tri-stated ( OE = High).  
Icc(1,2) is measured with WCLK and RCLK at 20 MHz.  
Design simulated, not tested.  
Table 3. DC Specifications (Continued)  
JANUARY 2003  
3F30918C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 10 of 43  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Commercial  
Commercial & Industrial  
FQV2113-6  
FQV2103-6  
FQV293-6  
FQV283-6  
FQV273-6  
FQV263-6  
FQV253-6  
FQV243-6  
FQV2113-7.5  
FQV2103-7.5  
FQV293-7.5  
FQV283-7.5  
FQV273-7.5  
FQV263-7.5  
FQV253-7.5  
FQV243-7.5  
FQV2113-10  
FQV2103-10  
FQV293-10  
FQV283-10  
FQV273-10  
FQV263-10  
FQV253-10  
FQV243-10  
FQV2113-15  
FQV2103-15  
FQV293-15  
FQV283-15  
FQV273-15  
FQV263-15  
FQV253-15  
FQV243-15  
Symbol  
Parameter  
Clock Cycle Frequency  
Min.  
-
Max.  
Min.  
-
Max.  
Min.  
-
Max.  
Min.  
-
Max.  
Unit  
MHz  
ns  
fS  
166  
4
-
133  
100  
66  
10  
-
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
A
Data Access Time  
1
2
5
-
-
-
-
-
-
-
-
-
-
-
2
6.5  
2
WCLK  
WCLKH  
WCLKL  
RCLK  
RCLKH  
RCLKL  
DS  
Write Clock Cycle Time  
Write Clock High Time  
Write Clock Low Time  
Read Clock Cycle Time  
Read Clock High Time  
Read Clock Low Time  
Data Set-up Time  
6
7.5  
3.5  
3.5  
7.5  
3.5  
3.5  
2.5  
0.5  
2.5  
0.5  
10  
15  
10  
-
10  
4.5  
4.5  
10  
4.5  
4.5  
3.5  
0.5  
3.5  
0.5  
10  
15  
10  
-
-
-
15  
6
ns  
2.5  
2.5  
6
-
-
ns  
-
-
6
-
ns  
-
-
15  
6
-
ns  
2.5  
2.5  
2.0  
0.5  
2.0  
0.5  
8
-
-
-
ns  
-
-
6
-
ns  
-
-
4
-
ns  
DH  
Data Hold Time  
-
-
1
-
ns  
ENS  
Enable Set-up Time  
-
-
4
-
ns  
ENH  
Enable Hold Time  
Reset Pulse Width(1)  
-
-
1
-
ns  
RST  
-
-
15  
15  
15  
-
-
ns  
RSTS  
RSTR  
RSTF  
OLZ  
Reset Set-up Time  
10  
10  
-
-
-
-
ns  
Reset Recovery Time  
-
-
15  
-
-
-
ns  
Reset to Flag and Output Time  
Output Enable to Output in Low-Z(1)  
Output Enable to Output Valid  
Output Enable to Output in High-Z(1)  
Write Clock to Full Flag  
Read Clock to Empty Flag  
Write Clock to Synchronous Almost-Full Flag  
10  
-
15  
-
15  
-
ns  
0
0
0
0
ns  
OE  
2
4
4
4
4
4
2
6
2
6
6
6.5  
6.5  
6.5  
2
8
8
10  
10  
10  
ns  
OHZ  
2
2
6
2
2
ns  
FULL  
EMPTY  
PRAFS  
-
-
5
-
-
ns  
-
-
5
-
-
ns  
-
-
5
-
-
ns  
Read Clock to Synchronous Almost-Empty  
Flag  
t
t
t
PRAES  
SKEW1  
-
4
-
-
5
-
-
7
6.5  
-
9
10  
-
ns  
ns  
ns  
Skew time between Read Clock & Write Clock  
for Full Flag / Empty Flag  
4
6
5
7
-
-
Skew time between Read Clock & Write Clock  
for PRAE & PRAF  
SKEW2  
-
-
10  
14  
-
t
t
LOADS  
LOADH  
Load Setup Time  
Load Hold Time  
2
-
-
2.5  
0.5  
-
-
3.5  
0.5  
-
-
4
1
-
-
ns  
ns  
0.5  
Table 4. AC Electrical Characteristics  
JANUARY 2003  
3F30918C  
Page 11 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Commercial  
Commercial & Industrial  
FQV2113-6  
FQV2103-6  
FQV293-6  
FQV283-6  
FQV273-6  
FQV263-6  
FQV253-6  
FQV243-6  
FQV2113-7.5  
FQV2103-7.5  
FQV293-7.5  
FQV283-7.5  
FQV273-7.5  
FQV263-7.5  
FQV253-7.5  
FQV243-7.5  
FQV2113-10  
FQV2103-10  
FQV293-10  
FQV283-10  
FQV273-10  
FQV263-10  
FQV253-10  
FQV243-10  
FQV2113-15  
FQV2103-15  
FQV293-15  
FQV283-15  
FQV273-15  
FQV263-15  
FQV253-15  
FQV243-15  
Symbol  
Parameter  
Retransmit Setup Time  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
t
t
RETS  
3
-
3.5  
-
3.5  
-
4
-
ns  
HALF  
-
12  
-
12.5  
-
16  
-
20  
ns  
Clock to HALF  
Write Clock to Asynchronous  
Programmable Almost-Full Flag  
t
t
PRAFA  
-
12  
-
12.5  
-
16  
-
20  
ns  
Read Clock to Asynchronous  
PRAEA  
-
12  
-
12.5  
-
16  
-
20  
ns  
Programmable Almost-Empty Flag  
NOTES:  
1.  
Design simulated, not tested.  
Table 4. AC Electrical Characteristics (Continued)  
JANUARY 2003  
3F30918C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 12 of 43  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Input Pulse Levels  
Input Rise/Fall Times  
GND to 3.0V  
3ns  
Input Timing Reference Levels  
Output Reference Levels  
1.5V  
1.5V  
Output Load, clock = 6ns, 7.5ns  
Output Load*, clock = 10ns, 15 ns  
Refer to Figure 4 & 6  
Refer to Figure 5  
* Include jig and scope capacitances  
Table 5. AC Test Condition  
3.3V  
Vcc/2  
330  
50 Ω  
D.U.T.  
30pF*  
510Ω  
I/O  
Z0 = 50 Ω  
Figure 5. Output Load  
Figure 4. AC Test Load  
for clock = 10ns, 15ns  
for clock = 6ns, 7.5ns  
*Includes jig and scope capacitances.  
4
3
2
1
20 30  
50  
80  
100  
200  
Capacitance (pF)  
Figure 6. Lumped Capacitive Load  
JANUARY 2003  
3F30918C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 13 of 43  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Pin Functions  
Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting  
MRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In  
FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state  
as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will  
not be maintained.  
MRST  
Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting  
PRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In  
FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state  
as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will  
be maintained.  
PRST  
WCLK  
Writes data into queue during low to high transitions of WCLK if WEN is activated. Synchronizes  
FULL / DRDY and PRAF flags. WCLK and RCLK are independent of each other.  
Controls write operation into queue or offset registers during low to high transition of WCLK.  
WEN  
During Master Reset, set LOAD low to select parallel programming and one of eight default offset  
values. Set LOAD high to select serial programming and one of eight default offset values. After Master  
Reset, LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK  
respectively for parallel programming. Use in conjunction with WEN / REN . During programming of  
offset registers, PRAF and PRAE flag status are invalid. For Serial programming, LOAD is used to  
enable serial loading of offset registers together with SDEN . Refer to Figure 7 & Table 11 for details.  
LOAD  
PFS1  
PFS0  
During Master Reset, select one of eight default-offset values. Use in conjunction with LOAD  
and PFS0. Refer to Table 11 for details.  
During Master Reset, select one of eight default-offset values. Use in conjunction with LOAD and  
PFS1. Refer to Table 11 for details.  
18 - bit wide input data bus.  
D17-0  
RCLK  
Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the  
EMPTY /QRDY and PRAE flags. RCLK and WCLK are independent of each other.  
Reads data from queue or offset registers during low to high transitions of RCLK if REN is set low. This  
also advances the Read pointer of the queue.  
REN  
OE  
Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers  
(High-Z). OE does not control advancement of Read pointer.  
18 - bit wide output data bus.  
Q17-0  
FWFT/SDI  
Selects FWFT timing or Standard timing mode during Master Reset. After Master Reset, if serial  
programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for the offset  
registers. Serial data is written during the low to high transition of WCLK. Use in conjunction with  
SDEN . In FWFT mode, DRDY and QRDY is used instead of FULL and EMPTY . Refer to Table 9  
for all flags status. In Standard mode, FULL and EMPTY are used instead of DRDY and QRDY .  
Refer to Table 8 for all flags status.  
SDEN  
If serial programming is selected, setting SDEN low and LOAD low enables serial data to be written into  
offset registers during the low to high transition of WCLK. During serial programming, PRAF and  
PRAE flags status are invalid. Refer to Figure 7 for details.  
JANUARY 2003  
3F30918C  
Page 14 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Pin Functions (Continued)  
During Master Reset, setting BM1 low selects x18 input bus width. Set BM1 high selects x9 input bus  
width. Refer to Table 10 for details.  
BM1  
BM0  
ES  
During Master Reset, set BM0 low to select x18 output bus width. Set BM0 high to select x9 output  
bus width. Refer to Table 10 for details.  
During Master Reset, Set ES high to select byte re-ordering on data outputs or set ES low to select no  
byte re-ordering on data outputs. ES must be static throughout device operation. Refer to Table 10 for  
details.  
RET  
Data previously read from the queue can be retransmitted by asserting RET pin at the low to high  
transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence,  
all re-reads will always start from the physical 0th (Read pointer = zero), location of the queue. Refer to  
Diagram 7 & 8 for details.  
RETZL  
During Master Reset, set RETZL low to select zero latency retransmit or set RETZL high to select  
normal latency retransmit.  
FULL / DRDY  
In Standard mode, queue is full when FULL goes low during the low to high transition of WCLK. This  
prohibits further writes into the queue and prevents advancement of Write pointer. In FWFT mode,  
queue is full when DRDY goes high during the low to high transition of WCLK. This prohibits further  
writes into the queue and prevents advancement of Write pointer. Refer to Table 8 & 9 for behavior of  
FULL / DRDY .  
EMPTY / QRDY In Standard mode, queue is empty when EMPTY goes low during the low to high transition of RCLK.  
This prohibits further reads from the queue and prevents advancement of Read pointer. In FWFT mode,  
queue is empty when QRDY goes high during the low to high transition of RCLK. This prohibits  
further reads from the queue and prevents advancement of Read pointer. Refer to Table 8 & 9 for  
behavior of EMPTY / QRDY .  
During Master Reset, set IPAR low to select 9-bit parallel programming mode or set IPAR high to  
select 8-bit parallel programming mode. In 9-bit mode, 9-bit wide data input/output bus width is used  
for storing/fetching offset values. In 8-bit mode, 8-bit wide data input/output bus is used for  
storing/fetching offset values.  
IPAR  
SFM  
During Master Reset, set SFM high to select Synchronous Partial Flag mode or set SFM low to select  
Asynchronous Partial Flag mode. In Synchronous mode, PRAF and PRAE are synchronous to WCLK  
and RCLK respectively. In Asynchronous mode, WCLK synchronizes the assertion of PRAF and de-  
assertion of PRAE RCLK synchronizes the assertion of PRAE and de-assertion of PRAF .  
.
PRAF  
PRAE  
HALF  
In Synchronous mode, queue is almost full when PRAF goes low during the low to high transition of  
WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . In  
Asynchronous mode, PRAF is triggered by both WCLK and RCLK. Refer to Table 8 & 9 for behavior  
of PRAF .  
In Synchronous mode, queue is almost empty when PRAE goes low during the low to high transition of  
RCLK. Default (Empty+offset) or programmed offset values determine the status of PRAE . In  
Asynchronous timing mode, PRAE is triggered by both WCLK and RCLK. Refer to Table 8 & 9 for  
behavior of PRAE .  
Queue is more than half full when HALF goes low during the low to high transition of WCLK.  
HALF goes high during low to high transition of RCLK when queue is less than half full. Refer to  
Table 8 & 9 for details.  
JANUARY 2003  
3F30918C  
Page 15 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
FQV283  
FQV273  
FQV263  
WCLK  
RCLK  
LOAD  
WEN  
REN  
SDEN  
FQV253  
FQV243  
Selection / Sequence  
Parallel write to  
Parallel write to offset  
registers:  
registers:  
Empty Offset (Low Byte)  
Empty Offset (High Byte)  
Full Offset (Low Byte)  
Full Offset (High Byte)  
1. PRAE Low Byte  
2. PRAE High Byte  
3. PRAF Low Byte  
4. PRAF High Byte  
0
0
1
1
X
Parallel read from  
Parallel read from offset  
registers:  
registers:  
Empty Offset (Low Byte)  
Empty Offset (High Byte)  
Full Offset (Low Byte)  
Full Offset (High Byte)  
1. PRAE Low Byte  
2. PRAE High Byte  
3. PRAF Low Byte  
4. PRAF High Byte  
0
0
1
1
0
1
1
0
X
x9 to x9 Mode  
Serial shift into registers:  
32 bits for the FQV283  
30 bits for the FQV273  
28 bits for the FQV263  
26 bits for the FQV253  
24 bits for the FQV243  
1 bit for each rising WCLK  
edge  
All Other Modes  
Serial shift into registers:  
30 bits for the FQV283  
28 bits for the FQV273  
26 bits for the FQV263  
24 bits for the FQV253  
22 bits for the FQV243  
1 bit for each rising WCLK  
edge  
Starting with Empty Offset  
(Low Byte)  
Ending with Full Offset  
(High Byte)  
X
Starting with Empty Offset  
(Low Byte)  
Ending with Full Offset  
(High Byte)  
X
1
1
0
1
1
X
X
X
No Operation  
Write Memory  
X
X
1
1
X
1
0
1
X
X
X
X
Read Memory  
No Operation  
X
Figure 7. Programmable Flag Offset Programming Sequence (FQV283, FQV273, FQV263, FQV253 and FQV243)  
JANUARY 2003  
3F30918C  
Page 16 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
FQV2113  
FQV2103  
WCLK  
RCLK  
SDEN  
LOAD  
REN  
WEN  
FQV293  
Selection / Sequence  
Parallel write to  
Parallel write to offset  
registers:  
registers:  
Empty Offset (Low Byte)  
Empty Offset (Mid Byte)  
Empty Offset (High Byte)  
Full Offset (Low Byte)  
Full Offset (Mid Byte)  
Full Offset (High Byte)  
1. PRAE Low Byte  
2. PRAE Mid Byte  
3. PRAE High Byte  
4. PRAF Low Byte  
5. PRAF Mid Byte  
6. PRAF High Byte  
0
0
1
1
X
Parallel read from  
Parallel read from offset  
registers:  
registers:  
Empty Offset (Low Byte)  
Empty Offset (Mid Byte)  
Empty Offset (High Byte)  
Full Offset (Low Byte)  
Full Offset (Mid Byte)  
Full Offset (High Byte)  
1. PRAE Low Byte  
2. PRAE Mid Byte  
3. PRAE High Byte  
4. PRAF Low Byte  
5. PRAF Mid Byte  
6. PRAF High Byte  
0
0
1
1
0
1
1
0
X
x9 to x9 Mode  
Serial shift into registers:  
38 bits for the FQV2113  
36 bits for the FQV2103  
34 bits for the FQV293  
1 bit for each rising WCLK  
edge  
Starting with Empty Offset  
(Low Byte)  
Ending with Full Offset  
(High Byte)  
All Other Modes  
Serial shift into registers:  
36 bits for the FQV2113  
34 bits for the FQV2103  
32 bits for the FQV293  
1 bit for each rising WCLK  
edge  
Starting with Empty Offset  
(Low Byte)  
Ending with Full Offset  
(High Byte)  
X
X
1
1
0
1
1
X
X
X
No Operation  
X
X
Write Memory  
1
1
X
1
0
1
X
X
X
X
Read Memory  
No Operation  
X
Figure 8. Programmable Flag Offset Programming Sequence (FQV2113, FQV2103, FQV293)  
JANUARY 2003  
3F30918C  
Page 17 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Device  
PRAF Programming (bits)  
PRAE Programming (bits)  
D/Q15 - 0  
Non-IPAR  
D/Q15 - 0  
Non-IPAR  
FQV2113  
D/Q16 – 9 & D/Q7 – 0  
D/Q15 - 0  
IPAR  
D/Q16 – 9 & D/Q7 – 0  
D/Q15 - 0  
IPAR  
Non-IPAR  
IPAR  
Non-IPAR  
IPAR  
FQV2103  
FQV293  
FQV283  
FQV273  
FQV263  
FQV253  
FQV243  
D/Q16 – 9 & D/Q7 – 0  
D/Q15 - 0  
D/Q16 – 9 & D/Q7 – 0  
D/Q15 - 0  
Non-IPAR  
IPAR  
Non-IPAR  
IPAR  
D/Q16 – 9 & D/Q7 – 0  
D/Q14 - 0  
D/Q16 – 9 & D/Q7 – 0  
D/Q14 - 0  
Non-IPAR  
IPAR  
Non-IPAR  
IPAR  
D/Q15 – 9 & D/Q7 – 0  
D/Q13 - 0  
D/Q15 – 9 & D/Q7 – 0  
D/Q13 - 0  
Non-IPAR  
IPAR  
Non-IPAR  
IPAR  
D/Q14 – 9 & D/Q7 – 0  
D/Q12 - 0  
D/Q14 – 9 & D/Q7 – 0  
D/Q12 - 0  
Non-IPAR  
IPAR  
Non-IPAR  
IPAR  
D/Q13 – 9 & D/Q7 – 0  
D/Q11 - 0  
D/Q13 – 9 & D/Q7 – 0  
D/Q11 - 0  
Non-IPAR  
IPAR  
Non-IPAR  
IPAR  
D/Q12 – 9 & D/Q7 – 0  
D/Q10 - 0  
D/Q12 – 9 & D/Q7 – 0  
D/Q10 - 0  
Non-IPAR  
IPAR  
Non-IPAR  
IPAR  
D/Q11 – 9 & D/Q7 – 0  
D/Q11 – 9 & D/Q7 – 0  
Condition Applies to: Write Cycle with x18 input Bus Width and/or  
Read Cycle with x18 output Bus Width  
Device  
PRAF Programming (bits)  
D/Q7 - 0  
PRAE Programming (bits)  
Low Byte  
Mid Byte  
High Byte  
Low Byte  
Mid Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
D/Q7 - 0  
D/Q7 - 0  
D/Q1 - 0  
D/Q7 - 0  
D/Q7 - 0  
D/Q 0  
Low Byte  
FQV2113  
D/Q7 - 0  
D/Q1 - 0  
D/Q7 - 0  
D/Q7 - 0  
D/Q0  
D/Q7 - 0  
D/Q7 - 0  
D/Q7 - 0  
D/Q6 - 0  
D/Q7 - 0  
D/Q5 - 0  
D/Q7 - 0  
D/Q4 - 0  
D/Q7 - 0  
D/Q3 - 0  
D/Q7 - 0  
D/Q2 - 0  
Mid Byte  
High Byte  
Low Byte  
Mid Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
FQV2103  
D/Q7 - 0  
D/Q7 - 0  
D/Q7 - 0  
D/Q6 - 0  
D/Q7 - 0  
D/Q5 - 0  
D/Q7 - 0  
D/Q4 - 0  
D/Q7 - 0  
D/Q3 - 0  
D/Q7 - 0  
D/Q2 - 0  
FQV293  
FQV283  
FQV273  
FQV263  
FQV253  
FQV243  
Condition Applies to: Write Cycle with x9 input Bus Width or  
Read Cycle with x9 output Bus Width (except x9 to x9 mode)  
JANUARY 2003  
3F30918C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 18 of 43  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Device  
PRAF Programming (bits)  
PRAE Programming (bits)  
D/Q7 - 0  
D/Q7 - 0  
D/Q7 - 0  
D/Q2 - 0  
D/Q7 - 0  
D/Q7 - 0  
D/Q1 - 0  
D/Q7 - 0  
D/Q7 - 0  
D/Q0  
D/Q7 - 0  
D/Q7 - 0  
D/Q7 - 0  
D/Q6 - 0  
D/Q7 - 0  
D/Q5 - 0  
D/Q7 - 0  
D/Q4 - 0  
D/Q7 - 0  
D/Q3 - 0  
Low Byte  
Mid Byte  
High Byte  
Low Byte  
Mid Byte  
High Byte  
Low Byte  
Mid Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
Mid Byte  
High Byte  
Low Byte  
Mid Byte  
High Byte  
Low Byte  
Mid Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
Low Byte  
High Byte  
FQV2113  
D/Q7 - 0  
D/Q2 - 0  
D/Q7 - 0  
D/Q7 - 0  
D/Q1 - 0  
D/Q7 - 0  
D/Q7 - 0  
D/Q0  
D/Q7 - 0  
D/Q7 - 0  
D/Q7 - 0  
D/Q6 - 0  
D/Q7 - 0  
D/Q5 - 0  
D/Q7 - 0  
D/Q4 - 0  
D/Q7 - 0  
D/Q3 - 0  
FQV2103  
FQV293  
FQV283  
FQV273  
FQV263  
FQV253  
FQV243  
Condition Applies to: Write Cycle with x9 input Bus Width and  
Read Cycle with x9 output Bus Width (only x9 to x9 mode)  
Table 6. Parallel Offset Write/Read Cycle Register Location  
Device  
Standard Mode  
FWFT Mode  
FQV2113  
FQV2103  
FQV293  
FQV283  
FQV273  
FQV263  
FQV253  
FQV243  
262,144 x 18 / 524,288 x9 262,145 x 18 / 524,289 x9  
131,072 x 18 / 262,144 x9 131,073 x 18 / 262,145 x 9  
65,536 x 18 / 131,072 x 9  
32,768 x 18 / 65,536 x 9  
16,384 x 18 / 32,768 x 9  
8,192 x 18 / 16,384 x 9  
4,096 x 18 / 8,192 x 9  
2,048 x 18 / 4,096 x 9  
65,537,x 18 / 131,073 x 9  
32,769 x 18 / 65,537 x 9  
16,385 x 18 / 32,769 x 9  
8,193 x 18 / 16,385 x 9  
4,097 x 18 / 8,193 x 9  
2,049 x 18 / 4,097 x 9  
Table 7. Maximum Depth of Queue for Standard and FWFT Mode  
JANUARY 2003  
3F30918C  
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Page 19 of 43  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0  
Data Width  
7
6
5
3
1
4
2
0
8
1st Cycle PRAE Low Byte  
15  
14  
13  
12  
11  
10  
9
High Byte  
PRAE  
2nd Cycle  
7
6
5
3
1
4
2
0
8
PRAF  
3rd Cycle  
4th Cycle  
Low Byte  
15  
14  
13  
12  
11  
10  
9
PRAF High Byte  
FQV293, FQV283, FQV273, FQV263, FQV253, FQV243  
Parallel Offset Write/Read Cycles for x9 Bus Width  
Condtion Applies to: Write Cycle with x9 input Bus Width  
and/or Read Cycle output with x9 Bus Width  
(except FQV293 x9 to x9 mode)  
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0  
Data Width  
1
7
6
5
4
3
2
0
PRAE Low Byte  
1st Cycle  
2nd Cycle  
15  
14  
13  
12  
11  
10  
9
8
PRAE  
Mid Byte  
18  
17  
16  
3rd Cycle PRAE High Byte  
1
7
6
5
4
3
2
0
Low Byte  
Mid Byte  
High Byte  
PRAF  
4th Cycle  
15  
14  
13  
12  
11  
10  
9
8
5th Cycle PRAF  
6th Cycle PRAF  
18  
17  
16  
FQV2113, FQV2103, FQV293  
Parallel Offset Write/Read Cycles for x9 Bus Width  
Condtion Applies to: FQV293 x9 to x9 mode or  
FQV2113, FQV2103 for all modes  
x9 to x9 Mode  
All Other Modes  
# of Bits for Offset Registers  
# of Bits for Offset Registers  
19 bits for FQV2113  
18 bits for FQV2103  
17 bits for FQV293  
16 bits for FQV283  
15 bits for FQV273  
14 bits for FQV263  
13 bits for FQV253  
12 bits for FQV243  
18 bits for FQV2113  
17 bits for FQV2103  
16 bits for FQV293  
15 bits for FQV283  
14 bits for FQV273  
13 bits for FQV263  
12 bits for FQV253  
11 bits for FQV243  
Note: Don’t Care applies to all unused bits  
Note: Don’t Care applies to all unused bits  
Figure 9. Parallel Offset Write/Read Cycle Diagram  
JANUARY 2003  
3F30918C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 20 of 43  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0  
Data Width  
1st Cycle PRAE  
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
15  
14  
14  
13  
13  
12  
12  
11  
11  
10  
10  
9
9
8
8
Non-Interspersed Parity  
15  
Interspersed Parity  
Data Width  
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0  
2nd Cycle PRAF  
Non-Interspersed Parity  
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
15  
14  
14  
13  
13  
12  
12  
11  
11  
10  
10  
9
9
8
8
Interspersed Parity  
15  
FQV293, FQV283, FQV273, FQV263, FQV253, FQV243  
Parallel Offset Write/Read Cycles for x18 Bus Width  
Condtion Applies to: Write Cycle with x18 input Bus Width  
and/or Read Cycle for x18 output Bus Width  
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0  
Data Width  
1st Cycle  
PRAE  
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
15  
14  
14  
13  
13  
12  
12  
11  
11  
10  
10  
9
9
8
8
Non-Interspersed Parity  
15  
Interspersed Parity  
2nd CyclePRAE  
17  
17  
16  
16  
Non-Interspersed Parity  
Interspersed Parity  
3rd Cycle PRAF  
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
15  
14  
14  
13  
13  
12  
12  
11  
11  
10  
10  
9
9
8
8
Non-Interspersed Parity  
15  
Interspersed Parity  
4th Cycle  
PRAF  
17  
17  
16  
16  
Non-Interspersed Parity  
Interspersed Parity  
FQV2113, FQV2103  
Parallel Offset Write/Read Cycles for x18 Bus Width  
Condtion Applies to: Write Cycle with x18 input Bus Width  
and/or Read Cycle for x18 output Bus Width  
Figure 9. Parallel Offset Write/Read Cycles Diagram (Continued)  
JANUARY 2003  
3F30918C  
Page 21 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
FQV2113  
BM1 = BM0 = x9  
FULL  
EMPTY  
PRAF  
HALF  
PRAE  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y(1)  
(y+1) to 262,144  
262,145 to [524,288-(x+1)]  
(524,288 -x(1)) to 524,287  
524,288  
H
H
H
H
L
FQV2103  
FQV2113  
BM1 = BM0 = x9  
BM1 BM0 or BM1 = BM0 = x18  
FULL  
EMPTY  
PRAF  
HALF  
PRAE  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y  
(y+1) to 131,072  
H
H
H
H
131,073 to [262,144-(x+1)]  
(262,144 -x) to 262,143  
262,144  
L
FQV293  
FQV2103  
BM1 = BM0 = x9  
BM1 BM0 or BM1 = BM0 = x18  
FULL  
EMPTY  
PRAF  
HALF  
PRAE  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y  
(y+1) to 65,536  
H
H
H
H
65,537 to [131,072-(x+1)]  
(131,072 -x) to 131,071  
131,072  
L
FQV283  
FQV293  
BM1 = BM0 = x9  
BM1 BM0 or BM1 = BM0 = x18  
FULL  
EMPTY  
PRAF  
HALF  
PRAE  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y  
(y+1) to 32,768  
32,769 to [65,536-(x+1)]  
(65,536 -x) to 65,535  
65,536  
H
H
H
H
L
FQV273  
FQV283  
BM1 = BM0 = x9  
BM1 BM0 or BM1 = BM0 = x18  
FULL  
EMPTY  
PRAF  
HALF  
PRAE  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y  
(y+1) to 16,384  
16,385 to [32,768-(x+1)]  
(32,768 -x) to 32,767  
32,768  
H
H
H
H
L
NOTES:  
1.  
See Table 11 for values x, y.  
Table 8. Status Flags (Standard Mode)  
JANUARY 2003  
3F30918C  
Page 22 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
FQV263  
FQV273  
BM1 = BM0 = x9  
BM1 BM0 or BM1 = BM0 = x18  
FULL  
EMPTY  
PRAF  
HALF  
PRAE  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y  
(y+1) to 8,192  
8,193 to [16,384-(x+1)]  
(16,384 –x) to 16,383  
16,384  
H
H
H
H
L
FQV253  
FQV263  
BM1 = BM0 = x9  
BM1 BM0 or BM1 = BM0 = x18  
FULL  
EMPTY  
PRAF  
HALF  
PRAE  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y  
(y+1) to 4,096  
4,097 to [8,192-(x+1)]  
(8,192 –x) to 8,191  
8,192  
H
H
H
H
L
FQV243  
FQV253  
BM1 = BM0 = x9  
BM1 BM0 or BM1 = BM0 = x18  
FULL  
EMPTY  
PRAF  
HALF  
PRAE  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y  
(y+1) to 2,048  
2,049 to [4,096-(x+1)]  
(4,096 –x) to 4,095  
4,096  
H
H
H
H
L
FQV243  
BM1 BM0 or BM1 = BM0 = x18  
FULL  
EMPTY  
PRAF  
HALF  
PRAE  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y  
(y+1) to 1,024  
1,025 to [2,048-(x+1)]  
(2,048–x) to 2,047  
2,048  
H
H
H
H
L
NOTES:  
1.  
See Table 11 for values x, y.  
Table 8. Status Flags (Standard Mode) (Continued)  
JANUARY 2003  
3F30918C  
Page 23 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
FQV2113  
BM1 = BM0 = x9  
QRDY  
DRDY  
PRAF  
HALF  
PRAE  
H
H
H
L
L
L
0
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
L
L
L
L
1 to y+1(1)  
(y+2) to 262,145  
262,146 to [524,289-(x+1)]  
(524,289-x(1)) to 524,288  
524,289  
H
H
H
H
L
FQV2103  
FQV2113  
BM1 = BM0 = x9  
BM1 BM0 or BM1 = BM0 = x18  
QRDY  
DRDY  
PRAF  
HALF  
PRAE  
H
H
H
L
L
L
0
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
L
L
L
L
1 to y+1  
(y+2) to 131,073  
H
H
H
H
131,074 to [262,145-(x+1)]  
(262,145-x) to 262,144  
262,145  
L
FQV293  
FQV2103  
BM1 = BM0 = x9  
BM1 BM0 or BM1 = BM0 = x18  
QRDY  
DRDY  
PRAF  
HALF  
PRAE  
H
H
H
L
L
L
0
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
L
L
L
L
1 to y+1  
(y+2) to 65,537  
H
H
H
H
65,538 to [131,073-(x+1)]  
(131,073-x) to 131,072  
131,073  
L
FQV283  
FQV293  
BM1 = BM0 = x9  
BM1 BM0 or BM1 = BM0 = x18  
QRDY  
DRDY  
PRAF  
HALF  
PRAE  
H
H
H
L
L
L
0
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
L
L
L
L
1 to y+1  
(y+2) to 32,769  
32,770 to [65,537-(x+1)]  
(65,537 -x) to 65,536  
65,537  
H
H
H
H
L
FQV273  
FQV283  
BM1 = BM0 = x9  
BM1 BM0 or BM1 = BM0 = x18  
QRDY  
DRDY  
PRAF  
HALF  
PRAE  
H
H
H
L
L
L
0
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
L
L
L
L
1 to y+1  
(y+2) to 16,385  
16,386 to [32,769-(x+1)]  
(32,769-x) to 32,768  
32,769  
H
H
H
H
L
NOTES:  
1.  
See Table 11 for values x, y.  
Table 9. Status Flags (FWFT Mode)  
JANUARY 2003  
3F30918C  
Page 24 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
FQV263  
FQV273  
BM1 = BM0 = x9  
BM1 BM0 or BM1 = BM0 = x18  
QRDY  
DRDY  
PRAF  
HALF  
PRAE  
H
H
H
L
L
L
0
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
L
L
L
L
1 to y+1  
(y+2) to 8,193  
8,194 to [16,385-(x+1)]  
(16,385 -x) to 16,384  
16,385  
H
H
H
H
L
FQV253  
FQV263  
BM1 = BM0 = x9  
BM1 BM0 or BM1 = BM0 = x18  
QRDY  
DRDY  
PRAF  
HALF  
PRAE  
H
H
H
L
L
L
0
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
L
L
L
L
1 to y+1  
(y+2) to 4,097  
4,098 to [8,193-(x+1)]  
(8,193 -x) to 8,192  
8,193  
H
H
H
H
L
FQV243  
FQV253  
BM1 = BM0 = x9  
BM1 BM0 or BM1 = BM0 = x18  
QRDY  
DRDY  
PRAF  
HALF  
PRAE  
H
H
H
L
L
L
0
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
L
L
L
L
1 to y+1  
(y+2) to 2,049  
2,050 to [4,097-(x+1)]  
(4,097-x) to 4,096  
4,097  
H
H
H
H
L
FQV243  
BM1 BM0 or BM1 = BM0 = x18  
QRDY  
DRDY  
PRAF  
HALF  
PRAE  
H
H
H
L
L
L
0
L
L
L
L
L
H
H
H
H
H
L
L
L
H
L
L
L
L
L
1 to y+1  
(y+2) to 1,025  
1,026 to [2,049 -(x+1)]  
(2,049 -x) to 2,048  
2,049  
H
H
H
H
L
NOTES:  
1.  
See Table 11 for values x, y.  
Table 9. Status Flags (FWFT Mode) (Continued)  
JANUARY 2003  
3F30918C  
Page 25 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
ES  
BM1  
BM0  
I/O  
Width  
D/Q17 - 9  
D/Q8 – 0  
Sequence  
0
0
0
I
O
18  
18  
Byte 2  
Byte 2  
Byte 1  
Byte 1  
1st Write  
1st Read  
0
0
0
1
1
1
0
1
I
O
18  
9
Byte 2  
X
X
Byte 1  
Byte 2  
Byte 1  
1st Write  
1st Read  
2nd Read  
I
O
I
9
18  
9
X
X
Byte 2  
Byte 2  
Byte 1  
Byte 1  
1st Write  
2nd Write  
1st Read  
X
X
X
X
X
Byte 2  
Byte 1  
Byte 2  
Byte 1  
1st Write  
2nd Write  
1st Read  
2nd Read  
O
9
1
1
0
0
0
1
I
O
18  
18  
Byte 2  
Byte 1  
Byte 1  
Byte 2  
1st Write  
1st Read  
I
O
18  
9
Byte 2  
X
X
Byte 1  
Byte 1  
Byte 2  
1st Write  
1st Read  
2nd Read  
1
1
0
I
9
X
X
Byte 1  
Byte 2  
Byte 1  
Byte 2  
1st Write  
2nd Read  
1st Read  
O
18  
Table 10. Bus-Matching Table  
JANUARY 2003  
3F30918C  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 26 of 43  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
FQV273  
FQV243  
FQV263  
Offsets x, y  
FQV253  
PFS0  
PFS1  
LOAD  
All Other  
Modes  
x9 to x9 Mode  
Offsets x, y  
0
0
0
0
1
1
1
1
1
0
0
0
0
1
127  
511  
255  
63  
31  
15  
7
127  
511  
255  
63  
127  
511  
255  
63  
1
0
1
1
0
0
1,023  
31  
1,023  
31  
0
1
1
0
15  
15  
1
1
3
7
7
X
X
X
X
Serial  
Parallel  
FQV2113  
FQV2103  
FQV293  
FQV283  
Offsets x, y  
PFS0  
PFS1  
LOAD  
All Other  
x9 to x9 Mode  
Offsets x, y  
Modes  
0
0
0
0
1
1
1
1
1
0
0
0
0
1
127  
127  
16,383  
8,191  
4,095  
1,023  
2,047  
511  
127  
16,383  
8,191  
4,095  
1,023  
2,047  
511  
511  
255  
63  
1
0
1
1
0
0
1,023  
31  
0
1
1
0
15  
1
1
7
255  
255  
X
X
X
X
Serial  
Parallel  
NOTES:  
1.  
x = PRAF offset, y = PRAE offset.  
Table 11. Default Programmable Flag Offsets  
JANUARY 2003  
3F30918C  
Page 27 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Timing Diagrams  
tRST  
MRST  
tRSTR  
tRSTR  
tRSTS  
tRSTS  
tRSTS  
tRSTS  
tRSTS  
REN  
WEN  
tRSTR  
FWFT/SDI  
tRSTR  
LOAD  
PFS1/PFS0  
tRSTS  
BM1/BM0  
ES  
tRSTS  
tRSTS  
tRSTS  
tRSTS  
tRSTS  
tRSTS  
RETZL  
SFM  
IPAR  
RET  
SDEN  
tRSTF  
tRSTF  
tRSTF  
tRSTF  
tRSTF  
If FWFT = 1,QRDY = 1  
If FWFT = 0,EMPTY= 0  
EMPTY/QRDY  
FULL/ DRDY  
PRAE  
If FWFT = 0,FULL = 1  
If FWFT = 1,DRDY = 0  
PRAF, HALF  
OE = 1  
OE = 0  
Q17- 0  
Diagram 1. Master Reset Timing  
JANUARY 2003  
3F30918C  
Page 28 of 43  
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
tRST  
PRST  
REN  
tRSTR  
tRSTR  
tRSTS  
tRSTS  
tRSTS  
tRSTS  
WEN  
RET  
SDEN  
EMPTY/QRDY  
FULL/ DRDY  
PRAE  
tRSTF  
tRSTF  
tRSTF  
tRSTF  
tRSTF  
If FWFT = 1,QRDY = 1  
If FWFT = 0,EMPTY= 0  
If FWFT = 0,FULL = 1  
If FWFT = 1,  
= 0  
DRDY  
PRAF, HALF  
OE = 1  
OE = 0  
Q17 - 0  
Diagram 2. Partial Reset Timing  
JANUARY 2003  
3F30918C  
Page 29 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
JANUARY 2003  
3F30918C  
Page 30 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
JANUARY 2003  
3F30918C  
Page 31 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
JANUARY 2003  
3F30918C  
Page 32 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
JANUARY 2003  
3F30918C  
Page 33 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
RCLK  
REN  
2
1
ENS  
ENH  
RETS  
ENS  
ENH  
t
t
t
t
t
A
A
t
A
t
t
Q 17 - 0  
DWi  
DWi+1  
DW1  
DW2  
SKEW2  
t
WCLK  
WEN  
1
2
RETS  
t
ENS  
ENH  
t
t
RET  
EMPTY  
PRAE  
EMPTY  
EMPTY  
t
t
PRAES  
t
HALF  
t
HALF  
PRAFS  
t
PRAF  
NOTES:  
1.  
2.  
3.  
4.  
Upon completion of retransmit setup, a read operation can begin only after EMPTY returns high.  
OE = Low.  
DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.  
Upon reset completion, there must be more than two words written to the queue for a retransmit setup to be valid.  
Diagram 7. Retransmit Timing (Standard Mode)  
JANUARY 2003  
3F30918C  
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
RCLK  
REN  
1
2
3
4
tENS  
tENH  
tRETS  
tENS  
tENH  
tA  
tA  
tA  
tA  
Q 17 - 0  
WCLK  
WEN  
DWi  
DWi+1  
DW1  
DW2  
DW3  
DW4  
tSKEW2  
1
2
tRETS  
tENS  
tENH  
RET  
QRDY  
PRAE  
tEMPTY  
tEMPTY  
tPRAES  
tHALF  
HALF  
PRAF  
tPRAFS  
NOTES:  
1.  
2.  
3.  
4.  
5.  
Upon completion of retransmit setup, a read operation can begin only after QRDY returns low.  
OE = Low.  
DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.  
Upon reset completion, there must be more than two words written to the queue for a retransmit setup to be valid.  
Please refer to Table 7 for Depth.  
Diagram 8. Retransmit Timing (FWFT Mode)  
JANUARY 2003  
3F30918C  
Page 35 of 43  
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
RCLK  
1
2
3
tENS  
tENH  
REN  
tA  
tA  
tA  
tA  
tA  
Q 17 - 0  
DWi+1  
DW1  
DW2  
DW3  
DW4  
DWi  
tSKEW2  
WCLK  
1
2
tRETS  
WEN  
RET  
tENS  
tENH  
EMPTY  
tPRAES  
PRAE  
HALF  
tHALF  
tPRAFS  
PRAF  
NOTES:  
1.  
If the part is empty at the point of retransmit, the Empty Flag ( EMPTY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will  
appear on the output.  
2.  
3.  
4.  
OE = Low; enables data to be read on outputs Q17 – 0.  
DW1= first word written to the queue after Master Reset; DW2= second word written to the queue after Master Reset.  
No more than D-2 may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, FULL will be high throughout the  
retransmit setup procedure. Please refer to Table 7 for Depth.  
5.  
6.  
There must be at least two words written to zero latency retransmit from the queue before a retransmit operation can be invoked.  
RETZL is set Low during MRST .  
Diagram 9. Zero Latency Retransmit Timing (Standard Mode)  
JANUARY 2003  
3F30918C  
Page 36 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
RCLK  
REN  
1
2
3
4
5
tENH  
tENS  
tA  
tA  
tA  
tA  
tA  
tA  
DWi  
DW i+1  
DW1  
DW2  
DW3  
DW4  
Q 17 - 0  
WCLK  
WEN  
DW5  
tSKEW2  
1
2
tRETS  
tENS  
tENH  
RET  
QRDY  
tPRAES  
PRAE  
HALF  
tHALF  
tPRAFS  
PRAF  
NOTES:  
1.  
If the part is empty at the point of retransmit, the output ready flag ( QRDY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will  
appear on the output.  
2.  
No more than D-2 words may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, DRDY will be low throughout  
the retransmit setup procedure. Please refer to Table 7 for Depth.  
3.  
4.  
5.  
6.  
OE = Low.  
DW1, DW2, DW3 = first, second and third words written to the queue after Master Reset.  
There must be at least two words written to the queue before a retransmit operation can be invoked.  
RETZL is set low during MRST .  
Diagram 10. Zero Latency Retransmit Timing (FWFT Mode)  
JANUARY 2003  
3F30918C  
Page 37 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
WCLK  
SDEN  
tENS  
tLOADS  
tDS  
tENH  
tENH  
tLOADH  
tDH  
tLOADH  
LOAD  
SDI  
BIT 0  
BIT MSB  
BIT 0  
BIT MSB  
PRAE  
Offset  
PRAF Offset  
*Refer to Table 12  
Diagram 11. Serial Loading of Programmable Flag Registers (Standard and FWFT Mode)  
FQV21113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV253 FQV243  
MSB for x9 to x9  
18  
17  
17  
16  
16  
15  
15  
14  
14  
13  
13  
12  
12  
11  
11  
10  
MSB for All  
Other Modes  
Table 12. Reference Table for Diagram 11  
JANUARY 2003  
3F30918C  
Page 38 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
tWCLK  
tWCLKH  
tWCLKL  
WCLK  
tLOADS  
tLOADH  
tLOADH  
tENH  
LOAD  
tENS  
tDS  
tENH  
WEN  
tDH tDS  
tDH tDS  
tDH tDS  
tDH  
D 17 - 0  
PRAE offset  
(Low Byte)  
PRAE offset  
(High Byte)  
PRAF offset  
(Low Byte)  
PRAF offset  
(High Byte)  
NOTES:  
1.  
Based on programming the x18 bus width. For the x9 bus width, add one extra cycle to both _P__R___A___E__ and _P__R___A___F__ offsets.  
Diagram 12. Parallel Loading of Programmable Flag Registers (Standard and FWFT Mode)  
tRCLK  
tRCLKH  
tRCLKL  
RCLK  
tLOADH  
tENH  
tLOADS  
tENS  
tLOADH  
LOAD  
REN  
tENH  
tA  
tA  
tA  
tA  
Q 17 - 0  
Data Output Register  
PRAE offset  
(Low Byte)  
PRAE offset  
(High Byte)  
PRAF offset  
(Low Byte)  
PRAF offset  
(High Byte)  
NOTES:  
1.  
Based on programming the x18 bus width. For the x9 bus width, add one extra cycle to both _P__R___A___E__ and _P__R___A___F__ offsets.  
Diagram 13. Parallel Read of Programmable Flag Registers (Standard and FWFT Mode)  
JANUARY 2003  
3F30918C  
Page 39 of 43  
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FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
tWCLKH  
tWCLKL  
WCLK  
1
2
1
2
tENS  
tENH  
WEN  
tPRAFS  
tPRAFS  
D - ( x + 1 ) words  
in Queue  
PRAF  
D- x words in Queue  
D- ( x + 1 ) words in Queue  
tSKEW2  
RCLK  
REN  
tENS  
tENH  
NOTES:  
1.  
2.  
3.  
x = _P__R___A___F__ offset.  
D = maximum queue depth. Please refer to Table 7 for Depth.  
___________  
If the time between a rising edge of RCLK to the rising edge of WCLK is greater or equal than tSKEW2, PRAF will go high (after one WCLK cycle plus  
tPRAFS). If tSKEW2 is not met, then _P__R___A___F__ will assert 1 or more WCLK cycles.  
___________  
4.  
PRAF synchronizes to the rising edge of WCLK only.  
Diagram 14. Synchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)  
tWCLKH  
tWCLKL  
WCLK  
tENS  
tENH  
WEN  
y words in Queue(2)  
y+1 words in Queue(3)  
;
y words in Queue(2) ; y+1 words in Queue(3)  
y+1 words in Queue(2) ; y+2 words in Queue(3)  
PRAE  
tSKEW2  
tPRAES  
tPRAES  
RCLK  
REN  
1
2
1
2
tENS  
tENH  
NOTES:  
1.  
2.  
3.  
4.  
y = _P__R___A___E__ offset.  
For Standard Mode.  
For FWFT Mode.  
If the time between a rising edge of WCLK to the rising edge of RCLK is greater or equal than tSKEW2, _P__R___A___E__ will go high (after one RCLK cycle plus  
tPRAES). If tSKEW2 is not met, then _P__R___A___E__ will assert 1 or more RCLK cycles.  
___________  
5.  
PRAE synchronizes to the rising edge of RCLK only.  
Diagram 15. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)  
JANUARY 2003  
3F30918C  
Page 40 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
tWCLKH  
tWCLKL  
WCLK  
WEN  
tENS  
tENH  
tPRAFA  
D - x words in  
D - ( x + 1) words in Queue  
D - ( x + 1) words in Queue  
Queue  
PRAF  
RCLK  
tPRAFA  
tENH  
tENS  
REN  
NOTES:  
1.  
2.  
3.  
4.  
x = _P__R___A___F__ offset.  
D = maximum queue depth. Please refer to Table 7 for Depth.  
___________  
PRAF is asserted to low on WCLK transition and reset to high on RCLK transition.  
Select this mode by setting SFM low during Master Reset.  
Diagram 16. Asynchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)  
tWCLKH  
tWCLKL  
WCLK  
WEN  
tENS  
tENH  
tPRAEA  
y words in Queue(2); y+1 words in Queue(3)  
y words in Queue(2); y+1 words in Queue(3)  
y+1 words in  
Queue(2); y+2  
PRAE  
RCLK  
words in Queue (3)  
tPRAEA  
tENH  
tENS  
REN  
NOTES:  
1.  
2.  
3.  
4.  
5.  
y = _P__R___A___E__ offset.  
For Standard Mode.  
For FWFT Mode.  
___________  
PRAE is asserted to low on RCLK transition and reset to high on WCLK transition.  
Select this mode by setting SFM low during Master Reset.  
Diagram 17. Asynchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)  
JANUARY 2003  
3F30918C  
Page 41 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
tWCLKH  
tWCLKL  
WCLK  
WEN  
tENS  
tENH  
D/2 + 1 words in  
Queue(1)  
;
tHALF  
[(D+1)/2 + 1] words  
in Queue(2)  
D/2 words in Queue(1); [(D+1)/2] words in Queue(2)  
HALF  
RCLK  
D/2 words in Queue(1)  
[(D+1)/2] words in Queue(2)  
;
tHALF  
tENS  
tENH  
REN  
NOTES:  
1.  
2.  
3.  
For Standard Mode.  
For FWFT Mode.  
Please refer to Table 7 for Depth.  
Diagram 18. Half-Full Flag Timing (Standard and FWFT Mode)  
JANUARY 2003  
3F30918C  
Page 42 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
FQV2113 · FQV2103 · FQV293 · FQV283 · FQV273 · FQV263 · FQV253· FQV243  
FlexQTMIII  
Order Information:  
HBA  
Device Type  
Power Speed (ns) *  
Package** Temperature Range  
Device Family  
XX  
FQ  
XXXXX  
X
Low  
XX  
6
XX  
PF  
X
V2113 (524,288 x 9)  
166 MHz  
Blank – Commercial (0°C to 70°C)  
(262,144 x 18)  
V2103 (262,144 x 9)  
(131,072 x 18)  
7-5 – 133 MHz  
10 – 100 MHz  
15 – 66 MHz  
I – Industrial (-40° to 85°C)  
V293 (131,072 x 9)  
(65,536 x 18)  
V283 (65,536 x 9)  
(32,768 x 18)  
V273 (32,768 x 9)  
(16,384 x 18)  
V263 (16,384 x 9)  
(8,192 x 18)  
V253 (8,192 x 9)  
(4,096 x 18)  
V243 (4,096 x 9)  
(2,048 x 18)  
*Speed – 6ns available only in Commercial temp (0°C to 70°C). Slower speeds available upon request.  
**Package – 80 pin Plastic Thin Quad Flat Pack (TQFP)  
Example:  
FQV283L6PF  
(64k x 9, 6ns, Commercial temp)  
(32k x 9, 10ns, Industrial temp)  
FQV273L10PFI  
Document Revision History:  
02/26/03 pg. 1, 2, 3, 5, 6, 7, 8, 9, 10, 13, 14, 15, 20, 21, 24, 25, 27, 28, 29, 30, 31, 32, 34, 38, 39, 40, 41, 42  
USA  
Taiwan  
2107 North First Street, Suite 415  
San Jose, CA 95131, USA  
www.hba.com  
Tel: 408.453.8885  
Fax: 408.453.8886  
No. 81, Suite 8F-9, Shui-Lee Rd.  
Hsinchu, Taiwan, R.O.C.  
www.hba.com  
Tel: 886.3.516.9118  
Fax: 886.3.516.9181  
JANUARY 2003  
3F30918C  
Page 43 of 43  
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  

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