FQV36100L7.5PF [AMICC]
FIFO, 64KX36, 5ns, Synchronous, CMOS, PQFP128;
| 型号： | FQV36100L7.5PF |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | FIFO, 64KX36, 5ns, Synchronous, CMOS, PQFP128 先进先出芯片 |
| 文件： | 总43页 (文件大小：623K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
3.3 Volt Synchronous x36 First-In / First-Out Queue
FlexQTM III
Document Title
3.3 Volt Synchronous x36 First-In / First-Out Queue
Revision History
Rev. No. History
Issue Date
Remark
C
D
January 10, 2002
December 20, 2006
pg. 1,2, 6, 9, 10, 11, 12, 13, 14, 16, 27, 28, 30, 31, 39
Add Pb-Free package type
(December, 2006, Version D)
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
3.3 Volt Synchronous x36 First-In / First-Out Queue
FlexQTM III
3.3 Volt Synchronous x36 First-In/First-Out Queue
Memory Organization
131,072 x 36
Device
FQV36110
FQV36100
FQV3690
FQV3680
Memory Organization
8,192 x 36
Device
FQV3670
FQV3660
FQV3650
FQV3640
65,536 x 36
4,096 x 36
32,768 x 36
2,048 x 36
16,384 x 36
1,024 x 36
Key Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Industry leading First-In/First-Out Queues (up to 166MHz)
Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns)
Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns)
User selectable input and output ports bus-sizing
Big Endian/Little Endian user selectable byte representation
3.3V power supply
5V input tolerant on all control and data input pins
5V output tolerant on all flags and data output pins
Master Reset clears all previously programmed configurations including Write and Read pointers
Partial Reset clears Write and Read pointers but maintains all previously programmed configurations
First Word Fall Through (FWFT) and Standard Timing modes
Presets for eight different Almost Full and Almost Empty offset values
Parallel/Serial programming of PRAF and PRAE offset values
Programmable 8-bit or 9-bit parallel programming mode for offset values
Full, Empty, Almost Full, Almost Empty, and Half Full indicators
PRAF and PRAE operate in either synchronous or asynchronous mode
Asynchronous output enable tri-state data output drivers
Data retransmission with programmable zero or normal latency mode
Available package: 128 - pin Plastic Thin Quad Flat Pack (TQFP)
(0°C to 70°C) Commercial operating temperature available for cycle time of 6.0ns and above
(-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above
Product Description
AMIC’s FlexQ™ III offers industry leading FIFO queuing bandwidth (up to 6.0 Gbps), with a wide range of memory configurations (from
1,024 x 36 to 131,072 x 36). System designer has full flexibility of implementing deeper and wider queues using FWFT mode and width
expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between transmitters and receivers. User programmable
Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation of virtual queue depths.
5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous Output
Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching capability.
Master Reset clears all previously programmed configurations by providing a low pulse on MRST pin. In addition, Write and Read pointers
to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will initialize Write and Read
pointers to zero.
In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high transition of
RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when implementing depth expansion functions.
In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively.
In Standard mode, always assert REN for read operation. FULL and EMPTY are used instead of DRDY and QRDY respectively.
(December, 2006, Version D)
1
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Product Description (Continued)
Bus matching feature is available with the following memory configurations:
Input Bus Width
Output Bus Width
x9
x36
x36
x36
x18
x9
x18
x36
x36
x36
In addition, Endian Select is available for implementing byte re-ordering on data outputs.
Eight different default offset values are available for Almost Full ( PRAF ) and Almost Empty ( PRAE ) flags. Parallel and Serial
programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 9-bit parallel
programming modes for offset values can be selected for convenience.
PRAF , PRAE , and HALF are available in either FWFT or Standard mode. PRAF and PRAE can operate in either synchronous or
asynchronous mode.
At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK for a
retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0th (Read
pointer = zero) location of the queue. Both zero and normal latency timing modes are available for retransmit operation.
These FlexQ™ III devices have low power consumption, hence minimizing system power requirements. In addition, industry standard 128
- pin Plastic TQFP is offered to save system board space.
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test equipment, network
switching, etc.
(December, 2006, Version D)
2
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Block Diagram of Single Synchronous Queue
131,072 x 36 / 65,536 x 36 / 32,768 x 36 / 16,384 x 36 / 8,192 x 36 / 4,096 x 36 / 2,048 x 36 / 1,024 x 36
PARTIAL RESET (PRST)
MASTER RESET (MRST)
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
x36, x18, x9 DATA OUT (Q35 - 0
RETRANSMIT (RET)
WEN
WRITE ENABLE (
)
FQV36110
FQV36100
FQV3690
FQV3680
FQV3670
FQV3660
FQV3650
FQV3640
LOAD
LOAD (
)
)
x36, x18, x9 DATA IN (D35 - 0
)
EMPTY FLAG / OUTPUT READY
( EMPTY/ QRDY)
PROGRAMMABLE ALMOST-
EMPTY (PRAE)
SERIAL DATA ENABLE (SDEN)
FIRST WORD FALL THROUGH/
SERIAL DATA INPUT (FWFT/SDI)
FULL FLAG / INPUT READY
(
/ DRDY)
FULL
HALF-FULL FLAG (
)
HALF
PROGRAMMABLE
ALMOST-FULL (PRAF)
BIG-ENDIAN / LITTLE-ENDIAN (ES)
INTERSPERSED/NON-INTERSPERSED
PARITY (IPAR)
BUS
MATCHING 2
(BM2)
BUS
MATCHING 0
(BM0)
BUS
MATCHING 1
(BM1)
Figure 1. Single Device Configuration Signal Flow Diagram
(December, 2006, Version D)
3
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
WCLK WEN
IPAR LOAD SDEN FWFT/SDI
/
FULL DRDY
Write Control
Logic
PRAF
EMPTY/QRDY
PRAE
Offset Register
Flag Logic
HALF
FWFT/SDI
SFM
PFS1
PFS0
Write Pointer
Output
Buffer
Input Register
Output Register
SRAM
Q 35-0
x36, x18, x9
D35-0
x36, x18, x9
OE
Read Pointer
Bus
Configuration
Read Control
Logic
Reset
RCLK
ES BM2 BM1 BM0
RETZL RET
REN
MRST PRST
Figure 2. Device Architecture
(December, 2006, Version D)
4
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Index
1
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
OE
WEN
SDEN
DNC1
Vcc
2
Vcc
Vcc
Q35
Q34
Q33
3
4
DNC1
BM1
D35
D34
D33
D32
Vcc
5
6
7
Q32
8
GND
9
GND
Q31
Q30
Q29
Q28
Q27
Q26
Vcc
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
D31
D30
GND
D29
D28
D27
D26
D25
D24
D23
GND
D22
Vcc
Q25
Q24
GND
GND
Q23
Q22
Q21
Q20
Q19
Q18
GND
Q17
Q16
Vcc
Vcc
Q15
Q14
Q13
Q12
GND
Q11
Q10
D21
D20
D19
D18
GND
D17
D16
D15
D14
D13
Vcc
D12
GND
D11
TQFP - 128 (Drw No: PF-02A; Order code: PF)
Top View
NOTES:
1.
DNC = Do Not Connect.
Figure 3. Device Pin Out
(December, 2006, Version D)
5
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Pin #
Pin Name
Pin Symbol Input/Output
Description
Master Reset is required to initialize Write and Read
pointers to the first position of the queue by setting
MRST low. In Standard mode, FULL and PRAF will
go high; EMPTY and PRAE will go low. In FWFT
mode, DRDY will go low and QRDY will go high.
PRAF and PRAE will go to the same state as Standard
mode. In both modes, all data outputs will go low.
Previous programmed configurations will not be
maintained.
126
Master Reset
Input
MRST
Partial Reset is required to initialize Write and Read
pointers to the first position of the queue by setting
PRST low. In Standard mode, FULL and PRAF will
go high; EMPTY and PRAE will go low. In FWFT
mode, DRDY will go low and QRDY will go high.
PRAF and PRAE will go to the same state as Standard
mode. In both modes, all data outputs will go low.
Previous programmed configurations will be maintained.
127
Partial Reset
Input
PRST
Writes data into queue during low to high transitions of
WCLK if WEN is set to low.
128
1
Write Clock
Write Enable
WCLK
WEN
Input
Input
Controls write operation into queue or offset registers
during low to high transition of WCLK.
During Master Reset, set LOAD low to select parallel
programming and one of eight default offset values. Set
LOAD high to select serial programming and one of
eight default offset values. After Master Reset,
LOAD controls write/read, to/from offset registers during
low to high transition of WCLK/RCLK respectively. Use
in conjunction with WEN / REN .
125
Load Enable
Input
LOAD
Default
Programming 1
During Master Reset, select one of eight default offset
values. Use in conjunction with LOAD and PFS0.
115
118
PFS1
PFS0
Input
Input
Default
Programming 0
During Master Reset, select one of eight default offset
values. Use in conjunction with LOAD and PFS1.
07,08,09,
10,12,13,
15,16,17,
18,19,20,
21,23,25,
26,27,28,
30,31,32,
33,34,36,
38,39,40,
41,42,43,
45,46,47,
49,50,51.
Data Inputs
D35-0
Input
36 - bit wide input data bus.
Reads data from queue during low to high transitions of
RCLK if REN is set to low.
105
104
Read Clock
Read Enable
RCLK
REN
Input
Input
Controls read operation from queue or offset registers
during low to high transition of RCLK.
Table 1. Pin Descriptions
(December, 2006, Version D)
6
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Pin #
Pin Name
Pin Symbol
Input/Output
Description
Setting OE low activates the data output drivers. Setting
OE high deactivates the data output drivers (High-Z).
102
Output Enable
Input
OE
99,98,97,
96,93,92,
91,90,89,
88,86,85,
82,81,80,
79,78,77,
75,74,71,
70,69,68,
66,65,64,
63,62,60,
58,57,56,
55,54,53
Data Outputs
Q35-0
Output
36 - bit wide output data bus.
Selects FWFT timing or Standard timing mode during
Master Reset. After Master Reset, if serial programming
is selected ( LOAD = high), FWFT/SDI is used as the
serial data input for the offset registers. Serial data is
written during the low to high transition of WCLK. Use in
conjunction with SDEN .
First Word Fall
Through/Serial
Data Input
124
FWFT/SDI
SDEN
Input
Input
If serial programming is selected, setting SDEN low and
LOAD low enables serial data input to be written into
offset registers during the low to high transition of WCLK.
Serial Data
Input Enable
2
During Master Reset, select one of five input and output
bus width configurations. Use in conjunction with BM1
and BM0.
112
6
Bus Matching 2
Bus Matching 1
Bus Matching 0
Endian Select
BM2
BM1
BM0
ES
Input
Input
Input
Input
During Master Reset, select one of five input and output
bus width configurations. Use in conjunction with BM2
and BM0.
During Master Reset, select one of five input and output
bus width configurations. Use in conjunction with BM2
and BM1.
119
114
During Master Reset, set ES high to select byte re-ordering
on data outputs or ES low to select no byte re-ordering on
data outputs.
Data previously read from the queue can be retransmitted
by asserting RET pin at the low to high transition of
RCLK for a retransmit operation. Retransmit initializes
the Read pointer to zero. Hence, all re-reads will always
start from the physical 0th (Read pointer = zero) location of
the queue.
103
Retransmit
Input
RET
During Master Reset, set RETZL low to select zero
latency retransmit or RETZL high to select normal latency
retransmit.
Zero Latency
Retransmit
107
123
Input
RETZL
Queue is full when FULL goes low during the low to high
transition of WCLK. This prohibits further writes into the
queue. In FWFT mode, queue is full when DRDY goes
high during low to high transition of WCLK. This
prohibits further writes into the queue.
Full/Data Input
Ready Flag
Output
FULL / DRDY
Table 1. Pin Descriptions (Continued)
(December, 2006, Version D)
7
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Description
Pin #
Pin Name
Pin Symbol
Input/Output
Queue is empty when EMPTY goes low during the
low to high transition of RCLK. This prohibits further
reads from the queue. In FWFT mode, queue is empty
when QRDY goes high during the low to high
transition of RCLK. This prohibits further reads from
the queue.
Empty/Data
Output Ready
Flag
108
EMPTY / QRDY
Output
During Master Reset, set IPAR low to select 9-bit
parallel programming mode or IPAR high to select 8-
bit parallel programming mode.
Interspersed
Parity
113
109
IPAR
SFM
Input
Input
During Master Reset, set SFM high to select
Synchronous Partial Flag mode or SFM low to select
Asynchronous Partial Flag mode.
Synchronous
Partial Flag
Mode
Queue is almost full when PRAF goes low during the
low to high transition of WCLK. Default (Full-offset)
or programmed offset values determine the status of
PRAF .
121
110
Almost Full
Output
Output
PRAF
PRAE
Queue is almost empty when PRAE goes low during
the low to high transition of RCLK. Default (Empty
+offset) or programmed offset values determine the
status of PRAE .
Almost Empty
Half Full
Queue is more than half full when HALF goes low.
Triggered by both WCLK and RCLK.
117
Output
N/A
HALF
DNC
Do Not
Connect
03, 05
Do not connect.
04,11,24,
35,48,61,
72,73,87,
100,101,
111,122.
14,22,29,
37,44,52,
59,67,76,
83,84,94,
95,106,
Power
Vcc
N/A
N/A
3.3V power supply.
Ground
GND
0V Ground.
116,120
Table 1. Pin Descriptions (Continued)
(December, 2006, Version D)
8
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Symbol
Rating
Com’l & Ind’l
Unit
Terminal Voltage with
respect to GND
VTERM
-0.5 to + 4.5
-55 to +125
V
NOTES:
Absolute Max Ratings are for reference only. Permanent damage to the device may
occur if extended period of operation is outside this range. Standard operation should
fall within the Recommended Operating Conditions.
TSTG
IOUT
Storage Temperature
DC Output Current
°C
-50 to +50
mA
Table 2. Absolute Maximum Ratings
FQV36110, FQV36100, FQV3690, FQV3680, FQV3670,
FQV3660, FQV3650, FQV3640
Commercial
Industrial
Clock = 6ns, 7.5ns, 10ns, 15ns
Clock = 7.5ns, 10ns, 15ns
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Recommended Operating Conditions
Vcc
Supply Voltage Com’l / Ind’l
3.15
3.3
3.45
3.15
3.3
3.45
V
GND
VIH
VIL
TA
Supply Voltage
0
2.0
-
0
-
0
0
2.0
-
0
-
0
V
V
Input High Voltage Com’l /
Ind’l
Input Low Voltage Com’l /
Ind’l
Operating Temperature
Commercial
Operating Temperature
Industrial
5.5
0.8
70
85
5.5
0.8
70
85
-
-
V
0
-
0
-
°C
°C
TA
-40
-
-40
-
DC Electrical Characteristics
Input Leakage Current (any
input)
ILI(1)
-10
-10
2.4
-
-
-
-
-
10
10
-
-10
-10
2.4
-
-
-
-
-
10
10
-
µA
µA
V
ILO
Output Leakage Current
Output Logic “1” Voltage,
IOH=-2mA
Output Logic “0” Voltage, IOL
= 8mA
VOH
VOL
0.4
0.4
V
Power Consumption
Icc1(2,3)
Active Power Supply Current
Standby Current
-
-
-
-
40
15
-
-
-
-
40
15
mA
mA
Icc2(4)
Capacitance at 1.0MHz Ambient Temperature (25°C)
Symbol
Parameter
Conditions
Max.
Unit
(2)
CIN
COUT
NOTES:
Input Capacitance
VIN= 0V
10
10
pF
pF
(2,4)
Output Capacitance
VOUT= 0V
1.
2.
3.
4.
Measurement with 0.4<=VIN<=Vcc
With output tri-stated ( OE = High)
Icc(1,2) is measured with WCLK and RCLK at 20 MHz
Design simulated, not tested.
Table 3. DC Specifications
(December, 2006, Version D)
9
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Commercial
Commercial & Industrial
FQV36110-6
FQV36100-6
FQV3690-6
FQV3680-6
FQV3670-6
FQV3660-6
FQV3650-6
FQV3640-6
FQV36110-7.5
FQV36100-7.5
FQV3690-7.5
FQV3680-7.5
FQV3670-7.5
FQV3660-7.5
FQV3650-7.5
FQV3640-7.5
FQV36110-10
FQV36100-10
FQV3690-10
FQV3680-10
FQV3670-10
FQV3660-10
FQV3650-10
FQV3640-10
FQV36110-15
FQV36100-15
FQV3690-15
FQV3680-15
FQV3670-15
FQV3660-15
FQV3650-15
FQV3640-15
Symbol
Parameter
Clock Cycle Frequency
Min. Max. Min. Max. Min. Max. Min. Max. Unit
fS
-
1
166
4.2
-
-
2
133
-
2
100
-
2
66
10
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
A
Data Access Time
5
-
-
-
-
-
-
-
-
-
-
-
6.5
WCLK
WCLKH
WCLKL
RCLK
RCLKH
RCLKL
DS
Write Clock Cycle Time
Write Clock High Time
Write Clock Low Time
6
7.5
3.5
3.5
7.5
3.5
3.5
2.5
0.5
2.5
0.5
10
15
10
-
10
4.5
4.5
10
4.5
4.5
3.5
0.5
3.5
0.5
10
15
10
-
-
-
15
6
2.5
2.5
6
-
-
-
-
6
-
Read Clock Cycle Time
Read Clock High Time
-
-
15
6
-
2.5
2.5
1.8
0.5
1.8
0.5
8
-
-
-
Read Clock Low Time
-
-
6
-
Data Set-up Time
-
-
4
-
DH
Data Hold Time
-
-
1
-
ENS
Enable Set-up Time
-
-
4
-
ENH
Enable Hold Time
-
-
1
-
RST
Reset Pulse Width(1)
-
-
15
15
15
-
-
RSTS
RSTR
RSTF
OLZ
Reset Set-up Time
10
10
-
-
-
-
Reset Recovery Time
-
-
15
-
-
-
Reset to Flag and Output Time
Output Enable to Output in Low-Z(1)
Output Enable to Output Valid
Output Enable to Output in High-Z(1)
Write Clock to Full Flag
Read Clock to Empty Flag
Write Clock to Synchronous Almost-Full Flag
Read Clock to Synchronous Almost-Empty Flag
10
-
15
-
15
-
0
0
0
0
OE
1
4
4
4
4
4
4
2
6
2
6
2
8
8
10
10
10
10
OHZ
1
2
6
2
6
2
FULL
EMPTY
PRAFS
PRAES
-
-
5
-
6.5
6.5
6.5
6.5
-
-
-
5
-
-
-
-
5
-
-
-
-
5
-
-
Skew time between Read Clock & Write Clock
for Full Flag / Empty Flag
t
t
SKEW1
SKEW2
4
5
-
-
5
7
-
-
7
-
-
9
-
-
ns
ns
Skew time between Read Clock & Write Clock
for PRAE & PRAF
10
14
t
t
LOADS
LOADH
Load Setup Time
Load Hold Time
2.0
0.5
-
-
2.5
0.5
-
-
3.5
0.5
-
-
4
1
-
-
ns
ns
Table 4. AC Electrical Characteristics
(December, 2006, Version D)
10
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Commercial
Commercial & Industrial
FQV36110-6
FQV36100-6
FQV3690-6
FQV3680-6
FQV3670-6
FQV3660-6
FQV3650-6
FQV3640-6
FQV36110-7.5
FQV36100-7.5
FQV3690-7.5
FQV3680-7.5
FQV3670-7.5
FQV3660-7.5
FQV3650-7.5
FQV3640-7.5
FQV36110-10
FQV36100-10
FQV3690-10
FQV3680-10
FQV3670-10
FQV3660-10
FQV3650-10
FQV3640-10
FQV36110-15
FQV36100-15
FQV3690-15
FQV3680-15
FQV3670-15
FQV3660-15
FQV3650-15
FQV3640-15
Symbol
Parameter
Retransmit Setup Time
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
t
t
RETS
2.5
-
3.5
-
3.5
-
4
-
ns
ns
HALF
-
-
10
10
-
-
12.5
12.5
-
-
16
16
-
-
20
Clock to HALF
Write Clock to Asynchronous
Programmable Almost-Full Flag
t
t
PRAFA
20
20
ns
ns
Read Clock to Asynchronous
Programmable Almost-Empty Flag
PRAEA
-
10
-
12.5
-
16
-
NOTES:
1. Design simulated, not tested.
Table 4. AC Electrical Characteristics (Continued)
(December, 2006, Version D)
11
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Input Pulse Levels
GND to 3.0V
3ns(1)
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
1.5V
1.5V
Output Load, clock = 6ns, 7.5 ns
Output Load*, clock = 10ns, 15ns
Refer to Figure 4 & 6
Refer to Figure 5
* Include jig and scope capacitances
NOTES:
1. For 166 MHz and 133 MHz, operation input rise/fall times are 1.5ns.
Table 5. AC Test Condition
3.3V
Vcc/2
330Ω
50 Ω
D.U.T.
30pF*
510Ω
I/O
Z0 = 50 Ω
Figure 4. AC Test Load
for clock = 6ns, 7.5ns
Figure 5. Output Load
for clock = 10ns, 15ns
*Includes jig and scope capacitances.
4
3
2
1
20 30
50
80
100
200
Capacitance (pF)
Figure 6. Lumped Capacitive Load
(December, 2006, Version D)
12
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Pin Functions
Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting
MRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In
FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as
Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will not
be maintained.
MRST
Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting
PRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In
FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as
Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will be
maintained.
PRST
WCLK
Writes data into queue during low to high transitions of WCLK if WEN is activated. Synchronizes
FULL / DRDY and PRAF flags. WCLK and RCLK are independent of each other.
Controls write operation into queue or offset registers during low to high transition of WCLK.
WEN
During Master Reset, set LOAD low to select parallel programming or one of eight default offset values.
Set LOAD high to select serial programming or one of eight default offset values. After Master Reset,
LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK
respectively for parallel programming. Use in conjunction with WEN / REN . During programming of
offset registers, PRAF and PRAE flag status is invalid. For Serial programming, LOAD is used to enable
serial loading of offset registers together with SDEN . Refer to Figure 7 & Table 13 for details.
LOAD
PFS1
PFS0
During Master Reset, select one of eight default offset values. Use in conjunction with LOAD
and PFS0. Refer to Table 13 for details.
During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS1.
Refer to Table 13 for details.
D35-0
36 - bit wide input data bus.
RCLK
Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the
EMPTY /QRDY and PRAE flags. RCLK and WCLK are independent of each other.
Reads data from queue or offset registers during low to high transitions of RCLK if REN is set to low.
This also advances the Read pointer of the queue.
REN
OE
Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers
(High-Z). OE does not control advancement of Read pointer.
Q35-0
36 - bit wide output data bus.
FWFT/SDI
Selects FWFT timing or Standard timing mode during Master Reset. After Master Reset, if serial
programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for the offset registers.
Serial data is written during the low to high transition of WCLK. Use in conjunction with SDEN . In
FWFT mode, DRDY and QRDY are used instead of FULL and EMPTY . Refer to Table 11 for all flags
status. In Standard mode, FULL and EMPTY are used instead of DRDY and QRDY . Refer to Table 10
for all flags status.
SDEN
If serial programming is selected, setting SDEN and LOAD low enables serial data to be written into offset
registers during the low to high transition of WCLK. During serial programming, PRAF and PRAE flags
status is invalid. Refer to Figure 7 for details.
(December, 2006, Version D)
13
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Pin Functions (Continued)
BM2
BM1
BM0
ES
During Master Reset, select one of five input and output bus width configurations. Use in conjunction
with BM1 and BM0. Refer to Table 12 for details.
During Master Reset, select one of five input and output bus width configurations. Use in conjunction
with BM2 and BM0. Refer to Table 12 for details.
During Master Reset, select one of five input and output bus width configurations. Use in conjunction
with BM2 and BM1. Refer to Table 12 for details.
During Master Reset, set ES high to select byte re-ordering on data outputs or set ES low to select no byte
re-ordering on data outputs. ES must be static throughout device operation. Refer to Table 12 for details.
RET
Data previously read from the queue can be retransmitted by asserting RET pin at the low to high
transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all
re-reads will always start from the physical 0th (Read pointer = zero) location of the queue. Refer to
Diagram 7 & 8 for details.
RETZL
During Master Reset, set RETZL low to select zero latency retransmit or set RETZL high to select
normal latency retransmit.
FULL / DRDY
In Standard mode, queue is full when FULL goes low during the low to high transition of WCLK. This
prohibits further writes into the queue and prevents advancement of Write pointer. In FWFT mode,
queue is full when DRDY goes high during the low to high transition of WCLK. This prohibits further
writes into the queue and prevents advancement of Write pointer. Refer to Table 10 & 11 for behavior of
FULL / DRDY .
EMPTY / QRDY In Standard mode, queue is empty when EMPTY goes low during the low to high transition of RCLK.
This prohibits further reads from the queue and prevents advancement of Read pointer. In FWFT mode,
queue is empty when QRDY goes high during the low to high transition of RCLK. This prohibits further
reads from the queue and prevents advancement of Read pointer. Refer to Table 10 & 11 for behavior of
EMPTY / QRDY .
IPAR
During Master Reset, set IPAR low to select 9-bit parallel programming mode or set IPAR high to select
8-bit parallel programming mode. In 9-bit mode, 9-bit wide data input/output bus width is used for
storing/fetching offset values. In 8-bit mode, 8-bit wide data input/output bus is used for
storing/fetching offset values.
SFM
During Master Reset, set SFM high to select Synchronous Partial Flag mode or set SFM low to select
Asynchronous Partial Flag mode. In Synchronous mode, PRAF and PRAE are synchronous to WCLK
and RCLK respectively. In Asynchronous mode, WCLK synchronizes the assertion of PRAF and de-
assertion of PRAE . RCLK synchronizes the assertion of PRAE and de-assertion of PRAF .
PRAF
In Synchronous mode, queue is almost full when PRAF goes low during the low to high transition of
WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . In
Asynchronous mode, PRAF is triggered by both WCLK and RCLK. Refer to Table 10 & 11 for behavior
of PRAF .
PRAE
HALF
In Synchronous mode, queue is almost empty when PRAE goes low during the low to high transition of
RCLK. Default (Empty+offset) or programmed offset values determine the status of PRAE . In
Asynchronous mode, PRAE is triggered by both WCLK and RCLK. Refer to Table 10 & 11 for
behavior of PRAE .
Queue is more than half full when HALF goes low during the low to high transition of WCLK.
HALF goes high during low to high transition of RCLK when queue is less than half full. Refer to
Table 10 & 11 for details.
(December, 2006, Version D)
14
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
FQV36110
FQV36100
FQV3690
FQV3680
FQV3670
FQV3660
WCLK RCLK
LOAD
WEN
REN
SDEN
FQV3650
FQV3640
Selection / Sequence
Parallel write
Parallel write to offset
registers:
Empty Offset
Full Offset
to registers:
1. PRAE
2. PRAF
0
0
0
1
1
0
1
1
X
Parallel read
from registers:
Parallel read from offset
registers:
Empty Offset
Full Offset
X
1. PRAE
2. PRAF
Serial shift into registers:
34 bits for the FQV36110
32 bits for the FQV36100
30 bits for the FQV3690
28 bits for the FQV3680
26 bits for the FQV3670
24 bits for the FQV3660
22 bits for the FQV3650
20 bits for the FQV3640
1 bit for each rising WCLK edge
0
1
1
0
X
Starting with Empty Offset (Low Byte)
Ending with Full Offset (High Byte)
X
1
1
0
1
1
X
X
X
No Operation
X
X
Write Memory
1
1
X
1
0
1
X
X
X
X
Read Memory
No Operation
X
Figure 7. Programmable Flag Offset Programming Sequence
(FQV36110, FQV36100, FQV3690, FQV3680, FQV3670, FQV3660, FQV3650 and FQV3640)
(December, 2006, Version D)
15
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Device
PRAF Programming (bits)
PRAE Programming (bits)
Non-IPAR
D/Q16 - 0
Non-IPAR
D/Q16 - 0
FQV36110
D/Q18 & D/Q16 – 9 & D/Q7 – 0
D/Q15 - 0
IPAR
D/Q18 & D/Q16 – 9 & D/Q7 – 0
D/Q15 - 0
IPAR
Non-IPAR
IPAR
Non-IPAR
IPAR
FQV36100
FQV3690
FQV3680
FQV3670
FQV3660
FQV3650
FQV3640
D/Q16 – 9 & D/Q7 – 0
D/Q14 - 0
D/Q16 – 9 & D/Q7 – 0
D/Q14 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q15 – 9 & D/Q7 – 0
D/Q13 - 0
D/Q15 – 9 & D/Q7 – 0
D/Q13 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q14 – 9 & D/Q7 – 0
D/Q12 - 0
D/Q14 – 9 & D/Q7 – 0
D/Q12 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q13 – 9 & D/Q7 – 0
D/Q11 - 0
D/Q13 – 9 & D/Q7 – 0
D/Q11 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q12 – 9 & D/Q7 – 0
D/Q10 - 0
D/Q12 – 9 & D/Q7 – 0
D/Q10 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q11 – 9 & D/Q7 – 0
D/Q9 - 0
D/Q11 – 9 & D/Q7 – 0
D/Q9 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q10 – 9 & D/Q7 – 0
D/Q10 – 9 & D/Q7 – 0
Table 6. Parallel Offset Register Data Mapping Table for x36 Bus Width
Device
PRAF Programming (bits)
PRAE Programming (bits)
D/Q15 - 0
D/Q0
Low Byte
Non-IPAR
D/Q15 - 0
D/Q0
Low Byte
Non-IPAR
High Byte
Non-IPAR
IPAR
High Byte
Non-IPAR
IPAR
FQV36110
D/Q16 – 9 & D/Q7 – 0 Low Byte
D/Q16 – 9 & D/Q7 – 0 Low Byte
D/Q0
High Byte
IPAR
D/Q0
High Byte
IPAR
D/Q15 - 0
Non-IPAR
IPAR
D/Q15 - 0
Non-IPAR
IPAR
FQV36100
FQV3690
FQV3680
FQV3670
FQV3660
FQV3650
FQV3640
D/Q16 – 9 & D/Q7 – 0
D/Q14 - 0
D/Q16 – 9 & D/Q7 – 0
D/Q14 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q15 – 9 & D/Q7 – 0
D/Q13 - 0
D/Q15 – 9 & D/Q7 – 0
D/Q13 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q14 – 9 & D/Q7 – 0
D/Q12 - 0
D/Q14 – 9 & D/Q7 – 0
D/Q12 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q13 – 9 & D/Q7 – 0
D/Q11 - 0
D/Q13 – 9 & D/Q7 – 0
D/Q11 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q12 – 9 & D/Q7 – 0
D/Q10 - 0
D/Q12 – 9 & D/Q7 – 0
D/Q10 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q11 – 9 & D/Q7 – 0
D/Q9 - 0
D/Q11 – 9 & D/Q7 – 0
D/Q9 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q10 – 9 & D/Q7 – 0
D/Q10 – 9 & D/Q7 – 0
Table 7. Parallel Offset Register Data Mapping Table for x18 Bus Width
(December, 2006, Version D)
16
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Device
PRAF Programming (bits)
PRAE Programming (bits)
D/Q7 - 0
D/Q7 – 0
D/Q0
Low Byte
Mid Byte
High Byte
Low Byte
High Byte
Low Byte
High Byte
Low Byte
High Byte
Low Byte
High Byte
Low Byte
High Byte
Low Byte
High Byte
Low Byte
High Byte
D/Q7 - 0
Low Byte
Mid Byte
High Byte
Low Byte
High Byte
Low Byte
High Byte
Low Byte
High Byte
Low Byte
High Byte
Low Byte
High Byte
Low Byte
High Byte
Low Byte
High Byte
FQV36110
D/Q7 – 0
D/Q0
D/Q7 - 0
D/Q7 – 0
D/Q7 - 0
D/Q6– 0
D/Q7 - 0
D/Q5 – 0
D/Q7 - 0
D/Q4 – 0
D/Q7 - 0
D/Q3 – 0
D/Q7 - 0
D/Q2 – 0
D/Q7 - 0
D/Q1 – 0
D/Q7 - 0
D/Q7 – 0
D/Q7 - 0
D/Q6– 0
D/Q7 - 0
D/Q5 – 0
D/Q7 - 0
D/Q4 – 0
D/Q7 - 0
D/Q3 – 0
D/Q7 - 0
D/Q2 – 0
D/Q7 - 0
D/Q1 – 0
FQV36100
FQV3690
FQV3680
FQV3670
FQV3660
FQV3650
FQV3640
Table 8. Parallel Offset Register Data Mapping for Table x9 Bus Width
Device
FQV36110
FQV36100
FQV3690
FQV3680
FQV3670
FQV3660
FQV3650
FQV3640
Standard Mode
131,072 x 36
65,536 x 36
32,768 x 36
16,384 x 36
8,192 x 36
FWFT Mode
131,073 x 36
65,537 x 36
32,769 x 36
16,385 x 36
8,193 x 36
4,096 x 36
4,097 x 36
2,048 x 36
2,049 x 36
1,024 x 36
1,025 x 36
Table 9. Maximum Depth of Queue for Standard and FWFT Mode
(December, 2006, Version D)
17
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
D/Q8
D/Q7
D/Q6
D/Q5 D/Q4
D/Q3
D/Q2 D/Q1
D/Q0
Data Width
1st Cycle PRAE
2nd Cycle PRAE
7
6
5
4
3
2
1
9
0
8
15
14
13
12
11
10
7
6
5
4
3
2
1
9
0
8
3rd Cycle
PRAF
15
14
13
12
11
10
4th Cycle PRAF
FQV36100, FQV3690, FQV3680, FQV3670, FQV3660, FQV3650, FQV3640
Parallel Offset Write/Read Cycles for x9 Bus Width
D/Q8
D/Q7
D/Q6
D/Q5 D/Q4
D/Q3
D/Q2 D/Q1
D/Q0
Data Width
7
6
5
4
3
2
1
9
0
8
1st Cycle PRAE
2nd Cycle PRAE
15
14
13
12
11
10
16
3rd Cycle
PRAE
7
6
5
4
3
2
1
0
8
4th Cycle PRAF
15
14
13
12
11
10
9
PRAF
PRAF
5th Cycle
6th Cycle
16
FQV36110
Parallel Offset Write/Read Cycles for x9 Bus Width
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7
D/Q6
D/Q5 D/Q4
D/Q3
D/Q2 D/Q1
D/Q0
Data Width
1st Cycle
PRAE
Non-Interspersed Parity
Interspersed Parity
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
1
1
3
3
2
2
0
0
15
Data Width
2nd Cycle PRAF
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9
D/Q8 D/Q7
D/Q6
D/Q5 D/Q4
D/Q3
D/Q2
D/Q1
D/Q0
Non-Interspersed Parity
Interspersed Parity
15
14
14
13
13
12
12
11
11
10
8
7
7
5
5
4
4
3
3
2
2
0
0
10
9
9
8
6
6
1
1
15
FQV36100, FQV3690, FQV3680, FQV3670, FQV3660, FQV3650, FQV3640
Parallel Offset Write/Read Cycles for x18 Bus Width
Figure 8. Parallel Offset Write/Read Cycle Diagram
(December, 2006, Version D)
18
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9
D/Q8 D/Q7
D/Q6
D/Q5 D/Q4
D/Q3
D/Q2
D/Q1
D/Q0
Data Width
1st Cycle
PRAE
Non-Interspersed Parity
Interspersed Parity
15
14
14
13
12
12
11
11
10
10
9
7
8
9
6
6
5
5
4
4
3
3
2
2
1
1
0
0
15
8
7
13
2nd Cycle
PRAE
Non-Interspersed Parity
Interspersed Parity
16
16
Data Width
3rd Cycle PRAF
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9
D/Q8 D/Q7
D/Q6
D/Q5 D/Q4
D/Q3
D/Q2
D/Q1
D/Q0
Non-Interspersed Parity
Interspersed Parity
15
14
14
13
13
12
12
11
11
10
8
7
7
5
5
4
4
3
3
2
2
0
0
10
9
9
8
6
6
1
1
15
4th Cycle
PRAF
Non-Interspersed Parity
Interspersed Parity
16
16
FQV36110
Parallel Offset Write/Read Cycles for x18 Bus Width
Data Width
1st Cycle PRAE
D/Q35 D/Q~ D/Q~ D/Q~ D/Q19 D/Q18 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9
D/Q5 D/Q4 D/Q3
D/Q2
D/Q1
D/Q0
D/Q8 D/Q7
D/Q6
Non-Interspersed Parity
Interspersed Parity
14
13
16
15
15
14
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
1
1
3
3
2
2
0
0
16
Data Width
D/Q35 D/Q~
D/Q~
D/Q~ D/Q19 D/Q18 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9
D/Q8 D/Q7
D/Q6
D/Q5 D/Q4
D/Q3
D/Q2
D/Q1
D/Q0
2nd Cycle
PRAF
15
14
14
13
16
15
12
11
11
10
10
9
7
7
9
8
8
6
6
5
4
Non-Interspersed Parity
Interspersed Parity
1
1
3
3
2
2
0
0
16
13
12
5
4
FQV36110, FQV36100, FQV3690, FQV3680, FQV3670, FQV3660, FQV3650, FQV3640
Parallel Offset Write/Read Cycles for x36 Bus Width
# of Bits for Offset Registers
17 bits for FQV36110
16 bits for FQV36100
15 bits for FQV3690
14 bits for FQV3680
13 bits for FQV3670
12 bits for FQV3660
11 bits for FQV3650
10 bits for FQV3640
Note: Don’t Care applies to all unused bits
Figure 8. Parallel Offset Write/Read Cycle Diagram (Continued)
(December, 2006, Version D)
19
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
FQV36110
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
H
1 to y(1)
(y+1) to 65,536
65,537 to [131,072-(x+1)]
(131,072-x) to 131,071
131,072
L
FQV36100
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
H
1 to y(1)
(y+1) to 32,768
32,769 to [65,536-(x+1)]
(65,536-x) to 65,535
65,536
L
FQV3690
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
H
1 to y(1)
(y+1) to 16,384
16,385 to [32,768-(x+1)]
(32,768-x) to 32,767
32,768
L
FQV3680
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
H
1 to y(1)
(y+1) to 8,192
8,193 to [16,384-(x+1)]
(16,384 -x) to 16,383
16,384
L
FQV3670
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
H
1 to y(1)
(y+1) to 4,096
4,097 to [8,192-(x+1)]
(8,192 -x) to 8,191
8,192
L
FQV3660
0
FULL
EMPTY
PRAF
HALF
PRAE
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
H
1 to y(1)
(y+1) to 2,048
2,049 to [4,096-(x+1)]
(4,096 –x) to 4,095
4,096
L
Table 10. Status Flags (Standard Mode)
(December, 2006, Version D)
20
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
FQV3650
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
H
1 to y(1)
(y+1) to 1,024
1,025 to [2,048-(x+1)]
(2,048 -x) to 2,047
2,048
L
FQV3640
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
L
H
H
H
H
H
1 to y(1)
(y+1) to 512
513 to [1,024-(x+1)]
(1,024 –x) to 1,023
1,024
L
NOTES:
1.
See Table 13 for values x, y.
Table 10. Status Flags (Standard Mode) (Continued)
(December, 2006, Version D)
21
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
FQV36110
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
1 to y+1(1)
(y+2) to 65,537
65,538 to [131,073-(x+1)]
(131,073-x) to 131,072
131,073
L
FQV36100
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
1 to y+1(1)
(y+2) to 32,769
32,770 to [65,537-(x+1)]
(65,537-x) to 65,536
65,537
L
FQV3690
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
1 to y+1(1)
(y+2) to 16,385
16,386 to [32,769-(x+1)]
(32,769-x) to 32,768
32,769
L
FQV3680
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
1 to y+1(1)
(y+2) to 8,193
8,194 to [16,385-(x+1)]
(16,385 -x) to 16,384
16,385
L
FQV3670
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
1 to y+1(1)
(y+2) to 4,097
4,098 to [8,193-(x+1)]
(8,193-x) to 8,192
8,193
L
FQV3660
QRDY
DRDY
PRAF
HALF
PRAE
0
L
H
H
L
H
1 to y+1(1)
(y+2) to 2,049
2,050 to [4,097-(x+1)]
(4,097 -x) to 4,096
4,097
L
L
L
L
H
H
H
H
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
Table 11. Status Flags (FWFT Mode)
(December, 2006, Version D)
22
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
FQV3650
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
1 to y+1(1)
(y+2) to 1,025
1,026 to [2,049-(x+1)]
(2,049 -x) to 2,048
2,049
L
FQV3640
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
H
H
H
H
L
L
L
L
L
1 to y+1(1)
(y+2) to 513
514 to [1,025-(x+1)]
(1,025 -x) to 1,024
1,025
L
NOTES:
1.
See Table 13 for values x, y.
Table 11. Status Flags (FWFT Mode) (Continued)
(December, 2006, Version D)
23
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
ES
BM2
BM1
BM0
I/O
Width D/Q35-27 D/Q26-18 D/Q17-9
D/Q8-0
Sequence
X
0
X
X
I
36
36
Byte 4
Byte 4
Byte 3
Byte 3
Byte 2
Byte 2
Byte 1
Byte 1
1st Write
1st Read
O
0
0
1
1
0
0
0
1
I
36
18
Byte 4
Byte 3
Byte 2
Byte 4
Byte 2
Byte 1
Byte 3
Byte 1
1st Write
1st Read
2nd Read
O
X
X
X
X
I
36
9
Byte 4
Byte 3
Byte 2
Byte 1
Byte 4
Byte 3
Byte 2
Byte1
1st Write
1st Read
2nd Read
3rd Read
4th Read
O
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
1
0
1
I
O
I
18
36
9
X
X
X
X
Byte 4
Byte 2
Byte 2
Byte 3
Byte 1
Byte 1
1st Write
2nd Write
1st Read
Byte 4
Byte 3
X
X
X
X
X
X
Byte 4
Byte 3
Byte 2
Byte1
Byte 1
1st Write
2nd Write
3rd Write
4th Write
1st Read
X
X
X
X
X
X
O
36
Byte 4
Byte 3
Byte 2
1
1
1
1
0
0
0
1
I
36
18
Byte 4
Byte 3
Byte 2
Byte 2
Byte 4
Byte 1
Byte 1
Byte 3
1st Write
1st Read
2nd Read
O
X
X
X
X
I
36
9
Byte 4
Byte 3
Byte 2
Byte 1
Byte 1
Byte 2
Byte 3
Byte4
1st Write
1st Read
2nd Read
3rd Read
4th Read
O
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
0
1
I
O
I
18
36
9
X
X
X
X
Byte 4
Byte 2
Byte 4
Byte 3
Byte 1
Byte 3
1st Write
2nd Write
1st Read
Byte 2
Byte 1
X
X
X
X
X
X
Byte 4
Byte 3
Byte 2
Byte1
Byte 4
1st Write
2nd Write
3rd Write
4th Write
1st Read
X
X
X
X
X
X
O
36
Byte 1
Byte 2
Byte 3
Table 12. Bus-Matching Table
(December, 2006, Version D)
24
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
FQV3650
FQV3640
Default Offsets x, y(1)
PFS1
PFS0
LOAD
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
127
255
511
63
31
7
15
3
FQV3650
FQV3640
PFS1
PFS0
LOAD
Program Mode
Serial
1
0
X
X
X
X
Parallel
FQV3690
FQV3680
FQV3670
FQV3660
PFS1
PFS0
LOAD
Default Offsets x, y(1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
127
255
511
63
1,023
15
31
7
FQV3690
FQV3680
FQV3670
FQV3660
PFS1
PFS0
LOAD
Program Mode
Serial
1
0
X
X
X
X
Parallel
NOTES:
1. x = PRAF offset, y = PRAE offset.
Table 13. Default Programmable Flag Offsets
(December, 2006, Version D)
25
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
FQV36110
FQV36100
Default Offsets x, y(1)
PFS1
PFS0
LOAD
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
127
8,191
16,383
4,095
1,023
511
2,047
255
FQV36110
FQV36100
PFS1
PFS0
LOAD
Program Mode
Serial
1
0
X
X
X
X
Parallel
NOTES:
1. x = PRAF offset, y = PRAE offset.
Table 13. Default Programmable Flag Offsets (Continued)
(December, 2006, Version D)
26
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Timing Diagrams
tRST
MRST
REN
tRSTR
tRSTR
tRSTS
tRSTS
tRSTS
tRSTS
tRSTS
WEN
tRSTR
FWFT/SDI
tRSTR
LOAD
PFS1,
PFS0
tRSTS
BM2, BM1, BM0
tRSTS
ES
tRSTS
tRSTS
tRSTS
tRSTS
tRSTS
RETZL
SFM
IPAR
RET
SDEN
tRSTF
tRSTF
tRSTF
tRSTF
tRSTF
If FWFT = 1,QRDY = 1
If FWFT = 0,EMPTY = 0
EMPTY / QRDY
FULL/ DRDY
PRAE
If FWFT = 0,FULL = 1
If FWFT = 1,DRDY = 0
PRAF , HALF
OE = 1
Q35- 0
OE = 0
Diagram 1. Master Reset Timing
(December, 2006, Version D)
27
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
tRST
PRST
REN
tRSTR
tRSTR
tRSTS
tRSTS
tRSTS
tRSTS
WEN
RET
SDEN
EMPTY/QRDY
FULL/ DRDY
PRAE
tRSTF
tRSTF
tRSTF
tRSTF
tRSTF
If FWFT = 1,QRDY = 1
If FWFT = 0,EMPTY= 0
If FWFT = 0,FULL = 1
If FWFT = 1,
= 0
DRDY
PRAF, HALF
OE = 1
OE = 0
Q35- 0
Diagram 2. Partial Reset Timing
(December, 2006, Version D)
28
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
(December, 2006, Version D)
29
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
(December, 2006, Version D)
30
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
(December, 2006, Version D)
31
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
(December, 2006, Verion D)
32
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
RCLK
REN
1
2
tENS
tENH
tRETS
tENS
tENH
tA
tA
tA
Q 35 - 0
WCLK
WEN
DWi
DWi+1
DW1
DW2
tSKEW2
1
2
tRETS
tENS
tENH
RET
EMPTY
PRAE
tEMPTY
tEMPTY
tPRAES
tHALF
HALF
tPRAFS
PRAF
NOTES:
1.
2.
3.
4.
Upon completion of retransmit setup, a read operation can begin only after EMPTY returns high.
OE = Low.
DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.
Upon reset completion, there must be more than two words written to the queue for a retransmit setup to be valid.
Diagram 7. Retransmit Timing (Standard Mode)
(December, 2006, Version D)
33
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
RCLK
REN
1
2
3
4
tENS
tENH
tRETS
tENS
tENH
tA
tA
tA
tA
Q
DWi
DWi+1
DW1
DW2
DW3
DW4
35 - 0
tSKEW2
WCLK
WEN
1
2
tRETS
tENS
tENH
RET
QRDY
PRAE
tEMPTY
tEMPTY
tPRAES
tHALF
HALF
PRAF
tPRAFS
NOTES:
1.
2.
3.
4.
5.
Upon completion of retransmit setup, a read operation can begin only after QRDY returns low.
OE = Low.
DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.
Upon reset completion, there must be more than two words written to the queue for a retransmit setup to be valid.
Please refer to Table 9 for Depth.
Diagram 8. Retransmit Timing (FWFT Mode)
(December, 2006, Version D)
34
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
RCLK
1
2
3
tENS
tENH
REN
tA
tA
tA
tA
tA
Q 35 - 0
DWi+1
DW1
DW2
DW3
DW4
DWi
tSKEW2
WCLK
1
2
tRETS
WEN
RET
tENS
tENH
EMPTY
PRAE
tPRAES
tHALF
HALF
tPRAFS
PRAF
NOTES:
1.
If the part is empty at the point of retransmit, the Empty Flag ( EMPTY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will appear on the
output.
2.
3.
4.
OE = Low; enables data to be read on outputs Q35 – 0.
DW1= first word written to the queue after Master Reset; DW2= second word written to the queue after Master Reset.
No more than D-2 may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, FULL will be high throughout the retransmit setup
procedure. Please refer to Table 9 for Depth.
5.
6.
There must be at least two words written to zero latency retransmit from the queue before a retransmit operation can be invoked.
RETZL is set Low during MRST .
Diagram 9. Zero Latency Retransmit Timing (Standard Mode)
(December, 2006, Version D)
35
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
RCLK
REN
1
2
3
4
5
tENH
tENS
tA
tA
tA
tA
tA
tA
DWi
DW i+1
DW1
DW2
DW3
DW4
Q 35 - 0
WCLK
WEN
DW5
tSKEW2
1
2
tRETS
tENS
tENH
RET
QRDY
tPRAES
PRAE
HALF
tHALF
tPRAFS
PRAF
NOTES:
1.
If the part is empty at the point of retransmit, the output ready flag ( QRDY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will appear on the
output.
2.
No more than D-2 words may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, DRDY will be low throughout the retransmit
setup procedure. Please refer to Table 9 for Depth.
3.
4.
5.
6.
OE = Low.
DW1, DW2, DW3 = first, second and third words written to the queue after Master Reset.
There must be at least two words written to the queue before a retransmit operation can be invoked.
RETZL is set low during MRST .
Diagram 10. Zero Latency Retransmit Timing (FWFT Mode)
(December, 2006, Version D)
36
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
WCLK
SDEN
LOAD
SDI
tENS
tLOADS
tDS
tENH
tENH
tLOADH
tDH
tLOADH
BIT 0
BIT MSB
BIT 0
BIT MSB
PRAF
PRAE offset
offset
*Refer to Table 14
Diagram 11. Serial Loading of Programmable Flag Registers (Standard and FWFT Mode)
FQV36110
FQV36100
FQV3690
FQV3680
FQV3670
FQV3660
FQV3650
10
FQV3640
16
15
14
13
12
11
9
MSB
Table 14. Reference Table for Diagram 11
(December, 2006, Version D)
37
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
tWCLK
tWCLKH
tWCLKL
WCLK
tLOADH
tLOADS
tLOADH
tENH
LOAD
WEN
D 35 - 0
tENS
tDS
tENH
tDH tDS
tDH
PRAE
PRAF
offset
offset
Diagram 12. Parallel Loading of Programmable Flag Registers (Standard and FWFT Mode)
tRCLK
tRCLKH
tRCLKL
RCLK
tLOADH
tLOADS
tENS
tLOADH
LOAD
REN
tENH
tENH
tA
tA
Q 35 - 0
Output Register Data
PRAF
PRAE offset
offset
Diagram 13. Parallel Read of Programmable Flag Registers (Standard and FWFT Mode)
(December, 2006, Version D)
38
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
tWCLKH
tWCLKL
WCLK
WEN
1
2
1
2
tENS
tENH
tPRAFS
tPRAFS
D - ( x + 1 ) words in Queue
D - ( x + 1 )
words in Queue
PRAF
RCLK
D - x words in Queue
tSKEW2
tENS
tENH
REN
NOTES:
1.
2.
3.
x = _P__R___A___F__ offset.
D = maximum queue depth. Please refer to Table 9 for Depth.
___________
If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF will go high (after one WCLK cycle plus
tPRAFS). If tSKEW2 is not met, then _P__R___A___F__ will assert 1 or more WCLK cycles.
___________
4.
PRAF synchronizes to the rising edge of WCLK only.
Diagram 14. Synchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)
tWCLKH
tWCLKL
WCLK
tENS
tENH
WEN
y words in Queue(2)
y+1 words in Queue
;
y words in Queue(2) ; y+1 words in Queue(3)
tSKEW2 tPRAES
(3)
y+1 words in Queue(2) ; y+2 words in Queue(3)
PRAE
tPRAES
1
2
1
2
RCLK
REN
tENS
tENH
NOTES:
1.
y = PRAE offset.
For Standard Mode.
For FWFT Mode.
2.
3.
4.
If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE will go high (after one RCLK cycle plus
tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles.
5.
PRAE synchronizes to the rising edge of RCLK only.
Diagram 15. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)
(December, 2006, Version D)
39
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
tWCLKH
tWCLKL
WCLK
tENS
tENH
WEN
PRAF
RCLK
tPRAFA
D - x words in
D - ( x + 1) words in Queue
D - ( x + 1) words in Queue
Queue
tPRAFA
tENS
REN
NOTES:
1. x = PRAF offset.
2. D = maximum queue depth. Please refer to Table 9 for Depth.
3. PRAF is asserted to low on WCLK transition and reset to high on RCLK transition.
4. Select this mode by setting SFM low during Master Reset.
Diagram 16. Asynchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)
tWCLKH
tWCLKL
WCLK
WEN
tENS
tENH
tPRAEA
y words in Queue(2); y+1 words in Queue(3)
y words in Queue(2); y+1 words in Queue(3)
tPRAEA
y+1 words in
Queue(2); y+2
words in Queue (3)
PRAE
RCLK
REN
tENS
NOTES:
1.
2.
3.
4.
5.
y = PRAE offset.
For Standard Mode.
For FWFT Mode.
PRAE is asserted to low on RCLK transition and reset to high on WCLK transition.
Select this mode by setting SFM low during Master Reset.
Diagram 17. Asynchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)
(December, 2006, Version D)
40
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
tWCLKH
tWCLKL
WCLK
WEN
tENS
tENH
D/2 + 1 words in
Queue(1)
tHALF
;
[(D+1)/2 + 1] words
in Queue(2)
D/2 words in Queue(1); [(D+1)/2] words in Queue(2)
HALF
RCLK
D/2 words in Queue(1)
;
[(D+1)/2] words in Queue(2)
tHALF
tENS
tENH
REN
NOTES:
1.
2.
3.
For Standard Mode.
For FWFT Mode.
Please refer to Table 9 for Depth.
Diagram 18. Half-Full Flag Timing (Standard and FWFT Mode)
(December, 2006, Version D)
41
AMIC Technology, Corp.
FQV36110 · FQV36100 · FQV3690 · FQV3680 ·
FQV3670 · FQV3660 · FQV3650 · FQV3640
FlexQTM III
Order Information:
AMIC
Device Type
Device Family
Power Speed (ns) *
Package**
Temperature Range
Material
XX
FQ
XXXXX
X
XX
6
XX
PF
X
X
V36110 (131,072 x 36)
– 166 MHz
Blank – Commercial (0°C to 70°C)
Blank – Normal material
Low
I – Industrial (-40° to 85°C)
-F – Pb-Free material
V36100 (65,536 x 36)
V3690 (32,768 x 36)
V3680 (16,384 x 36)
V3670 (8,192 x 36)
V3660 (4,096 x 36)
V3650 (2,048 x 36)
V3640 (1,024 x 36)
7-5 – 133 MHz
10 – 100 MHz
15 – 66 MHz
*Speed – 6ns available only in Commercial temp (0°C to 70°C). Slower speeds available upon request.
**Package – 128 pin Plastic Thin Quad Flat Pack (TQFP)
Example:
FQV3680L6PF
FQV3670L10PFI
FQV3670L10PFI-F
(16k x 36, 6ns, Commercial temp, Normal material)
(8k x 36, 10ns, Industrial temp, Normal material)
(8K x 36, 10ns, Industrial temp, Pb-Free material)
(December, 2006, Version D)
42
AMIC Technology, Corp.
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