FQV80100L7.5BB [AMICC]
FIFO, 64KX80, 5ns, Synchronous, CMOS, PBGA256;
| 型号： | FQV80100L7.5BB |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | FIFO, 64KX80, 5ns, Synchronous, CMOS, PBGA256 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总51页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
3.3 Volt Synchronous x 80 First-In/First-Out Queue
Memory Configuration
65,536 x 80
Device
FQV80100
FQV8090
FQV8080
FQV8070
Memory Configuration
4,096 x 80
Device
FQV8060
FQV8050
FQV8040
FQV8030
32,768 x 80
16,384 x 80
8,192 x 80
2,048 x 80
1,024 x 80
512 x 80
Key Features
•
Industry leading First-In/First-Out Queues (up to 166 MHz)
•
Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns)
Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns)
User selectable input and output bus-sizing
•
•
•
•
•
•
•
•
•
•
Big Endian/Little Endian user selectable byte representation
3.3V power supply
5V input tolerant on all control and data input pins
5V output tolerant on all flags and data output pins
Master Reset clears all previously programmed configurations including Write and Read pointers
Partial Reset clears Write and Read pointers but maintains all previously programmed configurations
First Word Fall Through (FWFT) and Standard Timing modes
Presets for eight different Almost Full and Almost Empty offset values
•
•
•
Parallel/Serial programming of PRAF and PRAE offset values
Programmable 8-bit or 10-bit parallel programming modes for offset values
Full, Empty, Almost Full, Almost Empty, and Half Full indicators
•
•
•
•
•
•
•
•
PRAF and PRAE operate in either synchronous or asynchronous modes
Asynchronous output enable tri-state data output drivers
Synchronous Read Chip Select
Data retransmission with programmable zero or normal latency modes
Boundary Scan (JTAG)
Available package: 256 - pin Fine Pitch Ball Grid Array (BGA)
(0°C to 70°C) Commercial operating temperature available for cycle time of 6.0ns and above
(-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above
Product Description
HBA’s FlexQ™ III Plus offers industry leading FIFO queuing bandwidth (up to 12.0 Gbps) with a wide range of memory
configurations (from 512 x 80 to 65,536 x 80). System designer has full flexibility of implementing deeper and wider queues
using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between
transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation
of virtual queue depths.
5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous
Output Enable pin configures the tri-state data output drivers. In addition, synchronous read chip select is also available to
control the state of data output drivers. Independent Write and Read controls provide rate-matching capability.
Master Reset clears all previous programmed configurations by providing a low pulse on MRST pin. In addition, Write and
Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will
initialize Write and Read pointers to zero.
In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high
transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when implementing
depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively.
3F3P80D
NOVEMBER 2002
Page 1 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Product Description (Continued)
In Standard mode, always assert REN for a read operation. FULL and EMPTY are used instead of DRDY and
QRDY respectively.
Bus matching feature is available with the following configurations:
Input Bus Width
Output Bus Width
x20
x40
x80
x80
x80
x80
x80
x80
x40
x20
In addition, Endian Select is available for implementing byte re-ordering on data outputs.
Eight different default offset values are available for Almost Full ( PRAF ) and Almost Empty ( PRAE ) flags. Parallel and Serial
programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 10-bit
parallel programming modes for offset values can be selected for convenience.
PRAF , PRAE , and HALF are available in either FWFT or Standard mode. In addition, PRAF and PRAE can operate in either
synchronous or asynchronous modes.
At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of
RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the
physical 0th (Read pointer = zero), location of the queue. Both zero and normal latency timing modes available for retransmit
operation.
These FlexQ™ III Plus devices have low power consumption, hence minimizing system power requirements. In addition,
industry standard 256 - pin BGA is offered to save system board space.
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test
equipment, network switching, etc.
3F3P80D
NOVEMBER 2002
Page 2 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Block Diagram of Single Synchronous Queue
65,536 x 80 / 32,768 x 80 / 16,384 x 80 / 8,192 x 80 / 4,096 x 80 / 2,048 x 80 / 1,024 x 80 / 512 x 80
PARTIAL RESET (PRST)
MASTER RESET (MRST)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (
)
OE
)
LOAD
READ CHIP SELECT (
)
RCS
(SFM)
(PFS0)
(PFS1)
x80, x40, x20 DATA OUT (Q79 - 0
)
FQV80100
FQV8090
FQV8080
FQV8070
FQV8060
FQV8050
FQV8040
FQV8030
(RETLZ)
RETRANSMIT (RET)
x80, x40, x20 DATA IN (D79 - 0
)
EMPTY FLAG / OUTPUT READY
( EMPTY/QRDY )
PROGRAMMABLE ALMOST-
EMPTY (PRAE)
SERIAL IN CLOCK (SCLK)
SERIAL DATA ENABLE (SDEN)
FIRST WORD FALL THROUGH/
SERIAL DATA INPUT (FWFT/SDI)
FULL FLAG / INPUT READY
HALF-FULL FLAG (
)
HALF
JTAG CLOCK (TCLK)
TRST
DRDY
)
FULL
(
/
JTAG RESET (
)
PROGRAMMABLE ALMOST-
FULL (PRAF)
JTAG MODE (TMS)
(TDO)
INTERSPERSED PARITY (IPAR)
ENDIAN SELECT (ES)
(TDI)
BUS
BUS
BUS
MATCHING 1
(BM1)
MATCHING 2
MATCHING 0
(BM2)
(BM0)
Figure 1. Single Device Configuration Signal Flow Diagram
3F3P80D
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2002
Page 3 of 51
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
WCLK WEN
IPAR LOAD SDEN FWFT/SDI
/ DRDY
FULL
PRAF
Write Control
Logic
/
EMPTY QRDY
PRAE
HALF
FWFT/SDI
Offset Register
Flag Logic
SFM
PFS1
PFS0
Write Pointer
Output
Buffer
Input Register
Output Register
SRAM
Q 79-0
x80, x40, x20
D79-0
x80, x40, x20
OE
Read Pointer
JTAG Control
(Boundary Scan)
Bus
Configuration
Read Control
Logic
Reset
TCK TRST TMS TDO TDI
RETZL RET RCLK REN
RCS
MRST PRST
ES BM2 BM1 BM0
Figure 2. Device Architecture
3F3P80D
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2002
Page 4 of 51
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
A1 BALL PAD CORNER
A
B
C
D
E
F
Q36
Q35
Q34
Q38
Q37
Q33
Q52
Q51
Q50
Q55
Q54
Q53
Q58
Q57
Q56
Q72
Q71
Q70
Q75
Q74
Q73
Q78
Q77
Q76
D78
D77
D76
D75
D74
D73
D72
D71
D70
D58
D57
D56
D55
D54
D53
D52
D51
D50
D38
D37
D33
D36
D35
D34
Q32
Q18
Q31
Q17
Q30
Q16
Q39
Q19
Q59
Q79
GND
GND
TCK
VCC
TDI
TRST
VCC
TDO
GND
TMS
D79
D59
D39
D30
D16
D31
D17
D32
D18
GND
VCC
GND
Q15
Q12
Q68
Q65
Q62
Q48
Q45
Q42
Q28
Q26
Q14
Q11
Q67
Q64
Q61
Q47
Q44
Q41
Q27
Q23
Q13
Q10
Q66
Q63
Q60
Q46
Q43
Q40
Q20
Q21
VCC
VCC
VCC
VCC
Q69
Q49
Q29
RET
Q6
GND
GND
GND
GND
GND
GND
Q9
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
BM2
RCS
OE
VCC
VCC
GND
GND
GND
GND
GND
GND
PFS1
ES
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
BM0
VCC
VCC
VCC
VCC
VCC
D29
D9
D19
GND
GND
D69
D13
D10
D66
D63
D60
D46
D43
D40
D20
D21
D14
D11
D67
D64
D61
D47
D44
D41
D27
D23
D15
D12
D68
D65
D62
D48
D45
D42
D28
D26
G
H
J
VCC
VCC
K
L
M
N
P
VCC
D49
VCC
BM1
SCLK
SDEN
D6
VCC
PFS0
HALF
PRST
GND
IPAR
PRAE
EMPTY
VCC
SFM
RETZL
Q3
FWFT/SDI
D0
LOAD
D3
Q0
Q1
MRST
PRAF
R
T
Q7
Q4
D1
D4
D7
WEN
Q25
Q24
Q22
Q8
Q5
Q2
RCLK
WCLK
D2
D5
D8
D22
D24
D25
REN
FULL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PBGA -256 (Drw No: BB-01A; Order code: BB)
Top View
Figure 3. Device Pin Out
3F3P80D
NOVEMBER 2002
Page 5 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Pin #
Pin Name
Pin Symbol
Input/Output
Description
Master Reset is required to initialize Write and Read
pointers to the first position of the queue by setting
MRST low. In Standard mode, FULL and PRAF will go
high; EMPTY and PRAE will go low. In FWFT mode,
DRDY will go low and QRDY will go high. PRAF
and PRAE will go to the same state as Standard mode. In
both modes, all data outputs will go low. Previous
programmed configurations will not be maintained.
Master Reset
MRST
Input
P9
Partial Reset is required to initialize Write and Read
pointers to the first position of the queue by setting PRST
low. In Standard mode, FULL and PRAF will go high;
EMPTY and PRAE will go low. In FWFT mode,
DRDY will go low and QRDY will go high. PRAF and
PRAE will go to the same state as Standard mode. In
both modes, all data outputs will go low. Previous
programmed configurations will be maintained.
P10
Partial Reset
PRST
Input
Writes data into queue during low to high transitions of
WCLK if WEN is set to low.
T10
R10
Write Clock
Write Enable
WCLK
WEN
Input
Input
Controls write operation into queue or offset registers
during low to high transition of WCLK.
During Master Reset, set LOAD low to select parallel
programming or one of eight default offset values. Set
LOAD high to select serial programming or one of eight
default offset values. After Master Reset, LOAD controls
write/read to/from offset registers during low to high
transition of WCLK/RCLK respectively. Use in
conjunction with WEN / REN .
N12
Load Enable
LOAD
Input
Default
During Master Reset, select one of eight default offset
M9
PFS1
PFS0
Input
Input
Programming 1
values. Use in conjunction with LOAD and PFS0.
Default
During Master Reset, select one of eight default offset
values. Use in conjunction with LOAD and PFS1.
M10
Programming 0
A9, A10, A11, A12, A13,
A14, A15, A16, B9, B10,
B11, B12, B13, B14, B15,
B16, C9, C10, C11, C12,
C13, C14, C15, C16, D13,
D14, D15, D16, E12, E13,
E14, E15, E16, F13, F14,
F15, F16, G14, G15, G16,
H14, H15, H16, J13, J14,
J15, J16, K13, K14, K15,
K16, L12, L14, L15, L16,
M12, M14, M15, M16, N14,
N15, N16, P11, P12, P13,
P14, P15, P16, R11, R12,
R13, R14, R15, R16, T11,
T12, T13, T14, T15, T16
Data Inputs
Read Clock
D79-0
Input
80 - bit wide input data bus.
Reads data from queue during low to high transitions of
RCLK if REN is set to low.
T8
RCLK
Input
Table 1. Pin Descriptions
3F3P80D
NOVEMBER 2002
Page 6 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Pin #
Pin Name
Pin Symbol
Input/Output
Description
Controls read operation from queue or offset registers
during low to high transition of RCLK.
T7
Read Enable
REN
Input
Setting RCS low during the low to high transition of
RCLK activates the data output drivers. Setting RCS
high during the low to high transition of RCLK deactivates
the data output drivers. OE must be set low when using
RCS to control the state of the drivers.
Read Chip
Select
P7
R7
RCS
OE
Input
Input
Setting OE low activates the data output drivers. Setting
OE high deactivates the data output drivers (High-Z).
Output Enable
Data Outputs
A1, A2, A3, A4, A5, A6,
A7, A8, B1, B2, B3, B4,
B5, B6, B7, B8, C1, C2,
C3, C4, C5, C6, C7, C8,
D1, D2, D3, D4, D5, D6,
E1, E2, E3, E4, F1, F2,
F3, G1, G2, G3, H1, H2,
H3, J1, J2, J3, K1, K2,
K3, K4, L1, L2, L3, L4,
M1, M2, M3, M4, M5,
N1, N2, N3, P1, P2, P3,
P4, P5, P6, R1, R2, R3,
R3, R4, R5, R6, T1, T2,
T3, T4, T5, T6
Q79-0
Output
80 - bit wide output data bus.
Selects FWFT timing or Standard timing mode during
Master Reset. After Master Reset, if serial programming
is selected ( LOAD = high), FWFT/SDI is used as the
serial data input for the offset registers. Serial data is
written during the low to high transition of WCLK. Use in
conjunction with SDEN .
First Word Fall
Through/Serial
Data Input
N11
FWFT/SDI
Input
During serial programming, SCLK is used to program
offset values through SDI.
M13
N13
Serial Clock
SCLK
SDEN
Input
Input
If serial programming is selected, setting SDEN and
LOAD low enables serial data input to be written into
offset registers during the low to high transition of SCLK.
Serial Data Input
Enable
During Master Reset, select one of five input and output
bus width configurations. Use in conjunction with BM1
and BM0.
N7
L13
M11
N9
Bus Matching 2
Bus Matching 1
Bus Matching 0
Endian Select
BM2
BM1
BM0
ES
Input
Input
Input
Input
During Master Reset, select one of five input and output
bus width configurations. Use in conjunction with BM2
and BM0.
During Master Reset, select one of five input and output
bus width configurations. Use in conjunction with BM2
and BM1.
During Master Reset, set ES high to select byte re-ordering
on data outputs or ES low to select no byte re-ordering on
data outputs.
Data previously read from the queue can be retransmitted
by asserting RET pin at the low to high transition of
RCLK for a retransmit operation. Retransmit initializes
the Read pointer to zero. Hence, all re-reads will always
start from the physical 0th (Read pointer = zero) location of
the queue.
N4
Retransmit
RET
Input
Table 1. Pin Descriptions (Continued)
3F3P80D
NOVEMBER 2002
Page 7 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Description
Pin #
Pin Name
Pin Symbol
Input/Output
During Master Reset, set RETZL low to select zero
latency retransmit or RETZL high to select normal
latency retransmit.
Zero Latency
Retransmit
N5
RETZL
Input
Queue is full when FULL goes low during the low to
high transition of WCLK. This prohibits further
writes into the queue. In FWFT mode, queue is full
when DRDY goes high during low to high transition
of WCLK. This prohibits further writes into the
queue.
Queue is empty when EMPTY goes low during the
low to high transition of RCLK. This prohibits further
reads from the queue. In FWFT mode, queue is empty
when QRDY goes high during the low to high
transition of RCLK. This prohibits further reads from
the queue.
Full/Data Input
Ready Flag
T9
R8
FULL / DRDY
Output
Output
Empty/Data
Output Ready
Flag
EMPTY / QRDY
During Master Reset, set IPAR low to select 10-bit
parallel programming mode or IPAR high to select 8-
bit parallel programming mode.
During Master Reset, set SFM high to select
Synchronous Partial Flag mode or SFM low to select
Asynchronous Partial Flag mode.
Interspersed
Parity
N8
N6
IPAR
SFM
Input
Input
Synchronous
Partial Flag
Mode
Queue is almost full when PRAF goes low during the
low to high transition of WCLK. Default (Full-offset)
or programmed offset values determine the status of
PRAF .
R9
Almost Full
PRAF
Output
Queue is almost empty when PRAE goes low during
the low to high transition of RCLK. Default
(Empty+offset) or programmed offset values
determine the status of PRAE .
P8
Almost Empty
Half Full
PRAE
HALF
Output
Output
Queue is more than half full when HALF goes low.
N10
Triggered by both WCLK and RCLK.
E6, E8, E10, F4,
F6, F8, F10, F12,
G4, G6, G8, G10,
G12, H4, H6, H8,
H10, H12, J4, J6,
J8, J10, J12, K6,
K8, K10, K12,
Power
Vcc
N/A
N/A
3.3V power supply.
L6, L8, L10, M6
D7, E5, E7, E9,
E11, F5, F7, F9,
F11, G5, G7, G9,
G11, G13, H5,
H7, H9, H11,
Ground
GND
0V Ground.
H13, J5, J7, J9,
J11, K5, K7, K9,
K11, L5, L7, L9,
L11, M7, M8
Table 1. Pin Description (Continued)
3F3P80D
NOVEMBER 2002
Page 8 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Description
Pin #
Pin Name
Pin Symbol
Input/Output
Clock for JTAG function. TMS and TDI are loaded
during low to high transitions of TCK. TDO is loaded
during high to low transitions of TCK. When JTAG is
not used, tie TCK to MRST .
D8
JTAG Clock
TCK
Input
Reset control for JTAG function. An asynchronous
input for the JTAG controller.
D10
D12
D9
JTAG Reset
TRST
TMS
TDI
Input
Input
Input
JTAG Mode
Selection
Mode select for JTAG function. TMS bits are loaded
serially during low to high transitions of the TCK.
Serial data input for JTAG function. TDI is loaded
during low to high transitions of the TCK.
Test Data Input
Serial data output for JTAG function. TDO is
unloaded during high to low transitions of the TCK.
During SHIFT-DR and SHIFT-IR operations, TDO
bus will be tri-stated.
Test Data
Output
D11
TDO
Output
Table 1. Pin Description (Continued)
3F3P80D
NOVEMBER 2002
Page 9 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Symbol
Rating
Com’l & Ind’l
Unit
NOTES:
Terminal Voltage with
respect to GND
VTERM
-0.5 to + 4.5
V
Absolute Max Ratings are for reference only. Permanent damage to the device may
occur if extended period of operation is outside this range. Standard operation should
fall within the Recommended Operating Conditions.
TSTG
IOUT
Storage Temperature
DC Output Current
-55 to +125
-50 to +50
°C
mA
Table 2. Absolute Maximum Ratings
FQV80100, FQV8090, FQV8080, FQV8070,
FQV8060, FQV8050, FQV8040, FQV8030
Commercial
Industrial
Clock = 6ns, 7.5ns, 10ns
Clock = 7.5ns, 10ns
Symbol
Parameter
Min.
Typ.
Max. Min.
Typ.
Max.
Unit
Recommended Operating Conditions
Vcc
Supply Voltage Com’l / Ind’l
3.15
3.3
3.45
3.15
3.3
3.45
V
GND
VIH
VIL
TA
Supply Voltage
0
2.0
-
0
-
0
0
2.0
-
0
-
0
V
V
Input High Voltage Com’l /
Ind’l
5.5
0.8
70
85
5.5
0.8
70
85
Input Low Voltage Com’l /
-
-
V
Ind’l
Operating Temperature
Commercial
0
-
0
-
°C
°C
Operating Temperature
TA
-40
-
-40
-
Industrial
DC Electrical Characteristics
Input Leakage Current (any
ILI(1)
-10
-10
2.4
-
-
-
-
-
10
10
-
-10
-10
2.4
-
-
-
-
-
10
10
-
µA
µA
V
input)
ILO
Output Leakage Current
Output Logic “1” Voltage,
IOH=-2mA
Output Logic “0” Voltage, IOL
= 8mA
VOH
VOL
0.4
0.4
V
Power Consumption
Icc1(2,3)
Active Power Supply Current
Standby Current
-
-
-
-
40
15
-
-
-
-
40
15
mA
mA
Icc2(4)
Table 3. DC Specifications
3F3P80D
NOVEMBER 2002
Page 10 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Capacitance at 100MHz Ambient Temperature (25°C)
Symbol
Parameter
Conditions
Max.
Unit
(2)
CIN
Input Capacitance
VIN= 0V
10
pF
(2,4)
COUT
Output Capacitance
VOUT= 0V
10
pF
NOTES:
1. Measurement with 0.4<=VIN<=Vcc
2. With output tri-stated ( OE = High)
3. Icc(1,2) is measured with WCLK and RCLK at 20 MHz
4. Design simulated, not tested.
Table 3. DC Specifications (Continued)
3F3P80D
NOVEMBER 2002
Page 11 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Commercial
Commercial & Industrial
FQV80100-6
FQV8090-6
FQV8080-6
FQV8070-6
FQV8060-6
FQV8050-6
FQV8040-6
FQV8030-6
FQV80100-7.5
FQV80100-10
FQV8090-10
FQV8080-10
FQV8070-10
FQV8060-10
FQV8050-10
FQV8040-10
FQV8030-10
FQV8090-7.5
FQV8080-7.5
FQV8070-7.5
FQV8060-7.5
FQV8050-7.5
FQV8040-7.5
FQV8030-7.5
Symbol
fS
Parameter
Clock Cycle Frequency
Min.
-
Max.
Min.
-
Max.
133
Min.
-
Max.
100
Unit
MHz
ns
166
4
-
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
A
Data Access Time
1
2
5
-
-
-
-
-
-
-
-
-
-
-
2
6.5
WCLK
WCLKH
WCLKL
RCLK
RCLKH
RCLKL
DS
Write Clock Cycle Time
Write Clock High Time
Write Clock Low Time
Read Clock Cycle Time
Read Clock High Time
Read Clock Low Time
Data Set-up Time
6
7.5
3.5
3.5
7.5
3.5
3.5
2.5
0.5
2.5
0.5
10
15
10
-
10
4.5
4.5
10
4.5
4.5
3.5
0.5
3.5
0.5
10
15
10
-
-
-
ns
2.5
2.5
6
-
ns
-
-
ns
-
-
ns
2.5
2.5
2.0
0.5
2.0
0.5
8
-
-
ns
-
-
ns
-
-
ns
DH
Data Hold Time
-
-
ns
ENS
Enable Set-up Time
-
-
ns
ENH
Enable Hold Time
Reset Pulse Width(1)
-
-
ns
RST
-
-
ns
RSTS
RSTR
RSTF
OLZ
Reset Set-up Time
10
10
-
-
-
ns
Reset Recovery Time
-
-
15
-
-
ns
Reset to Flag and Output Time
Output Enable to Output in Low-Z(1)
Output Enable to Output Valid
Output Enable to Output in High-Z(1)
Write Clock to Full Flag
Read Clock to Empty Flag
10
-
15
-
ns
0
0
0
ns
OE
2
4
4
4
4
2
6
2
6
6
6.5
6.5
ns
OHZ
2
2
6
2
ns
FULL
EMPTY
-
-
5
-
ns
-
-
5
-
ns
Write Clock to Synchronous Almost-Full
Flag
t
t
PRAFS
PRAES
-
-
4
4
-
-
5
5
-
-
6.5
6.5
ns
ns
Read Clock to Synchronous Almost-
Empty Flag
t
t
t
t
RCSS
RCS Setup Time
2
0.5
1
-
-
3.5
0.5
1
-
3.5
0.5
1
-
ns
ns
ns
ns
RCSH
RCSLZ
RCSHZ
RCS Hold Time
-
-
RCLK to Active from High-Z
RCLK to High-Z
4
4
6.5
6.5
6.5
6.5
1
1
1
Table 4. AC Electrical Characteristics
3F3P80D
NOVEMBER 2002
Page 12 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Commercial
Commercial & Industrial
FQV80100-6
FQV8090-6
FQV8080-6
FQV8070-6
FQV8060-6
FQV8050-6
FQV8040-6
FQV8030-6
FQV80100-7.5
FQV80100-10
FQV8090-10
FQV8080-10
FQV8070-10
FQV8060-10
FQV8050-10
FQV8040-10
FQV8030-10
FQV8090-7.5
FQV8080-7.5
FQV8070-7.5
FQV8060-7.5
FQV8050-7.5
FQV8040-7.5
FQV8030-7.5
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Skew time between Read Clock &
Write Clock for Full Flag / Empty
Flag
t
t
SKEW1
4
-
5
-
7
-
ns
Skew time between Read Clock &
Write Clock for PRAE & PRAF
SKEW2
6
-
7
-
10
-
ns
t
t
t
t
LOADS
LOADH
RETS
Load Setup Time
Load Hold Time
2.0
0.5
2.5
-
-
-
2.5
0.5
3.5
-
-
3.5
0.5
3.5
-
-
-
ns
ns
ns
ns
-
-
Retransmit Setup Time
-
-
HALF
12
12.5
16
Clock to HALF
Write Clock to Asynchronous
Programmable Almost-Full Flag
t
t
PRAFA
-
-
12
12
-
-
12.5
12.5
-
-
16
16
ns
ns
Read Clock to Asynchronous
PRAEA
Programmable Almost-Empty Flag
NOTES:
1. Design simulated, not tested.
Table 4. AC Electrical Characteristics (Continued)
3F3P80D
NOVEMBER 2002
Page 13 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Input Pulse Levels
Input Rise/Fall Times
GND to 3.0V
3ns(1)
Input Timing Reference Levels
Output Reference Levels
Output Load, clock = 6ns, 7.5ns, 10ns
NOTES:
1.5V
1.5V
Refer to Figure 4
1. For 166 MHz and 133 MHz operations, input rise/fall times are 1.5ns
Table 5. AC Test Condition
Vcc/2
50 Ω
I/O
Z0 = 50 Ω
Figure 4. AC Test Load
for clock = 6ns, 7.5ns, 10ns
3F3P80D
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2002
Page 14 of 51
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Pin Functions
Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting
MRST low. In Standard mode, FULL and PRAF will go high, EMPTY and PRAE will go low. In
FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state
as Standard mode. In both modes, all data outputs will go low, and previous programmed configurations
will not be maintained.
MRST
Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting
PRST low. In Standard mode, FULL and PRAF will go high. EMPTY and PRAE will go low. In
FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state
as Standard mode. In both modes, all data outputs will go low, and previously programmed
configurations will be maintained.
PRST
WCLK
Writes data into queue during low to high transitions of WCLK if WEN is activated. Synchronizes
FULL / DRDY and PRAF flags. WCLK and RCLK are independent of each other.
Controls write operation into queue or offset registers during low to high transition of WCLK.
WEN
During Master Reset, set LOAD low to select parallel programming or one of eight default offset values.
Set LOAD high to select serial programming or one of eight default offset values. After Master Reset,
LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK
respectively for parallel programming. Use in conjunction with WEN / REN . During programming of
offset registers, PRAF and PRAE flag status are invalid. For Serial programming, LOAD is used to
enable serial loading of offset registers together with SDEN . Refer to Figure 5 for details.
LOAD
PFS1
PFS0
During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS0.
Refer to Table 11 for details.
During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS1.
Refer to Table 11 for details.
D79..0
80 - bit wide input data bus.
RCLK
Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the
EMPTY /QRDY and PRAE flags. RCLK and WCLK are independent of each other.
Reads data from queue during low to high transitions of RCLK if REN is set to low. This also advances
the Read pointer of the queue.
REN
Setting RCS low during the low to high transition of RCLK activates the data output drivers. Setting
RCS high during the low to high transition of RCLK deactivates the data output drivers. OE must be
set low when using RCS to control the state of the drivers.
RCS
OE
Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers
(High-Z). OE does not control advancement of Read pointer.
Q79..0
80 - bit wide output data bus.
FWFT/SDI
Selects First Word Fall Through timing or Standard timing mode during Master Reset. After Master
Reset, if serial programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for
the offset registers. Serial data is written during the low to high transition of WCLK. Use in conjunction
with SDEN . In FWFT mode, DRDY and QRDY are used instead of FULL and EMPTY . In
Standard mode, FULL and EMPTY are used instead of DRDY and QRDY . Refer to Table 8 & 9 for
all flags status.
SCLK
During serial programming, SCLK is used to program offset values through SDI.
3F3P80D
NOVEMBER 2002
Page 15 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Pin Functions (Continued)
SDEN
If serial programming is selected, setting SDEN and LOAD low enables serial data to be written
into offset registers during the low to high transition of SCLK. During serial programming, PRAF
and PRAE flags status are invalid. Refer to Figure 5 for details.
BM2
BM1
BM0
ES
During Master Reset, select one of five input and output bus width configurations. Use in
conjunction with BM1 and BM0. Refer to Table 10 for details.
During Master Reset, select one of five input and output bus width configurations. Use in
conjunction with BM2 and BM0. Refer to Table 10 for details.
During Master Reset, select one of five input and output bus width configurations. Use in
conjunction with BM2 and BM1. Refer to Table 10 for details.
During Master Reset, set ES high to select byte re-ordering on data outputs or set ES low to select no
byte re-ordering on data outputs. ES must be static throughout device operation. Refer to Table 10
for details.
RET
Data previously read from the queue can be retransmitted by asserting RET pin at the low to high
transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence,
all re-reads will always start from the physical 0th (Read pointer = zero) location of the queue. Refer
to Diagram 9 & 10 for details.
RETZL
During Master Reset, set RETZL low to select zero latency retransmit. Set RETZL high to select
normal latency retransmit.
FULL / DRDY
In Standard mode, queue is full when FULL goes low during the low to high transition of WCLK.
This prohibits further writes into the queue and prevents advancement of Write pointer. In FWFT
mode, queue is full when DRDY goes low during the low to high transition of WCLK. This
prohibits further writes into the queue and prevents advancement of Write pointer. Refer to Table 8
& 9 for behavior of FULL / DRDY .
EMPTY / QRDY In Standard mode, queue is empty when EMPTY goes low during the low to high transition of
RCLK. This prohibits further reads from the queue and prevents advancement of Read pointer. In
FWFT mode, queue is empty when QRDY goes low during the low to high transition of RCLK.
This prohibits further reads from the queue and prevents advancement of Read pointer. Refer to
Table 8 & 9 for behavior of EMPTY / QRDY .
IPAR
During Master Reset, set IPAR low to select 10-bit parallel programming mode or set IPAR high to
select 8-bit parallel programming mode. In 10-bit mode, 10-bit wide data input / output bus width is
used for storing / fetching offset values. In 8-bit mode, 8-bit wide data input / output bus is used for
storing / fetching offset values.
SFM
During Master Reset, set SFM high to select Synchronous Partial Flag mode or set SFM low to select
Asynchronous Partial Flag mode. In Synchronous mode, PRAF and PRAE are synchronous to
WCLK and RCLK respectively. In Asynchronous mode, WCLK synchronizes the assertion of
PRAF and de-assertion of PRAE . RCLK synchronizes the assertion of PRAE and de-assertion of
PRAF .
PRAF
PRAE
Queue is almost full when PRAF goes low during the low to high transition of WCLK. Default
(Full-offset) or programmed offset values determine the status of PRAF . Refer to Table 8 & 9 for
behavior of PRAF .
Queue is almost empty when PRAE goes low during the low to high transition of RCLK. Default
(Empty+offset) or programmed offset values determine the status of PRAE . Refer to Table 8 & 9
for behavior of PRAE .
3F3P80D
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2002
Page 16 of 51
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Pin Functions (Continued)
HALF
Queue is more than half full when HALF goes low during the low to high transition of WCLK.
Queue is less than half full when HALF goes high during low to high transition of RCLK when.
Refer to Table 8 & 9 for details.
3F3P80D
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2002
Page 17 of 51
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
FQV80100
FQV8090
FQV8080
FQV8070
WCLK
RCLK
SCLK
LOAD
WEN
REN
SDEN
FQV8060
FQV8050
FQV8040
FQV8030
Selection / Sequence
Parallel write to offset
Parallel write
to registers:
1. PRAE
registers:
0
0
0
1
1
0
1
1
X
X
X
Empty Offset
Full Offset
2. PRAF
Parallel read from offset
registers:
Empty Offset
Full Offset
Parallel read
from registers:
1. PRAE
X
2. PRAF
Serial shift into registers:
32 bits for the FQV80100
30 bits for the FQV8090
28 bits for the FQV8080
26 bits for the FQV8070
24 bits for the FQV8060
22 bits for the FQV8050
20 bits for the FQV8040
18 bits for the FQV8030
1 bit for each rising SCLK edge
0
1
1
0
X
X
X
Starting with Empty Offset (Low Byte)
Ending with Full Offset (High Byte)
X
1
1
0
1
1
X
X
X
X
No Operation
X
X
Write Memory
1
1
X
1
0
1
X
X
X
X
X
X
Read Memory
No Operation
X
Figure 5. Programmable Flag Offset Programming Sequence
(FQV80100, FQV8090, FQV8080, FQV8070, FQV8060, FQV8050, FQV8040 and FQV8030)
3F3P80D
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2002
Page 18 of 51
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Device
PRAF Programming (bits)
Non-IPAR
PRAE Programming (bits)
Non-IPAR
D/Q15 - 0
D/Q15 - 0
FQV80100
D/Q17 –10 & D/Q7 – 0
D/Q14 - 0
IPAR
D/Q17 – 10 & D/Q7 – 0
D/Q14 - 0
IPAR
Non-IPAR
IPAR
Non-IPAR
IPAR
FQV8090
FQV8080
FQV8070
FQV8060
FQV8050
FQV8040
FQV8030
D/Q16 – 10 & D/Q7 – 0
D/Q13 - 0
D/Q16 – 10 & D/Q7 – 0
D/Q13 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q15 – 10 & D/Q7 – 0
D/Q12 - 0
D/Q15 – 10 & D/Q7 – 0
D/Q12 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q14 – 10 & D/Q7 – 0
D/Q11 - 0
D/Q14 – 10 & D/Q7 – 0
D/Q11 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q13 – 10 & D/Q7 – 0
D/Q10 - 0
D/Q13 – 10 & D/Q7 – 0
D/Q10 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q12 – 10 & D/Q7 – 0
D/Q9 - 0
D/Q12 – 10 & D/Q7 – 0
D/Q9 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q11 – 10 & D/Q7 – 0
D/Q8 - 0
D/Q11 – 10 & D/Q7 – 0
D/Q8 - 0
Non-IPAR
IPAR
Non-IPAR
IPAR
D/Q10 & D/Q7 – 0
D/Q10 & D/Q7 – 0
Table 6. Parallel Offset Register Data Mapping Table for x80 & x40& x20
Device
Standard Mode
FWFT Mode
FQV80100
FQV8090
FQV8080
FQV8070
FQV8060
FQV8050
FQV8040
FQV8030
65,536 x 80
32,768 x 80
16,384 x 80
8,192 x 80
4,096 x 80
2,048 x 80
1,024 x 80
512 x 80
65,537 x 80
32,769 x 80
16,385 x 80
8,193 x 80
4,097 x 80
2,049 x 80
1,025 x 80
513 x 80
Table 7. Maximum Depth of Queue for Standard and FWFT Mode
3F3P80D
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2002
Page 19 of 51
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
D/Q6
D/Q19 D/Q18 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9
D/Q8
D/Q7
D/Q5
D/Q4
D/Q3
D/Q2 D/Q1
D/Q0
Data Width
1st Cycle PRAE
Non-Interspersed Parity
Interspersed Parity
15
15
14
14
13
13
12
12
11
11
10
10
9
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
17
16
D/Q6
D/Q19 D/Q18 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9
D/Q8
D/Q7
D/Q5
D/Q4
D/Q3
D/Q2 D/Q1
D/Q0
Data Width
PRAF
2nd Cycle
15
15
14
14
13
13
12
12
11
11
10
10
9
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Non-Interspersed Parity
17
16
Interspersed Parity
FQV80100, FQV8090, FQV8080, FQV8070, FQV8060, FQV8050, FQV8040, FQV8030
Parallel Offset Write/Read Cycles for x20 Bus Width
D/Q39 D/Q~
D/Q~
D/Q~ D/Q19 D/Q18 D/Q17 D/Q16 D/Q15
D/Q3
D/Q2
D/Q1 D/Q0
Data Width
D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9
D/Q8
D/Q7 D/Q6
D/Q5
D/Q4
1st Cycle PRAE
Non-Interspersed Parity
Interspersed Parity
15
14
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
13
11
12
10
11
9
10
8
9
8
15
14
13
12
D/Q39
D/Q~
D/Q17 D/Q16 D/Q15
D/Q3
D/Q2
D/Q1 D/Q0
D/Q14 D/Q13 D/Q12
D/Q10 D/Q9
D/Q8
D/Q7 D/Q6
D/Q5
D/Q4
D/Q~
D/Q~ D/Q19 D/Q18
D/Q11
Data Width
2nd Cycle
PRAF
13
11
12
10
11
9
10
8
9
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
15
13
14
12
Non-Interspersed Parity
Interspersed Parity
15
14
FQV80100, FQV8090, FQV8080, FQV8070, FQV8060, FQV8050, FQV8040, FQV8030
Parallel Offset Write/Read Cycles for x40 Bus Width
D/Q16 D/Q15
D/Q3
D/Q2
D/Q1 D/Q0
D/Q17
D/Q14 D/Q13 D/Q12
D/Q10 D/Q9
D/Q8
D/Q7 D/Q6
D/Q5
D/Q4
D/Q79 D/Q~
D/Q~
D/Q~ D/Q19 D/Q18
D/Q11
Data Width
1st Cycle
PRAE
15
14
13
11
12
10
11
9
10
8
9
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Non-Interspersed Parity
Interspersed Parity
15
14
13
12
D/Q17 D/Q16 D/Q15
D/Q3
D/Q2
D/Q1 D/Q0
D/Q79 D/Q~
D/Q~
D/Q~
D/Q19 D/Q18
D/Q14 D/Q13 D/Q12
D/Q10 D/Q9
D/Q8
D/Q7 D/Q6
D/Q5
D/Q4
D/Q11
Data Width
PRAF
2nd Cycle
13
11
12
10
11
9
10
8
9
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
15
13
14
12
Non-Interspersed Parity
Interspersed Parity
15
14
FQV80100, FQV8090, FQV8080, FQV8070, FQV8060, FQV8050, FQV8040, FQV8030
Parallel Offset Write/Read Cycles for x80 Bus Width
Figure 6. Parallel Offset Write/Read Cycles Diagram
3F3P80D
NOVEMBER 2002
Page 20 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
# of Bits for Offset Registers
16 bits for FQV80100
15 bits for FQV8090
14 bits for FQV8080
13 bits for FQV8070
12 bits for FQV8060
11 bits for FQV8050
10 bits for FQV8040
9 bits for FQV8030
Note: Don’t Care applies to all unused bits
Figure 6. Parallel Offset Write/Read Cycles Diagram (Continued)
3F3P80D
NOVEMBER 2002
Page 21 of 51
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
FQV80100
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y(1)
(y+1) to 32,768
32,769 to [65,536-(x+1)]
(65,536 –x(1)) to 65,535
65,536
H
H
H
H
L
FQV8090
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y
(y+1) to 16,384
16,385 to [32,768-(x+1)]
(32,768 –x) to 32,767
32,768
H
H
H
H
L
FQV8080
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y
(y+1) to 8,192
8,193 to [16,384-(x+1)]
(16,384 –x) to 16,383
16,384
H
H
H
H
L
FQV8070
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y
(y+1) to 4,096
4,097 to [8,192-(x+1)]
(8,192 -x) to 8,191
8,192
H
H
H
H
L
FQV8060
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y
(y+1) to 2,048
2,049 to [4,096-(x+1)]
(4,096 –x) to 4,095
4,096
H
H
H
H
L
FQV8050
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y
(y+1) to 1,024
1,025 to [2,048-(x+1)]
(2,048 -x) to 2,047
2,048
H
H
H
H
L
Table 8. Status Flags (Standard Mode)
3F3P80D
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
FQV8040
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y
(y+1) to 512
513 to [1,024-(x+1)]
(1,024 –x) to 1,023
1,024
H
H
H
H
L
FQV8030
0
FULL
PRAF
HALF
PRAE
EMPTY
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y
(y+1) to 256
257 to [512-(x+1)]
(512 –x) to 511
512
H
H
H
H
L
NOTES:
1.
See Table 11 for values x, y.
Table 8. Status Flags (Standard Mode)(Continued)
3F3P80D
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NOVEMBER 2002
Page 23 of 51
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
FQV80100
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to y+1
(y+2) to 32,769
32,770 to [65,537-(x+1)]
(65,537 –x) to 65,536
65,537
H
H
H
H
L
FQV8090
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to y+1
(y+2) to 16,385
16,386 to [32,769-(x+1)]
(32,769 –x) to 32,768
32,769
H
H
H
H
L
FQV8080
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to y+1
(y+2) to 8,193
8,194 to [16,385-(x+1)]
(16,385 -x) to 16,384
16,385
H
H
H
H
L
FQV8070
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to y+1
(y+2) to 4,097
4,098 to [8,193-(x+1)]
(8,193-x) to 8,192
8,193
H
H
H
H
L
FQV8060
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to y+1
(y+2) to 2,049
2,050 to [4,097-(x+1)]
(4,097 -x) to 4,096
4,097
H
H
H
H
L
FQV8050
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to y+1
(y+2) to 1,025
1,026 to [2,049-(x+1)]
(2,049 -x) to 2,048
2,049
H
H
H
H
L
Table 9. Status Flags (FWFT Mode)
3F3P80D
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NOVEMBER 2002
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
FQV8040
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to y+1
(y+2) to 513
514 to [1,025-(x+1)]
(1,025 -x) to 1,024
1,025
H
H
H
H
L
FQV8030
QRDY
DRDY
PRAF
HALF
PRAE
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to y+1
(y+2) to 257
258 to [513-(x+1)]
(513 -x) to 512
513
H
H
H
H
L
Table 9. Status Flags (FWFT Mode)(Continued)
3F3P80D
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NOVEMBER 2002
Page 25 of 51
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
ES
BM2
BM1
BM0
I/O
Width D/Q79-60 D/Q59-40 D/Q39-20 D/Q19-0
Sequence
X
0
X
X
I
O
80
80
Byte 4
Byte 4
Byte 3
Byte 3
Byte 2
Byte 2
Byte 1
Byte 1
1st Write
1st Read
0
0
1
1
0
0
0
1
I
O
80
40
Byte 4
X
X
Byte 3
X
X
Byte 2
Byte 4
Byte 2
Byte 1
Byte 3
Byte 1
1st Write
1st Read
2nd Read
I
O
80
20
Byte 4
Byte 3
Byte 2
Byte 1
Byte 4
Byte 3
Byte 2
Byte1
1st Write
1st Read
2nd Read
3rd Read
4th Read
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
1
0
1
I
O
I
40
80
20
X
X
Byte 4
X
X
Byte 3
Byte 4
Byte 2
Byte 2
Byte 3
Byte 1
Byte 1
1st Write
2nd Write
1st Read
X
X
X
X
Byte 4
X
X
X
X
Byte 3
X
X
X
X
Byte 2
Byte 4
Byte 3
Byte 2
Byte1
Byte 1
1st Write
2nd Write
3rd Write
4th Write
1st Read
O
80
1
1
1
1
0
0
0
1
I
O
80
40
Byte 4
X
X
Byte 3
X
X
Byte 2
Byte 2
Byte 4
Byte 1
Byte 1
Byte 3
1st Write
1st Read
2nd Read
I
O
80
20
Byte 4
Byte 3
Byte 2
Byte 1
Byte 1
Byte 2
Byte 3
Byte4
1st Write
1st Read
2nd Read
3rd Read
4th Read
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
0
1
I
O
I
40
80
20
X
X
Byte 2
X
X
Byte 1
Byte 4
Byte 2
Byte 4
Byte 3
Byte 1
Byte 3
1st Write
2nd Write
1st Read
X
X
X
X
Byte 1
X
X
X
X
Byte 2
X
X
X
X
Byte 3
Byte 4
Byte 3
Byte 2
Byte1
Byte 4
1st Write
2nd Write
3rd Write
4th Write
1st Read
O
80
Table 10. Bus-Matching Table
3F3P80D
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NOVEMBER 2002
Page 26 of 51
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
FQV8040
FQV8030
PFS1
PFS0
LOAD
Default Offsets x, y(1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
127
255
511
63
31
7
15
3
FQV8040
FQV8030
Program Mode
Serial
PFS1
PFS0
LOAD
1
0
X
X
X
X
Parallel
FQV8080
FQV8070
FQV8060
FQV8050
PFS1
PFS0
LOAD
Default Offsets x, y(1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
127
255
511
63
1,023
15
31
7
FQV8080
FQV8070
FQV8060
FQV8050
PFS1
PFS0
LOAD
Program Mode
Serial
1
0
X
X
X
X
Parallel
NOTES:
1.
y = PRAE offset, x = PRAF offset
Table 11. Default Programmable Flag Offsets
3F3P80D
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NOVEMBER 2002
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
FQV80100
FQV8090
PFS1
PFS0
LOAD
Default Offsets x, y(1)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
127
8,191
16,383
4,095
1,023
511
2,047
255
FQV80100
FQV8090
Program Mode
Serial
PFS1
PFS0
LOAD
1
0
X
X
X
X
Parallel
NOTES:
1.
y = PRAE offset, x = PRAF offset
Table 11. Default Programmable Flag Offsets (Continued)
3F3P80D
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NOVEMBER 2002
Page 28 of 51
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
JTAG Interface
Standard JTAG interface is used for boundary scan purposes. For a complete description, please refer to the IEEE Standard Test
Access Port Specification (IEEE STD.1149.1 – 1990)
JTAG TIMING SPECIFICATIONS
tTCK
t4
t3
t1
t2
TCK
TDI / TMS
TDO
tDS
tDH
TDO
t6
tDO
TRST
t5
Figure 7. Standard JTAG Timing
FQV80100
FQV8090
FQV8080
FQV8070
FQV8060
FQV8050
FQV8040
FQV8030
Max.
Test
Parameter
Symbol
Conditions
Min.
Units
System Interface Parameters
Data Output
Data Output Hold
-
-
5
5
30
30
50
ns
ns
tDO = Max
-
-
-
tDOH
tDS
trise = 3ns
Data Input
ns
tDH
tfall = 3ns
JTAG AC Electrical Characteristics
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
-
-
-
-
-
-
-
100
40
40
-
-
50
50
-
-
-
5
5
-
ns
ns
ns
ns
ns
ns
ns
tTCK
tTCKHIGH (t2)
tTCKLOW (t1)
tTCKRise (t4)
tTCKFall (t3)
tRST (t5)
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
JTAG Reset Recovery
-
tRSR (t6)
Table 12. JTAG AC Electrical Characteristics
3F3P80D
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NOVEMBER 2002
Page 29 of 51
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
JTAG BLOCK DIAGRAM
HBA’s FlexQ™ offers IEEE Std. 1149.1-1990 standard JTAG interface to facilitate system debugging in all PBGA packages.
STANDARD JTAG INTERFACE ELEMENTS:
1. TAP
2. TAPCNTL
3. IR
– TEST ACCESS PORT
– TAP CONTROLLER
– INSTRUCTION REGISTER
– DATA REGISTER
4. DR
Boundary Scan Reg.
TDO
TDI
Device ID Reg.
Bypass Reg.
TAP
TMS
TCLK
TRST
Instruction Decode
Instruction Register
DR
IR
TAP
Controller
Figure 8. Boundary Scan Architecture Diagram
3F3P80D
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NOVEMBER 2002
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
1. TAP
The basic ports to access the JTAG function. That includes four general input ports: TRST ,
TCK, TMS, and TDI, and one general output port: TDO.
A finite state machine that provides instructions to the Instruction and Data Registers for data
capture and update. Individual states are explained below.
2. TAPCNTL
1
0
Test-Logic
Reset
0
1
1
1
Run-Test /
Idle
Select-DR-
Scan
Select-IR-
Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
0
0
Shift-DR
Shift-IR
1
1
Input = TMS
1
1
Exit1-DR
Exit1-IR
0
0
Pause-DR
Pause-IR
1
1
0
0
Exit2-DR
Exit2-IR
1
1
Update-DR
Update-IR
1
0
1
0
Figure 9. TAP Controller State Diagram
Data are captured in parallel into the instruction register.
Data are captured in parallel into the data register.
•
•
•
Capture-IR
Capture-DR
SHIFT-IR
LSB of the instruction register is shift in serially during a low to high transition of the
TCK through TDI/TDO path
LSB of the data register is shift in serially during a low to high transition of the TCK
through TDI/TDO path.
•
SHIFT-DR
3F3P80D
NOVEMBER 2002
Page 31 of 51
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
To shift Instruction Register Data to the parallel outputs. Instruction Register Data can
be accessed through the internal bus.
To shift Data Register Data to the parallel outputs. Data Register Data can be accessed
through the internal bus.
A transition state that terminates the scanning process. All Instruction Register data
selected will retain their previous instruction state.
•
•
•
•
•
•
UPDATE-IR
UPDATE-DR
EXIT1-IR/
EXIT2-IR
EXIT1-DR/
EXIT2-DR
A transition state that terminates the scanning process. All Data Register data selected
will retain their previous data state.
The temporary state to halt all serial shifting process between TDI and TDO. All data
will retain their previous instruction state.
The temporary state to halt all serial shifting process between TDI and TDO. All data
will retain their previous data state.
PAUSE-IR
PAUSE-DR
A 4 - bit instruction register that is shifted serially at the rising edge of TCLK. The instruction is
latched through the least significant bits of the nearest serial OUTPUT.
3. INSTRUCTION
REGISTER
Hex Value
Instruction
EXTEST
IDCODE
SAMPLE/PRELOAD
HI-Z
BYPASS
Function
0 x 00
0 x 02
0 x 01
0 x 03
0 x 0F
Select Boundary Scan Register
Select Chip Identification data register
Select Boundary Scan Register
JTAG
Select Bypass Register
Table 13. JTAG Instruction Register Decoding Table
An instruction to facilitate external circuitry and board level interconnection verification.
An instruction to read out manufacture’s identification, part number and version number.
•
•
•
EXTEST
IDCODE
An instruction to allow snapshots of data flowing through the system pins. SAMPLE
instruction MUST be executed prior to the selection of Boundary Scan test.
SAMPLE/
PRE-LOAD
An Instruction to place all output pins to high impedance state.
•
•
HIGH Z
BYPASS
An Instruction to allow direct serial data shifting through TDI and TDO without any device
operation.
There are three data registers, Device ID register, BYPASS register, and Boundary Scan register.
These parallel-connected registers are access through the common serial input and the common
serial output.
4. DATA REGISTER
A 32-bit register that contains the specific manufacturer, part number and version
number.
•
Device ID
Register
3F3P80D
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NOVEMBER 2002
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
31(MSB)
Version (4 bits)
0x0
28 27
Part Number (16-bit)
12 11
Manufacturer ID (11-bit)
0x16E
1
0(LSB)
1
Device
FQV80100
FQV8090
FQV8080
FQV8070
FQV8060
FQV8050
FQV8040
FQV8030
Part # Field
0 x 8050
0 x 8056
0 x 8055
0 x 8054
0 x 8053
0 x 8052
0 x 8051
0 x 8057
Table 14. Device ID Register Decode Table
The data register that allows direct serial data shifting through TDI and TDO without
any device operation.
•
•
BYPASS
Register
BOUNDARY
The data register that allows the serial writes and read through TDI and TDO.
SCAN Register
3F3P80D
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NOVEMBER 2002
Page 33 of 51
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Timing Diagrams
tRST
MRST
tRSTR
tRSTS
REN
WEN
tRSTR
tRSTS
tRSTR
tRSTS
tRSTS
tRSTS
FWFT/SDI
tRSTR
LOAD
PFS1/PFS0
tRSTS
BM2/BM1/BM0
ES
tRSTS
tRSTS
tRSTS
tRSTS
tRSTS
tRSTS
RETZL
SFM
IPAR
RET
SDEN
tRSTF
tRSTF
tRSTF
tRSTF
tRSTF
If FWFT = 1,QRDY = 1
If FWFT = 0,EMPTY = 0
EMPTY /QRDY
FULL / DRDY
PRAE
If FWFT = 0,FULL = 1
If FWFT = 1,DRDY = 0
PRAF , HALF
OE = 1
OE = 0
Q79- 0
Diagram 1. Master Reset Timing
3F3P80D
NOVEMBER 2002
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© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
tRST
PRST
REN
tRSTR
tRSTR
tRSTS
tRSTS
tRSTS
tRSTS
WEN
RET
SDEN
EMPTY/QRDY
FULL/ DRDY
PRAE
tRSTF
tRSTF
tRSTF
tRSTF
tRSTF
If FWFT = 1,QRDY = 1
If FWFT = 0,EMPTY= 0
If FWFT = 0,FULL = 1
If FWFT = 1,
= 0
DRDY
PRAF, HALF
OE = 1
OE = 0
Q79-0
Diagram 2. Partial Reset Timing
3F3P80D
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NOVEMBER 2002
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
3F3P80D
NOVEMBER 2002
Page 36 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
3F3P80D
NOVEMBER 2002
Page 37 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
3F3P80D
NOVEMBER 2002
Page 38 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
3F3P80D
NOVEMBER 2002
Page 39 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
3F3P80D
NOVEMBER 2002
Page 40 of 51
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
3F3P80D
NOVEMBER 2002
Page 41 of 51
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
RCLK
REN
1
2
tENS
tENH
tA
tRETS
tENS
tENH
tA
tA
Q 79- 0
DWi
DWi+1
DW1
DW2
tSKEW2
WCLK
WEN
1
2
tRETS
tENS
tENH
RET
tEMPTY
tEMPTY
EMPTY
PRAE
HALF
PRAF
tPRAES
tHALF
tPRAFS
NOTES:
1.
2.
3.
4.
Upon completion of retransmit setup, a read operation can begin only after EMPTY returns high.
OE = Low.
DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.
Upon reset completion, there must be more than 2 words written to the queue for a retransmit setup to be valid.
Diagram 9. Retransmit Timing (Standard Mode)
3F3P80D
NOVEMBER 2002
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
4
RCLK
REN
1
2
3
tENS
tENH
tRETS
tENS
tENH
tA
tA
tA
tA
Q
DWi
DWi+1
DW1
DW2
DW3
DW4
79 - 0
tSKEW2
WCLK
1
2
tRETS
WEN
RET
tENS
tENH
tEMPTY
tEMPTY
QRDY
PRAE
tPRAES
tHALF
HALF
PRAF
tPRAFS
NOTES:
1.
2.
3.
4.
5.
Upon completion of retransmit setup, a read operation can begin only after QRDY returns low.
OE = Low.
DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.
Upon reset completion, there must be more than 2 words written to the queue for a retransmit setup to be valid.
Please refer to Table 7 for Depth.
Diagram 10. Retransmit Timing (FWFT Mode)
3F3P80D
NOVEMBER 2002
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
RCLK
1
2
3
tENS
tENH
REN
tA
tA
tA
tA
tA
Q 79- 0
DWi+1
DW1
DW2
DW3
DW4
DWi
tSKEW2
WCLK
1
2
tRETS
WEN
RET
tENS
tENH
EMPTY
PRAE
tPRAES
tHALF
HALF
tPRAFS
PRAF
NOTES:
1.
If the part is empty at the point of retransmit, the Empty Flag ( EMPTY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will
appear on the output.
2.
3.
4.
OE = Low; enables data to be read on outputs Q79 – 0.
DW1= first word written to the queue after Master Reset; DW2= second word written to the queue after Master Reset.
No more than D-2 may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, FULL will be high throughout the
retransmit setup procedure. Please refer to Table 7 for Depth.
5.
6.
There must be at least two words written to zero latency retransmit from the queue before a retransmit operation can be invoked.
RETZL is set Low during MRST .
Diagram 11. Zero Latency Retransmit Timing (Standard Mode)
3F3P80D
NOVEMBER 2002
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
1
RCLK
REN
2
3
4
5
tENH
tENS
tA
tA
tA
tA
tA
tA
DWi
DW i+1
DW1
DW2
DW3
DW4
Q 79 - 0
WCLK
WEN
DW5
tSKEW2
1
2
tRETS
tENS
tENH
RET
QRDY
tPRAES
PRAE
HALF
tHALF
tPRAFS
PRAF
NOTES:
1.
If the part is empty at the point of retransmit, the output ready flag ( QRDY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will
appear on the output.
2.
No more than D-2 words maybe written to the queue between reset (Master or Partial) and retransmit setup. Therefore, DRDY will be low throughout
the retransmit setup procedure. Please refer to Table 7 for Depth.
3.
4.
5.
6.
OE = Low.
DW1, DW2, DW3 = first, second and third words written to the queue after Master Reset.
There must be at least two words written to the queue before a retransmit operation can be invoked.
RETZL is set low during MRST .
Diagram 12. Zero Latency Retransmit Timing (FWFT Mode)
3F3P80D
NOVEMBER 2002
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
SCLK
SDEN
LOAD
SDI
tENS
tLOADS
tDS
tENH
tENH
tLOADH
tDH
tLOADH
BIT 0
BIT MSB
BIT 0
BIT MSB
PRAF
PRAE offset
offset
*Refer to Table 13
Diagram 13. Serial Loading of Programmable Flag Registers (Standard and FWFT Mode)
FQV80100
FQV8090
FQV8080
FQV8070
FQV8060
FQV8050
FQV8040
FQV8030
15
14
13
12
11
10
9
8
MSB
Table 13. Reference Table for Diagram 13
3F3P80D
NOVEMBER 2002
Page 46 of 51
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
tWCLK
tWCLKH
tWCLKL
WCLK
tLOADH
tLOADS
tENS
tLOADH
tENH
LOAD
WEN
D 79 - 0
tENH
tDS
tDH tDS
tDH
PRAE
PRAF
offset
offset
Diagram 14. Parallel Loading of Programmable Flag Registers for (Standard and FWFT Mode)
tRCLK
tRCLKH
tRCLKL
RCLK
tLOADH
tENH
tLOADS
tLOADH
LOAD
REN
tENS
tENH
tA
tA
Q 79- 0
Output Register Data
PRAF
PRAE offset
offset
NOTES:
1.
OE = Low, RCS = Low.
Diagram 15. Parallel Read of Programmable Flag Registers for (Standard and FWFT Mode)
3F3P80D
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NOVEMBER 2002
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
tWCLKH
tWCLKL
WCLK
1
2
1
2
tENS
tENH
WEN
tPRAFS
tPRAFS
D - ( x + 1 )
PRAF
D - x words in Queue
D - ( x + 1 ) words in Queue
words in Queue
tSKEW2
RCLK
REN
tENS
tENH
NOTES:
1.
2.
3.
x = _P__R___A___F__ offset.
D = maximum queue depth. Please refer to Table 7 for Depth.
___________
If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF will go high (after on WCLK cycle
plus tPRAFS). If tSKEW2 is not met, then _P__R___A___F__ will assert 1 or more WCLK cycles.
___________
4.
PRAF synchronizes to the rising edge of WCLK only.
Diagram 16. Synchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)
tWCLKH
tWCLKL
WCLK
tENS
tENH
WEN
y words in Queue(2)
y+1 words in Queue(3)
;
y words in Queue(2) ; y+1 words in Queue(3)
y+1 words in Queue(2) ; y+2 words in Queue(3)
PRAE
tSKEW2
tPRAES
tPRAES
RCLK
REN
1
2
1
2
tENS
tENH
NOTES:
1.
2.
3.
4.
y = PRAE offset.
For Standard Mode.
For FWFT Mode.
If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE will go high (after one RCLK cycle
plus tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles.
5.
PRAE synchronizes to the rising edge of RCLK only.
Diagram 17. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)
3F3P80D
NOVEMBER 2002
Page 48 of 51
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
tWCLKH
tWCLKL
WCLK
WEN
tENS
tENH
tPRAFA
D - x words in
Queue
PRAF
RCLK
D - ( x + 1) words in Queue
D - ( x + 1) words in Queue
tPRAFA
tENS
REN
NOTES:
1.
2.
3.
4.
x = PRAF offset.
D = maximum queue depth. Please refer to Table 7 for Depth.
PRAF is asserted to low on WCLK transition and reset to high on RCLK transition.
Select this mode by setting SFM low during Master Reset.
Diagram 18. Asynchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)
tWCLKH
tWCLKL
WCLK
WEN
tENS
tENH
tPRAEA
y+1 words in
Queue(2); y+2
y words in Queue(2); y+1 words in Queue(3)
y words in Queue(2); y+1 words in Queue(3)
PRAE
RCLK
REN
words in Queue (3)
tPRAEA
tENS
NOTES:
1.
2.
3.
4.
5.
y = PRAE offset.
For Standard Mode.
For FWFT Mode.
PRAE is asserted to low on RCLK transition and reset to high on WCLK transition.
Select this mode by setting SFM low during Master Reset.
Diagram 19. Asynchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)
3F3P80D
NOVEMBER 2002
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
tWCLKH
tWCLKL
WCLK
WEN
tENS
tENH
D/2 + 1 words in
Queue(1)
;
tHALF
[(D+1)/2 + 1] words in
Queue(2)
D/2 words in Queue(1); [(D+1)/2]
words in Queue(2)
D/2 words in Queue(1); [(D+1)/2] words in Queue(2)
HALF
RCLK
tHALF
tENS
REN
NOTES:
1.
2.
3.
For Standard Mode.
For FWFT Mode.
Please refer to Table 7 for Depth.
Diagram 20. Half-Full Flag Timing (Standard and FWFT Mode)
3F3P80D
NOVEMBER 2002
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FQV80100 · FQV8090 · FQV8080 · FQV8070 · FQV8060 · FQV8050 · FQV8040· FQV8030
TMIII Plus
Order Information:
HBA
Device Type
Power Speed (ns) *
Package**
Temperature Range
Device Family
XX
FQ
XXXXX
X
Low
XX
6
XX
BB
X
– 166 MHz
Blank – Commercial (0°C to 70°C)
V80100 (65,536 x 80)
7-5 – 133 MHz
10 – 100 MHz
I – Industrial (-40° to 85°C)
V8090 (32,768 x 80)
V8080 (16,384 x 80)
V8070 (8,192 x 80)
V8060 (4,096 x 80)
V8050 (2,048 x 80)
V8040 (1,024 x 80)
V8030 (512 x 80)
*Speed – 6ns available only in Commercial temp (0°C to 70°C)
**Package – 256 pin Fine Pitch Ball Grid Array (BGA)
Example:
FQV8070L6BB
FQV8060L10BBI
(8k x 80, 6ns, Commercial temp)
(4k x 80, 10ns, Industrial temp)
Document Revision History:
11/04/02 pg. 1, 3, 4, 5, 6, 15, 18, 31
11/15/02 pg. 9, 11, 12, 14, 15, 16, 22, 23, 31, 34, 35, 36, 37, 38, 39, 45, 47, 48, 50
USA
Taiwan
2107 North First Street, Suite 415
San Jose, CA 95131, USA
www.hba.com
Tel: 408.453.8885
Fax: 408.453.8886
No. 81, Suite 8F-9, Shui-Lee Rd.
Hsinchu, Taiwan, R.O.C.
www.hba.com
Tel: 886.3.516.9118
Fax: 886.3.516.9181
3F3P80D
NOVEMBER 2002
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© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
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