FQV291L7.5PFI [AMICC]

FIFO, 128KX9, 5ns, Synchronous, CMOS, PQFP64;
FQV291L7.5PFI
型号: FQV291L7.5PFI
厂家: AMIC TECHNOLOGY    AMIC TECHNOLOGY
描述:

FIFO, 128KX9, 5ns, Synchronous, CMOS, PQFP64

时钟 先进先出芯片 内存集成电路
文件: 总33页 (文件大小:355K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
3.3 Volt Synchronous x9 First-In/First-Out Queue  
Memory Configuration Part Number  
524,288 x 9  
262,144 x 9  
131,072 x 9  
65,536 x 9  
32,768 x 9  
16,384 x 9  
FQV2111  
FQV2101  
FQV291  
FQV281  
FQV271  
FQV261  
Key Features  
Industry leading First-In/First-Out Queues (up to 133MHz)  
Write cycle time of 7.5ns independent of Read cycle time  
Read cycle time of 7.5ns independent of Write cycle time  
User selectable input and output port bus-sizing  
Big Endian/Little Endian user selectable byte representation  
3.3V power supply  
5V input tolerant on all control and data input pins  
5V output tolerant on all flags and data output pins  
Master Reset clears all previously programmed configurations including Write and Read pointers.  
Partial Reset clears Write and Read pointers but maintains all previously programmed configurations.  
First Word Fall Through (FWFT) and Standard Timing modes  
Preset for Almost Full ( PRAF ) and Almost Empty ( PRAE ) offsets values  
Parallel/Serial programming of PRAF and PRAE offset values  
Full, Empty, Almost Full, Almost Empty and Half Full indicators  
Asynchronous output enable tri-state data output drivers  
Data retransmission  
Available package: 64 - pin Plastic Thin Quad Flat Pack (TQFP), 64 – pin Slim Thin Quad Flat Pack (STQFP)  
(0°C to 70°C) Commercial operating temperature available for cycle time of 7.5ns and above  
(-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above  
Product Description  
HBA’s FlexQ™ II offers industry leading FIFO queuing bandwidth (up to 1.5 Gbps) with a wide range of memory  
configurations (from 16,384 x 9 to 524,288 x 9). System designer has full flexibility of implementing deeper and wider queues  
using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between  
transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation  
of virtual queue depths.  
5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous  
Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching  
capability.  
Master Reset clears all previously programmed configurations by providing a low pulse on MRST pin. In addition, Write and  
Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will  
initialize Write and Read pointers to zero.  
In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high  
transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when implementing  
depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively.  
In Standard mode, always assert REN for read operation. FULL and EMPTY are used instead of DRDY and QRDY  
respectively.  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 1 of 1  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
Product Description (Continued)  
PRAF , PRAE , and HALF are available in either FWFT or Standard mode. PRAF and PRAE can operate in either  
synchronous or asynchronous modes.  
At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK  
for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical  
0th (Read pointer = zero), location of the queue.  
These FlexQ™ II devices have low power consumption, hence minimizing system power requirements. In addition, industry  
standard 64 - pin Plastic TQFP and 64 - pin STQFP are offered to save system board space.  
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test  
equipment, network switching, etc.  
Block Diagram of Single Synchronous Queue  
524,288 x 9 / 262,144 x 9 / 131,072 x 9 / 65,536 x 9 / 32,768 x 9 / 16,384 x 9  
PARTIAL RESET (PRST)  
MASTER RESET (MRST)  
WRITE CLOCK (WCLK)  
WRITE ENABLE (WEN)  
READ CLOCK (RCLK)  
READ ENABLE (REN)  
OUTPUT ENABLE (OE)  
FQV2111  
FQV2101  
FQV291  
FQV281  
FQV271  
FQV261  
LOAD  
LOAD (  
)
DATA IN (D8 - 0  
)
DATA OUT (Q 8- 0)  
SERIAL DATA ENABLE (SDEN)  
RETRANSMIT (RET)  
FIRST WORD FALL THROUGH/  
SERIAL DATA INPUT (FWFT/SDI)  
FULL FLAG / INPUT READY  
EMPTY FLAG / OUTPUT READY  
( EMPTY /QRDY )  
PROGRAMMABLE ALMOST-  
EMPTY (PRAE)  
(
/
)
FULL DRDY  
PROGRAMMABLE  
HALF-FULL FLAG (  
)
HALF  
ALMOST-FULL (PRAF)  
Figure 1. Single Device Configuration Signal Flow Diagram  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 2 of 2  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
WCLK WEN  
LOAD SDEN FWFT/SDI  
Offset Register  
Write Control  
Logic  
/ DRDY  
FULL  
PRAF  
EMPTY/ QRDY  
Flag Logic  
PRAE  
HALF  
FWFT/SDI  
Write Pointer  
Output  
Buffer  
Input Register  
Output Register  
D 8-0  
SRAM  
Q
8-0  
OE  
Read Pointer  
Read Control  
Logic  
Reset  
RCLK  
RET  
REN  
MRST PRST  
Figure 2. Device Architecture  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 3 of 3  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
PIN 1  
DNC(2)  
48  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
16  
WEN  
SDEN  
DC(1)  
Vcc  
DNC(2)  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
GND  
DNC(2)  
DNC(2)  
Vcc  
Vcc  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
D8  
DNC(2)  
DNC(2)  
DNC(2)  
GND  
DNC(2)  
DNC(2)  
Q8  
Q7  
Q6  
GND  
D7  
TQFP - 64 (Drw No: PF-01A; Order code: PF)  
STQFP - 64 (Drw No: TF-01A; Order code: TF)  
Top View  
NOTES:  
1.  
2.  
DC = Don’t Care. Must be tied to GND or Vcc, cannot be left open.  
DNC = Do Not Connect.  
Figure 3. Device Pin Out  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 4 of 4  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
Description  
Pin #  
Pin Name  
Pin Symbol  
Input/Output  
Master Reset is required to initialize Write and Read  
pointers to the first position of the queue by setting  
MRST low. In Standard mode, FULL and PRAF  
will go high; EMPTY and PRAE will go low.  
In FWFT mode, DRDY will go low and QRDY  
will go high. PRAF and PRAE will go to the same  
state as Standard mode. In both modes, all data  
outputs will go low. Previous programmed  
62  
Master Reset  
Input  
MRST  
configurations will not be maintained.  
Partial Reset is required to initialize Write and Read  
pointers to the first position of the queue by setting  
PRST low. In Standard mode, FULL and PRAF  
will go high; EMPTY and PRAE will go low. In  
FWFT mode, DRDY will go low and QRDY will  
go high. PRAF and PRAE will go to the same  
state as Standard mode. In both modes, all data  
outputs will go low. Previous programmed  
63  
Partial Reset  
Input  
PRST  
configurations will be maintained.  
Writes data into queue during low to high transitions  
of WCLK if WEN is set to low.  
64  
1
Write Clock  
Write Enable  
WCLK  
WEN  
Input  
Input  
Controls write operation into queue or offset registers  
during low to high transition of WCLK.  
During Master Reset, set LOAD low to select  
parallel programming or default offset value of 127.  
Set LOAD high to select serial programming or  
default offset value of 1023. After Master Reset,  
LOAD controls write/read, to/from offset registers  
during low to high transition of WCLK/RCLK  
respectively. Use in conjunction with WEN / REN .  
61  
Load Enable  
Input  
LOAD  
15,16,17,  
18,19,20,  
21,22,23  
Data Inputs  
D8 - 0  
Input  
9 - bit wide input data bus.  
Reads data from queue during low to high transitions  
of RCLK if REN is set to low.  
52  
51  
Read Clock  
Read Enable  
RCLK  
REN  
Input  
Input  
Controls read operation from queue or offset registers  
during low to high transition of RCLK.  
Setting OE low activates the data output drivers.  
Setting OE high deactivates the data output drivers  
(High-Z).  
49  
Output Enable  
Data Outputs  
Input  
OE  
36,35,34,  
32,31,29,  
28,26,25  
Q8 - 0  
Output  
9 - bit wide output data bus.  
Selects FWFT timing or Standard timing mode during  
Master Reset. After Master Reset, if serial  
programming is selected ( LOAD = high), FWFT/SDI  
is used as the serial data input for the offset registers.  
Serial data is written during the low to high transition  
of WCLK. Use in conjunction with SDEN .  
First Word Fall  
Through/Serial  
Data Input  
60  
FWFT/SDI  
Input  
Table 1. Pin Descriptions  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 5 of 5  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
Description  
Pin #  
Pin Name  
Pin Symbol  
Input/Output  
If serial programming is selected, setting SDEN and  
LOAD low enables serial data input to be written into  
offset registers during the low to high transition of  
WCLK.  
Serial Data  
2
Input  
SDEN  
Input Enable  
Data previously read from the queue can be  
retransmitted by asserting RET pin at the low to high  
transition of RCLK for a retransmit operation.  
Retransmit initializes the Read pointer to zero. Hence,  
all re-reads will always start from the physical 0th (Read  
pointer = zero) location of the queue.  
50  
58  
Retransmit  
Input  
RET  
Queue is full when FULL goes low during the low to  
high transition of WCLK. This prohibits further writes  
into the queue. In FWFT mode, queue is full when  
DRDY goes high during the low to high transition of  
WCLK. This prohibits further writes into the queue.  
Full / Data  
Input Ready  
Flag  
Output  
FULL / DRDY  
Queue is empty when EMPTY goes low during the  
low to high transition of RCLK. This prohibits further  
reads from the queue. In FWFT mode, queue is empty  
when QRDY goes high during the low to high  
transition of RCLK. This prohibits further reads form  
the queue.  
Empty / Data  
Output Ready  
Flag  
53  
57  
Output  
Output  
EMPTY / QRDY  
PRAF  
Queue is almost full when PRAF goes low during the  
low to high transition of WCLK. Default (Full-offset)  
or programmed offset values determine the status of  
PRAF .  
Almost Full  
Queue is almost empty when PRAE goes low during  
the low to high transition of RCLK. Default  
(Empty+offset) or programmed offset values determine  
the status of PRAE .  
54  
56  
Almost Empty  
Half Full  
Output  
Output  
PRAE  
HALF  
Queue is more than half full when HALF goes low.  
Triggered by both WCLK and RCLK.  
3
Don’t Care  
Power  
DC  
N/A  
N/A  
This pin can be tied high or low, cannot be left open.  
3.3V power supply.  
4, 5, 30, 43, 55  
Vcc  
6, 7, 8, 9, 10, 11,  
12, 13, 14, 24, 27,  
33, 39, 46, 59  
37, 37, 40, 41, 42,  
44, 45, 47, 48  
Ground  
GND  
DNC  
N/A  
N/A  
0V Ground.  
Do Not  
Do not connect.  
Connect  
Table 1. Pin Descriptions (Continued)  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 6 of 6  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
Symbol  
Rating  
Com’l & Ind’l  
Unit  
NOTES:  
Terminal Voltage with  
respect to GND  
Absolute Max Ratings are for reference only. Permanent damage to the device may  
occur if extended period of operation is outside this range. Standard operation should  
fall within the Recommended Operating Conditions.  
VTERM  
-0.5 to + 4.6  
V
TSTG  
IOUT  
Storage Temperature  
DC Output Current  
-55 to +125  
-50 to +50  
°C  
MA  
Table 2. Absolute Maximum Ratings  
FQV2111, FQV2101, FQV291,  
FQV281, FQV271, FQV261  
Commercial  
Industrial  
Clock = 7.5ns, 10ns, 15ns,  
20ns  
Clock = 7.5ns, 10ns, 15ns,  
20ns  
Symbol  
Parameter  
Min.  
Typ.  
Max. Min.  
Typ.  
Max.  
Unit  
Recommended Operating Conditions  
VCC  
Supply Voltage Com’l / Ind’l  
3.0  
3.3  
3.6  
3.0  
3.3  
3.6  
V
GND  
VIH  
VIL  
TA  
Supply Voltage  
0
2.0  
-
0
-
0
0
2.0  
-
0
-
0
V
V
Input High Voltage Com’l /  
Ind’l  
5.0  
0.8  
70  
85  
5.0  
0.8  
70  
85  
Input Low Voltage Com’l /  
Ind’l  
-
-
V
Operating Temperature  
Commercial  
0
-
0
-
°C  
°C  
Operating Temperature  
Industrial  
TA  
-40  
-
-40  
-
DC Electrical Characteristics  
Input Leakage Current (any  
(1)  
ILI  
-10  
-10  
2.4  
-
-
-
-
-
10  
10  
-
-10  
-10  
2.4  
-
-
-
-
-
10  
10  
-
µA  
µA  
V
input)  
ILO  
Output Leakage Current  
Output Logic “1” Voltage,  
IOH=-2mA  
Output Logic “0” Voltage, IOL  
= 8mA  
VOH  
VOL  
0.4  
0.4  
V
Power Consumption  
Icc1(2,3)  
Active Power Supply Current  
Standby Current  
-
-
-
-
55  
20  
-
-
-
-
55  
20  
mA  
mA  
Icc2(4)  
Table 3. DC Specifications  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 7 of 7  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
Capacitance at 100MHz Ambient Temperature (25°C)  
Symbol  
Parameter  
Conditions  
Max.  
Unit  
CIN(2)  
Input Capacitance  
VIN= 0V  
10  
pF  
COUT(2,4)  
Output Capacitance  
VOUT= 0V  
10  
pF  
NOTES:  
1.  
Measurement with 0.4<=VIN<=Vcc  
With output tri-stated ( OE = High)  
Icc(1,2) is measured with WCLK and RCLK at 20 MHz  
Design simulated, not tested.  
2.  
3.  
4.  
Table 3. DC Specifications (Continued)  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 8 of 8  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
Commercial & Industrial  
FQV2111-7.5  
FQV2101-7.5  
FQV291-7.5  
FQV281-7.5  
FQV271-7.5  
FQV261-7.5  
FQV2111-10  
FQV2101-10  
FQV291-10  
FQV281-10  
FQV271-10  
FQV261-10  
FQV2111-15  
FQV2101-15  
FQV291-15  
FQV281-15  
FQV271-15  
FQV261-15  
FQV2111-20  
FQV2101-20  
FQV291-20  
FQV281-20  
FQV271-20  
FQV261-20  
Symbol  
fS  
Parameter  
Clock Cycle Frequency  
Data Access Time  
Min. Max. Min. Max. Min. Max. Min. Max. Unit  
-
133  
-
100  
-
66  
10  
-
-
50  
12  
-
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tA  
1
5
-
-
-
-
-
-
-
-
-
-
-
2
6.5  
2
2
tWCLK  
tWCLKH  
tWCLKL  
tRCLK  
tRCLKH  
tRCLKL  
tDS  
Write Clock Cycle Time  
Write Clock High Time  
Write Clock Low Time  
Read Clock Cycle Time  
Read Clock High Time  
Read Clock Low Time  
Data Set-up Time  
7.5  
3.5  
3.5  
7.5  
3.5  
3.5  
2.5  
0.5  
2.5  
0.5  
10  
10  
10  
-
10  
4.5  
4.5  
10  
4.5  
4.5  
3
-
-
15  
6
20  
8
-
-
-
6
-
8
-
-
15  
6
-
20  
8
-
-
-
-
-
6
-
8
-
-
4
-
5
-
tDH  
Data Hold Time  
0.5  
3
-
1
-
1
-
tENS  
Enable Set-up Time  
-
4
-
1
-
tENH  
Enable Hold Time  
Reset Pulse Width(1)  
0.5  
10  
10  
10  
-
-
1
-
1
-
tRST  
-
15  
15  
15  
-
-
20  
20  
20  
-
-
tRSTS  
tRSTR  
tRSTF  
tOLZ  
Reset Set-up Time  
-
-
-
Reset Recovery Time  
-
12  
-
-
-
-
Reset to Flag and Output Time  
Output Enable to Output in Low-Z(1)  
Output Enable to Output Valid  
Output Enable to Output in High-Z(1)  
Write Clock to Full Flag  
Read Clock to Empty Flag  
Write Clock to Almost-Full Flag  
Read Clock to Almost-Empty Flag  
10  
-
15  
-
20  
-
0
0
0
0
tOE  
2
5
2
6
3
8
3
10  
10  
12  
12  
12  
12  
tOHZ  
2
5
2
6
3
8
3
tFULL  
tEMPTY  
tPRAFS  
tPRAES  
-
5
-
6.5  
6.5  
6.5  
6.5  
-
10  
10  
10  
10  
-
-
5
-
-
-
-
13  
13  
-
-
-
-
-
-
-
Skew time between Read Clock &  
tSKEW1  
tSKEW2  
4
7
-
-
5
-
-
6
-
-
10  
20  
-
-
ns  
ns  
Write Clock for Full Flag / Empty Flag  
Skew time between Read Clock &  
Write Clock for PRAF & PRAE  
12  
15  
Skew time between Read Clock &  
Write Clock for EMPTY / QRDY  
tSKEW3  
60  
-
60  
-
60  
-
60  
-
ns  
Table 4. AC Electrical Characteristics  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 9 of 9  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
Commercial & Industrial  
FQV2111-7.5  
FQV2101-7.5  
FQV291-7.5  
FQV281-7.5  
FQV271-7.5  
FQV261-7.5  
FQV2111-10  
FQV2101-10  
FQV291-10  
FQV281-10  
FQV271-10  
FQV261-10  
FQV2111-15  
FQV2101-15  
FQV291-15  
FQV281-15  
FQV271-15  
FQV261-15  
FQV2111-20  
FQV2101-20  
FQV291-20  
FQV281-20  
FQV271-20  
FQV261-20  
Symbol  
tLOADS  
tLOADH  
tRTS  
Parameter  
Load Setup Time  
Min. Max. Min. Max. Min. Max. Min. Max. Unit  
2.5  
0.5  
3
-
-
-
3
0.5  
3
-
-
-
4
1
4
-
-
-
5
1
5
-
-
-
ns  
ns  
ns  
Load Hold Time  
Retransmit Setup Time  
tHF  
-
14  
-
16  
-
20  
-
22  
ns  
Clock to HALF  
NOTES:  
1.  
Design simulated, not tested.  
Table 4. AC Electrical Characteristics (Continued)  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 10 of 10  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
Input Pulse Levels  
Input Rise/Fall Times  
GND to 3.0V  
3ns  
Input Timing Reference Levels  
Output Reference Levels  
Output Load, clock = 7.5 ns  
Output Load*, clock = 10ns, 15ns, 20ns  
1.5V  
1.5V  
Refer to Figure 4  
Refer to Figure 5  
* Include jig and scope capacitances  
Table 5. AC Test Condition  
3.3V  
Vcc/2  
330 Ω  
50 Ω  
D.U.T.  
30pF*  
510  
I/O  
Z0 = 50  
Figure 4. AC Test Load  
Figure 5. Output Load  
for clock = 10ns, 15ns, 20ns  
*Includes jig and scope capacitances.  
for clock = 7.5ns  
OCTOBER 2002  
3F209C  
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Page 11 of 11  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
Pin Functions  
Master Reset is required to initialize Write and Read pointers to the first position of the queue  
by setting MRST low. In Standard mode, FULL and PRAF will go high; EMPTY and  
PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and  
PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low.  
Previous programmed configurations will not be maintained.  
MRST  
Partial Reset is required to initialize Write and Read pointers to the first position of the queue  
by setting PRST low. In Standard mode, FULL and PRAF will go high; EMPTY and  
PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF  
and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go  
low. Previous programmed configurations will be maintained.  
PRST  
WCLK  
Writes data into queue during low to high transitions of WCLK if WEN is activated.  
Synchronizes FULL / DRDY and PRAF flags. WCLK and RCLK are independent of each  
other.  
Controls write operation into queue or offset registers during low to high transition of WCLK.  
WEN  
During Master Reset, set LOAD low to select parallel programming or default offset value of  
127. Set LOAD high to select serial programming or default offset value of 1023. After  
Master Reset, LOAD controls write/read, to/from offset registers during low to high transition  
of WCLK/RCLK respectively for parallel programming. Use in conjunction with  
WEN / REN . During programming of offset registers, PRAF and PRAE flag status is  
invalid. For Serial programming, LOAD is used to enable serial loading of offset registers  
together with SDEN . Refer to Figure 6 & 7 for details.  
LOAD  
D8-0  
9 - bit wide input data bus.  
RCLK  
Reads data from queue during low to high transitions of RCLK if REN is set low.  
Synchronizes the EMPTY / QRDY and PRAE flags. RCLK and WCLK are independent of  
each other.  
Reads data from queue during low to high transitions of RCLK if REN is set to low. This also  
advances the Read pointer of the queue.  
REN  
OE  
Setting OE low activates the data output drivers. Setting OE high deactivates the data output  
drivers (High-Z). OE does not control advancement of Read pointer.  
Q8-0  
9 - bit wide output data bus.  
FWFT/SDI  
Selects FWFT timing or Standard timing mode during Master Reset. After Master Reset, if  
serial programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for  
the offset registers. Serial data is written during the low to high transition of WCLK. Use in  
conjunction with SDEN . In FWFT mode, DRDY and QRDY is used instead of FULL and  
EMPTY . In Standard mode, FULL and EMPTY are used instead of DRDY and QRDY .  
Refer to Table 9 for all flags status.  
If serial programming is selected, setting SDEN and LOAD low enables serial data to be  
written into offset registers during the low to high transition of WCLK. During serial  
programming, PRAF and PRAE flags status is invalid. Refer Figure 6 & 7 for details.  
SDEN  
RET  
Data previously read from the queue can be retransmitted by asserting RET pin at the low to  
high transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to  
zero. Hence, all re-reads will always start from the physical 0th (Read pointer = zero) location  
of the queue. Refer to Diagram 7 & 8 for details.  
OCTOBER 2002  
3F209C  
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Page 12 of 12  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
Pin Functions (Continued)  
In Standard mode, queue is full when FULL goes low during the low to high transition of WCLK.  
This prohibits further writes into the queue and prevents advancement of Write pointer. In  
FWFT mode, queue is full when DRDY goes high during the low to high transition of WCLK.  
This prohibits further writes into the queue and prevents advancement of Write pointer. Refer to  
Table 8 & 9 for behavior of FULL / DRDY .  
FULL / DRDY  
In Standard mode, queue is empty when EMPTY goes low during the low to high transition of  
RCLK. This prohibits further reads from the queue and prevents advancement of Read pointer. In  
FWFT mode, queue is empty when QRDY goes low during the low to high transition of RCLK.  
This prohibits further reads from the queue and prevents advancement of Read pointer. Refer to  
Table 8 & 9 for behavior of EMPTY / QRDY .  
EMPTY / QRDY  
In Synchronous mode, queue is almost full when PRAF goes low during the low to high transition  
of WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . In  
Asynchronous timing mode, PRAF is triggered by both WCLK and RCLK. Refer to Table 8 & 9  
for behavior of PRAF .  
PRAF  
PRAE  
HALF  
In Synchronous mode, queue is almost empty when PRAE goes low during the low to high  
transition of RCLK. Default (Empty+offset) or programmed offset values determine the status of  
PRAE . In Asynchronous timing mode, PRAE is triggered by both WCLK and RCLK. Refer to  
Table 8 & 9 for behavior of PRAE .  
Queue is more than half full when HALF goes low during the low to high transition of WCLK.  
HALF goes high during low to high transition of RCLK when queue is less than half full. Refer  
to Table 8 & 9 for details.  
OCTOBER 2002  
3F209C  
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Page 13 of 13  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
FQV281  
FQV271  
WCLK  
RCLK  
SDEN  
LOAD  
WEN  
REN  
FQV261  
Selection / Sequence  
Parallel write to offset  
Parallel write to  
registers:  
registers:  
Empty Offset (Low Byte)  
Empty Offset (High Byte)  
Full Offset (Low Byte)  
Full Offset (High Byte)  
1. PRAE Low Byte  
2. PRAE High Byte  
3. PRAF Low Byte  
4. PRAF High Byte  
0
0
1
1
X
Parallel read from offset  
registers:  
Parallel read from  
registers:  
Empty Offset (Low Byte)  
Empty Offset (High Byte)  
Full Offset (Low Byte)  
Full Offset (High Byte)  
1. PRAE Low Byte  
2. PRAE High Byte  
3. PRAF Low Byte  
4. PRAF High Byte  
0
0
1
1
0
1
1
0
X
Serial shift into registers:  
32 bits for the FQV281  
30 bits for the FQV271  
28 bits for the FQV261  
1 bit for each rising WCLK edge  
X
Starting with Empty Offset (Low Byte)  
Ending with Full Offset (High Byte)  
X
1
1
0
1
1
X
X
X
No Operation  
X
X
Write Memory  
1
1
X
1
0
1
X
X
X
X
Read Memory  
No Operation  
X
Figure 6. Programmable Flag Offset Programming Sequence (FQV281, FQV271 and FQV261)  
OCTOBER 2002  
3F209C  
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Page 14 of 14  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
FQV2111  
FQV2101  
WCLK  
RCLK  
SDEN  
LOAD  
WEN  
REN  
FQV291  
Selection / Sequence  
Parallel write to  
Parallel write to offset  
registers:  
registers:  
Empty Offset (Low Byte)  
Empty Offset (Mid Byte)  
Empty Offset (High Byte)  
Full Offset (Low Byte)  
Full Offset (Mid Byte)  
Full Offset (High Byte)  
1. PRAE Low Byte  
2. PRAE Mid Byte  
3. PRAE High Byte  
4. PRAF Low Byte  
5. PRAF Mid Byte  
6. PRAF High Byte  
0
0
1
1
X
Parallel read from  
Parallel read from offset  
registers:  
registers:  
Empty Offset (Low Byte)  
Empty Offset (High Byte)  
Empty Offset (Mid Byte)  
Full Offset (Low Byte)  
Full Offset (Mid Byte)  
Full Offset (High Byte)  
1. PRAE Low Byte  
2. PRAE Mid Byte  
3. PRAE High Byte  
4. PRAF Low Byte  
5. PRAF Mid Byte  
6. PRAF High Byte  
0
0
1
1
0
1
1
0
X
Serial shift into registers:  
38 bits for the FQV2111  
36 bits for the FQV2101  
X
34 bits for the FQV291  
1 bit for each rising WCLK edge  
Starting with Empty Offset (Low Byte)  
Ending with Full Offset (High Byte)  
X
1
1
0
1
1
X
X
X
No Operation  
X
X
Write Memory  
1
1
X
1
0
1
X
X
X
X
Read Memory  
No Operation  
X
Figure 7. Programmable Flag Offset Programming Sequence (FQV291, FQV2101, FQV2111)  
OCTOBER 2002  
3F209C  
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Page 15 of 15  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
Device  
PRAF Programming (bits)  
PRAE Programming (bits)  
D/Q7 - 0  
D/Q7 - 0  
D/Q 2-0  
Low Byte  
Mid Byte  
High Byte  
D/Q7 - 0  
Low Byte  
Mid Byte  
High Byte  
FQV2111  
D/Q7 - 0  
D/Q 2-0  
D/Q7 - 0  
D/Q7 - 0  
D/Q 1-0  
D/Q7 - 0  
D/Q7 - 0  
D/Q 0  
Low Byte  
Mid Byte  
High Byte  
Low Byte  
Mid Byte  
High Byte  
D/Q7 - 0  
D/Q7 - 0  
D/Q 1-0  
D/Q7 - 0  
D/Q7 - 0  
D/Q 0  
Low Byte  
Mid Byte  
High Byte  
Low Byte  
Mid Byte  
High Byte  
FQV2101  
FQV291  
D/Q7 - 0  
D/Q7 - 0  
D/Q7 - 0  
D/Q6 – 0  
Low Byte  
High Byte  
Low Byte  
High Byte  
D/Q7 - 0  
D/Q7 - 0  
D/Q7 - 0  
D/Q6 – 0  
Low Byte  
High Byte  
Low Byte  
High Byte  
FQV281  
FQV271  
FQV261  
D/Q7 - 0  
D/Q5 - 0  
Low Byte  
High Byte  
D/Q7 - 0  
D/Q5 - 0  
Low Byte  
High Byte  
FQV2111  
FQV281  
FQV271  
FQV261  
FQV2101  
FQV291  
DV = 7FH, if LOAD = 0  
DV = FFH, if LOAD = 1  
DV = 7FH, if LOAD = 0  
DV = FFH, if LOAD = 1  
Low Byte  
DV = 00H, if LOAD = 0  
DV = 03H, if LOAD = 1  
N/A  
Mid Byte  
High Byte  
DV = 00H, if LOAD = 0  
DV = 03H, if LOAD = 1  
DV = 00H  
Table 6. Parallel Offset Register Data Mapping and Default Values  
Device  
FQV2111  
FQV2101  
FQV291  
FQV281  
FQV271  
FQV261  
Standard Mode  
524,288 x 9  
262,144 x 9  
131,072 x 9  
65,536 x 9  
FWFT Mode  
524,289 x 9  
262,145 x 9  
131,073 x 9  
65,537 x 9  
32,768 x 9  
32,769 x 9  
16,384 x 9  
16,385 x 9  
Table 7. Maximum Depth of Queue for Standard and FWFT Mode  
OCTOBER 2002  
3F209C  
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Page 16 of 16  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0  
Data Width  
7
6
5
4
3
2
1
0
8
1st Cycle PRAE (Low Byte)  
9
15  
14  
13  
12  
11  
10  
18  
PRAE  
PRAE  
2nd Cycle  
3rd Cycle  
(Mid Byte)  
(High Byte)  
17  
16  
7
6
5
4
3
2
1
9
0
8
PRAF (Low Byte)  
4th Cycle  
5th Cycle  
6th Cycle  
15  
14  
13  
12  
11  
10  
PRAF  
PRAF  
(Mid Byte)  
(High Byte)  
18  
17  
16  
FQV2111, FQV2101, FQV291  
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0  
Data Width  
7
6
5
4
3
2
1
9
0
8
1st Cycle PRAE (Low Byte)  
15  
14  
13  
12  
11  
10  
2nd Cycle PRAE  
(High Byte)  
7
6
5
4
3
2
1
9
0
8
(Low Byte)  
(High Byte)  
PRAF  
PRAF  
3rd Cycle  
4th Cycle  
15  
14  
13  
12  
11  
10  
FQV281 , FQV271 , FQV261  
# of Bits for Offset Registers  
19 bits for FQV2111  
18 bits for FQV2101  
17 bits for FQV291  
16 bits for FQV281  
15 bits for FQV271  
14 bits for FQV261  
Note: Don’t Care applies to all unused bits for both High Byte and Low Byte  
Figure 8. Parallel Offset Write/Read Cycle Diagram  
OCTOBER 2002  
3F209C  
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Page 17 of 17  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
FQV2111  
FULL  
PRAF HALF PRAE EMPTY  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y(1)  
(y+1) to 262,144  
262,145 to [524,288-(x+1)]  
(524,288-x(2))to 524,287  
524,288  
H
H
H
H
L
FQV2101  
FULL  
PRAF HALF PRAE EMPTY  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y(1)  
(y+1) to 131,072  
131,073 to [262,144-(x+1)]  
(262,144-x(2))to 262,143  
262,144  
H
H
H
H
L
FQV291  
FULL  
PRAF HALF PRAE EMPTY  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y(1)  
(y+1) to 65,536  
65,537 to [131,072-(x+1)]  
(131,072-x(2))to 131,071  
131,072  
H
H
H
H
L
FQV281  
FULL  
PRAF HALF PRAE EMPTY  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y(1)  
(y+1) to 32,768  
32,769 to [65,536-(x+1)]  
(65,536-x(2))to 65,535  
65,536  
H
H
H
H
L
FQV271  
FULL  
PRAF HALF PRAE EMPTY  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y(1)  
(y+1) to 16,384  
16,385 to [32,768-(x+1)]  
(32,768-x(2)) to 32,767  
32,768  
H
H
H
H
L
FQV261  
FULL  
PRAF HALF PRAE EMPTY  
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to y(1)  
(y+1) to 8,192  
8,193 to [16,384-(x+1)]  
(16,384 -x(2))t o 16,383  
16,384  
H
H
H
H
L
NOTES:  
1.  
y = PRAE offset; Default Values: y = 127 when parallel offset loading is selected or y = 1,023 when serial offset loading is selected.  
2.  
x = PRAF offset; Default Values: x = 127 when parallel offset loading is selected or x = 1,023 when serial offset loading is selected.  
Table 8. Status Flags (Standard Mode)  
OCTOBER 2002  
3F209C  
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Page 18 of 18  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
FQV2111  
QRDY  
DRDY PRAF HALF PRAE  
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to y+1(1)  
(y+2) to 262,145  
262,146 to [524,289-(x+1)]  
(524,289-x(2))to 524,288  
524,289  
H
H
H
H
L
FQV2101  
QRDY  
DRDY PRAF HALF PRAE  
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to y+1(1)  
(y+2) to 131,073  
131,074 to [262,145-(x+1)]  
(262,145-x(2))to 262,144  
262,145  
H
H
H
H
L
FQV291  
QRDY  
DRDY PRAF HALF PRAE  
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to y+1(1)  
(y+2) to 65,537  
65,538 to [131,073-(x+1)]  
(131,073-x(2)) to 131,072  
131,073  
H
H
H
H
L
FQV281  
QRDY  
DRDY PRAF HALF PRAE  
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to y+1(1)  
(y+2) to 32,769  
32,770 to [65,537-(x+1)]  
(65,537-x(2)) to 65,536  
65,537  
H
H
H
H
L
FQV271  
QRDY  
DRDY PRAF HALF PRAE  
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to y+1(1)  
(y+2) to 16,385  
16,386 to [32,769-(x+1)]  
(32,769-x(2)) to 32,768  
32,769  
H
H
H
H
L
FQV261  
QRDY  
DRDY PRAF HALF PRAE  
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to y(1)  
(y+2) to 8,193  
8,194 to [16,385-(x+1)]  
(16,385 -x(2)) to 16,384  
16,385  
H
H
H
H
L
NOTES:  
1.  
y = PRAE offset; Default Values: y = 127 when parallel offset loading is selected or y = 1,023 when serial offset loading is selected.  
2.  
x = PRAF offset; Default Values: x = 127 when parallel offset loading is selected or x = 1,023 when serial offset loading is selected.  
Table 9. Status Flags (FWFT Mode)  
OCTOBER 2002  
3F209C  
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Page 19 of 19  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
Timing Diagrams  
tRST  
MRST  
REN  
tRSTS  
tRSTS  
tRSTR  
tRSTR  
WEN  
tRSTR  
tRSTR  
tRSTS  
FWFT/SDI  
LOAD  
RET  
tRSTS  
tRSTS  
tRSTS  
SDEN  
tRSTF  
tRSTF  
tRSTF  
tRSTF  
tRSTF  
If FWFT = 1,QRDY = 1  
If FWFT = 0,EMPTY= 0  
EMPTY/QRDY  
If FWFT = 0,FULL = 1  
If FWFT = 1,DRDY = 0  
FULL DRDY  
/
PRAE  
PRAF/HALF  
OE = 1  
OE = 0  
Q8- 0  
Diagram 1. Master Reset Timing  
OCTOBER 2002  
3F209C  
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Page 20 of 20  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
tRST  
PRST  
REN  
tRSTS  
tRSTS  
tRSTS  
tRSTS  
tRSTR  
tRSTR  
WEN  
RET  
SDEN  
EMPTY/QRDY  
FULL/ DRDY  
PRAE  
If FWFT = 1,QRDY = 1  
If FWFT = 0,EMPTY= 0  
tRSTF  
tRSTF  
tRSTF  
tRSTF  
If FWFT = 0,FULL = 1  
If FWFT = 1,  
= 0  
DRDY  
PRAF/HALF  
OE = 1  
OE = 0  
Q8- 0  
Diagram 2. Partial Reset Timing  
OCTOBER 2002  
3F209C  
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Page 21 of 21  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 22 of 22  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 23 of 23  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 24 of 24  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 25 of 25  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
RCLK  
REN  
1
2
tENS  
tENH  
tA  
tRETS  
tENS  
tENH  
tA  
tA  
Q 8 - 0  
DWi  
DWi+1  
DW1  
DW2  
tSKEW2  
WCLK  
WEN  
1
2
tRETS  
tENS  
tENH  
RET  
EMPTY  
PRAE  
tEMPTY  
tEMPTY  
tPRAES  
tHALF  
HALF  
tPRAFS  
PRAF  
NOTES:  
1.  
2.  
3.  
4.  
Upon completion of retransmit setup, a read operation can begin only after EMPTY returns high.  
OE = Low.  
DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.  
Upon reset completion, there must be more than 2 words written to the queue for a retransmit setup to be valid.  
Diagram 7. Retransmit Timing (Standard Mode)  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 26 of 26  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
RCLK  
REN  
1
2
3
4
tENS  
tENH  
tRETS  
tENS  
tENH  
tA  
tA  
tA  
tA  
Q
DWi  
DWi+1  
DW1  
DW2  
DW3  
DW4  
8 - 0  
tSKEW2  
WCLK  
WEN  
1
2
tRETS  
tENS  
tENH  
RET  
QRDY  
PRAE  
tEMPTY  
tEMPTY  
tPRAES  
tHALF  
HALF  
PRAF  
tPRAFS  
NOTES:  
1.  
2.  
3.  
4.  
Upon completion of retransmit setup, a read operation can begin only after QRDY returns low.  
OE = Low.  
DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.  
Upon reset completion, there must be more than 2 words written to the queue for a retransmit setup to be valid.  
Diagram 8. Retransmit Timing (FWFT Mode)  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 27 of 27  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
WCLK  
SDEN  
LOAD  
SDI  
tENS  
tLOADS  
tDS  
tENH  
tENH  
tLOADH  
tDH  
tLOADH  
BIT 0  
BIT MSB  
BIT 0  
BIT MSB  
PRAE offset  
PRAF offset  
*Refer to Table 10.  
Diagram 9. Serial Loading of Programmable Flag Registers (Standard and FWFT Mode)  
FQV2111  
FQV2101  
FQV291  
FQV281  
FQV271  
FQV261  
18  
17  
16  
15  
14  
13  
MSB  
Table 10. Reference Table for Diagram 9  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 28 of 28  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
tWCLK  
t
WCLKH  
t
WCLKL  
WCLK  
t
LOADS  
tLOADH  
t
LOADH  
LOAD  
tENS  
t
ENH  
t
ENH  
WEN  
D 8 - 0  
tDS  
t
DH  
t
DH  
offset  
offset  
PRAE  
PRAE  
PRAFoffset  
(Low Byte)  
PRAFoffset  
(High Byte)  
(High Byte)  
(Low Byte)  
Diagram 10. Parallel Loading of Programmable Flag Registers for FQV281, FQV271 and FQV261  
(Standard and FWFT Mode)  
t
WCLK  
WCLKH  
t
t
WCLKL  
WCLK  
t
LOADS  
t
LOADH  
t
LOADH  
LOAD  
WEN  
D 8 - 0  
t
ENS  
t
ENH  
t
ENH  
t
DH  
t
DS  
t
DH  
offset  
offset  
offset  
PRAF offset  
(Low Byte)  
PRAF offset  
(Mid Byte)  
PRAF offset  
(High Byte)  
PRAE  
PRAE  
PRAE  
(Low Byte)  
(Mid Byte)  
(High Byte)  
Diagram 11. Parallel Loading of Programmable Flag Registers for FQV291 (Standard and FWFT Mode)  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 29 of 29  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
t
RCLK  
RCLKH  
t
t
RCLKL  
RCLK  
t
LOADH  
t
LOADS  
t
LOADH  
LOAD  
REN  
t
ENH  
t
ENS  
t
ENH  
t
A
t
A
Q 8 - 0  
Output Register Data  
offset  
PRAE offset  
(Low Byte)  
PRAE offset  
(High Byte)  
PRAF offset  
(Low Byte)  
PRAF  
(High Byte)  
Diagram 12. Parallel Read of Programmable Flag Registers for FQV281, FQV271 and FQV261  
(Standard and FWFT Mode)  
t
RCLK  
t
RCLKH  
t
RCLKL  
RCLK  
t
LOADS  
t
LOADH  
t
LOADH  
LOAD  
REN  
tENS  
tENH  
tENH  
tA  
t
A
Q 8 - 0  
Output Register Data  
-
PRAE offset  
(Low Byte)  
PRAE offset  
(Mid Byte)  
PRAE offset  
(High Byte)  
PRAF offset  
(Low Byte)  
PRAF offset  
(Mid Byte)  
offset  
PRAF  
(High Byte)  
Diagram 13. Parallel Read of Programmable Flag Registers for FQV291 (Standard and FWFT Mode)  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 30 of 30  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
tWCLKH  
tWCLKL  
WCLK  
1
2
1
2
tENS  
tENH  
WEN  
tPRAFS  
tPRAFS  
D - ( x + 1 )  
PRAF  
D - x words in Queue  
D - ( x + 1 ) words in Queue  
words in Queue  
tSKEW2  
RCLK  
REN  
tENS  
tENH  
NOTES:  
1.  
2.  
3.  
x = _P__R___A___F__ offset.  
D = maximum queue depth. Please refer to Table 7 for Depth.  
___________  
If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF will go high (after on WCLK cycle  
plus tPRAFS). If tSKEW2 is not met, then _P__R___A___F__ will assert 1 or more WCLK cycles.  
___________  
4.  
PRAF synchronizes to the rising edge of WCLK only.  
Diagram 14. Synchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)  
tWCLKH  
tWCLKL  
WCLK  
tWCLKH  
tWCLKL  
WEN  
y words in Queue(2)  
y+1 words in Queue(3)  
;
y words in Queue(2) ; y+1 words in Queue(3)  
y+1 words in Queue(2) ; y+2 words in Queue(3)  
PRAE  
tSKEW2  
tPRAES  
tPRAES  
RCLK  
REN  
1
2
1
2
tENS  
tENH  
NOTES:  
1.  
2.  
3.  
4.  
y = PRAE offset.  
For Standard Mode.  
For FWFT Mode.  
If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE will go high (after one RCLK cycle  
plus tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles.  
5.  
PRAE synchronizes to the rising edge of RCLK only.  
Diagram 15. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 31 of 31  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
tWCLKH  
tWCLKL  
WCLK  
WEN  
tENS  
tENH  
D/2 + 1 words in  
Queue(1)  
;
tHALF  
[(D+1)/2 + 1] words  
in Queue(2)  
D/2 words in Queue(1); [(D+1)/2] words in Queue(2)  
HALF  
RCLK  
D/2 words in Queue(1)  
;
[(D+1)/2] words in Queue(2)  
tHALF  
tENS  
REN  
NOTES:  
1.  
2.  
3.  
For Standard Mode.  
For FWFT Mode.  
Refer to Table 7 for Depth.  
Diagram 16. Half-Full Flag Timing (Standard and FWFT Mode)  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 32 of 32  
FQV2111 · FQV2101 · FQV291 · FQV281 · FQV271 · FQV261  
FlexQTMII  
Order Information:  
HBA  
Device Type  
Power Speed (ns) *  
Package** Temperature Range  
Device Family  
XX  
FQ  
XXXXX  
V2111 (524,288 x 9)  
X
Low  
XX  
XX  
PF  
X
7-5 – 133 MHz  
Blank – Commercial (0°C to 70°C)  
10 – 100 MHz  
15 – 66 MHz  
20 – 50 MHz  
I – Industrial (-40° to 85°C)  
V2101 (262,144 x 9)  
V291 (131,072 x 9)  
V281 (65,536 x 9)  
V271 (32,768 x 9)  
V261 (16,384 x 9)  
TF  
*Speed – Slower speeds available upon request.  
**Package – 64 pin Plastic Thin Quad Flat Pack (TQFP), 64 pin Slim Thin Quad Flat Pack (STQFP)  
Example:  
FQV281L7-5PF (64k x 9, 7.5ns, Commercial temp)  
FQV271L10PFI (32k x 9, 10ns, Industrial temp)  
USA  
Taiwan  
2107 North First Street, Suite 415  
San Jose, CA 95131, USA  
www.hba.com  
Tel: 408.453.8885  
Fax: 408.453.8886  
No. 81, Suite 8F-9, Shui-Lee Rd.  
Hsinchu, Taiwan, R.O.C.  
www.hba.com  
Tel: 886.3.516.9118  
Fax: 886.3.516.9181  
OCTOBER 2002  
3F209C  
© 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.  
Page 33 of 33  

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