ALT80600KESJSR_技术文档

ALT80600

LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

FEATURES AND BENEFITS

DESCRIPTION

The ALT80600 is a multi-output LED driver for small-size

LCDbacklighting.Itintegratesacurrent-modeboostconverter

with internal power switch and four current sinks. The boost

converter can drive up to 44 white LEDs, 11 LED per string,

at 120 mA (V_F= 3.3 V max). LED sinks can be paralleled

together to achieve higher currents up to 480 mA.

• Automotive AEC-Q100 qualified

• Wide input voltage range of 4.5 to 40 V for start/stop,

cold crank, and load dump requirements

• Fully integrated LED current sinks and boost converter

with internal power MOSFET

• Operate in Boost or SEPIC mode for flexible output

• Drives up to 11 series white LED in 4 parallel strings, at

up to 120 mA per string (V_F= 3.3 V max).

TheALT80600 operates from single power supply from 4.5 to

40 V; once started, it can continue to operate down to 3.9 V.

This allows the part to withstand stop/start, cold crank, and

load dump conditions encountered in automotive systems.

• Programmable boost switching frequency or sync

externally from 200 kHz to 2.3 MHz

• Clock-Out feature for internal switching frequency

• Adjustable boost frequency dithering to reduce EMI

• Advanced control allows minimum PWM on-time down

to 0.3 µs, and avoids MLCC audible noises

• LED contrast ratio: 15,000:1 at 200 Hz using PWM

dimming alone, 150,000:1 when combining PWM and

analog dimming

The ALT80600 can control LED brightness through external

PWM signal. By using the patented ‘Pre-emptive Boost’

control, an LED brightness contrast ratio of 15,000:1 can be

achieved using PWM dimming at 200 Hz. A higher ratio of

150,000:1 is possible when using a combination of PWM and

analog dimming.

Continued on next page...

PACKAGE:

APPLICATIONS

24-Pin 4 mm × 4 mm QFN

with Wettable Flank

• Automotive infotainment backlighting

• Automotive cluster

• Automotive center stack

Not to scale

• Automotive exterior lighting

V_IN= 4.5 to 40 V

V_OUT≤ 40 V

ꢀoptional

10 µH

0.024 Ω

Q1

C_in

383 Ω

187 kΩ

SW

GATE

OVP

PGND

LED1

4.7 µF

Vsense

Vin

V

c

1 µF

V_DD

10 kΩ

FAULT

ALT80600

LED2

LED3

Up to 11 WLEDs in series

Up to 120 mA/channel

EN

Enable

PWM

APWM

PWM t_ON≥ 0.3 µs

LED4

CLKOUT

AGND

COMP

PEB

FSET

ISET

DITH

APWM 100 kHz 0-90%

845 Ω

8.25 kΩ

100 pF

40.2 kΩ

10 nF

10 kΩ

68 nF

9.09 kΩ

Figure 1: Typical application diagram showing ALT80600 in Boost mode

ALT80600-DS, Rev. 2

MCO-0000393

March 13, 2019

LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

FEATURES AND BENEFITS (continued)

DESCRIPTION (continued)

• Excellent input voltage transient response even at lowest

PWM duty cycle

• Gate driver for optional PMOS input disconnect switch

• Extensive protection against:

Switching frequency can be either above or below AM band.

A programmable dithering feature further reduces EMI. A

synchronization pin allows switching frequency to be synchronized

externally between 200 kHz and 2.3 MHz.A‘Clock-Out’pin allows

other converters to be synchronized to the ALT80600’s switching

frequency.

□ Shorted boost switch, inductor or output capacitor

□ Shorted FSET or ISET resistor

□ Open or shorted LED pins and LED strings

□ Open boost Schottky diode

□ Overtemperature

TheALT80600providesprotectionagainstoutputshort, overvoltage,

openorshorteddiode,openorshortedLEDpin,andovertemperature.

Acycle-by-cyclecurrentlimitprotectstheinternalboostswitchagainst

high current overloads. An external P-MOSFET can optionally be

usedtodisconnectinputsupplyincaseofoutputtogroundshortfault.

SELECTION GUIDE ^[1]

Part Number

Package

Packing

Leadframe Plating

24-pin 4 × 4 mm wettable flank QFN

with exposed thermal pad and sidewall plating

ALT80600KESJSR

6000 pieces per reel

100% matte tin

^[1]Contact Allegro for additional packing options.

ABSOLUTE MAXIMUM RATINGS ^[2]

Characteristi

Symbol

Notes

Rating

Unit

V

LEDx Pin

OVP pin

VIN

V_LEDx

V_OVP

V_IN

x = 1..4

–0.3 to 40

V

Higher of –0.3

and (V_IN– 7.4) to

V_IN+0.4

V_SENSE

V_GATE

,

VSENSE, GATE

V

Continuous

–0.6 to 50

–1.0 to 54

–1.5 to 60

–0.3 to 40

V

SW

V_SW

t < 50 ns (repetitious, <2.5 MHz)

Single-event in case of Fault ^[3]

FAULT

V_FAULT

APWM, EN, PWM, CLKOUT, COMP,

DITH, FSET, ISET, VDD, PEB

–0.3 to 5.5

V

Operating Ambient Temperature

Maximum Junction Temperature

Storage Temperature

T_A

T_J(max)

T_stg

Range K

–40 to 125

150

°C

–55 to 150

^[2]Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

^[3]SW DMOS is self-protecting and will conduct when VSW exceeds 60 V.

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information

Characteristic

Symbol

Test Conditions ^[4]

Value

Unit

Package Thermal Resistance

R_θJA

ES package measured on 4-layer PCB based on JEDEC standard

37

°C/W

^[4]Additional thermal information available on the Allegro website.

2

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

Table of Contents

Switching Frequency Dithering ......................................... 14

Clock Out Function.......................................................... 14

LED Current Setting ........................................................ 15

PWM Dimming ............................................................... 15

Pre-Emptive Boost (PEB)................................................. 16

Analog Dimming with APWM Pin....................................... 18

Extending LED Dimming Ratio.......................................... 19

Analog Dimming with External Voltage............................... 19

VDD.............................................................................. 20

Shutdown....................................................................... 20

Fault Detection and Protection............................................. 21

LED String Partial-Short Detect ........................................ 21

Boost Switch Overcurrent Protection ................................. 22

Input Overcurrent Protection and Disconnect Switch ........... 23

Setting the Current Sense Resistor ................................... 24

Input UVLO.................................................................... 24

Fault Protection During Operation ..................................... 24

Fault Recovery Mechanism.............................................. 26

Package Outline Drawing.................................................... 28

Appendix A: Design Example..............................................A-1

Features and Benefits........................................................... 1

Description.......................................................................... 1

Applications......................................................................... 1

Package ............................................................................. 1

Selection Guide ................................................................... 2

Absolute Maximum Ratings................................................... 2

Thermal Characteristics ........................................................ 2

Typical Application – SEPIC .................................................. 3

Functional Block Diagram ..................................................... 4

Pinout Diagram and Terminal List........................................... 5

Electrical Characteristics....................................................... 6

Functional Description .......................................................... 9

Enabling the IC................................................................. 9

Powering Up: LED Detection Phase.................................. 10

Powering Up: Boost Output Undervoltage...........................11

Soft Start Function .......................................................... 12

Frequency Selection........................................................ 13

Synchronization.............................................................. 13

Loss of External Sync Signal............................................ 14

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3

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

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ALT80600

Figure 3: Functional Block Diagram

4

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

PINOUT DIAGRAM AND TERMINAL LIST

FAULT

CLKOUT

VDD

1

2

3

4

5

6

18 PGND

17 PGND

16 LED4

15 LED3

14 LED2

13 LED1

PAD

AGND

COMP

ISET

Package ES, 24-Pin QFN Pinouts

Terminal List Table

Number

Name

Function

The pin is an open-drain type configuration that will be pulled low when a fault occurs. Connect a 10 kΩ resistor between this pin and desired

logic level voltage.

1

FAULT

Logic output representing the switching frequency of internal boost oscillator. This allows other converters to be synchronized to the same f_SW

with the same dithering modulation, if applicable. Output is active as long as EN = H.

2

CLKOUT

3

4

5

6

7

VDD

AGND

COMP

ISET

Output of internal LDO (bias regulator). Connect a 1 µF decoupling capacitor between this pin and GND.

LED current ground. Also serves as ‘quiet’ ground for analog signals.

Output of the error amplifier and compensation node. Connect a series R_Z-C_Znetwork from this pin to GND for control loop compensation.

Connect R_ISETresistor between this pin and GND to set the 100% LED current.

PEB

Connect resistor to GND to adjust delay time (~2 to 6 µs) for Pre-Emptive Boost. Leave pin open to select shortest delay of ~1 µs.

Dithering control: connect a capacitor to GND to set the dithering modulation frequency (typically 1 to 3 kHz). Connect a resistor between

DITH and FSET pins to set the dithering range (such as ±5% of f_SW).

8

9

DITH

FSET/SYNC

APWM

Frequency/synchronization pin. A resistor R_FSETfrom this pin to GND sets the switching frequency f_SW(with dithering super-imposed). It

can also be used to synchronize two or more converters in the system to an external frequency between 200 kHz and 2.3 MHz (dithering is

disabled in this case).

Analog dimming. Apply APWM clock (40 kHz to 1 MHz) to this pin, and the duty cycle of this clock determines the LED current. Leave open or

connect to GND for 100%

10

Controls the on/off state of LED current sinks to reduce the light intensity by using pulse-width modulation. Typical PWM dimming frequency

is in the range of 200 to 2 kHz. EN and PWM pins may be tied together to allow single-wire dimming control.

11

12

PWM

EN

Enables the IC when this pin is pulled high. If EN goes low, the IC remains in standby mode for up to 32k cycles, then shuts down completely.

LED current sinks #1 - 4. Connect the cathode of each LED string to pin. Unused LED pin must be terminated to GND through a 6.19 kΩ

resistor.

13-16

LED1-4

17-18

19

PGND

OVP

SW

Power ground for internal NMOS switching device.

Overvoltage protection. Connect external resistor from V_OUTto this pin to adjust the over voltage protection level.

The drain of the internal NMOS switching device of the boost converter.

20-21

22

GATE

Output gate driver pin for external P-channel FET (optional input disconnect switch for overcurrent protection).

Connect this pin to the negative sense side of the current sense resistor R_SC. The threshold voltage is measured as V_IN– V_SENSE. There is

also a fixed ~20 µA current sink to allow for trip threshold adjustment for input overcurrent protection.

23

24

–

VSENSE

VIN

Input power to the IC as well as the positive input used for current sense resistor.

Exposed pad of the package providing enhanced thermal dissipation. Must be connected to the ground plane(s) of the PCB with at least

8 vias, directly in the pad.

PAD

5

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

ELECTRICAL CHARACTERISTICS ^[1]: Unless otherwise noted, speciﬁcations are valid at V_IN= 16 V, T_J= 25°C, • indicates speciﬁca-

tions guaranteed over the full operating temperature range with T_J= –40°C to 125°C, typical speciﬁcations are at T_J= 25°C

Characteristics

INPUT VOLTAGE SPECIFICATIONS

Operating Input Voltage Range ^[3]

VIN UVLO Start Threshold

VIN UVLO Stop Threshold

UVLO Hysteresis ^[2]

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

V_IN

●

4.5

−

–

40

4.35

3.9

V

V_UVLO(rise)

V_UVLO(fall)

V_{UVLO_HYS}

V_INrising

V_INfalling

−

–

V

300

450

600

mV

INPUT CURRENTS

VIN Pin Operating Current

VIN Pin Quiescent Current

VIN Pin Sleep Current

I_OP

I_Q

EN and PWM = H, f_SW= 2 MHz

EN = H and PWM = L, f_CLKOUT= 2 MHz

V_IN= 16 V, V_EN= 0 V

●

−

13

10

2

18

−

mA

µA

I_QSLEEP

10

INPUT LOGIC LEVELS (EN, PWM, APWM)

Input Logic Level-Low

Input Logic Level-High

V_IL

●

−

0.4

V

V_IH

1.5

−

R

_EN,R_PWM,

R_APWM

Input Pull-Down Resistor

Input = 5 V

60

100

140

kΩ

OUTPUT LOGIC LEVELS (CLKOUT)

Output Logic Level-Low

Output Logic Level-High

CLKOUT Duty Cycle

V_OL

V_OH

5 V < V_IN< 40 V

●

−

1.8

33

−

0.3

−

V

5 V < V_IN< 40 V

D_CLKOUT

f_SW= 2 MHz, no external sync

External sync = 200 kHz to 2.3 MHz

50

200

67

−

%

ns

CLKOUT Negative Pulse Width ^[2]

APWM PIN

DCLKNPW

APWM Frequency Range ^[2]

APWM Duty Cycle Range ^[2]

VDD REGULATOR

f_APWM

Clock signal applied to pin

●

40

0

−

1000

90

kHz

%

D_APWM

Regulator Output Voltage

VDD UVLO Start Threshold

VDD UVLO Stop Threshold

ERROR AMPLIFIER

V_DD

V_IN> 4.5 V, i_LOAD< 1 mA

4.05

4.25

3.2

4.45

V

V_DDUVLOriseV_DDrising, no external load

V_DDUVLOfallV_DDfalling, no external load

2.65

Amplifier Gain ^[2]

Gm

V_COMP= 1.5 V

−

1000

–600

+600

1.4

−

μA/V

μA

Source Current

I_EA(SRC)

I_EA(SINK)

R_COMP

V_COMP= 1.5 V

Sink Current

V_COMP= 1.5 V

μA

COMP Pin Pull Down Resistance

FAULT = 0, V_COMP= 1.5 V

kΩ

Continued on the next page…

6

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

ELECTRICAL CHARACTERISTICS ^[1](continued): Unless otherwise noted, speciﬁcations are valid at V_IN= 16 V, T_J= 25°C, • indi-

cates speciﬁcations guaranteed over the full operating temperature range with T_J= –40°C to 125°C, typical speciﬁcations are at T_J= 25°C

Characteristics

DITHERING CONTROL

DITH Pin Source Current

DITH Pin Sink Current

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

i_DITH(src)

i_DITH(sink)

Output current when V_DITH< 0.8 V

Output current when V_DITH> 1.2 V

−

20

−

μA

−20

OVERVOLTAGE PROTECTION

OVP Pin Voltage Threshold

OVP Pin Sense Current Threshold

OVP Pin Leakage Current

OVP Variation at Output

V_OVP(th)

i_OVP(th)

I_OVPLKG

ΔOVP

OVP pin connected to V_OUT

●

2.25

143

−

2.5

150

0.1

−

2.75

157

1

V

µA

%

V

Current into OVP pin

V_OUT= 16 V, EN = L

Measured at V_OUTwhen R_OVP= 249 kΩ

Measured at V_OUTwhen R_OVP= 249 kΩ ^[2]

Measured at V_OUTwhen R_OVP= 0 Ω

−

5

−

3.3

0.2

4.2

0.25

Undervoltage Detection Threshold

Secondary Overvoltage Protection

V_UVP(th)

−

V

Measured at SW pin; part latches when OVP2

is detected

V_OVP2

●

51

55

59

V

BOOST SWITCH

Switch On Resistance

R_SW

I_SW= 0.75 A, V_IN= 16 V

−

250

0.1

−

500

1

mΩ

µA

I_SWLKG25

V_SW= 13.5 V, PWM = VIL, T_J= 25°C

V_SW= 13.5 V, PWM = VIL, T_J= 85°C

Switch Pin Leakage Current

[2]

I_SWLKG85

10

IC truncates present switching cycle when

primary limit is reached

Switch Pin Current Limit

I_SW(LIM)

●

3.0

3.65

4.5

A

Secondary Switch Current Limit ^[2]

Minimum Switch On-Time

I_SW(LIM2)

t_SW(ON)

t_SW(OFF)

IC latches off when secondary limit is reached

−

45

−

4.9

65

50

−

A

●

85

66

ns

Minimum Switch Off-Time

OSCILLATOR FREQUENCY

R_FSET= 10 kΩ

●

1.95

−

2.15

200

2.35

−

MHz

kHz

V

Oscillator Frequency

f_SW

R

_FSET= 110 kΩ

FSET Pin Voltage

V_FSET

R_FSET= 10 kΩ

−

1.00

−

SYNCHRONIZATION

V_SYNCL

V_SYNCH

FSET/SYNC pin logic Low

FSET/SYNC pin logic High

●

−

0.4

−

V

Sync Input Logic Level

1.5

260

150

Synchronized PWM Frequency

Synchronization Input Min Off-Time

Synchronization Input Min On-Time

F_SWSYNC

t_PWSYNCOFF

t_PWSYNCON

2300

−

KHz

ns

−

ns

Continued on the next page…

7

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

ELECTRICAL CHARACTERISTICS ^[1](continued): Unless otherwise noted, speciﬁcations are valid at V_IN= 16 V, T_J= 25°C, • indi-

cates speciﬁcations guaranteed over the full operating temperature range with T_J= –40°C to 125°C, typical speciﬁcations are at T_J= 25°C

Characteristics

LED CURRENT SINKS

LEDx Accuracy ^[4]

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Err_LED

i_ISET= 120 µA (R_ISET= 8.33 kΩ), V_APWM= 0 V

●

−

0.7

0.8

3

2

%

LEDx Matching

ΔLEDx

i_ISET= 120 µA, V_APWM= 0 V

Measured individually with all other LED pins

tied to 1 V, i_ISET= 120 µA, V_APWM= 0 V

LEDx Regulation Voltage

V_LED

●

600

700

800

mV

I

_ISETto I_LEDxCurrent Gain

A_ISET

V_ISET

i_ISET

i_ISET= 120 µA, V_APWM= 0 V

816

0.97

20

833

1

850

1.03

144

A/A

V

ISET Pin Voltage

Allowable ISET Current

●

−

µA

Sensed from each LED pin to GND while its

current sink is in regulation; all other LED pins

tied to 1 V

LED String Partial-Short-Detect

Soft-Start Ramp Up Time ^[2]

Enable Pin Shut Down Delay ^[2]

V_LEDSC

4.5

18

5.2

6

V

Maximum time duration before all LED

channels come into regulation, or OVP is

tripped, whichever comes first

t_SSRU

21.5

25

ms

EN goes from High to Low; exceeding t_EN(OFF)

results in IC shutdown; measured in terms of

switching cycles

t_EN(OFF)

t_PWMH

−

32768

0.3

−

cycles

µs

Minimum PWM Dimming On-Time

GATE PIN

First and subsequent PWM pulses

●

0.4

Gate Pin Sink current

Gate Pin Source current

I_GSINK

V_GS= V_IN, no input OCP fault

−

−113

−

µA

I_GSOURCE

V_GS= V_IN– 6 V, input OCP fault tripped

6

mA

Gate Shutdown Delay When Over-

Current Fault Is Tripped ^[2]

t_FAULTT

V_GS

V_IN– V_SENSE= 200 mV; monitored at FAULT pin

−

3

µs

V

Measured between GATE and VIN when gate

is fully on

Gate Voltage

−6.7

−

VSENSE PIN

VSENSE Pin Sink Current

VSENSE Trip Point

i_ADJ

●

16

88

20

24

µA

V_SENSETRIPMeasured between V_INand V_SENSE, R_ADJ= 0

100

110

mV

FAULT PIN

FAULT Pull Down Voltage

FAULT Pin Leakage Current

THERMAL PROTECTION (TSD)

Thermal Shutdown Threshold ^[2]

Thermal Shutdown Hysteresis ^[2]

V_FAULT

I_FAULT= 1 mA

V_FAULT= 5 V

−

0.5

1

V

i_FAULT-LKG

µA

TSD

Temperature rising

155

170

20

−

°C

TSD_HYS

−

^[1]For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing);

positive current is defined as going into the node or pin (sinking).

^[2]Ensured by design and characterization; not production tested.

^[3]Minimum V_IN= 4.5 V is only required at startup. After startup is completed, IC can continue to operate down to V_IN= 4 V.

^[4]LED current is trimmed to cancel variations in both Gain and ISET voltage.

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LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

FUNCTIONAL DESCRIPTION

The ALT80600 is a multistring LED regulator with an integrated

boost switch and four precision current sinks. It incorporates a

patented Pre-Emptive Boost (PEB) control algorithm to achieve

PWM dimming ratio over 15,000:1 at 200 Hz. PEB control

also minimizes output ripple to avoid audible noise from output

ceramic capacitors.

Only if no faults were detected, then the IC can proceed to start

switching.

As long as EN = H, the PWM pin can be toggled to control the

brightness of LED channels by using PWM dimming. Alterna-

tively, EN and PWM can be tied together to allow single-wire

control for both power on/off and PWM dimming. If EN is pulled

low for longer than 32k clock cycles, the IC shuts off.

The switching frequency can be either synchronized to an

external clock or generated internally. Spread-spectrum tech-

nique (with user-programmable dithering range and modulation

frequency) is provided to reduce EMI. A clock-out signal (CLK-

OUT) allows other converters to be synchronized to the switching

frequency of ALT80600.

Enabling the IC

The ALT80600 wakes up when EN pin is pulled above logic

high level, provided that VIN pin voltage is over the VIN_UVLO

threshold. The boost stage and LED channels are enabled sepa-

rately by PWM = H signal after the IC powers up.

The IC performs a series of safety checks at power up, to deter-

mine if there are possible fault conditions that might prevent the

system from functioning correctly. Power-up checks include:

• VOUT shorted to GND

Figure 4: Startup showing EN, VDD, CLKOUT, and ISET (PWM =

L). Note that CLKOUT is available as soon as V_DDramps up, even

though Boost stage and LED drivers are not yet enabled.

• LED pin shorted to GND

• FSET pin open/shorted

• ISET pin open/shorted to GND, etc.

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LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

ꢄꢅUꢆ

Powering Up: LED Detection Phase

ꢄꢅUꢆ

The VIN pin has an undervoltage lockout (UVLO) function that

prevents the ALT80600 from powering up until the UVLO thresh-

old is reached. Once the VIN pin goes above UVLO and a high

signal is present on the EN pin, the IC proceeds to power up. At

this point, the ALT80600 is going to enable the disconnect switch

and will try to check if any LED pins are shorted to GND and/or

are not used. The LED detect phase starts when the GATE volt-

age of the input disconnect PMOS switch is pulled down to 3.3 V

below V_INand PWM = H.

Using all Lꢀꢁ

Channels

Using Lꢀꢁ

Channels 1-3

Lꢀꢁ1

Lꢀꢁꢈ

Lꢀꢁ3

Lꢀꢁ1

Lꢀꢁꢈ

Lꢀꢁ3

Lꢀꢁꢂ

ꢃNꢁ

Lꢀꢁꢂ

ꢃNꢁ

ꢇ.19 kΩ

Figure 6: How to signal an unused LED channel

during startup LED detection phase

Table 2: LED Detection phase voltage threshold levels

LED Pin

Voltage Measured

Interpretation

Outcome

Cannot proceed with

soft-start unless fault

is removed

LED pin shorted to

GND fault

< 120 mV

LED channel is

removed from

operation

LED channel not in

use

~ 230 mV

> 340 mV

LED channel in use

Proceed with soft-start

Figure 5: Startup showing EN+PWM, GATE, LED1, and ISET.

Switching frequency = 2.15 MHz. Note that LED Detection Phase

starts as soon as GATE pin is pulled down to 3.3 V below V_IN.

Once the voltage threshold on VLED pins exceeds ~120 mV, a

delay of 3584 clock cycles is used to determine the status of the

pins. Therefore the duration of LED Detection phase depends on

the switching frequency selected:

Table 1: Duration of LED Detection phase with respect

to switching frequency

Switching Frequency

2.15 MHz

Approximate Detection Time

1.67 ms

3.6 ms

7.2 ms

14 ms

1 MHz

Figure 7: Normal startup showing all channels passed LED Detec-

tion phase. Total LED current = 100 mA × 4 (only LED1 and LED2

pin voltages are shown).

500 kHz

250 kHz

Unused LED pin should be terminated with a 6.19 kΩ resistor to

GND. At the end of LED detection phase, any channel with pull

down resistor is then disabled and will not contribute to the boost

regulation loop.

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LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

Power Up: Boost Output Undervoltage

During startup, after the input disconnect switch has been

enabled, the output voltage is checked through the OVP (over-

voltage protection) pin. If the sensed voltage does not rise above

V_UVP(th), the output is assumed to be at fault and the IC will not

proceed with soft start.

Undervoltage protection may be caused by one of the following

faults:

• Output capacitor shorted to GND

• Boost inductor or diode open

• OVP sense resistor open

After an UVP (undervoltage protection) fault, the ALT80600 is

immediately shutdown and latched off. To enable the IC again,

the latched fault must be cleared. This can be achieved by

Figure 8: Normal startup showing LED1 channel is disabled. Total

LED current = 100 mA × 3.

powering-cycling the IC, which means either:

• V_INfalls below falling UVLO threshold, or

• EN = L for >32k clock cycles (about 16 ms at 2 MHz).

If an LED pin is shorted to ground, the ALT80600 will not pro-

ceed with soft start until the short is removed from the LED pin.

This prevents the ALT80600 from ramping up the output voltage

Alternatively, latched fault can be cleared by keeping EN = H

and putting an uncontrolled amount of current through the LEDs. but pulling PWM = L for >32k clock cycles. This method has the

advantage that it does not interrupt the CLKOUT signal.

Figure 9: LED1 is shorted-to-GND initially, then released. After the

fault is removed, the IC auto-recovers and proceeds with soft-start.

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LED Driver with Pre-Emptive Boost

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ALT80600

enabled. IC is now waiting for PWM = H to startup.

Soft Start Function

C: Once PWM = H, the IC checks each LEDx pins to determine

if it is in use, disabled, or shorted to GND.

During startup, the ALT80600 ramps up its boost output voltage

following a fixed slope, as determined by OVP set point and Soft-

Start Timer. This technique limits the input inrush current, and

ensures consistent startup time regardless of the PWM dimming

duty cycle.

D: Soft-Start begins at the completion of LED pin short-detect

phase (3584 clock cycles). V_OUTramps up following a fixed

slope set by OVP and soft-start timer (21.5 ms).

The soft-start process is completed when any one of the follow-

ing conditions is met:

E: Soft-start terminates when all LED currents reached regula-

tion, V_OUTreached 93% OVP, or soft-start timer expired.

• All enabled LED channels have reached their regulation

current,

• Output voltage has reached 93% of its OVP threshold, or

• Soft-start ramp time (t_SS) has expired.

ꢃC ꢄꢅꢅ

ꢎNꢔH ꢕ

ꢈꢃNꢖUꢈLꢄ

To summarize, the complete startup process of ALT80600 con-

sists of:

Power ꢁꢆ

ꢇꢈꢉꢉ, ꢊꢋ readyꢌ ꢋAꢍꢎ

ꢆꢁlled Lꢌ ꢀaꢁlt checꢏingꢐ

ꢎNꢔL

• Power-up error checking

• Enabling input disconnect switch

• LED pin open/short detection

• Soft-start ramp

ꢀAULꢍ State

ꢇꢀAULꢍ ꢆꢁlled Lꢐ

Any ꢀaꢁlt

detectedꢂ

ꢑes

This is illustrated by the following startup timing diagram (not to

scale):

No

ꢀꢁ

ꢎNꢔH ꢕ

PꢗMꢔL

ꢃC Ready

ꢇCLꢒꢄUꢍ actiꢓe,

ꢀAULꢍꢔHꢐ

ꢎNꢔL

ꢂꢃꢄ

ꢀꢁN

ꢎNꢔH ꢕ PꢗMꢔH

3.3ꢀ

ꢂ.ꢃꢀ

ꢅATꢀ

Pin shorted

to ꢋNꢉ ꢅaꢁlt

Lꢎꢉ Pin Checꢏ

ꢇꢃn Use, ꢉisaꢘled, or

Shorted to ꢋNꢉꢐ

0

Lꢀꢉꢊ^1ꢀ

0

ꢍime-oꢁt withoꢁt ꢅaꢁlts

Lꢉꢊ detection

ꢋhase

ꢄꢀP

Soꢅt Start

ꢇenaꢘle ꢘoost Sꢗ and

Lꢎꢉ cꢁrrent sinꢏsꢐ

93ꢈ ꢄꢀP

35ꢎꢏ cycles

ꢆꢇꢈT

Soꢅt start ꢅinished

ꢀꢁN

Any ꢀaꢁlt

detectedꢂ

0

t_SSꢅꢆ1.5msꢇ

ꢑes

ꢋ

No

Lꢀꢉ

PꢗM ꢉimming

0

Soꢌt-Start

Regꢍlation

A

ꢌ

ꢍ

ꢉ

ꢀ

Lꢎꢉꢔon

Clear 3ꢙꢏ clꢏ timer

Figure 10: Complete startup process of ALT80600

ꢎN ꢕꢕ PꢗM ꢔL

ꢎN ꢕꢕ PꢗM ꢔH

Explanation of Events:

Lꢎꢉꢔoꢅꢅ

Start 3ꢙꢏ clꢏ timer

A: EN = H wakes up the IC. V_DDramps up and CLKOUT

ꢍimer eꢚꢆired

becomes available. IC starts to pull down GATE slowly.

B: When GATE is pulled down to 3.3 V below V_IN, I_SETbecomes

Figure 11: Startup Flow Chart

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LED Driver with Pre-Emptive Boost

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ALT80600

the timing restrictions for a synchronization clock at 2.2 MHz.

Frequency Selection

t _{PꢂSꢃNCꢄN}

The switching frequency of the boost regulator is programmed

by a resistor connected to FSET pin. The switching frequency

can be selected anywhere from 200 kHz to 2.3 MHz. The chart

below shows the typical switching frequency verses FSET resis-

tor value.

15ꢁ ns

150 ns

t_{PꢂSꢃNCꢄꢅꢅ}

t ꢀ ꢁ5ꢁ ns

Figure 13: Pulse width requirements

for an External Sync clock at 2.2 MHz

Based on the above, any clock with a duty cycle between 33%

and 66% at 2.2 MHz can be used. The table below summarizes

the allowable duty cycle range at various synchronization fre-

quencies.

Table 3: Acceptable Duty Cycle range for External Sync

clock at various frequencies

Sync. Pulse Frequency

2.2 MHz

Duty Cycle Range

33% to 66%

2 MHz

30% to 70%

1 MHz

15% to 85%

Figure 12: Switching Frequency

as a function of FSET Resistance

600 kHz

9% to 91%

300 kHz

4.5% to 95.5%

Alternatively, the following empirical formula can be used:

Equation 1:

f_SW= 21.5 / (R_FSET+ 0.2)

If it is necessary to switch over between internal oscillator and

external sync during operation, ensure the transition takes place

at least 500 ns after the previous PWM = H rising edge. Alterna-

tively, execute the switchover during PWM = L only. This restric-

tion does not apply if PWM dimming is not being used.

where f_SWis in MHz and R_FSETis in kΩ.

If a fault occurs during operation that will increase the switch-

ing frequency, the internal oscillator frequency is clamped to a

maximum of 3.5 MHz. If the FSET pin is shorted to GND, the

part will shut down. For more details, refer to the Fault Mode

Table section.

ꢃꢑ

ꢀꢁꢂ

Synchronization

500 ns

ꢃꢄꢅꢆꢇꢈꢉꢊ

ꢋ ꢌꢇꢃT

The ALT80600 can also be synchronized using an external clock.

At power up, if the FSET pin is held low, the IC will not start.

Only when the FSET pin is tristated to allow for the pin to rise to

about 1 V, or when a sync clock is detected, the ALT80600 will

then try to power up.

1 ꢀ

ꢍLꢎꢏꢐT

ꢁnternal oscillator

ꢂꢃternal Sync

The basic requirement of the external sync signal is 150 ns minimum

on-time and 150 ns minimum off time. The diagram below shows

Figure 14: Avoid switching over between Internal

Oscillator and External Sync in highlighted region

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LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

The dithering Range is given by the approximate equation:

Loss of External Sync Signal

Equation 3:

Range (±%) = 20 × R_FSET/ R_DITH

Suppose the ALT80600 started up with a valid external SYNC

signal, but the SYNC signal is lost during normal operation. In

that case, one of the following happens:

where R_FSETis the resistor from FSET pin to GND, R_DITHis

the resistor between DITH and FSET pins.

• If the external SYNC signal is high impedance (open), the

IC continues normal operation after approximately 5 μs, at

the switching frequency set by R_FSET. No FAULT flag is

generated.

As an example, by using R_FSET= 10 kΩ, R_DITH= 40.2 kΩ,

and C_DITH= 22 nF, the resulted switching frequency is f_SW

2.15 MHz ±5% modulated at 1.1 kHz. This is illustrated by the

following diagram.

=

• If the external SYNC signal is stuck low (shorted to ground),

the IC will detect an FSET-shorted-to-GND fault. FAULT

pin is pulled low after approximately 10 μs, and switching is

disabled. Once the FSET pin is released or SYNC signal is

detected again, the IC will proceed to soft-start.

ꢇ_ꢃꢄTꢅ

ꢆ

_ꢀꢁꢂTꢈ 100 ꢊA

ꢉ5 ꢊA

ꢀꢁꢂT

ꢃꢄTꢅ

1.ꢄ ꢌ

1.0 ꢌ

0.ꢋ ꢌ

ꢆ_ꢃꢄTꢅꢈ ꢉꢄ0 ꢊA

ꢇ_ꢆSꢇꢂ

R_ꢀꢁꢂH

ꢃ0.ꢄ ꢅΩ

R_ꢆSꢇꢂ

10 ꢅΩ

C_ꢀꢁꢂH

ꢄꢄ nꢆ

ꢆ_ꢃꢄTꢅ

ꢄ0 ꢊA

0

ꢀithering Range ꢈ

ꢉ5ꢖ

To prevent generating a fault when the external SYNC signal

is stuck at low, the circuit shown below can be used. When the

external SYNC signal goes low, the IC will continue to operate

normally at the switching frequency set by the R_FSET. No FAULT

flag is generated.

ꢍꢄ0 ꢊA

Modꢒlation

ꢓreꢔꢒency

ꢈ 1.1 ꢅHꢕ

Period ꢈ 0.ꢋ ꢎ C ꢏ i

ꢐ0.ꢋꢋ ms when C ꢈ ꢄꢄ nꢆꢑ

ꢈ_ꢁꢉꢊꢋꢅꢌꢍ

ꢄ.ꢄ5

ꢄ.15

ꢄ.05

ꢁꢅternal

Sychroniꢆation

ꢊꢊ0ꢋꢀ

Signal

ꢂime ꢐmsꢑ

ꢀSꢁꢂꢃSꢄNC

0

0.ꢋꢋ

Figure 16: How to Program Switching Frequency

Dithering Range and Modulation Frequency

R_ꢀSꢁꢂ

10kΩ

Schottꢇy

ꢈarrier

ꢉiode

There are no hard limits on dithering range and modulation

frequency. As a general guideline, pick a dithering range between

±5% and 10%, with the modulation frequency between 1 kHz and

3 kHz. In practice, using a larger dithering range and/or higher

modulation frequency do not generate any noticeable benefits.

Figure 15: Countermeasure for

External Sync Stuck-at-Low Fault

Switching Frequency Dithering

If dithering function is not desired, it can be disabled by discon-

necting the R_DITHbetween DITH and FSET pins. Connect DITH

pin to VDD if C_DITHis not populated.

To minimize the peak EMI spikes at switching frequency har-

monics, the ALT80600 offers the option of frequency dithering,

or spread-spectrum clocking. This feature simplifies the input

filters needed to meet the automotive CISPR 25 conducted and

radiated emission limits.

Clock Out Function

The ALT80600 allows other ICs to be synchronized to its internal

switching frequency through the CLKOUT pin.

For maximum flexibility, the ALT80600 allows both dithering

range and modulation frequency to be independently program-

mable using two external components.

The CLKOUT signal is available as soon as the IC is enabled

(EN = H), even when the boost stage is not active (PWM = L).

Its frequency is the same as that of the internal oscillator. Its

duty cycle, however, depends on how the switching frequency is

generated:

The Dithering Modulation Frequency is given by the approximate

equation:

Equation 2:

f_DM(kHz) = 25 / C_DITH(nF)

• If f_SWis programmed by FSET resistor, the CLKOUT duty

cycles is approximately 50%.

• If f_SWis controlled by external sync, the output signal has a

where C_DITHis the value of capacitor connected from DITH

pin to GND.

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LED Driver with Pre-Emptive Boost

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ALT80600

fixed 150 ns negative pulse width (CLKOUT = L), regardless

of the external sync frequency.

I_LED= I_SET× A_ISET

I_SET= V_ISET/ R_ISET

This is illustrated by the following waveforms:

Therefore R_ISET= (V_ISET× A_ISET) / I_LED

= 833 / I_LED

where I_LEDcurrent is in mA and R_ISETis in kΩ.

This sets the maximum current through the LEDs, referred to

as the ‘100% current’. The average LED current can be reduced

from the 100% current level by using either PWM dimming or

analog dimming.

Table 4: ISET resistor values vs. LED current. Resistances

are rounded to the nearest E-96 (1%) resistor value.

Standard Closest RISET

LED current per channel

Resistor Value

6.98 kΩ

8.25 kΩ

10.5 kΩ

13.7 kΩ

21.0 kΩ

120 mA

100 mA

80 mA

60 mA

40 mA

Figure 17: Without external sync, the CLKOUT signal has a ﬁxed

duty cycle of 50%. Delay from CLKOUT falling edge to SW falling

edge is approximately 50 ns.

PWM Dimming

When both EN and PWM pins are pulled high, the ALT80600

turns on all enabled LED current sinks. When either EN or PWM

is pulled low, all LED current sinks are turned off. The compen-

sation (COMP) pin is floated, and critical internal circuits are

kept active.

Figure 18: With external sync, the CLKOUT signal has a ﬁxed

negative pulse width of 200 ns. Delay from SYNC rising edge to

CLKOUT falling edge is approximately 60 ns.

LED Current Setting

The maximum LED current can be up to 120 mA per chan-

nel, and is set through the ISET pin. Connect a resistor RISET

between this pin and GND. The relation between ILED and

RISET is given below:

Figure 19: PWM dimming operation at 20% 1 kHz. CH1 = PWM (5 V/

div), CH2 = SW (20 V/div), CH3 = V_OUT, CH4 = i_LED(200 mA/div).

Equation 4:

By using the patented Pre-Emptive Boost (PEB) control algo-

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LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

rithm, the ALT80600 is able to achieve minimum PWM dimming

on-time down to 300 ns. This translates to PWM dimming ratio

up to 15,000:1 at the PWM dimming frequency of 200 Hz. Tech-

nical details on PEB will be explained in the next section.

Table 5: Maximum PWM Dimming Ratio that can be achieved

when operating at different PWM Dimming Frequency

Maximum PWM

PWM Frequency

PWM Period

Dimming Ratio

15,000:1

3,000:1

200 Hz

1 kHz

5 ms

1 ms

3.3 kHz

20 kHz

300 µs

50 µs

1,000:1

150:1

Pre-Emptive Boost

The basic principle of pre-emptive boost (PEB) can be best

explained by the following two waveforms. The first one shows

how a conventional LED driver operates during PWM dimming

operation. The second one shows that of the ALT80600.

Common test conditions for both cases:

PWM = 1% at 1 kHz (on-time=10 µs), f_SW= 2.15 MHz, L =

10 µH, V_IN= 12 V, LED load = 8 series (V_OUT= ~25 V) at

100 mA × 4. C_OUT= 2 × 4.7 µF 50 V 1210 MLCC. COMP: R_Z

= 280 Ω, C_Z= 68 nF.

Figure 20: Zoom in view for PWM on-time = 10 µs. Notice that the

LED current is shifted with respect to PWM signal. Ripple at V_OUT

is ~0.2 V when using 2 × 4.7 µF MLCC as output capacitors.

Common scope settings:

CH1 (Yellow) = PWM (5 V/div); CH2 (Red) = Inductor current

(500 mA/div); CH3 (Blue) = V_OUT(1 V/div); CH4 (Green) =

LED current (200 mA/div); time scale = 2 µs/div.

Figure 21: Zoom-in view showing ALT80600 is able to regulate LED

current at PWM on-time down to 300 ns.

The typical PWM dimming frequencies fall between 200 Hz and

1 kHz. There is no hard limit on the highest PWM dimming fre-

quency that can be used. However at higher PWM frequency, the

maximum PWM dimming ratio will be reduced. This is shown in

the following table:

Figure 22: Traditional PWM Dimming operation where boost switch

and LED current are enabled at the same time. Note that V_OUT

shows overall ripple of ~0.5 V

When PWM signal goes high, a conventional LED driver turns

on its boost switching at the time with LED current sinks. The

problem is that the inductor current takes several switching cycles

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LED Driver with Pre-Emptive Boost

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ALT80600

to ramp up to its stead-state value before it can deliver full power

to the output load. During the first few cycles, energy to the LED

load is mainly supplied by the output capacitor, which results in

noticeable dip in output voltage.

Figure 24: How PEB delay time varies with value of PEB pin resis-

tor to GND.

Ideally, t_PEBis equal to the inductor current ramp up time. But the

latter is affected by many external parameters, such as switching

frequency, inductance, V_INand V_OUTratio, etc. Therefore, some

experimentation is required to optimize the PEB delay time. In

general for switching frequency at 2 MHz, t_PEB= 2 to 4 µs is a

good starting point.

Figure 23: ALT80600 PWM dimming operation with PEB delay set

to 3 µs. Note that V_OUTripple is reduced to ~0.2 V.

In the ALT80600, the boost switch is also enabled when PWM

goes high. However, the LED current is not turned on until after

a short delay of t_PEB. This allows the inductor current to build up

before it starts to deliver the full power to LED load. During the

pre-boost period, V_OUTactually bumps up very slightly, while

the following dip is essentially eliminated. When PWM goes low,

both boost switching and LED remains active for the same delay

of t_PEB. Therefore the PWM on-time is preserved in LED current.

The advantage of PEB is that even a non-optimized delay time

can significantly reduce the output ripple voltage compared to a

conventional LED driver.

PEB delay can be programmed using an external resistor, R_PEB

,

from PEB pin to GND. Their relationship is shown in the follow-

ing chart:

17

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LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

Analog Dimming with APWM Pin

APꢀM

ꢁSꢂꢃ

Cꢄrrent

Mirror

APꢀM ꢁSꢂꢃ

ꢁSꢂꢃ

Cꢄrrent

Adꢅꢄst ꢆlocꢇ

R_ꢁSꢂꢃ

PꢀM

Lꢂꢈ ꢈriꢉer

Figure 25: Simpliﬁed block diagram of APWM function

The APWM pin is used in conjunction with the ISET pin to

achieve analog dimming. This is a digital signal pin that inter-

nally adjusts the ISET current. The typical input signal frequency

is between 40 kHz and 1 MHz. The duty cycle of this signal is

inversely proportional to the percentage of current delivered to

the LED. The relationship is shown below:

Figure 27: PWM = H. Total LED current drops from 400 mA (4 ×

100 mA/ch) to 300 mA when APWM of 25% duty cycle is applied.

Note that LED current takes ~0.5 ms to settle after change in APWM.

Figure 28: PWM = 25% at 1 kHz. Peak LED current drops from

400 mA (4 × 100 mA/ch) to 300 mA when APWM of 25% duty cycle

is applied

One popular application of analog dimming is for LED brightness

calibration, commonly known as ‘LED Binning’. LEDs from

the same manufacturer and series are often grouped into differ-

ent ‘bins’ according to their light efficacy (lumens per watt). It is

therefore necessary to calibrate the ‘100% current’ for each LED

bin, in order to achieve uniform luminosity.

Figure 26: Showing LED current is inversely proportional to the

APWM duty cycle. Test conditions: V_IN=12 V, V_OUT= 25 V (8 ×

WLED), total LED current = 100 mA × 4, APWM frequency = 100 kHz

As an example, a system that delivers a full LED current of

100 mA per channel would deliver 75 mA when an APWM signal

with a duty-cycle of 25% is applied (because analog dimming

level is 100% – 25% = 75%). This is demonstrated by the fol-

lowing waveforms.

To use APWM pin as a trim function, the user should first set

the 100% current based on efficacy of LED from the lowest bin.

When using LED with higher efficacy, the required current is then

trimmed down to the appropriate level using APWM duty cycle.

18

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LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

As an example, assume that:

Note that the ALT80600 is capable of providing analog dim-

ming range greater than 10:1. By applying APWM with 96%

• LED from lowest bin has an efficacy of 80 lm/W

• LED highest bin has an efficacy of 120 lm/W

duty cycle, for example, an analog dimming range of 25:1 can

be achieved. However, this requires the external APWM signal

source to have very fine pulse-width resolution. At 200 kHz

APWM frequency, a resolution of 50 ns is required to adjust its

duty cycle by 1%.

Suppose the maximum LED current was set at 100 mA based

LEDs from lowest bin. When using LEDs from highest bin, the

current should then be reduces to 67% (80/120). This can be

achieved by sending APWM clock with 33% duty cycle.

Analog Dimming with External Voltage

When analog dimming is not used, APWM pin should be either

tied to GND or left floating (there is an internal pull-down resis-

tor to GND).

Besides using APWM signal, the LED current can also be

reduced by using an external voltage source applied through a

resistor to the ISET pin. The dynamic range of this type of dim-

ming is dependent on the ISET pin current. The recommended

i_SETrange is from 20 µA to 125 µA for the ALT80600. Note that

the IC will continue to work at i_SETbelow 20 µA, but the relative

error in LED current becomes larger at lower dimming level.

Extending LED Dimming Ratio

The dynamic range of LED brightness can be further extended,

by using a combination of PWM duty cycle, APWM duty cycle,

and analog dimming method.

Below is a typical application circuit using a DAC (digital-analog

converter) to control the LED current. The ISET current (which

For example, the following approach can be used to achieve a

100,000:1 dimming ratio at 200 Hz:

directly controls the LED current) is normally set as V_ISET/R_ISET

.

• Vary PWM duty cycle from 100% down to 0.01% to give

10,000:1 dimming. This requires PWM dimming on-time be

reduced down to 0.5 µs.

The DAC voltage can be higher or lower than V_ISET, thus adjust-

ing the LED current to a lower or higher value.

• With PWM dimming on-time fixed at 0.5µs, vary APWM

duty from 0% to 90% to reduce peak LED current from 100%

down to 10%. This gives a net effect of 100,000:1 dimming.

ALꢂꢃ0ꢄ00

Rꢅ

ꢈꢇAC

ꢀSꢁꢂ

R_ꢀSꢁꢂ

ꢆNꢇ

Figure 30: Adjusting LED current

with an external voltage source

Equation 5:

V_ISET

R_ISET

VDAC −V

R2





ISET

i_ISET

=

−









where V_ISETis the ISET pin voltage (typically 1.0 V), and

VDAC is the DAC output voltage.

When VDAC is higher than 1.00 V, the LED current is reduced.

When VDAC is lower than 1.00 V, the LED current is increased.

Some common applications for the above scheme include:

Figure 29: How to achieve 100,000:1 dimming ratio by using both

PWM and APWM. Test conditions: V_IN= 12 V, V_OUT= 25 V (8 ×

WLED), total LED current = 400 mA, PWM frequency = 200 Hz,

APWM frequency = 100 kHz.

• LED binning

• Thermal fold-back using external NTC (negative temperature

coefficient) thermistor

19

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LED Driver with Pre-Emptive Boost

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ALT80600

In the following application example, the thermistor used is NTC- 15.2 ms to completely shut down the IC. The next time EN pin

S0805E3684JXT (680 kΩ @ 25°C). R1 = 340 kΩ, R2 = 20 kΩ,

and R3 = 8.45 kΩ. The LED current per channel is reduced from

97 mA at 25°C to 34 mA at 125°C.

goes high, all internal fault registers are cleared. The IC needs to

go through a complete soft start process after PWM goes high.

ꢀꢁꢁ

ꢂꢃ.ꢄ5 ꢀꢅ

ALꢈꢉ0ꢊ00

NTC

Rꢄ

ꢆSꢇꢈ

ꢂ1.0 ꢀꢅ

R1

ꢋNꢁ

R3

Figure 31: Thermal foldback of

LED current using NTC thermistor

Figure 33: After EN = L for 32k clock cycles (~15 ms at 2.15 MHz),

the IC completely shuts down so VDD (Blue) decays.

There is an alternative way to reset the internal fault status regis-

ters. By keeping EN = H and PWM = L for longer than 32k clock

cycles, the ALT80600 clears all internal fault registers but does

not go into sleep mode. The next time PWM pin goes high, the IC

will still go through soft start process. The difference is that VDD

voltage and CLKOUT signal are always available as long as EN

= H.

Figure 32: LED current varies with temperature

when using thermistor NTCS0805E3684JXT

for thermal foldback

VDD

The VDD pin provides regulated bias supply for internal circuits.

Connect a C_VDDcapacitor with a value of 1 μF or greater to this

pin. The internal LDO can deliver up to 2 mA of current with a

typical VDD voltage of about 4.25 V. This allows it to serve as

the pull up voltage for FAULT pin.

Shutdown

If EN pin is pulled low for longer than t_EN(OFF)(32k clock

cycles), the ALT80600 enters shutdown (sleep mode). As an

example, at 2.15 MHz clock frequency, it will take approximately

Figure 34: As long as EN = H, the IC does not shut down VDD and

CLKOUT. But internal latched faults are cleared by PWM = L for

32k clock cycles.

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LED Driver with Pre-Emptive Boost

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ALT80600

FAULT DETECTION AND PROTECTION

While the IC is being PWM dimmed, the IC will recheck the

LED String Partial-Short Detect

disabled LED every time the PWM signal goes high. This allows

for some self-correction in case an intermittent LED pin shorted

to VOUT fault is present.

All LED current sink pins (LED1 to LED4) are designed to with-

stand the maximum output voltage, as specified in the AbsMax

section. This prevents the IC from being damaged if V_OUTis

directly applied to an LED pin due to an output connector short.

At least one LED pin must be at regulation voltage (below

~1.2 V) for the LED string partial-short detection to activate.

In case all of the LED pins are above regulation voltage (this

could happen when the input voltage rises too high for the LED

strings), they will continue to operate normally.

In case of direct-short or partial-shorted fault in any LED string dur-

ing operation, the LED pin with voltage exceeding V_LEDSCwill be

removed from regulation. This prevents the IC from dissipating too

much power due to large voltage drop across the LED current sink.

Overvoltage Protection

The ALT80600 offers a programmable output overvoltage

protection (OVP), plus a fixed secondary overvoltage protection

(OVP2).

The OVP pin has a threshold level of 2.5 V typical. Overvoltage

protection is tripped when current into this pin exceeds ~150 µA.

A resistor can be used to set the OVP threshold up to 40 V approxi-

mately. This is sufficient for driving 11 white LEDs in series.

The formula for calculating the OVP resistor is shown below:

Equation 6:

R_OVP= (V_OVP– V_OVP(th)) / i_OVP(th)

where V_OVPis the desired OVP threshold, V_OVP(th)= 2.5 V

typical, i_OVP(th)= 150 µA typical.

To determine the desired OVP threshold, take the maximum LED

string voltage at cold and add ~10% margin on top of it.

Figure 35: Normal startup sequence showing voltage at LED2 and

LED3 pins. V_IN= 6 V, output = 6 × WLED in series, current = 4 × 100 mA

The OVP event is not a latched fault and, by itself, does not pull

the FAULT pin to low. If the OVP condition occurs during a load

dump, for example, the IC will stop switching but not shut down.

There are several possibilities of why an OVP condition is

encountered during operation. The two most common being an

open LED string and a disconnected output connector.

The waveform below shows a typical OVP condition. When one

LED string becomes open, current through its LED driver drops

to zero. The ALT80600 responses by boosting the output voltage

higher. When output reaches OVP threshold, the LED string with-

out current is removed from regulation. The rest of LED strings

continue to draw current and drain down V_OUT. Once V_OUTfalls

below ~94% OVP, boost will resume switching to power the

remaining LED strings.

Figure 36: Startup sequence when LED string#2 has a partial-short

fault (4 × WLED instead of 6). As soon as LED2 pin rises above

V_LEDSC(~4.6 V), the channel is disabled. Output is now 300 mA.

21

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LED Driver with Pre-Emptive Boost

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ALT80600

Boost Switch Overcurrent Protection

The boost switch is protected with cycle-by-cycle current limit-

ing set at typical 3.65 A, minimum 3.0 A. The waveform below

shows normal switching at V_IN= 6 V, V_OUT= 25 V, and total

LED current 400 mA.

Figure 37: An open-LED string faults causes V_OUTto ramp up and

trip OVP. The ALT80600 then disables the open LED string and

continues with remaining strings.

The ALT80600 also has a fixed secondary overvoltage protection

to protect its internal switch. If the boost Schottky diode suddenly

becomes open during normal operation, the energy stored in the

inductor will force SW node voltage to increase rapidly. Once

voltage on the SW pin exceeds OVP2, switching and all LED

drivers are disabled. The IC remains latched off until it is reset.

Figure 39: Normal switching waveform showing the SW node volt-

age and inductor current.

When the input voltage is reduced further, input current increases

and peak switch current reaches 3.2 A. SW_OCP is tripped and

the IC skips a switching cycle to reduce the current

Figure 38: An open-diode fault is introduced during normal opera-

tion. SW voltage jumps to ~70 V, causing the MOSFET to self-con-

duct and dissipate energy in the inductor.

Figure 40: When peak current in SW pin reaches ~3.2 A, overcur-

rent protection kicks in and the IC skips a switching cycle.

It should be noted that the SW MOSFET in ALT80600 is

designed to avalanche and dissipate the excess energy safely in

case of open-diode fault. Therefore the IC is not damaged even

though SW node rises above AbsMax rating momentarily.

There is also a secondary current limit (I_SW(LIM2)) that is sensed

on the boost switch. This current limit is set at about 33% higher

than the cycle-by-cycle current limit. It is to protect the switch

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LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

from destructive current spikes in case the boost inductor is

shorted. Once this limit is tripped, the ALT80600 will immedi-

ately shut down and latch off.

The waveform below illustrates the typical input overcurrent

fault condition. As soon as input OCP limit is reached, the part

disables the gate of the disconnect switch Q1 and latches off.

Input Overcurrent Protection and

Disconnect Switch

i_SꢈNSꢈ

ꢉꢊN

ꢀo L1

R_SC

ꢃ1

ꢄPMꢅSꢆ

R_Aꢋꢌ

C_ꢇ

i_Aꢋꢌ

ꢇAꢀꢈ

ꢉ_SꢈNSꢈ

ALꢀꢁ0ꢂ00

ꢉ_ꢊN

ꢉ_ꢊNꢍ ꢉ_SꢈNSꢈꢎ R_SCꢏ i_SꢈNSꢈꢐ R_Aꢋꢌꢏ i_Aꢋꢌ

Figure 41: Optional input disconnect switch using a PMOSFET

Figure 42: Startup into an output shorted-to-GND fault. Input OCP

is tripped when current (Green trace) exceeds 4 A. PMOS Gate

(Red) is turned oﬀ immediately and IC latches oﬀ.

The primary function of the input disconnect switch is to protect

the system and the device from catastrophic input currents during

a fault condition.

During startup when Q1 first turns on, an inrush current flows

through Q1 into the output capacitance. If Q1 turns on too fast

(due to its low gate capacitance), the inrush current may trip

input OCP limit. In this case, an external gate capacitance CG is

added to slow down the turn-on transition. Typical value for CG

is around 4.7 to 22 nF. Do not make CG too large, since it also

slows down the turn-off transient during a real input OCP fault.

If the input current level goes above the preset current limit

threshold, the part will be shut down in less than 3 µs. This is

a latched condition. The fault flag is also set to indicate a fault.

This feature protects the input from drawing too much current

during heavy load. It also prevents catastrophic failure in the

system due to a short of the inductor, diode, or output capacitors

to GND.

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LED Driver with Pre-Emptive Boost

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ALT80600

Setting the Current Sense Resistor

Fault Protection During Operation

The typical threshold for the current sense is 100 mV when R_ADJ

is 0 Ω. The ALT80600 can have this voltage trimmed using the

R_ADJresistor. The typical trip point should be set to at least

3.65 A, which coincides with the cycle-by-cycle current limit

The ALT80600 constantly monitor the state of the system to

determine if any fault conditions occur during normal operation.

The response to a triggered fault condition is summarized in the

table below. It is important to note that there are several points at

typical threshold. A sample calculation is done below for 4.2 A of which the ALT80600 monitors for faults during operation. The

input current.

locations are input current, switch current, output voltage, switch

voltage, and LED pins. Some of the protection features might not

be active during startup to prevent false triggering of fault condi-

tions.

When R_ADJis not used:

Equation 7:

V_SENSETRIP= R_SC× i_SENSE= 100 mV

The desired sense resistor is R_SC= 100 mV / 4.2 A = 23.8 mΩ.

But this is not a standard E-24 resistor value. Pick the closest

lower value which is 22 mΩ.

The possible fault conditions that the part can detect include:

• Open LED Pin or open LED string

• Shorted or partially shorted LED string

• LED pin shorted to GND

When R_ADJis used:

• Open or shorted boost diode

• Open or shorted boost inductor

• VOUT short to GND

Equation 8: V_SENSETRIP= R_SC× i_SENSE+ R_ADJ× i_ADJ

Therefore

• SW shorted to GND

• ISET shorted to GND

R_ADJ= [V_SENSETRIP– (R_SC× i_SENSE)] / i_ADJ

ꢀ

=ꢀ[100ꢀmVꢀ–ꢀ92.4ꢀmV]ꢀ/ꢀ20ꢀµAꢀ=ꢀ380ꢀΩ

• FSET shorted to GND

• Input disconnect switch source shorted to GND

Input UVLO

Note that some of these faults will not be protected if the input

disconnect switch is not being used. An example of this is VOUT

short to GND fault.

When V_INand V_SENSErise above V_UVLOrisethreshold, the

ALT80600 is enabled. The IC is disabled when V_INfalls below

V_UVLOfallthreshold for more than 50 μs. This small delay is used

to avoid shutting down because of momentary glitches in the

input power supply.

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LED Driver with Pre-Emptive Boost

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ALT80600

Table 6: Fault Mode Table

Fault Flag

Set

Disconnect

Switch

Fault Name

Type

Active

Description

Boost Switch

LED Sink drivers

This fault condition is triggered when the SW current exceeds the

cycle-by-cycle current limit, I_SW(LIM).The present SW on-time is

truncated immediately to limit the current. Next switching cycle starts

normally.

Primary Switch Overcurrent

Protection (Cycle-By-Cycle Auto-restart

Current Limit)

Off for a single

cycle

Always

NO

YES

ON

OFF

ON

When current through boost switch exceeds secondary SW current

limit (i_SW(LIM2)) the device immediately shuts down the disconnect

switch, LED drivers and boost. The Fault flag is set. To reset the fault

the EN or PWM pin needs to be pulled low for 32k clock cycles.

Secondary Switch Current

Latched

Limit

Always

OFF

The device is immediately shut off if the voltage

across the input sense resistor is above the

VSENSEtrip threshold. To reset the fault the EN or PWM pin must be

pulled low for 32k clock cycles.

Input Disconnect Current

Latched

Limit

Secondary overvoltage protection is used for open diode detection.

When diode D1 opens, the SW pin voltage will increase until

V_OVP(SEC)is reached . This fault latches the IC. The input disconnect

switch and LED drivers are disabled. To reset the fault the EN or

PWM pin needs to be pulled low for 32k clock cycles.

Secondary OVP

LEDx Pin Shorted to GND

LEDx Pin Open

Latched

Always

Startup

YES

NO

OFF

ON

OFF

ON

OFF

If any of the LED pins is determined to be shorted to GND when PWM

first goes high, soft-start process is halted. Only when the short is

removed, then soft-start is allowed to proceed.

Auto-restart

If an LED string is not getting enough current, the device will first

response by increasing the output voltage until OVP is reached. Any

LED string that is still not in regulation will be disabled. The device will

then go back to normal operation by reducing the output voltage to

the appropriate voltage level.

OFF for open

pins.

ON for all others.

Normal

operation

NO

ON

Fault occurs when the ISET current goes above 150% of max current.

The boost will stop switching and the IC will disable the LED sinks

until the fault is removed. When the fault is removed, the IC will try to

regulate to the preset LED current.

ISET Short Protection

Auto-restart

Always

NO

OFF

ON

OFF

Fault occurs when the FSET current goes above 150% of max

current. The boost will stop switching, Disconnect switch will turn off

and the IC will disable the LED sinks until the fault is removed. When

the fault is removed, the IC will try to restart with soft-start.

FSET/SYNC Short

Protection

YES

OFF

Fault occurs when current into OVP pin exceeds i_OVP(th)(typically

150 µA). The IC will immediately stop switching but keep the LED

drivers active, to drain down the output voltage. Once the output

voltage decreases to ~94% OVP level, the IC will restart switching to

regulate the output current.

STOP during

OVP event.

Overvoltage Protection

Undervoltage Protection

Auto-restart

Always

NO

ON

Device immediately shuts off boost and current sinks if the voltage at

VOUT is below V_UVP(th). This may happen if VOUT is shorted to GND,

or boost diode is open before startup. It will auto-restart once the fault

is removed.

YES

OFF

ON

OFF

Fault occurs if an LED pin voltage exceeds V_LEDSCwith its current

sink in regulation, while at least one other LED pin is below ~1.2 V.

This may happen when two or more LEDs are shorted within a string.

The LED string exceeding the threshold will then be disabled and

removed from operation. Device will re-enable the LED string when its

pin voltage falls below threshold, or at the next PWM = H.

OFF for shorted

string. ON for all

others.

LED String Partial Short

Detection

Auto-restart

Always

NO

ON

Fault occurs when the die temperature exceeds the over-temperature

threshold, typically 170°C. IC will restart after temperatures drops

lower by T_SDHYS

Overtemperature Protection Auto-restart

Always

YES

NO

OFF

Fault occurs when VIN drops below VUVLO(fall), which is 3.9V max.

This fault resets all latched faults.

VIN UVLO

Auto-restart

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LED Driver with Pre-Emptive Boost

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ALT80600

Fault Recovery Mechanism

ꢀꢁ ꢂꢃꢃ

ꢉNꢐH ꢑ

ꢃꢒNꢓUꢃLꢎ

Power ꢀꢁ

ꢂꢃꢄꢄ, ꢅꢆ readyꢇ ꢆAꢈꢉ

ꢁꢀlled Lꢇ ꢊaꢀlt checꢋingꢌ

ꢉNꢐH ꢑ

PꢔMꢐL

ꢀꢁ ꢒꢌꢈꢍꢓ

ꢂCLꢍꢎUꢈ actiꢏe,

ꢊAULꢈꢐHꢌ

ꢉNꢐL

ꢉNꢐH ꢑ PꢔMꢐH

Pin shorted

to ꢆNꢄ ꢕaꢀlt

Lꢉꢄ Pin Checꢋ

ꢂꢒn-Use, ꢄisaꢖled, or

Shorted-to-ꢆNꢄꢌ

ꢈime-oꢀt withoꢀt ꢕaꢀlts

Soꢕt Start

ꢂꢖoost Sꢔ and Lꢉꢄ sinꢋs

enaꢖledꢌ

Soꢕt start ꢕinished

ꢉNꢐH ꢑ

PꢔMꢐL ꢕor

ꢓ3ꢗꢋ cycles

ꢒꢏꢆꢆꢔꢆꢕ

ꢂꢖoost and Lꢉꢄ sinꢋs

controlled ꢖy PꢔMꢌ

ꢉNꢐL ꢕor

ꢓ3ꢗꢋ cycles

ꢕaꢀlt cleared

ꢉNꢐH ꢑ PꢔMꢐL

ꢕor ꢓ3ꢗꢋ cycles

ꢄꢅꢆꢇꢐꢈꢉꢊꢋꢔꢆꢕ

ꢃꢈꢏꢐꢉ ꢍꢌꢉꢌꢊꢉꢌꢍ ꢖ

Lꢈꢉꢊꢋꢔꢆꢕ ꢃꢈꢏꢐꢉ

ꢍꢌꢉꢌꢊꢉꢌꢍ ꢖ

ꢉNꢐL ꢕor

ꢓ3ꢗꢋ cycles

Lꢈꢉꢊꢋꢌꢍ ꢂꢃꢃ

ꢂꢆAꢈꢉ ꢁꢀlled H, ꢖoost

Sꢔ and Lꢉꢄ sinꢋs

disaꢖled, ꢊAULꢈꢐLꢌ

ꢄꢅꢆꢇLꢈꢉꢊꢋꢌꢍ

ꢎꢈꢏꢐꢉ ꢑꢉꢈꢉꢌ

* Note: Fault conditions may be detected in any state or during

any state transition. Most faults are non-latching, meaning the IC

will auto-restart as soon as the fault is removed. Only the follow-

ing faults are latching:

Input Disconnect Overcurrent, SW Secondary OCP, and SW

Secondary OVP.

Latching faults can only be cleared by:

1. Reset the IC by bring VIN below UVLO,

2. Reset the IC by bring EN=L for >32k cycles, or

3. EN=H and PWM=L for >32k cycles.

26

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LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

The last method has the advantage that it does not interrupt the

CLKOUT signal. In case the fault condition (e.g. VOUT shorted

to GND) is still present when the latching fault is cleared by

PWM=L for >32k cycles, the IC will trip fault once again and

stay latched off.

Normal

ꢂꢃUꢄ-ꢅNꢆ Shorted ꢇaꢈlt

ꢇaꢈlt Remoꢉed

ꢃCP

ꢅꢆꢇꢈ

0

ꢃAꢄLT

ꢀꢁꢂ

3ꢀꢁ clocꢁ cycles

ꢊ

ꢉ

A

ꢋ

ꢌ

ꢃ

ꢌꢍꢎꢏꢐꢑꢐꢒꢅꢓꢑ ꢓꢔ ꢕꢖꢕꢑꢒꢗꢊ

Aꢊ ꢂꢃUꢄ-to-ꢅNꢆ Short ꢋaꢈlt introdꢈced. ꢌC triꢍs inꢍꢈt ꢃCP which is a latched ꢋaꢈlt. ꢇAULꢄ is

then ꢍꢈlled Low and ꢌC stays in Latched mode ꢎCLꢏꢃUꢄ remains aꢉailaꢐleꢑ.

ꢉꢊ Aꢋter PꢒMꢓL ꢋor 3ꢀꢁ cycles, ꢌC clears the latched ꢋaꢈlt so ꢇAULꢄ goes High

ꢊꢊ ꢌnꢍꢈt ꢃCP is triꢍꢍed again since ꢂꢃUꢄ is still shorted to ꢅNꢆ. So ꢇAULꢄ is ꢍꢈlled Low again

and ꢌC retꢈrns to Latched mode.

ꢋꢊ PꢒMꢓH and ꢂꢃUꢄ-to-ꢅNꢆ Short ꢋaꢈlt is remoꢉed, ꢐꢈt ꢌC cannot startꢈꢍ since it is still in

Latched mode.

ꢌꢊ Aꢋter PꢒMꢓL ꢋor 3ꢀꢁ cycles, ꢌC clears the latched ꢋaꢈlt so ꢇAULꢄ goes High

ꢃꢊ ꢌC restarts at the neꢔt PꢒMꢓH and resꢈmes normal oꢍeration

Figure 43: Timing Diagram to show how to clear Latched Fault with PWM = L

27

Allegro MicroSystems, LLC

955 Perimeter Road

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www.allegromicro.com

LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

PACKAGE OUTLINE DRAWING

For Reꢀerence ꢁnly ꢂ Not ꢀor Tooling ꢃse

Reference Allegro DWG-2871 (Rev. A) or ꢀEDEC MO-220WGGD.

Dimensions in millimeters – NOT TO SCALE.

Exact case and lead conﬁguration at supplier discretion within limits shown.

0.50

0.30

4.00 ꢂ0.10

24

0.95

1

2

1

2

A

4.00 ꢂ0.10

4.10

2.80

DETAIL A

2.80

4.10

D

C

24ꢁ

0.75 ꢂ0.05

0.0-0.05

0.08

C

SEATING

PLANE

C PCB Layout Reference View

ꢄ0.05

–0.07

0.25

0.50 BSC

0.40 ꢂ0.10

0.14 REF

0.10 REF

0.20 REF

0.203 REF

0.05 REF

0.40 ꢂ0.10

B

Detail A

ꢄ0.10

–0.15

2.70

2

1

A

B

Terminal ꢃ1 mark area

Exposed thermal pad (reference only, terminal #1 identiﬁer appearance at supplier discretion)

24

C

Reference land pattern layout (reference IPC7351 QFN50P400X400X80-25W6M); all pads a minimum of 0.20 mm

from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances;

when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation

(reference EIA/ꢀEDEC Standard ꢀESD51-5)

0.20 REF

ꢄ0.10

–0.15

2.70

0.10 REF

D

Coplanarity includes exposed thermal pad and terminals

Figure 44: Package ES, 24-Pin 4 mm × 4 mm QFN with Exposed Thermal Pad and Wettable Flank

28

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

APPENDIX A: DESIGN EXAMPLE

This section provides step-by-step instructions to select compo-

nent values for an ALT80600 application.

Step 3: Determining the OVP resistor according to equation 6:

R_OVP= (V_OVP– V_OVP(th)) / i_OVP(th)

The nominal output voltage is:

V_{OUT_nom}= n × V_f+ V_REG

.

For the purposes of this example, the following operating condi-

tions are assumed:

• V_IN= 12 V nominal (6 V min, 18 V max)

• Number of LED channels: nc = 4

where V_REGis the LED pin regulation voltage. Substitute n = 8,

V_f= 3.2 V, and V_REG= 0.8 V to get V_{OUT_nom}= 26.4 V.

• Number of series LEDs per channel: n = 8

• LED current per channel: I_LED= 100 mA

• LED forward drop: V_f= 3.2 V max at cold

• Switching frequency: f_SW= 2.15 MHz

Set the OVP threshold voltage approximately 10% higher to

account for error margin and component tolerances:

V_OVP= V_{OUT_nom}× 1.1 = 29 V .

The OVP resistor is therefore:

R_OVP= (29 V – 2.5 V) / 150 µA

= 177 kΩ (pick 178 kΩ) .

• Dithering modulation frequency: f_DITH= 1 kHz

• Dithering frequency range: ∆f_SW= ±5%

• Max Ambient temperature: T_A(max)= 65°C

• PWM dimming frequency: f_PWM= 200 Hz

Step 1: Program the Switching Frequency from equation 1:

Step 3a: Check to ensure the maximum boost duty cycle is suf-

ficient to achieve the required conversion ratio.

D_MAX(boost)= 1 – t_SW(off)× f_SW(max)

f_SW= 21.5 / (R_FSET+ 0.2)

therefore

where t_SW(off)is the worst-case minimum SW on-time, f_SW(max)is

the maximum switching frequency with dithering.

R_FSET– 0.2 = 21.5 / f_SW

Substitute t_SW(off)= 85 ns and f_SW(max)= 2.26 MHz to get

D_MAX(boost)= 0.808.

where f_SWis in MHz and R_FSETis in kΩ.

Substitute f_SW= 2.15 MHz to get R_FSET= 9.8 kΩ (pick 10 kΩ).

Theoretical maximum output voltage at the lowest input voltage is:

V_OUT(max)= V_IN(min)/ (1 – D_MAX(boost)) – V_D

Step 1a: Program the Dithering Modulation Frequency from

equation 2:

where V_Dis the forward drop of boost Schottky diode.

f_DITH(kHz) = 25 / C_DITH(nF) .

Substitute V_IN(min)= 6 V, D_MAX(boost)= 0.808, and V_D= 0.4 V to

get V_OUT(max)= 30.8 V.

Substitute f_DITH= 1 kHz to get C_DITH= 25 nF (pick 22 nF).

Step 1b: Select Dithering Range from equation 3:

∆f_SWRange (±%) = 20 × R_FSET/ R_DITH

Theoretical V_OUT(max)has to be greater than V_OVP. If this is not

the case, then switching frequency of the boost converter must be

reduced to meet the maximum duty cycle requirement.

Substitute ∆f_SWRange = 5 and R_FSET= 10 kΩ to get R_DITH

=

40 kΩ (pick 40.2 kΩ). The switching frequency now linearly

sweeps between 2.04 and 2.26 MHz.

Step 4: Inductor selection.

The inductor needs to be chosen based on ripple current require-

ment. In most applications due to stringent EMI requirements,

the system also needs to operate in continuous conduction mode

(CCM) throughout the whole input voltage range. A simple

guideline is to start with 30% peak-to-peak ripple current at

nominal input and output voltages.

Step 2: Determine the LED current set Resistor R_ISETfrom

equation 4:

R_ISET= (V_ISET× A_ISET) / I_{LED .}

Substitute V_ISET= 1 V, A_ISET= 833, and I_LED= 100 mA to get

R_ISET= 8.33 kΩ (pick 8.25 kΩ).

A-1

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LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

Substitute V_{OUT_nom}= 26.4 V, V_{IN_max}= 18 V, and η = 0.9 to get

i

_{IN_min}= 0.652 A.

Step 4a: Determine the Boost Duty Cycle

D = 1 – V_IN/ (V_OUT+ V_D) .

At maximum V_IN= 18 V, D = 0.328, ∆i_L= 0.275 A, and so i_{L_valley}

= 0.652 – 0.275/2 = 0.51 A. Therefore, the converter operates in

CCM throughout the input voltage range.

For nominal operation, substitute V_{IN_nom}= 12 V, V_{OUT_nom}

26.4 V, and V_D= 0.4 V to get D_nom= 0.552.

=

Step 5: To verify that there is sufficient slope compensation for

the inductor chosen, the ALT80600 generates a variable internal

Slope Comp (SC) according to f_SWand V_IN.

Step 4b: Calculate the nominal Input Current based on esti-

mated efficiency:

• If V_INis between 9 V and 15 V:

SC = 3 × f_SW× V_IN/ 12

i_IN= V_OUT× i_OUT/ (V_IN× η)

where η = efficiency of the converter (typically in the 85-90%

• If V_IN< 9 V:

range).

SC = 3 × f_SW× 9 / 12

For nominal operation, substitute V_OUT= 26.4 V, i_OUT= 0.4 A,

V_IN= 12 V, and η = 0.9 to get i_IN= 0.98 A.

• If V_IN> 15 V:

SC = 3 × f_SW× 15 / 12

Step 4c: Select Boost Inductance based on 30% Ripple Current.

For nominal operation, ∆i_L= 0.3 × i_IN= 0.29 A.

∆i_L= t_ON× V_IN/ L = D × V_IN/ (f_SW× L)

therefore

where f_SWis in MHz and SC is in A/µs.

At f_SW= 2.15 MHz and V_IN= 6 V, for example, then SC = 4.74 A/

µs.

The falling slope of inductor current is given as:

di_L/dt = –∆i_L/ t_OFF= –∆i_L× f_SW/ (1 – D)

L = D × V_IN/ (f_SW× ∆i_L) .

Based on equations from previous section, at V_IN= 6 V and

Substitute D_nom= 0.552, V_{IN_nom}= 12 V, and f_SW= 2.15 MHz to

get L = 10.6 µH (pick 10 µH).

V_OUT(OVP)= 29 V, then D = 0.796 and ∆i_L= 0.22 A.

Therefore | di_L/dt | = 2.32 A/µs, which is slower than the internal

slope. That means there is sufficient slope compensation.

STEP 4d: Determine the maximum and minimum input current

to the system. The maximum current determines the inductor’s

saturation current rating. The minimum current determines its

critical inductance.

In case the negative slope of inductor current is faster than the

internal slope comp, a higher inductance value must be used.

Maximum input current occurs at minimum V_INand maximum

V_OUT(OVP).

Step 6: Select the switching diode.

A Schottky barrier diode (SBD) is typically selected based on its

voltage and current ratings:

i_{IN_max}= V_OVP× i_OUT/ (V_{IN_min}× η) .

Substitute V_OVP= 29 V, V_{IN_min}= 6 V, and η = 0.85 to get i_{IN_max}

= 2.27 A.

• The reverse voltage rating must be higher than the maximum

voltage stress, which is equal to the OVP threshold in this

case.

Peak inductor current:

The average forward current rating must be higher than the total

LED current. The peak current through diode is given as:

i_{D_peak}= i_{L_peak}= i_{IN_max}+ ∆i_L/ 2

i_{L_peak}= i_{IN_max}+ ∆i_L/ 2 .

At minimum V_IN= 6 V, D = 0.796, ∆i_L= 0.22 A, and so i_{L_peak}

= 2.27 + 0.22/2 = 2.38 A. Therefore the inductor should have a

saturation current of at least 2.5 A.

From previous calculation at minimum V_IN, i_{L_peak}= 2.38 A.

However, during transient this current could reach cycle-by-cycle

Minimum input current occurs at maximum V_INand nominal

SW current limit, i_SW(LIM)

.

V_OUT

:

Another critical parameter is the diode’s reverse leakage current

at hot. This is especially important when using PWM dimming.

i_{IN_min}= V_{OUT_nom}× i_OUT/ (V_{IN_max}× η) .

A-2

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

During PWM off time, the boost converter is not switching, so

voltage at output capacitor decays due to leakage current. This

increases output ripple voltage, which may generate audible noise

from ceramic capacitors.

shown in the table below:

Rated C at Derating at Actual C at

Part#

Package

0 V (µF)

25 V

–80%

–45%

–30%

25 V (µF)

GRM21BC71H475KE11

GRM31CR71H475MA12

GRM32ER71H475KA88

0805

1206

1210

4.7

0.94

Make sure to verify the diode’s reverse current at hot (such as

125°C) and at the nominal V_OUT. As a general guideline, look

for a diode with leakage of 100 µA or less. If necessary, consider

using a diode with higher voltage rating (such as 100 V instead

of 50 V). Doing so can significantly reduce the leakage current at

4.7

2.59

4.7

3.29

Step 8: Selection of input capacitor.

A combination of MLCC and electrolytic capacitor is recom-

mended. The MLCC provides low ESR to reduce input switching

ripple. The electrolytic capacitor provides larger capacitance to

stabilize input voltage during PWM dimming operation.

nominal V_OUT

.

For this design example, a 100 V, 2 A Schottky diode SS2PH9 is

selected. It has a very low i_R= 100 µA at T_J= 150°C and V_R=

30 V.

A good rule of thumb is to set the input voltage ripple ΔV_INto be

1% of the minimum input voltage. The minimum input capacitor

requirements are as follows.

Step 7: Selection of output capacitors.

The use of multilayer ceramic capacitor (MLCC) is recommend.

MLCC has extremely low ESR, which is necessary to reduce

output switching ripple for boost converter. In addition, the total

output capacitance needs to be sufficient to reduce output droop

during PWM dimming operation.

C_IN= ∆i_L/ (8 × f_SW× ∆V_IN) .

Substitute ∆i_L= 0.22 A at V_IN= 6 V (from step 4b) and

f_SW= 2.15 MHz to get C_IN= 0.21 µF. Due to the DC bias derat-

ing, the actual MLCC selected should be rated 1 µF or higher.

The biggest contributing factors for total output capacitance are

PWM off-time and leakage current (i_LK). This current is mainly

due to the reverse current of switching diode, plus a small/negli-

gible leakage current into the OVP pin.

A much larger input capacitance is required to provide the inrush

current during PWM dimming operation. The exact requirement

depends on many external factors, such as length of power cables

and response time of the power supply. As a first-order estimate:

assuming the power supply takes 25 µs to response, and the input

capacitor must keep the V_INdrip under 0.2 V while input cur-

rent ramps up from zero to full load. Therefore the following is

needed:

In this design example, the PWM dimming frequency is 200 Hz

with minimum duty cycle of 0.01%. So the maximum PWM

off-time is essentially t_OFF= 5 ms. A typical goal is to keep the

output voltage variation at 250 mV or less, so that no audible

hum can be heard.

C_IN= i_IN× t_PS/ (8 × ∆V_IN) .

∆V_OUT= t_OFF× i_LK/ C_OUT

Substitute i_IN= 2.27 A at V_IN= 6 V (from step 4b) and t_PS

=

therefore

25 µs to get C_IN= 36 µF. Use an electrolytic capacitor of 33 µF

or 47 µF in parallel with the MLCC.

C_OUT= t_OFF× i_LK/ ∆V_OUT

.

Step 9: Choosing the input disconnect switch components.

Set the input disconnect current limit to 4 A. From equation 7:

R_SC= V_SENSETRIP/ i_SENSE= 25 mΩ

Substitute t_OFF= 5 ms, i_LK=110 µA, and ∆V_OUT= 0.25 V to get

C_OUT= 2.2 µF.

A major problem with multilayer ceramic capacitor (MLCC)

is that its actual capacitance drops with respect to DC bias. For

example, the capacitance of a 4.7 µF, 50 V, 0805 MLCC may

be derated by 80% when it is biased at 25 V. That means its real

capacity is less than 1 µF in actual application.

Pick the closest lower resistance value from E-24 series, which is

24 mΩ.

From equation 8:

MLCC with larger physical size and higher voltage rating typi-

cally suffers less derating problem. For example, a 4.7 µF, 50 V,

1210 MLCC may retain 3.3 µF of capacitance at 25 V. This is

R_ADJ= [V_SENSETRIP– (R_SC× i_SENSE)] / i_ADJ

= 200 Ω

A-3

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

The following schematic diagram shows calculated values from

the design example:

ꢁ_ꢊNꢒ ꢎ ꢓ 1ꢌ ꢁ

ꢁ_ꢀUꢅꢒ ꢋꢎ.ꢇ ꢁ nominal

10 ꢑH

ꢘ

0.0ꢋꢇ Ω

ꢇꢐ ꢑꢉ

35 ꢁ

elco

ꢇ.ꢐ ꢑꢉ

50 ꢁ

1ꢋ10

ꢂ1

ꢋ00 Ω

1ꢐꢌ ꢍΩ

Sꢈ

ꢄAꢅꢆ

ꢀꢁP

PꢄNꢃ

Lꢆꢃ1

ꢇ.ꢐ ꢑꢉ

50 ꢁ

1ꢋ10

ꢇ.ꢐ ꢑꢉ

50 ꢁ

1ꢋ10

ꢁsense

ꢁin

ꢁ_CC

ꢁ_ꢃꢃ

10 ꢍΩ

1 ꢑꢉ

ꢉAULꢅ

ALT80600

Lꢆꢃꢕ

ꢌ series

ꢇ ꢏarallel

100 mAꢖch

Lꢆꢃꢋ

Lꢆꢃ3

ꢆN

PꢈM

APꢈM

Lꢆꢃꢇ

CLꢔꢀUꢅ

AꢄNꢃ

CꢀMP

Pꢆꢗ

ꢉSꢆꢅ

ꢊSꢆꢅ

ꢃꢊꢅH

ꢋꢌ0 Ω

ꢇ0 ꢍΩ

10 nꢉ

100 ꢏꢉ

10 ꢍΩ

ꢌ.ꢋ5 ꢍΩ

ꢎꢌ nꢉ

10 ꢍΩ

Figure 45: ALT80600 Design Example Schematic

A-4

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ALT80600

Revision History

Number

Date

Description

–

1

2

March 20, 2018

November 9, 2018

March 13, 2019

Initial release

Corrected reel quantity in Selection Guide (page 2); added Appendix A.

Updated Synchronization section (page 13)

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to

permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its

use; nor for any infringement of patents or other rights of third parties which may result from its use.

Copies of this document are considered uncontrolled documents.

For the latest version of this document, visit our website:

www.allegromicro.com

A-5

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www.allegromicro.com


型号：	ALT80600KESJSR
厂家：	ALLEGRO MICROSYSTEMS
描述：	LED Driver with Pre-Emptive Boost for Ultra-High Dimming Ratio and Low Output Ripple
文件：	总33页 (文件大小：4266K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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