ALT80802KEJJTR [ALLEGRO]
LED Driver,;
| 型号： | ALT80802KEJJTR |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | LED Driver, 驱动 光电二极管 接口集成电路 |
| 文件： | 总33页 (文件大小：3043K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ALT80802
Wide Input Voltage, Adjustable Frequency,
Buck-Boost or Buck 2 Amp LED Driver
FEATURES AND BENEFITS
• Automotive AEC-Q100 qualified
DESCRIPTION
The ALT80802 is a high-frequency switching regulator that
• Supports buck-boost or buck mode operation
• Supply voltage from 3.8 to 50 V
provides constant output current to drive high-power LEDs. It
integrates a power MOSFET for step-down or inverting buck-
boostconversion.Withcurrent-modecontrolandsimpleexternal
compensation,theALT80802canachievefasttransientresponse.
▫ Handles automotive load dump and cold crank
▫ Can be run in buck mode from a pre-boost supply
• 150 mΩ integrated MOSFET switch
• Supports up to 16 V output in buck-boost mode for
4 WLEDs
• Programmable switching frequency up to 2.5 MHz for
small solution size and operation above AM band
• Designed for low EMC with frequency dithering
• Integrated level shifting allows ground-referenced enable
and fault flag in buck-boost mode
The wide input range of 3.8 to 50 V makes the ALT80802
suitable for a wide range of lighting applications, including
thoseinanautomotiveinputenvironment.Thedeviceratingalso
enables a simple solution for driving 3 to 4 WLEDs in buck-
boost configuration—a verycommonapplicationrequirement
for automotive lighting applications.
The ALT80802 is designed to aid in EMC/EMI design by
frequency dithering, soft freewheel diode turn-off, and well-
controlled switch node slew rates. A programmable oscillator
allowstheALT80802toswitchoutsideEMI-sensitivefrequency
bands such as the AM band.
• PWM dimming via direct logic input or power supply
voltage
• Robust protection against:
▫ Adjacent pin-to-pin short
▫ Pin-to-VSS (IC ground) short
▫ Component open/short faults
With current-mode control and simple external compensation,
theALT80802 can achieve fast transient response. The control
loopoftheALT80802isdesignedforPWMdimmingoperation
to achieve low dimming on-time and low turn-on overshoot.
In buck-boost operation, the ALT80802 reduces the current
overshoot normally caused by right half plane zero effect
during a PWM dimming turn-off transient.
APPLICATIONS
Automotive lighting
• Daytime running lights
• Front and rear fog lights
• Turn/stop lights
• Map light
• Dimmable interior lights
ExtensiveprotectionfeaturesoftheALT80802includepulse-by-
pulse current limit, hiccup mode short-circuit protection, open/
short freewheeling diode protection, BOOT open/short voltage
protection, VIN undervoltage lockout, and thermal shutdown.
Also,itincludesinternalclamptopreventoutputvoltagerunaway
if output LED string is opened in buck-boost operation.
PACKAGE:
10-Pin DFN with Exposed Thermal Pad and Wettable Flank
(suffix EJ)
The ALT80802 is available in industry-standard 10 pin DFN-
package with thermal pad and wettable flank.
Not to scale
CBST
CBST
LO
LO
LED+
BST
SW
CS
LED+
SW
CS
BST
VIN
EN
VIN
EN
+
VIN
–
FFn
GND
FFn
CIN
COUT
COUT
COMP
COMP
GND
+
VIN
–
D
CZ
D
CZ
LED–
LED–
RSENSE
RSENSE
CIC
CIN
RFREQ
RFREQ
RZ
RZ
Figure 1: ALT80802 Buck Simplified Schematic
Figure 2: ALT80802 Buck-Boost Simplified Schematic
ALT80802-DS
MCO-0000502
September 10, 2018
Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
SPECIFICATIONS
SELECTION GUIDE
Part Number
Package
10-pin DFN with thermal pad and wettable flank
Packing [1]
ALT80802KEJJTR
1500 pieces per 7-inch reel
[1] Contact Allegro for additional packing options.
ABSOLUTE MAXIMUM RATINGS [2]
Characteristic
Symbol
Notes
Rating
−0.3 to 55
−0.3 to VIN + 0.3
−1.5
Unit
V
Input Voltage
VIN
V
Switch Node Voltage
VSW
t < 250 ns
t < 50 ns
V
VIN + 3
V
Bootstrap Pin to Switch Node
VSS to GND
VBST-SW
−0.3 to 6
−0.3 to 20
V
VGND-VSS
Limits output to –20 V
With respect to VSS pin
With respect to VSS pin
V
EN, FREQ, CS, FFn
All other pins
−0.3 to VIN + 0.3
−0.3 to 6
V
V
Junction Temperature
Storage Temperature Range
TJ
−40 to 150
−40 to 150
°C
°C
Tstg
[2] Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Characteristic
Symbol
Test Conditions
Value
Unit
DC Input voltage
VIN
GND connected to VSS
6 to 36
V
Transient Input Voltage
Junction Temperature
VIN
TJ
GND connected to VSS
3.8 to 50
V
−40 to 150
°C
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Symbol
Test Conditions [3]
Value
Unit
Junction-to-Ambient Thermal Resistance
RθJA
DFN-10 (EJ) package on 4-layer PCB based on JEDEC standard
45
°C/W
[3] Additional thermal information available on the Allegro website.
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
Table of Contents
Features and Benefits........................................................... 1
Description.......................................................................... 1
Applications......................................................................... 1
Package ............................................................................. 1
Simplified Schematics........................................................... 1
Specifications ...................................................................... 2
Selection Guide ................................................................ 2
Absolute Maximum Ratings................................................ 2
Recommended Operating Conditions .................................. 2
Thermal Characteristics..................................................... 2
Functional Block Diagram ..................................................... 3
Pinout Diagram and Terminal List........................................... 5
Electrical Characteristics....................................................... 6
Fault Table .......................................................................... 8
Functional Description .......................................................... 9
Overview ......................................................................... 9
PWM Control.................................................................... 9
Error Amplifier .................................................................. 9
Slope Compensation....................................................... 10
Internal Regulator ........................................................... 10
Enable and PWM Dimming .............................................. 10
Undervoltage Lockout (UVLO).......................................... 10
Startup and Shutdown ..................................................... 10
MOSFET Driver and Bootstrap Capacitor........................... 10
Frequency Dithering.........................................................11
Pulse-by-Pulse Current Limit.............................................11
Switch Overcurrent Protection and Hiccup Mode .................11
Secondary Switch Overcurrent Protection...........................11
BOOT Capacitor Protection...............................................11
Freewheeling Diode Protection..........................................11
Output Overcurrent Protection.......................................... 12
Output Overvoltage Protection.......................................... 12
Thermal Shutdown.......................................................... 12
Applications Information...................................................... 13
Setting the Switching Frequency....................................... 13
Setting the Output Voltage ............................................... 13
Inductor ......................................................................... 13
Freewheeling Diode ........................................................ 14
Input Capacitor............................................................... 14
Output Capacitor............................................................. 15
Compensation Components ............................................. 15
Design Example ............................................................. 18
Typical Application Schematics ............................................ 21
PCB Component Placement and Routing.............................. 22
Buck LED Driver ............................................................. 22
Buck-Boost LED Driver.................................................... 24
Application Circuit Examples ............................................... 26
Package Outline Drawing.................................................... 33
UVLO
Boot
BST
SW
Charge
VIN
Level
Off
EN
Shiꢀ
Delay
ON
Fault
LDO
VREG
Detect
BST
Level
FFn
Shiꢀ
ON PWM
-
+
Generator
FREQ
CS
Osc
-
+
COMP
VSS
18 V
Dither
Generator
0.2 V
GND
Figure 3: Functional Block Diagram
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
PINOUT DIAGRAM AND TERMINAL LIST
VIN
EN
1
2
3
4
5
10
9
BST
SW
FFn
8
PAD
CS
FREQ
GND
7
COMP
VSS
6
Package EJ Pinouts
Terminal List Table
Pin
Name
Pin
Number
Description
Power input for the control circuits and the drain of the internal high-side N-channel MOSFET. Connect this pin to a
power source. A high quality ceramic capacitor should be placed very close to this pin and GND.
VIN
EN
1
2
3
Input for Enable and PWM dimming; rated up to VIN and logic-level compatible.
Open-drain fault flag output which is pulled low in case of fault. Connect through an external pull-up resistor to the
desired level. This pin should be left open if not used.
FFn
Frequency setting pin. A resistor, RFREQ, from this pin to VSS sets the PWM switching frequency. See Table 2 to
FREQ
GND
4
determine the value of RFREQ
.
5
Enable and fault flag ground reference. Connect to input supply ground.
ALT80802 return. Connect to lowest circuit potential. This is input ground when configured as a buck converter
and should be connected to the GND pin. It is the negative output when configured as a buck-boost converter. See
typical application schematics for more detail.
VSS
6
Output of the error amplifier and compensation node for the current-mode control loop. Connect a series RC
network from this pin to VSS for loop compensation. See the Applications section of this datasheet for further
details.
COMP
CS
7
8
Feedback (negative) input to the error amplifier. Connect a resistor from this pin to VSS to program the output load
current.
The source of the internal MOSFET. The output inductor (LO) and cathode of the free-wheeling diode (D) should
be connected to this pin. LO and D should be placed as close as possible to this pin and connected with relatively
wide traces.
SW
9
Bootstrap capacitor connection. A 0.22 µF or higher capacitor is recommended between this pin and SW pin. The
voltage on this capacitor drives the internal MOSFET via the high side gate driver.
BST
10
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
ELECTRICAL CHARACTERISTICS [1]: Valid for VIN = 12 V, VEN = 2.5 V, VCOMP = 1.4 V, VSS = GND,
–40°C ≤ TJ ≤ 125°C, typical values at TJ = 25°C, unless otherwise specified
Characteristics
GENERAL SPECIFICATIONS
Operating Input Voltage
VIN UVLO Start
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VIN
VEN ≥ 2.5 V, VIN with respect to VSS
3.8
3.0
2.7
–
12
3.3
3.0
11
50
3.6
3.3
20
V
V
VIN(START) VIN rising, with respect to VSS
VIN UVLO Stop
VIN(STOP)
IQ(SLEEP)
VIN falling, with respect to VSS
V
Supply Quiescent Current [1]
PWM SWITCHING FREQUENCY
VEN = 0 V
µA
RFSET = 8.06 kΩ
1.8
360
–
2.0
400
±5
2.2
440
–
MHz
kHz
%
Switching Frequency
fSW
RFSET = 41.2 kΩ
Dither Frequency Sweep
Dither Modulation Frequency
THERMAL PROTECTION
Thermal Shutdown Threshold [2]
Thermal Shutdown Hysteresis [2]
PULSE-WIDTH MODULATION (PWM)
Minimum On-Time
∆fSW
fMOD
–
12
–
kHz
TTSD
THYS
TJ rising
–
–
170
20
–
–
°C
°C
tON(MIN)
–
–
80
100
–
ns
ns
Minimum Off-Time
tOFF(MIN)
100
INTERNAL MOSFET
MOSFET On Resistance
ERROR AMPLIFIER
RDS(on)
VBOOT-SW = 5 V, TJ = 25°C [2]
–
150
–
mΩ
Current Sense Voltage
VCS
ICS
3.8 V ≤ VIN ≤ 50 V, –40°C ≤ TJ ≤ 150°C
0.192
0.200
–
0.208
V
nA
Current Sense Pin Bias Current
Error Amplifier Voltage Gain
Error Amplifier Transconductance
–
–
–
–
–
100
–
AVOL
gm
1000
120
V/V
µA/V
µA
ICOMP = ±3 µA
–
Error Amplifier Min. Source Current [3] IEA(SOURCE) VCS = 0.1 V
Error Amplifier Min. Sink Current [3]
IEA(SINK) VCS = 0.3 V
–13.6
13.6
–
–
µA
[1] For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or
pin (sinking).
[2] Ensured by design and characterization; not production tested.
[3] Minimum source and sink current is the minimum current ensured to be provided when COMP demands maximum sink/source current.
Continued on next page...
5
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
ELECTRICAL CHARACTERISTICS [1] (continued): Valid for VIN = 12 V, VEN = 2.5 V, VCOMP = 1.4 V, VSS = GND,
–40°C ≤ TJ ≤ 125°C, typical values at TJ = 25°C, unless otherwise specified
Characteristics
CURRENT PROTECTION
Pulse-by-Pulse Switch Current Limit
Secondary Current Limit
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
ILIM
Duty cycle 0 to 85%
3.5
5.5
7.1
6.5
A
A
ILIM(SEC)
Hiccup after 2 counts
–
–
COMP to Current Sense
Transconductance [2]
GCS
–
9
–
A/V
Slope Compensation
Output Overcurrent
SE(2MHz)
VOCP
Measured at fSW = 2 MHz
–
–
3.1
–
–
A/µs
With respect to nominal VCS voltage
400
%
OVERVOLTAGE PROTECTION
Maximum Output Voltage
LOGIC ENABLE
VOVP
GND – VSS, when in buck-boost topology
16
18
20
V
EN Logic High Voltage
EN Logic Low Voltage
EN Hysteresis
VEN(H)
VEN(L)
VEN(HYS)
RENPN
VEN with respect to GND
VEN with respect to GND
1.8
–
–
–
–
0.4
–
V
V
–
100
80
mV
kΩ
EN Pin Pull-Down Resistance
VEN = 5 V
–
–
Measured while EN = low, during dimming
control, and internal references are powered-on
(exceeding tPWML results in shutdown)
Maximum PWM Dimming Off Time
tPWML
12
20
–
ms
FAULT PIN (FFn)
Fault Pull-Down Voltage
Fault Pin Leakage Current
Cooldown Timer for Fault Retry
VFFn(PD)
IFFn(LKG)
tRETRY
Fault condition asserted, pull-up current = 1 mA
Fault condition cleared, pull-up to 12 V
–
–
–
–
–
6
0.4
1
V
µA
ms
–
Delay Timer for Reporting
Open LED Fault
tOPEN
–
50
–
µs
[1] For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or
pin (sinking).
[2] Ensured by design and characterization, not production tested.
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
Table 1: Fault Table
Failure Mode
Fault Flag Protection
Symptom Observed
ALT80802 Response
Asserted?
Mode
Internal MOSFET switch is shorted. Current spike trips secondary current
limit after 2 counts. IC enters hiccup mode with 6 ms retry timer.
Inductor shorted
Dim light from LED
Yes
Hiccup
In buck topology, IC continues to switch at maximum tON (since this fault
cannot be distinguished from VIN too low for LED forward drop). Output
voltage, VOUT, increases until it reaches input voltage, VIN. Fault flag will
be asserted if current sense pin voltage, VCS, drops below 150 mV for
more than 50 µs.
In buck-boost topology, IC continues to switch at maximum tON. Output
voltage VOUT keeps increasing until it is clamped to VOVP. Fault flag will be
asserted if current sense pin voltage, VCS, drops below 150 mV for more
than 50 µs.
LED string open
No light from LED
No light from LED
Depends*
Clamp
VOUT will be regulated to current sense voltage VCS (200 mV typical), no
fault is detected.
LED string shorted
LED string
No
No
No
Some LEDs are not on
Dim light from LED
No light from LED
No
Normal operation, no fault is detected.
partially shorted
Detects missing diode fault and shuts off switching. IC enters hiccup
mode with 6 ms retry timer.
Diode open
Yes
Yes
Hiccup
Hiccup
Current spike trips SW secondary current limit. IC enters hiccup mode. IC
enters hiccup mode with 6 ms retry timer.
Diode shorted
IC unable to regulate LED current at VOUT = 0 V. Switch current increases
until it trips current limit protection. IC enters hiccup mode with 6 ms retry
timer.
Output capacitor
shorted
No light from LED
Yes
Hiccup
Output capacitor
open
LED may flicker
Depends
Yes
Depends LED current ripple increases.
Output overcurrent protection is triggered. IC enters hiccup mode with
Sense resistor open
No light from LED
Hiccup
6 ms retry timer.
Sense resistor
shorted
SW current increases, which eventually trips pulse-by-pulse SW current
limit. IC enters hiccup mode with 6 ms retry timer.
Dim light from LED
Dim light from LED
Dim light from LED
Yes*
Yes
Yes
Hiccup
No
FSET resistor open
Operates at 772 kHz switching frequency. May hit thermal limit.
Operates at 772 kHz switching frequency. May hit thermal limit.
FSET resistor
shorted
No
IC triggers missing Boot protection. IC enters hiccup mode with 6 ms retry
timer.
Boot capacitor open
Dim light from LED
No light from LED
Yes
Yes
Hiccup
Hiccup
Boot capacitor
shorted
IC triggers Boot shorted protection. IC enters hiccup mode with 6 ms retry
timer.
Note (*)
•
In case of LED current not in regulation, fault flag is asserted after approximately 50 μs timeout delay. In buck-boost topology, if binning resistors
are used, fault flag may not be asserted during an open LED fault.
•
If sense resistor is shorted with high resistance wire, protection may not be triggered.
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
FUNCTIONAL DESCRIPTION
If the current sense signal is lower than the error amplifier volt-
age for the entire PWM cycle, the PWM flip-flop will be reset
100 ns before the next PWM cycle. This maximum on-time
mode of operation means the regulator is in dropout region where
output cannot be regulated up to its target value. LED cannot be
turned on if output voltage cannot reach to its turn-on threshold.
Overview
The ALT80802 is a buck or buck-boost regulator that incorpo-
rates all the control and protection circuitry necessary to satisfy
a wide range of LED driver applications. The device employs
current-mode control to provide fast transient response, simple
compensation, and excellent stability.
In buck topology, the device will be in dropout region when:
The ALT80802 is designed to satisfy the most demanding auto-
motive applications. Extensive protection features prevent the
device and the external components from most of the common
fault conditions. Care was taken when defining the device pinout
to optimize protection against adjacent pin-to-pin short circuits
and pin-to-ground (VSS) short circuits.
Equation 3:
1
In buck-boost topology, the device will be in dropout region
when:
PWM Control
Equation 4:
A high-speed PWM comparator, with minimum on-time less than
100 ns, is included in the ALT80802. The inverting input of the
comparator is connected to the output of the error amplifier. The
non-inverting input is connected to the current sense signal.
1
where fSW is the switching frequency and tOFF(MAX) is the maxi-
mum on-time.
At the beginning of each PWM cycle, the clock signal sets the
PWM flip-flop and the internal power MOSFET is turned on.
When the current sense signal rises above the error amplifier
voltage (COMP pin voltage), the comparator resets the PWM
flip-flop and the high-side MOSFET is turned off.
It is recommended to keep VIN above dropout region to avoid
LED brightness change. ALT80802 does not support dropout
region operation with PWM dimming.
Error Amplifier
If current sense signal is still higher than the error amplifier volt-
age before the next clock on signal, the PWM flip-flop will not be
set and the next PWM cycle is skipped to prevent output over-
charged. This pulse-skipping mode of operation usually happens
at high input voltage and low output voltage when extremely
small duty cycle is required. Note that in pulse-skipping mode,
output ripple will be much higher.
The primary function of the transconductance error amplifier is to
regulate the voltage at the CS pin. By connecting a CS resistor in
series with the LED, output current is regulated. The negative input
of the error amplifier is connected to the CS pin, and the positive
input is connected to the internal reference voltage of 200 mV. The
voltage difference between the two inputs is amplified to charge or
discharge the compensation network connected to the COMP pin.
In buck topology, the device will start to pulse skip when:
To stabilize the regulator, a series RC compensation network (RZ-
CZ) must be connected from the error amplifier output (COMP
pin) to VSS as shown in the typical application schematic. In most
applications, an additional low-value capacitor (CP) should be con-
nected in parallel with the RZ-CZ compensation network to roll-off
the loop gain at higher frequencies. However, if the CP capacitor
is too large, the phase margin of the regulator may be reduced. In
most cases, a CP value of 39 pF or less is recommended.
Equation 1:
1
In buck-boost topology, the device will start to pulse skip when:
Equation 2:
1
The minimum COMP voltage is clamped to 750 mV and its
maximum is clamped to 1.5 V. COMP is internally pulled down
to VSS during hiccup mode.
where fSW is the switching frequency and tON(MIN) is the mini-
mum on-time.
8
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
be overcharged and an LED current spike will be seen. To reduce
this current spike, the ALT80802 incorporates an internal bleed-
ing circuit that will divert the extra current away from the LED
during the PWM dimming turn-off period.
Slope Compensation
The ALT80802 incorporates internal slope compensation (SE) to
allow PWM duty cycles above 50% for a wide range of input/
output voltages and inductor values. The slope compensation sig-
nal is added to the sum of the current sense amplifier output and
the PWM ramp offset. The amount of slope compensation scales
with the maximum on-time (1/fSW – tOFF(MIN)) centered around
3.1 A/μs at 2 MHz. The value of the output inductor should be
chosen such that SE is between 0.5× and 2× the down slope of the
inductor current (SLD).
If EN is low for more than tPWML, the IC enters shutdown mode
to reduce power consumption. The next high signal on EN will
initialize a full startup sequence before LED current starts to
build. Note that this startup sequence is not present during PWM
dimming operation.
The EN signal is referenced to the GND pin of the ALT80802. This
allows the user to use system-referenced signals to this pin even
when the output is configured as an inverting buck-boost regulator.
Internal Regulator
An internal series-pass regulator (LDO) generates around 2.9 V
for most of the internal circuits of the ALT80802. The power for
this LDO is derived from VIN. The LDO is in full regulation once
VIN is greater than 3.0 V.
Undervoltage Lockout (UVLO)
An undervoltage lockout (UVLO) comparator monitors the
voltage at the VIN pin (with reference to VSS) and keeps the
regulator disabled if the voltage is below the lockout threshold
(VIN(START)). The UVLO comparator incorporates enough hyster-
esis (VIN(HYS)) to prevent on/off cycling of the regulator due to IR
drops in the VIN path during heavy loading or during startup.
Enable and PWM Dimming
The enable (EN) input allows the system to selectively turn on/
off the ALT80802 control loop. The EN pin is rated to 55 V, so
the EN pin can be connected directly to VIN if there is no suit-
able logic signal available to wake up the regulator.
Startup and Shutdown
If both VIN and VEN are higher than their thresholds, the IC starts
up. The reference block starts first, generating stable reference
voltages and currents, and then the internal regulator is enabled.
The regulator provides stable supply for the remaining circuits.
An external logic signal can be applied to the EN pin to control
the on/off of LED current. Average brightness of the LED is
directly proportional to the duty cycle of the control signal. This
technique is commonly known as PWM dimming.
Three events can shut down the IC: EN low, VIN low, and thermal
shutdown. In the shutdown procedure, the power MOSFET is
turned off first to avoid any fault triggering. The COMP voltage
and the internal supply rail are then pulled down.
When the EN pin is forced from high to low, the power MOS-
FET and the error amplifier are turned off, but the IC remains
in standby mode for tPWML (20 ms typical) before it completely
shuts down. This delay allows PWM dimming frequency down
to 100 Hz. In standby mode, the COMP pin is disconnected from
the error amplifier and the COMP pin voltage stays at the level
before EN turns low. In this way, the steady-state control signal
is stored. When the IC receives another EN turn-on signal within
MOSFET Driver and Bootstrap Capacitor
The position of the internal N-channel power MOSFET requires
special consideration when driving it. The source of this MOS-
FET is connected to the SW node and its voltage can be either
close to VIN or VSS. For this reason, a floating gate charge driver
is required. This driver requires a voltage greater than VIN to
ensure the MOSFET can be turned on.
tPWML, the system immediately recovers to steady-state opera-
tion. As a result, ALT80802 allows down to 15 µs PWM dim-
ming on-time.
In buck-boost topology, the average inductor current is the sum
of the average input current and output current. When EN is
forced off during PWM dimming operation, the power MOS-
FET is turned off, cutting the connection from inductor to input
capacitor. The inductor current will dump all its energy in terms
of current to the output capacitor. This current is much higher
than the output current as it also contains the input current por-
tion in buck-boost topology. As a result, the output capacitor will
A simple charge pump—consisting of an internal charge circuit,
an external capacitor (BST capacitor), and the freewheeling diode
—is required to power the high-side gate driver. The internal
charge circuit is power by VIN. When the SW node is sufficiently
below VIN, the charge circuit will charge the BST capacitor to
around 5 V with respect to the SW node. This BST voltage is
used to turn the high-side MOSFET on. As the SW node rises, the
9
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Wide Input Voltage, Adjustable Frequency,
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ALT80802
BST capacitor will maintain the BST pin at 5 V above SW, ensur-
ing sufficient voltage to keep the MOSFET on.
Secondary Switch Overcurrent Protection
If the switch current continues to rise during the OC counting
period, a secondary switch current limit of 7.1 A can be reached
and the power MOSFET is turned off. If this secondary over-
current is detected for more than 1 clock cycle, the hiccup latch
is set immediately, and the part enters hiccup mode. This usually
happens when SW is shorted to VSS.
Also, the BST charge circuit incorporates its own UVLO of 1.8 V
rising and 0.4 V hysteresis. When BST voltage (with respect to
SW pin) is less than UVLO, the power MOSFET is turned off.
Frequency Dithering
The ALT80802 includes a dithering function, which changes the
switching frequency within a certain frequency range. By shift-
ing the switching frequency of the regulator in a triangle fashion
around the programmed switching frequency, the overall system
noise magnitude can be greatly reduced.
BOOT Capacitor Protection
The ALT80802 monitors the voltage across the BOOT capaci-
tor to detect if the capacitor is missing or short-circuited. If the
BOOT capacitor is missing, the device enters hiccup mode after 7
clock cycles. If the BOOT capacitor is shorted, the device enters
hiccup mode after 120 clock cycles. If BOOT capacitor voltage is
overcharged to more than 6.3 V, BOOT overvoltage protection is
triggered, and the IC enters hiccup mode after 7 PWM cycles.
The dithering sweep is internally set at ±5%. The switching
frequency will ramp from a low of 0.95 times the programmed
frequency to a high of 1.05 times the programmed frequency. The
rate or modulation at which the frequency sweeps is governed by
an internal 12 kHz triangle pattern.
Freewheeling Diode Protection
Pulse-by-Pulse Current Limit
If the freewheeling diode is missing or damaged (open), the SW
pin is subjected to unusually high negative voltages. This nega-
tive voltage may cause the device to malfunction and could lead
to damage. The ALT80802 includes protection circuitry to detect
when the freewheeling diode is missing. If the SW pin is below
−1.25 V for more than 50 ns, the device enters hiccup mode
after detecting one missing diode fault. Also, if the freewheeling
diode is shorted, the device experiences extremely high currents
through the high-side MOSFET. If this occurs, the device triggers
a secondary switch current limit and enters hiccup mode.
A high-bandwidth current sense amplifier monitors the current in
the power MOSFET. The current signal is supplied to the PWM
comparator and overcurrent comparator. If the MOSFET current
exceeds ILIM, the MOSFET will be turned off. This protects the
MOSFET from excessive current and possible damage.
Switch Overcurrent Protection
and Hiccup Mode
A switch overcurrent (OC) counter and hiccup mode circuit
protect the regulator when the output of the regulator is shorted
to VSS (shorting output capacitor) or when the load current is too
high (shorting CS resistor).
During a diode short-circuit fault in buck-boost topology, VIN is
directly connected to VSS pin when the power MOSFET turns
on. This might cause a voltage spike from VSS to GND. Note
that the maximum rating for GND is –0.3 V with respect to VSS.
If the VSS voltage spike is higher than GND, it may cause a logic
error in the IC. As a result, for buck-boost topology, a Schottky
diode must be connected between VSS to GND to clamp the volt-
age spike during this fault.
The OC counter is enabled and begin counting every clock cycle
when COMP pin voltage, VCOMP, is clamped at its maximum
voltage. If VCOMP remains at its maximum voltage, the counter
keeps counting pulses from the overcurrent comparator. If VCOMP
decreases, the OC counter is cleared. If the OC counter reaches
120 counts, a hiccup latch is set, and the part enters hiccup mode.
Note that the reverse breakdown voltage of the diode must be
higher than the maximum output voltage (18 V) and the current
rating should be higher than 500 mA.
In hiccup mode, the COMP pin is quickly pulled down by a rela-
tively low resistance (4 kΩ). Switching is halted for 6 ms to pro-
vide time for the device to cool down. The FFn pin is pulled low
to indicate a fault condition. After the hiccup off time expires, the
device begins a startup sequence. If the fault condition remains,
another hiccup cycle occurs. If the fault has been removed, the
device starts up normally and the output automatically recovers
to target value.
ALꢃꢄ0ꢄ0ꢅ
ꢀNꢁ
ꢂSS
Figure 4: VSS to GND Positive Clamp in Buck-Boost Applications
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Wide Input Voltage, Adjustable Frequency,
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ALT80802
Output Overcurrent Protection
10 ꢆΩ
100 Ω
ꢀN or PꢇM
ꢃimming
The ALT80802 provides an always-on output overcurrent protec-
tion that monitors CS pin voltage to protect against extremely
high LED current. If CS pin voltage, VCS, rises to 800 mV, the
device enters hiccup mode immediately.
ꢀN
NPN
ALT80802
ꢈnꢉꢊt
ꢂroꢊnd
Lꢀꢃꢋ
CꢄUꢅ
ꢂNꢃ
40.2 Ω
Output Overvoltage Protection in Buck-Boost
ꢁSS
ꢈC
ꢂroꢊnd
In buck-boost topology, during an open LED fault, output current
drops to zero and the control loop will try to compensate the loss
of current by demanding higher inductor current. Output voltage
across the capacitor is charged up immediately. In the ALT80802,
an 18 V Zener diode is placed between the positive output (GND)
to the negative input of the error amplifier. When output volt-
age rises to over 18 V, the negative input of the error amplifier
is charged up, forcing the inductor current to drop. In this way,
output voltage can be clamped to 18 V.
Figure 5: VSS to GND Positive Clamp
in Buck-Boost Applications
During an open LED fault, the CS pin voltage drops to zero and
the FFn pin will be pulled low if the CS pin voltage stays below
150 mV for more than 50 µs. Note that this undervoltage timer
is halted during the PWM dimming off period and will resume
when the next dimming cycle starts.
However, if the part starts up with an open LED fault, it may take
much longer time for the error amplifier to discharge the COMP
pin voltage. This delay time may cause the output voltage to rise
beyond 20 V, which is higher than the maximum rating for the IC.
If inductor current happens to be at a high level, a large current
may flow into the IC via the GND pin and the IC may be dam-
aged. To prevent any damage to the IC, it is suggested to use an
external circuit, as shown in Figure 5, to stop the switching event
before high current flows into the GND pin.
Thermal Shutdown
The ALT80802 protects itself from overheating by means of an
internal thermal monitoring circuit. If the junction temperature
exceeds the thermal shutdown threshold (TTSD, 170°C typical),
the COMP pin will be pulled to VSS and the power MOSFET
will be turned off. The ALT80802 will automatically restart when
the junction temperature decreases more than the thermal shut-
down hysteresis (THYS, 20°C typical).
11
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Wide Input Voltage, Adjustable Frequency,
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ALT80802
APPLICATIONS INFORMATION
mal foldback of the LED current or changing current based on
binning resistors.
Setting the Switching Frequency
The switching frequency (fSW) of a regulator using the ALT80802
Figure 6 shows the application schematic for adjusting LED cur-
rent based on binning resistors. In this schematic, R1 is in parallel
with R3 and RBIN. These 3 resistors combining with R2 form a
resistor divider that raises the voltage across the sense resistor.
can be set by connecting a resistor from the FREQ pin (RFREQ
to VSS. The recommended RFREQ value for various switching
frequencies can be obtained from Table 2:
)
Table 2: RFREQ vs. fSW
Lꢀꢁꢂ
Lꢀꢁꢂ
fSW (MHz)
2.5
RFREQ (kΩ)
6.34
9
U1
10
ꢄSꢎ
1
Lꢀꢁ1
Lꢀꢁꢃ
Lꢀꢁ3
R3
ꢄꢅN
ꢄꢅN
ꢍꢅN
Sꢆ
CS
ALꢎꢇ0ꢇ0ꢃ
2.0
8.06
ꢃ
3
ꢇ
ꢉ
ꢀN
1.8
8.87
RꢄꢅN
Lꢀꢁ-
R1
ꢊꢊn
1.5
10.7
CꢈMP
Lꢀꢁ-
ꢌ
Rꢃ
ꢊRꢀꢋ
1.0
16.2
ꢍSS
ꢏ
Rsense
ꢐNꢁ
5
0.8
20.5
0.5
33.2
0.4
41.2
Figure 6: Application Circuit Example
0.3
56.2
for Binning Resistors
0.2
84.5
The regulated voltage across RSENSE can be calculated with the
following equation:
0.2
619
Equation 7:
RFREQ resistor can also be calculated with following equation:
Equation 5:
Output current can be calculated with the following equation:
Equation 8:
where RFREQ is in kΩ and fSW is in MHz.
While the ALT80802 can switch at frequencies up to 2.5 MHz,
care must be taken when operating at higher frequencies. The
minimum controllable on-time for the ALT80802 is around 80 ns.
This means that at higher frequencies, high input voltages, and
low output voltages, pulse skipping may be seen.
In this way, the regulated output current can be tuned by chang-
ing RBIN. Note that the purpose of R3 is to filter potential high
frequency noise coming from the long LED string cable.
Inductor
Setting the Output Voltage
To ensure that the inductor operates in continuous mode, the
value of the inductor should be set such that half of the peak-to-
peak inductor current is not greater than the average inductor cur-
rent. In buck topology, the average inductor current is the average
output current. In buck-boost topology, the average inductor
current is the sum of average input current and output current.
A resistor (RSENSE) from the CS pin to VSS sets the output current.
The output current can be calculated with following equation:
Equation 6:
As a result, for buck regulators, the following must be guaranteed:
Equation 9:
The bias current of the CS is sufficiently low that is allows for a
series resistor between RSENSE and CS pin. This resistor allows
the user to perform analog dimming. This can be useful for ther-
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Wide Input Voltage, Adjustable Frequency,
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For buck-boost regulators, the following must be guaranteed:
Equation 10:
For buck regulators, the peak inductor current can be calculated by:
Equation 16:
For buck-boost regulators, the peak inductor current can be calcu-
lated by:
where Dmin is the minimum duty cycle at maximum input voltage.
To avoid subharmonic oscillation in the current-mode controlled
regulators when duty cycle is greater than 50%, the inductor
value should be set to match the slope compensation value at the
designed frequency.
Equation 17:
Slope compensation (SE) will vary with switching frequency.
SE can be calculated with the following equation:
The saturation current of the inductor should be higher than the
pulse-by-pulse current limit of the IC (5.5 A typical).
Equation 11:
Freewheeling Diode
The freewheeling diode allows the current in the inductor to flow to
the load when the high-side switch is off. To reduce losses due to the
diode forward voltage and recovery times, use a Schottky diode.
where SE is in A/µs and fSW is in MHz. The typical value of
SE(2MHz) is 3.1 A/µs.
In buck topology, the voltage rating of the diode must be higher
than the maximum input voltage. The average current rating of
the diode must be higher than maximum output current. In buck-
boost topology, the voltage rating of the diode must be higher
than the maximum sum of input voltage and output voltage. The
average current rating of the diode must be higher than maximum
sum of output current and input current. Note that the peak cur-
rent of the diode is the peak inductor current.
For a stable system, the following is recommended:
Equation 12:
where SLD is the down slope of the inductor. For buck or buck-
boost regulators:
If the application requires PWM dimming, it is recommended to
choose a diode with low reverse current IR. During PWM dim-
ming off period, output capacitor voltage is discharged mostly by
the reverse current of the diode, especially at high temperature. A
smaller IR helps to reduce voltage drop of the output capacitor.
Equation 13:
where L is the inductor value in µH.
As a result, the following must be guaranteed:
Equation 14:
Input Capacitor
Three factors should be considered when choosing the input
capacitors. First, they must be chosen to support the maximum
expected input voltage with adequate design margin.
The recommended inductor value based on SE can be calculated
using the following equation:
Second, their RMS current rating must be higher than the
expected RMS input current to the regulator. For simplification,
choose the input capacitor with an RMS current rating greater
than half of the load current. Generally, a MLCC capacitor can
provide enough RMS current with low heat generation.
Equation 15:
where Dmax is the maximum duty cycle at minimum input voltage.
Third, they must have enough capacitance and a low enough ESR
to limit the input voltage dv/dt to much less than the hysteresis of
the VIN pin UVLO circuitry (350 mV (typ)) at maximum loading
and minimum input voltage.
The current rating of the inductor should be higher than the peak
current during operation.
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The input capacitor(s) must limit the voltage deviations at the
Equation 21:
VIN pin to something significantly less than the ALT80802 VIN
pin UVLO hysteresis during maximum load and minimum input
voltage.
where ∆IL is the peak-to-peak inductor current, ILPK is the peak
inductor current.
For buck regulators, the minimum input capacitance can be
calculated as:
To reduce the overall output ripple, it is recommended to use
ceramic output capacitors, especially for buck-boost regulators.
The ESR and ESL of the ceramic capacitors are virtually zero.
Equation 18:
If ceramic output capacitors are used, for buck regulators, calculate:
Equation 22:
For buck-boost regulators, the minimum input capacitance can be
calculated as:
Equation 19:
For buck-boost regulators, calculate:
Equation 23:
where ΔVIN is the output capacitor voltage deviation, η is the
estimated efficiency of the regulator. ΔVIN should be chosen to be
much less than the hysteresis of the VIN pin, UVLO comparator
(ΔVIN ≤ 100 mV is recommended).
In general, for 2 MHz applications, a 1 µF ceramic output capaci-
tor with X7R dielectric is sufficient.
Note that the DC bias on the capacitor can derate the capacitance
value. For example, a 50 V, 4.7 µF rated ceramic capacitor can be
less than 3 µF when 30 V DC bias is applied. Capacitance value
can also change due to temperature. X7R capacitors are recom-
mended for low capacitance variation over temperature.
Compensation Components
The ALT80802 employs current-mode control for easy compen-
sation and fast transient response. The system stability and tran-
sient response are controlled through the COMP pin. The COMP
pin is the output of the internal transconductance error amplifier.
A series capacitor-resistor combination sets a pole-zero pair to
control the characteristics of the control system.
In general, for 2 MHz applications, a 4.7 µF ceramic capacitor
with X7R dielectric is sufficient.
Output Capacitor
The output capacitors filter the output voltage to provide an
acceptable level of ripple voltage, and they store energy to help
maintain voltage regulation during a transient event. The voltage
rating of the output capacitors must support the output voltage
with sufficient design margin.
ꢀꢁꢂꢃꢄ
ꢅꢆꢇꢈꢃ
ꢂꢃUꢄ
ꢅc
ꢀCS
CꢃUꢄ
ꢉꢄꢄꢁꢄ
Aꢊꢋꢌꢍꢎꢍꢃꢄ
ꢅꢆꢇꢈꢃ
The output voltage ripple (ΔVOUT) is a function of the output
capacitor parameters: COUT, ESR, and ESL.
CS
CꢃMP
gm
RSꢁNSꢁ
For buck regulators, the output voltage ripple can be calculated by:
Equation 20:
Rꢆ
Cꢆ
CP
Rꢃ
0.ꢇ ꢅ
For buck-boost regulators, the output voltage ripple can be calcu-
lated by:
Figure 7: Basic Current-Mode Control Schematic
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Wide Input Voltage, Adjustable Frequency,
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ALT80802
The objective of the selection of compensation components is to
ensure a high DC gain and wide bandwidth for optimal small-
signal transient response, and adequate margin to avoid instabil-
ity. As an LED driver or current regulator, output current is the
controlled target.
dꢉ
1500
1ꢀ00
1000
ꢁ00
The small-signal loop can be modeled as shown in Figure 7,
where the loop is broken into two blocks: power stage and error
amplifier stage.
ꢄꢅ ꢆmAꢇ
di
ꢂ00
The power stage includes an inner current loop of the current-
mode controller, COUT and LED load. Although the peak inductor
current is being controlled, to a first approximation for simplify-
ꢃ00
ing the equations, it is acceptable to use the output current IOUT
.
ꢀ00
ꢀ.ꢃ ꢀ.ꢂ ꢀ.ꢁ 3.0 3.ꢀ 3.ꢃ 3.ꢂ
ꢈꢅ ꢆꢈꢇ
The error amplifier stage includes a current sense resistor
RSENSE, an error amplifier, and compensation components.
Figure 8: Typical I-V Curve of a White LED
Compensation Design for Buck Regulators
The power stage DC gain can be calculated as:
Equation 24:
There is also a zero in the power stage formed by the ESR of the
output capacitor. However, if ceramic capacitors are used, this
zero can be ignored.
For the error amplifier stage, the DC gain of the amplifier is
1000 V/V, and the transconductance gm value is 120 µA/V. The
effective output impedance of the error amplifier RO can be given
as:
where GCS is the current sense gain of the current amplifier. The
typical value of GCS is 9 A/V.
Equation 27:
The output capacitor integrates the ripple current through the
inductor, effectively forming a single pole with the output load.
The pole fP(ps) can be found at:
1000
MΩ
Equation 25:
The DC gain of the error amplifier is high enough to ensure good
output current regulation. The gain is rolled off with a single
pole formed by the output impedance of the amplifier RO and the
capacitor CZ connected to the COMP pin. The position of this
pole is:
1
where RLED is the effective resistance for the LED when conduct-
ing target output current IOUT. The small signal LED resistance
can be calculated as:
Equation 28:
1
Equation 26:
A zero is positioned at a higher frequency to cancel the effects of
the power stage pole. This zero can be found at:
Note that this dv and di can be found by the I-V curve of the
LED. For example, if the target output current is 700 mA, dV and
dI are set around that level as shown in Figure 8.
Equation 29:
1
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A second pole is needed to suppressed high-frequency noise. It
Equation 32:
should be placed far away from the crossover frequency to have
minimal effect on the control. This pole can be found at:
where D is the duty cycle, and GCS is 9 A/V.
The power stage pole can be calculated as:
Equation 33:
Equation 30:
1
The current sense resistor introduces a DC gain for the control
loop, which can be calculated as:
where RLED is the effective resistance for the LED.
Equation 31:
The power stage also includes a right half plane zero, which
frequency can be calculated as:
Overall loop response is the combination of the power stage and
error amplifier stage. This feedback loop should be designed to
have a suitable crossover frequency and phase margin.
Equation 34:
where L is the inductor in the power stage.
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢈꢃ
ꢀain
dꢁ
Recommended Control Loop Design Strategy
ꢏꢐꢃꢄꢇꢌꢌ Lꢁꢁꢋ
1. Choose a crossover frequency fC to be 1/10 of the switching
frequency fSW. However, the maximum fC should be set be-
low 75 kHz to have good noise suppression. For buck-boost
regulators, cross-over frequency should be less than 1/5 of
the right half plane zero frequency.
ꢀain
dꢁ
ꢂPꢃꢄsꢅ
ꢋꢇ0 dꢁꢌdecade
ꢀain
dꢁ
2. Calculate DC gain of the overall loop in dB, which is:
GLOOP(dB) = GPS(dB) + gm(dB) + GFB(dB)
ꢂC
ꢈreꢉꢊency
3. The estimated –20 dB/decade roll-off slew rate from the first
amplifier pole to the crossover frequency will set the position
of the pole fP1(ea). Calculate the CZ value.
ꢂP1ꢃeaꢅ
ꢂꢆꢃeaꢅ
ꢈreꢉꢊency
ꢂPꢇꢃeaꢅ
ꢉꢄꢄꢁꢄ Aꢊꢋꢌꢍꢎꢍꢃꢄ ꢅꢆꢇꢈꢃ
4. Calculate the position of the power stage pole fP(ps)
.
Figure 9: Basic Current-Mode Control Schematic
5. Set the error amplifier zero fZ(ea) to be at the same frequency
of the power stage pole. Calculate the RZ value. If the power
stage pole fP(ps) is significantly higher than the crossover
frequency (more than 5×), RZ can be removed. However, RZ
is helpful in instant transient response.
It is recommended to achieve a –20 dB/decade roll-off for the over-
all loop, which means that the error amplifier zero should be placed
at the same frequency of the power stage pole. Figure 9 shows rec-
ommended gain plot of the power stage, the error amplifier stage,
and the combined overall loop response.
6. Set the high frequency error amplifier pole to be higher than
the error amplifier zero and calculate the CP value. Typically,
choose a CP value between 22 pF and 39 pF.
Compensation Design for Buck-Boost Regulators
The compensation design for buck-boost regulators follows the
same idea as the buck. The error amplifier stage of the buck-
boost regulators is the same as the buck. The only difference is
the power stage response.
7. If possible, test the overall loop bode plot of the system.
Adjust the RZ and CZ to fine-tune the control loop crossover
frequency and phase margin. Typically, phase margin should
be more than 45 degrees to guarantee stability.
The power stage DC gain of buck-boost regulators can be calcu-
lated as:
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can be calculated as:
Equation 39:
Design Example
Buck LED Driver
This example application is a buck LED driver using the
ALT80802. The operating voltage range is 9 to 18 V, nominal
input voltage is 12 V, and the target switching frequency is
The power stage DC gain can be calculated as:
2 MHz; the output load is 2 white LEDs (LUW CQAR) with 3 V
forward voltage; target output current is 700 mA.
Equation 40:
To set the output current to 700 mA, current sense resistor
RSENSE is:
The current sense DC gain is:
Equation 41:
Equation 35:
The DC gain of the error amplifier is 1000 V/V.
The overall loop gain can be calculated as:
Equation 42:
Note that 280 mΩ is the common resistor value with 1% accu-
racy. As a result, 280 mΩ is chosen.
The nominal duty cycle can be calculated as:
Equation 36:
6
12
with estimated –20 dB/decade roll-off slew, the position of the
first amplifier pole can be calculated as:
To guarantee CCM operation over all input range, inductor L
must satisfy:
Equation 43:
40 kHz
Equation 37:
10
The CZ value can be calculated as:
Equation 44:
A 3.3 µH inductor can be selected. The down slope of the induc-
tor can be calculated as:
1
1
Equation 38:
⁄
To match the standard capacitor value, a 1.5 nF CZ can be selected.
The power stage pole can be calculated as:
Equation 45:
3.1
1.82
1
1
The slope compensation to inductor down slope ratio is within
the range of 0.5 to 2. As a result, the slope compensation should
have little influence on the overall loop response.
This power stage pole is at much higher frequency than the
designed crossover frequency. As a result, RZ is not needed. How-
ever, to improve the instant response, a 2.49 kΩ resistor is selected.
Input capacitors and output capacitors are selected to the standard
values of 4.7 µF and 1 µF.
For CP, a typical value of 22 pF can be chosen to suppress high
frequency noise.
For a 2 MHz design, the maximum crossover frequency should
be set below 75 kHz. The crossover frequency can be set to
40 kHz in this application.
If PWM binning applications, the binning circuit resistors and
binning resistor selected by the design tools.
From LUW CQAR datasheet, the small signal LED resistance
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Wide Input Voltage, Adjustable Frequency,
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ALT80802
Equation 50:
Buck-Boost LED Driver
This example application is a buck-boost LED driver using the
ALT80802. The operating voltage range is 6 to 18 V, nominal
input voltage is 12 V, and the target switching frequency is
The right half plane zero of buck-boost regulators can be calcu-
2 MHz; the output load is 4 white LEDs (LUW CQAR) with 3 V
forward voltage; target output current is 350 mA.
lated as:
Equation 51:
To set the output current to 700 mA, current sense resistor
RSENSE is:
Equation 46:
As a result, the crossover frequency can be set at 20 kHz.
The power stage DC gain can be calculated as:
Equation 52:
Note that 560 mΩ is the common resistor value with 1% accu-
racy. As a result, 560 mΩ is chosen. The nominal output current
with 560 mΩ is 357 mA.
0.5
1.5
The nominal duty cycle can be calculated as:
Equation 47:
The current sense DC gain is:
Equation 53:
To guarantee CCM operation over all input range, inductor L
must satisfy:
The DC gain of the error amplifier is 1000 V/V.
The overall loop gain can be calculated as:
Equation 54:
Equation 48:
With estimated –20 dB/decade roll-off slew, the position of the
first amplifier pole can be calculated as:
To reduce the output ripple, a 4.7 µH inductor can be selected.
The down slope of the inductor can be calculated as:
Equation 55:
Equation 49:
20 kHz
⁄
10
3.1
The CZ value can be calculated as:
Equation 56:
2.55
1
1
The slope compensation to inductor down slope ratio is within
the range of 0.5 to 2. As a result, the slope compensation should
have little influence on the overall loop response.
To match the standard capacitor value, a 1.5 nF CZ can be selected.
The power stage pole can be calculated as:
Equation 57:
Input capacitors and output capacitors are selected to be the stan-
dard values of 4.7 µF and 1 µF.
As a buck-boost regulator, crossover frequency should be less
than 1/5 of the right half plane zero.
From the LUW CQAR datasheet, the small signal LED resistance
can be calculated as:
18
Allegro MicroSystems, LLC
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Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
This power stage pole is at much higher frequency than the
designed crossover frequency. As a result, RZ is not needed.
However, to improve the instant response, a 2.49 kΩ resistor is
selected.
For CP, a typical value of 22 pF can be chosen to suppress high
frequency noise.
For PWM binning applications, the binning circuit resistors and
binning resistor can be selected by the design tools.
To improve the EMI/EMC performance, a 100 nF capacitor
should be placed between VIN and VSS to supply the Boot
capacitor during boot charging transients. Note that this capaci-
tor cannot be too large, or it will affect the output stability during
VIN transients.
19
Allegro MicroSystems, LLC
955 Perimeter Road
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Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
TYPICAL APPLICATION SCHEMATICS
Cꢌ
ꢈꢈ0 nꢒ
U1
ꢖSꢗ
ꢄꢁN
L1
Lꢎꢀꢐ
ꢄꢁN
Sꢆ
3.3 ꢍH
ALT80802
ꢎNꢚPꢆM
Lꢎꢀꢏ
ꢎN
CS
Lꢎꢀꢐ
ꢒꢒn
ꢒꢒn
ꢀ1
CꢑMP
Lꢎꢀ1
ꢒRꢎꢓ
ꢘNꢀ
Rꢌ
0.28 Ω
C1
ꢌ.ꢕ ꢍꢒ
C3
100 nꢒ
Cꢈ
100 nꢒ
Cꢕ
1.0 ꢍꢒ
Cꢅ
100 nꢒ
Rꢈ
10 kΩ
C5
1.5 nꢒ
ꢄSS
Lꢎꢀꢈ
Lꢎꢀꢏ
Cꢔ
ꢈꢈ ꢂꢒ
R1
8.06 kΩ
ꢎꢙꢗ
ꢇ5 ꢄ Sꢃꢂꢂlyꢊ
R3
2.49 kΩ
Lꢎꢀ MꢑꢀULꢎ
ꢈ ꢆhite Lꢎꢀs
ꢇꢄꢛ ꢜ 3.05 ꢄꢊ
ꢘNꢀ
ꢀC ꢁnꢂꢃt ꢄoltage Range
PꢆM ꢀimming Range ꢇꢈ00 Hꢉꢊ
9-1ꢅ ꢄ
1ꢋ-100ꢋ
Figure 10: 2 MHz, 700 mA, 2 LEDs Buck LED Driver with Fault Flag and PWM Dimming
C1
ꢄꢁN
ꢘNꢀ
Cꢉ
ꢍ.ꢎ ꢏꢔ
Cꢍ
L1
100 nꢔ
Lꢐꢀ ꢒ
ꢐꢙꢗ
ꢍ.ꢎ ꢏH
ꢈ5 ꢄ Sꢃꢂꢂly ꢋ
ꢉꢉ0 nꢔ
Cꢎ
0.ꢍꢎ ꢏꢔ
Cꢆ
100 nꢔ
ꢀ1
U1
R3
10 kΩ
Lꢐꢀ ꢒ
ꢖSꢗ
ꢄꢁN
Sꢇ
Lꢐꢀ 1
ALT80802
ꢔꢔn
ꢔꢔn
Lꢐꢀ ꢑ
CS
Lꢐꢀ ꢉ
ꢔRꢐꢕ
CꢓMP
ꢐNꢚPꢇM
Lꢐꢀ 3
Lꢐꢀ ꢍ
ꢐN
C3
100 nꢔ
R5
10 kΩ
C5
1.5 nꢔ
Rꢍ
0.56 Ω
ꢄSS
ꢘNꢀ
R1
ꢆ.0ꢅ kΩ
ꢀꢉ
Cꢅ
ꢉꢉ ꢂꢔ
Lꢐꢀ ꢑ
Rꢉ
ꢉ.ꢍ9 kΩ
NPN
Sꢃggested Circꢃit
Lꢐꢀ MꢓꢀULꢐ
ꢉ ꢇhite Lꢐꢀs
ꢈꢄꢛ ꢝ 3.05 ꢄꢋ
ꢛor ꢓꢂen Lꢐꢀ ꢔaꢃlt
dꢃring Startꢃꢂ ꢐꢜent
Rꢅ
40.2 Ω
Rꢎ
100 Ω
ꢀC ꢁnꢂꢃt ꢄoltage Range
PꢇM ꢀimming Range ꢈꢉ00 Hꢊꢋ
ꢅ-1ꢆ ꢄ
1ꢌ-100ꢌ
Figure 11: 2 MHz, 350 mA, 4 LEDs Inverting Buck-Boost LED Driver with Fault Flag and PWM Dimming
20
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Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
PCB COMPONENT PLACEMENT AND ROUTING
loop should be less than 300 mA, and the trace width should
be set accordingly.
Buck LED Driver
A good PCB layout is critical for the ALT80802 to provide clean,
stable output voltages. Figure 12 shows a typical ALT80802-based
buck LED driver schematic with the critical power paths/loops.
Figure 13 shows an example PCB component placement and
routing with the same critical power paths/loops as shown in the
schematic. Follow these guidelines to ensure a good PCB layout.
3. A 100 nF capacitor, C3, from VIN to GND provides a solid
ground reference for the input of the internal LDO. This
capacitor should be placed close to VIN pin and VSS pin of
the IC.
4. VSS and GND pins should be tied together with a single
solid ground plane. Note that to ensure the lowest junction
temperature, multiple vias are recommended to connect the
thermal pad to the bottom layer ground plane.
1. The high di/dt pulsating current loop for a buck regulator is
formed by the ceramic input capacitor (C1 and C2), power
MOSFET inside of the IC, and freewheeling diode (D1).
These components must be closely placed with wide traces
and the loop area must be minimized. Ideally, these compo-
nents are all connected using only the top metal layer.
5. Compensation components, FSET resistor, and current sense
resistors should be connected close to the IC with clean
ground reference.
6. SW node is a high dv/dt node. This high dv/dt copper area
should be minimized to reduce any voltage coupling to the
other layers.
2. Another pulsating current loop is the boot charging path
which includes the input capacitor (C1 and C2), boot charge
capacitor (C4), and freewheeling diode. The current of this
Cꢁ
ꢀꢀ0 nꢋ
U1
2
ꢑSꢒ
ꢇꢈN
L1
Lꢄꢂꢆ
ꢇꢈN
Sꢉ
3.3 ꢃH
ALT80802
ꢀ
ꢄNꢘPꢉM
Lꢄꢂꢅ
ꢄN
CS
Lꢄꢂꢆ
ꢋꢋn
ꢋꢋn
ꢂ1
CꢊMP
Lꢄꢂ1
Rꢁ
0.ꢀ8 Ω
ꢋRꢄꢌ
C1
C3
Cꢀ
Cꢐ
1.0 ꢃꢋ
Cꢏ
100 nꢋ
Rꢀ
10 kΩ
C5
1.5nꢋ
ꢁ.ꢐ ꢃꢋ 100 nꢋ 100 nꢋ
ꢓNꢂ
ꢇSS
Lꢄꢂꢀ
Lꢄꢂ-
R1
8.06 kΩ
Cꢎ
ꢀꢀ ꢍꢋ
ꢄꢔꢒ
ꢕ5 ꢇ Sꢖꢍꢍlyꢗ
R3
ꢀ.ꢁ9 kΩ
Lꢄꢂ MꢊꢂULꢄ
ꢀ ꢉhite Lꢄꢂs
ꢕꢇꢙ ꢚ 3.05 ꢇꢗ
ꢓNꢂ
Figure 12: Typical Buck LED Driver Application with Critical Loops Shown
21
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Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
LOOP 1 (RED)
LOOP 2 (BLUE)
This loop contains the main switching frequency pulsating cur-
rent during operation. The loop area should be minimized to
reduce the loop inductance and noise antenna size.
This loop contains pulsating current when the Boot capacitor is
charged. The frequency of this pulsating current can also be as
high as the switching frequency. The loop area should be mini-
mized.
The turn-on and turn-off of the power MOSFET will generate
high di/dt transients. Parasitic inductance within this loop will
cause oscillation during these transients. Also, the peak current in
this loop can be as high as 5.5 A. It is recommended to use short
and wide traces to reduce the parasitic inductance and resistance.
1
ꢀ
Figure 13: Example PCB Layout for Buck LED Driver Application
22
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Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
ceramic capacitor should be connected as close as possible to
the IC.
Buck-Boost LED Driver
Figure 14 shows a typical ALT80802-based buck-boost LED
driver schematic with the critical power paths/loops. Figure 15
shows an example PCB component placement and routing with
the same critical power paths/loops as shown in the schematic.
Follow the following guidelines to ensure a good PCB layout.
3. The solid ground reference for the IC is VSS instead of GND.
In buck topology, these two pins should be tied together with
a single solid ground plane. In buck-boost topology, these
two pins are completely separated. The ground plane on the
PCB should be tied to VSS pin and thermal pad of the IC.
Note that to ensure the lowest junction temperature, multiple
vias are recommended to connect the thermal pad to the bot-
tom layer ground plane.
1. The high di/dt pulsating current loop for a buck-boost regula-
tor is formed by the ceramic input capacitor (C1 and C2),
power MOSFET inside of the IC, freewheeling diode (D1),
and the ceramic output capacitor (C7 and C8). These compo-
nents need to be placed closely with wide traces and the loop
area needs to be minimized. Ideally, these components are all
connected using only the top metal layer.
4. Compensation components, FSET resistor, and current sense
resistors should be connected close to the IC with clean
ground reference.
5. The clamping diode from VSS to GND should be connected
close to these two pins.
2. Another pulsating current loop is the boot charging path
which includes the VIN to VSS ceramic capacitor (C3), boot
charge capacitor, and freewheeling diode. The current of this
loop should be less than 300 mA, and the trace width should
be set accordingly. The boot capacitor and the VIN to VSS
6. SW node is a high dv/dt node. This high dv/dt copper area
should be minimized to reduce any voltage coupling to the
other layers.
C1
ꢊꢋN
ꢓNꢄ
ꢃ.ꢅ ꢆꢎ
Cꢂ
100 nꢎ
Cꢃ
L1
Lꢇꢄꢉ
ꢀ
ꢃ.ꢅ ꢆH
ꢂꢂ0 nꢎ
Cꢀ
Cꢅ
ꢄ1
U1
100 nꢎ 0.ꢃꢅ ꢆꢎ
Lꢇꢄꢉ
ꢑSꢒ
ꢊꢋN
Sꢌ
Lꢇꢄ1
ALT80802
ꢇNꢘPꢌM
Lꢇꢄꢈ
ꢇN
CS
Lꢇꢄꢂ
ꢎꢎn
ꢎꢎn
CꢍMP
Lꢇꢄ3
Lꢇꢄꢃ
R3
10 kΩ
ꢎRꢇꢏ
ꢓNꢄ
C3
100 nꢎ
C5
1.5 nꢎ
Rꢃ
0.56 Ω
ꢊSS
R1
ꢀ.0ꢁ kΩ
Lꢇꢄꢈ
Cꢁ
ꢂꢂ ꢐꢎ
ꢇꢔꢒ
ꢕ5 ꢊ Sꢖꢐꢐlyꢗ
Rꢂ
ꢄꢂ
Lꢇꢄ MꢍꢄULꢇ
ꢃ ꢌhite Lꢇꢄs
2
2.49 kΩ
ꢕꢊꢙ ꢚ 3.05 ꢊꢗ
Figure 14: Typical Buck-Boost LED Driver Application with Critical Loops Shown
23
Allegro MicroSystems, LLC
955 Perimeter Road
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Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
LOOP 1 (RED)
LOOP 2 (BLUE)
This loop contains the main switching frequency pulsating cur-
rent during operation. The loop area should be minimized to
reduce the loop inductance and noise antenna size.
This loop contains pulsating current when the Boot capacitor is
charged. The frequency of this pulsating current can also be as
high as the switching frequency. The loop area should be mini-
mized.
The turn-on and turn-off of the power MOSFET will generate
high di/dt transients. Parasitic inductance within this loop will
cause oscillation during these transients. Also, the peak current in
this loop can be as high as 5.5 A. It is recommended to use short
and wide traces to reduce the parasitic inductance and resistance.
1
ꢀ
c
Figure 15: Example PCB Layout for Buck-Boost LED Driver Application
24
Allegro MicroSystems, LLC
955 Perimeter Road
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Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
APPLICATION CIRCUIT EXAMPLES
Application 1: CHMSL with 10 Red LEDs
C1
ꢊꢍN
ꢛNꢁ
C3
ꢆ.ꢈ ꢖꢗ
Cꢆ
100 nꢗ
Lꢀꢁꢂ
L1
Lꢀꢁꢂ
ꢀꢜꢚ
ꢑ5 ꢊ Sꢏꢎꢎlyꢓ
ꢆ.ꢈ ꢖH
ꢃꢃ0 nꢗ
Lꢀꢁ1
Lꢀꢁ3
Lꢀꢁ5
Lꢀꢁꢃ
Lꢀꢁꢆ
Lꢀꢁꢇ
Cꢈ
1 ꢖꢗ
Cꢉ
100 nꢗ
ꢁ1
U1
ꢙSꢚ
Rꢃ
10 ꢕΩ
ꢊꢍN
Sꢐ
ALT80802
ꢗꢗn
ꢗꢗn
Lꢀꢁꢄ
CS
Lꢀꢁ MꢅꢁULꢀ
10 Red Lꢀꢁs
ꢊꢋ ꢌ ꢃ.3ꢃ ꢊ
ꢗRꢀꢘ
CꢅMP
ꢀNꢝPꢐM
ꢀN
Cꢃ
100 nꢗ
C5
1.5 nꢗ
R5
10 ꢕΩ
Rꢆ
0.ꢆ Ω
ꢊSS
ꢛNꢁ
Lꢀꢁꢈ
Lꢀꢁ9
Lꢀꢁꢉ
ꢁꢃ
Cꢇ
ꢃꢃ ꢎꢗ
R1
ꢉ.0ꢇ ꢕΩ
R3
ꢃ.ꢆ9 ꢕΩ
ꢘ1
Lꢀꢁ10
Sꢏggested Circꢏit
ꢋor ꢅꢎen Lꢀꢁ
ꢗaꢏlt dꢏring
Rꢇ
40.2 Ω
Rꢈ
100 Ω
Lꢀꢁꢄ
Startꢏꢎ ꢀꢞent
ꢁC ꢍnꢎꢏt ꢊoltage Range
ꢇ-1ꢉ ꢊ
1ꢔ-100ꢔ
PꢐM ꢁimming Range ꢑꢃ00 Hꢒꢓ
Figure 16: 2 MHz, 250 mA, 10 Red LEDs Inverting Buck-Boost LED Driver with Fault Flag
Application 1: Recommended Bill of Materials
Reference
Description
Manufacturer/Part Number
C1
C2, C3, C8
C4
4.7 µF, ceramic capacitor, X7R, 50 V, 1210
100 nF, ceramic capacitor, X7R, 50 V, 0603
220 nF, ceramic capacitor, X7R, 16 V, 0402 or 0603
1.5 nF, ceramic capacitor, X7R, 16 V, 0603
22 pF, ceramic capacitor, X7R, 16 V, 0603
1 µF, ceramic capacitor, X7R, 50 V, 0805
8.06 kΩ resistor, 1/10 W, 1%
C5
C6
C7
R1
R2
10 kΩ resistor, 1/10 W, 1%
R3
2.49 kΩ resistor, 1/10 W, 1%
R4
400 mΩ resistor, 1/2 W, 1%
R6
40.2 Ω resistor, 1/10 W, 1%
R7
100 Ω resistor, 1/10 W, 1%
D1
Diode, Schottky, 60 V, 5 A, 670 mV @ 5 A
Diode, Schottky, 40 V, 1 A, 410 mV @ 1 A
Transistor, NPN, 65 V, 0.1 A, SOT23
Inductor, 4.7 µH, 9.8 A(sat), 15.32 mΩ (max)
Diodes Incorporated, PDS560-13
Diodes Incorporated, 1N5819HW-7-F
On Semiconductor, BC846ALT1G
Vishay, IHLP4040DZER4R7M8A
D2
Q1
L1
25
Allegro MicroSystems, LLC
955 Perimeter Road
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Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
Application 1: Performance
System Efficiency with Full Brightness
LED Current Line Regula�on
Switching Waveform
SW 10V/div
ILED 200mA/div
Time: 500ns/div
Startup Waveform
10% LED Dimming Waveform
6-18 V Fast VIN Transient
VIN 5V/div
VIN 5V/div
200mA/div
EN 5V/div
VIN 5V/div
ILED 200mA/div
Time: 500µs/div
Time: 1ms/div
ILED 200mA/div
Time: 5ms/div
26
Allegro MicroSystems, LLC
955 Perimeter Road
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Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
Application 2: Buck-Boost LED Driver with Binning Resistor
C1
ꢋꢌN
Cꢃ
ꢄ.ꢆ ꢇꢏ
100 nꢏ
Cꢄ
Lꢈꢅꢊ
L1
ꢄ.ꢆ ꢇH
ꢃꢃ0 nꢏ
Cꢆ
0.ꢄꢆ ꢇꢏ
Cꢀ
100 nꢏ
ꢅ1
U1
ꢑSꢓ
C3
100 nꢏ
Rꢄ
ꢑꢌN
ꢋꢌN
Sꢍ
ALT80802
ꢏꢏn
1ꢃ0 Ω
Lꢈꢅꢊ
CS
R5
1 ꢂΩ
ꢏRꢈꢐ
CꢎMP
ꢋSS
Lꢈꢅ1
ꢈNꢔPꢍM
ꢑꢌN
ꢈN
Lꢈꢅꢉ
R3
ꢃ ꢂΩ
Rꢆ
10 ꢂΩ
C5
1.5 nꢏ
Lꢈꢅꢃ
ꢕNꢅ
R1
ꢀ.0ꢁ ꢂΩ
ꢅꢃ
RꢑꢌN
Cꢁ
ꢃꢃ ꢒꢏ
Lꢈꢅ3
Lꢈꢅꢄ
Rꢁ
Rꢃ
ꢃ.ꢄ9 ꢂΩ
Sꢖggested Circꢖit
ꢗor ꢎꢒen Lꢈꢅ
ꢏaꢖlt dꢖring
ꢐ1
0.ꢀꢃ Ω
Lꢈꢅꢉ
Rꢀ
40.2 Ω
R9
Startꢖꢒ ꢈꢘent
100 Ω
Lꢈꢅ MꢎꢅULꢈ
ꢄ ꢍhite Lꢈꢅs
ꢙꢋꢗ ꢚ 3.05 ꢋꢛ
ꢌnꢒꢖt Range
PꢍM ꢅimming Range ꢙꢃ00 Hꢜꢛ
ꢁ-1ꢀ ꢋ
1ꢝ-100ꢝ
ꢑinning resistor ꢘalꢖes ꢗor Lꢈꢅ cꢖrrent redꢖctionꢞ
Lꢈꢅ Cꢖrrent
RꢑꢌN
100ꢝ
90ꢝ
ꢀ0ꢝ
ꢆ0ꢝ
Open
2.21 kΩ
549 Ω
Short
Figure 17: 2 MHz, 350 mA Inverting Buck-Boost LED Driver for 1-4 LEDs with Binning Resistor on LED Module
Application 2: Recommended Bill of Materials
Reference
Description
Manufacturer/Part Number
C1
C2, C3, C8
C4
4.7 µF, ceramic capacitor, X7R, 50 V, 1210
100 nF, ceramic capacitor, X7R, 50 V, 0603
220 nF, ceramic capacitor, X7R, 16 V, 0402 or 0603
1.5 nF, ceramic capacitor, X7R, 16 V, 0603
22 pF, ceramic capacitor, X7R, 16 V, 0603
1 µF, ceramic capacitor, X7R, 50 V, 0805
8.06 kΩ resistor, 1/10 W, 1%
C5
C6
C7
R1
R2
2.49 kΩ resistor, 1/10 W, 1%
R3
2 kΩ resistor, 1/10 W, 1%
27
Allegro MicroSystems, LLC
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Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
Application 2: Recommended Bill of Materials (continued)
Reference
Description
Manufacturer/Part Number
R4
R5
R6
R7
R8
D1
D2
Q1
L1
120 Ω resistor, 1/10 W, 1%
120 Ω resistor, 1/10 W, 1%
820 mΩ resistor, 1/2 W, 1%
10 kΩ resistor, 1/10 W, 1%
40.2 Ω resistor, 1/10 W, 1%
Diode, Schottky, 60 V, 5 A, 670 mV @ 5 A
Diode, Schottky, 40 V, 1 A, 410 mV @ 1 A
Transistor, NPN, 65 V, 0.1 A, SOT23
Inductor, 4.7 µH, 9.8 A(sat), 15.32 mΩ (max)
Diodes Incorporated, PDS560-13
Diodes Incorporated, 1N5819HW-7-F
On Semiconductor, BC846ALT1G
Vishay, IHLP4040DZER4R7M8A
Application 2: Performance
System Efficiency with Full Brightness
LED Current Line Regula�on
Switching Waveform
SW 10V/div
ILED 200mA/div
Time: 500ns/div
Startup Waveform
10% LED Dimming Waveform
6-18 V Fast VIN Transient
VIN 5V/div
VIN 5V/div
EN 5V/div
VIN 5V/div
ILED 200mA/div
200mA/div
Time: 500µs/div
Time: 5ms/div
ILED 200mA/div
Time: 1ms/div
28
Allegro MicroSystems, LLC
955 Perimeter Road
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www.allegromicro.com
Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
Application 3: High Input Voltage Buck with 8 White LEDs
C5
ꢌꢌ0 nꢊ
U1
ꢐSꢑ
ꢆꢇN
L1
Lꢄꢁꢅ
Lꢄꢁꢅ
ꢆꢇN
Sꢈ
CS
ꢀꢂ ꢃH
ALT80802
ꢄN
ꢄNꢗPꢈM
Lꢄꢁ1
Lꢄꢁ-
ꢊꢊn
ꢊꢊn
ꢁ1
CꢉMP
ꢊRꢄꢋ
ꢒNꢁ
C1
Cꢌ
C3
Cꢀ
100 nꢊ
Rꢀ
0.56 Ω
Cꢏ
ꢀ.ꢂ ꢃꢊ
C9
100 nꢊ
Rꢌ
10 kΩ
Cꢍ
ꢀ.ꢂ nꢊ
ꢀ.ꢂ ꢃꢊ ꢀ.ꢂ ꢃꢊ 100 nꢊ
ꢆSS
Lꢄꢁꢏ
Lꢄꢁ-
R1
41.2 kΩ
Cꢂ
ꢌꢌ ꢎꢊ
ꢄꢓꢑ
ꢔ5 ꢆ Sꢕꢎꢎlyꢖ
R3
3.24 kΩ
Lꢄꢁ MꢉꢁULꢄ
ꢏ ꢈhite Lꢄꢁs
ꢔꢆꢘ ꢙ 3.05 ꢆꢖ
ꢒNꢁ
ꢇnꢎꢕt Range
ꢌꢏ-3ꢍ ꢆ
PꢈM ꢁimming Range ꢔꢌ00 Hꢚꢖ
5ꢛ-100ꢛ
Figure 18: 32 VIN, 400 kHz, 350 mA, 8 White LEDs Buck LED Driver with Fault Flag
Application 3: Recommended Bill of Materials
Reference
Description
Manufacturer/Part Number
C1, C2, C8
4.7 µF, ceramic capacitor, X7R, 50 V, 1210
100 nF, ceramic capacitor, X7R, 50 V, 0603
220 nF, ceramic capacitor, X7R, 16 V, 0402 or 0603
4.7 nF, ceramic capacitor, X7R, 16 V, 0603
22 pF, ceramic capacitor, X7R, 16 V, 0603
41.2 kΩ resistor, 1/10 W, 1%
C3, C4, C9
C5
C6
C7
R1
R2
R3
R4
D1
L1
10 kΩ resistor, 1/10 W, 1%
3.24 kΩ resistor, 1/10 W, 1%
560 mΩ resistor, 1/4 W, 1%
Diode, Schottky, 60 V, 5 A, 670 mV @ 5 A
Inductor, 47 µH, >5 A(sat)
Diodes Incorporated, PDS560-13
29
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
Application 3: Performance
System Efficiency with Full Brightness
LED Current Line Regula�on
Switching Waveform
SW 10V/div
ILED 200mA/div
Time: 2µs/div
Startup Waveform
20% LED Dimming Waveform
6-18 V Fast VIN Transient
VIN 10V/div
EN 5V/div
VIN 5V/div
200mA/div
EN 2V/div
ILED 200mA/div
ILED 200mA/div
Time: 500µs/div
Time: 500µs/div
Time: 2ms/div
30
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
Current Sense Block with NTC and Binning Resistor Example
Lꢀꢁꢃ
Lꢀꢁꢃ
9
U1
ꢄSꢏ
R3
30.1 Ω
1
10
ꢈ
ꢄꢅN
ꢄꢅN
CS
ꢎꢅN
Sꢇ
Lꢀꢁ1
ALT80802
ꢆ
3
ꢀN
CS
Lꢀꢁꢆ
Lꢀꢁ3
CS
RꢄꢅN
ꢋꢋn
R1
1.58 kΩ
ꢊ
NꢏC
Lꢀꢁꢂ
CꢉMP
ꢍ
ꢋRꢀꢌ
Lꢀꢁꢂ
ꢎSS
ꢐ
ꢑNꢁ
5
Rꢆ
1.0 kΩ
NꢏCꢒ ꢍꢊ kΩ
ꢄ5ꢊ35ꢆꢎ5ꢍꢊ3H0ꢐ0
Rsense
1.ꢍ7 Ω
ꢄinning resistor ꢓalꢔes ꢕor Lꢀꢁ cꢔrrent redꢔction
BIN1
100%
Open
BIN2
90%
BIN3
80%
LED Current
RBIN
8.06 kΩ
3.24 kΩ
Figure 19: 350 mA Inverting Buck-Boost LED Driver with Binning Resistor on LED Module
31
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference JEDEC MO-229)
Dimensions in millimeters – NOT TO SCALE
Exact case and lead configuration at supplier discretion within limits shown
0.30
0.50
3.00 0.05
10
10
0.85
3.00 0.05
3.10
1.64
A
1
2
1
DETAIL A
2.38
D
C
10X
0.75 0.05
0.05
C
C PCB Layout Reference View
SEATING
PLANE
0.25 0.05
0.40 0.10
0.05
0.00
0.5 BSC
0.40 0.10
0.203 REF
0.08 REF
1
2
0.05 REF
1.65 0.10
Detail A
B
0.05 REF
Terminal #1 mark area
A
B
C
Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion)
10
Reference land pattern layout (reference IPC7351 SON50P300X300X80-11WEED3M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet
application process requirements and PCB layout tolerances; when mounting on a
multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
2.38 0.10
Coplanarity includes exposed thermal pad and terminals
D
Figure 20: Package EJ, 10-Pin DFN with Exposed Thermal Pad and Wettable Flank
32
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Wide Input Voltage, Adjustable Frequency,
Buck or Buck-Boost 2 Amp LED Driver
ALT80802
Revision History
Number
Date
Description
–
September 10, 2018 Initial release
Copyright ©2018, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
33
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
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