A3982SLBTR-T [ALLEGRO]
Stepper Motor Controller, 2A, NMOS, PDSO24, LEAD FREE, MS-013AD, SOIC-24;
| 型号： | A3982SLBTR-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Stepper Motor Controller, 2A, NMOS, PDSO24, LEAD FREE, MS-013AD, SOIC-24 驱动器 转换器 电机 |
| 文件： | 总11页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A3982
DMOS Stepper Motor Driver with Translator
Features and Benefits
▪ Low RDS(on) outputs
Description
The A3982 is a complete stepper motor driver with built-
▪ Automatic current decay mode detection/selection
▪ Mixed and Slow current decay modes
▪ Synchronous rectification for low power dissipation
▪ Internal UVLO and thermal shutdown circuitry
▪ Crossover-current protection
in translator for easy operation. It is designed to operate
bipolar stepper motors in full- and half-step modes, with an
output drive capacity of up to 35 V and ±2 A. The A3982
includes a fixed off-time current regulator which has the
ability to operate in Slow or Mixed decay modes.
The translator is the key to the easy implementation of the
A3982. Simply inputting one pulse on the STEP input drives
the motor one step. There are no phase sequence tables, high
frequency control lines, or complex interfaces to program.
The A3982 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.
The chopping control in the A3982 automatically selects
the current decay mode (Slow or Mixed). When a signal
occurs at the STEP input pin, the A3982 determines if
that step results in a higher or lower current in each of the
motor phases. If the change is to a higher current, then the
decay mode is set to Slow decay. If the change is to a lower
current, then the current decay is set to Mixed (set initially
to a fast decay for a period amounting to 31.25% of the
Package: 24 pin SOICW with internally
fused leads (suffix LB)
Continued on the next page…
Not to scale
Pin-out Diagram
OUT1A
SENSE1
VBB1
OUT1B
DIR
OUT2A
SENSE2
VBB2
1
2
24
23
22
21
20
19
18
17
16
15
14
13
3
OUT2B
ENABLE
PGND
PGND
CP1
4
5
PGND
PGND
REF
6
7
8
CP2
STEP
VDD
9
VCP
10
11
12
VREG
MS1
ROSC
RESET
26184.28C
A3982
DMOS Stepper Motor Driver with Translator
Description (continued)
fixed off-time, then to a slow decay for the remainder of the
Internal circuit protection includes: thermal shutdown with
hysteresis, undervoltage lockout (UVLO), and crossover-current
protection. Special power-on sequencing is not required.
off-time). This current decay control scheme results in reduced
audible motor noise, increased step accuracy, and reduced power
dissipation.
The A3982 is supplied in a 24-pin wide-body SOIC
(package LB) with internally-fused power ground leads for
enhanced thermal dissipation. It is lead (Pb) free, with 100%
matte tin plated leadframe.
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation.
Selection Guide
Part Number
Packing*
Package
A3982SLB-T
31 pieces per tube
24-pin Wide SOIC with pins 6 and 7, and 18
and 19, fused internally
A3982SLBTR-T
1000 pieces per reel
*Contact Allegro for additional packing options
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
35
Units
Load Supply Voltage
VBB
VIN
V
V
V
V
Logic Input Voltage
Sense Voltage
–0.3 to 7
0.5
VSENSE
VREF
Reference Voltage
4
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under
any set of conditions, do not exceed the specified
current rating or a junction temperature of 150°C.
Output Current
IOUT
±2
A
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
TA
TJ(max)
Tstg
Range S
–20 to 85
150
ºC
ºC
ºC
–55 to 150
Allegro MicroSystems, Inc.
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3982
DMOS Stepper Motor Driver with Translator
Functional Block Diagram
0.1 μF
0.22 μF
CP1
CP2
VREG
ROSC
VDD
REF
Current
Regulator
Charge
Pump
OSC
VCP
0.1 μF
DMOS Full Bridge
VBB1
DAC
Translator
DAC
OUT1A
OUT1B
PWM Latch
Blanking
Mixed Decay
SENSE1
VBB2
STEP
DIR
Gate
Drive
RS1
DMOS Full Bridge
RESET
MS1
Control
Logic
OUT2A
OUT2B
PWM Latch
Blanking
Mixed Decay
ENABLE
SENSE2
RS2
VREF
Allegro MicroSystems, Inc.
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3982
DMOS Stepper Motor Driver with Translator
ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)
2
Characteristics
Output Drivers
Symbol
Test Conditions
Min.
Max.
Units
Typ.
Load Supply Voltage Range
Logic Supply Voltage Range
VBB
VDD
Operating
8
3.0
–
–
–
35
5.5
0.460
0.380
1.2
1.2
4
V
V
Operating
Source Driver, IOUT = –1.5 A
Sink Driver, IOUT = 1.5 A
Source Diode, IF = –1.5 A
Sink Diode, IF = 1.5 A
fPWM < 50 kHz
0.370
Ω
Output On Resistance
Body Diode Forward Voltage
Motor Supply Current
RDSON
VF
–
0.330
Ω
–
–
–
–
–
–
–
V
–
V
–
mA
mA
mA
mA
IBB
Operating, outputs disabled
fPWM < 50 kHz
–
2
–
8
Logic Supply Current
IDD
Outputs off
–
5
Control Logic
VIN(1)
–
–
V
VDD×0.7
–
Logic Input Voltage
Logic Input Current
VIN(0)
IIN(1)
IIN(0)
–
V
VDD×0.3
–20
<1.0
<1.0
20
μA
μA
VIN = VDD×0.7
VIN = VDD×0.3
–20
20
Input Hysteresis
Blank Time
VHYS(IN)
tBLANK
150
0.7
20
23
0
300
1
500
1.3
40
37
4
mV
ꢀs
ꢀs
ꢀs
V
OSC > 3 V
30
30
–
Fixed Off-Time
tOFF
ROSC = 25 kΩ
Reference Input Voltage Range
Reference Input Current
VREF
IREF
–3
–
0
3
ꢀA
%
VREF = 2 V, %ITripMAX = 70.71%
VREF = 2 V, %ITripMAX = 100.00%
–
±5
±5
800
Current Trip-Level Error3
errI
tDT
–
–
%
Crossover Dead Time
Protection
100
475
ns
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
TJ
–
165
15
–
–
3
–
°C
°C
V
TJHYS
UVLO
UVHYS
–
VDD rising
2.35
0.05
2.7
0.10
V
1
2
Negative current is defined as coming out of (sourcing from) the specified device pin.
Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
3errI = (ITrip – IProg) ⁄ IProg, where IProg = %ITripMAX
I
.
×
TripMAX
Allegro MicroSystems, Inc.
115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3982
DMOS Stepper Motor Driver with Translator
THERMAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions*
Value Units
One-layer PCB, one-sided with copper limited to solder pads
77 ºC/W
One-layer PCB, two-sided with copper limited to solder pads and
3.57 in.2 of copper area on each side, connected to PGND pins
RθJA
Package Thermal Resistance
45 ºC/W
35 ºC/W
Four-layer PCB, based on JEDEC standard
*Additional thermal information available on Allegro Web site.
Power Dissipation versus Ambient Temperature
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0
20
40
60
80
100
120
140
160
Temperature, T (°C)
A
Allegro MicroSystems, Inc.
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3982
DMOS Stepper Motor Driver with Translator
t
t
B
A
STEP
t
t
D
C
MS1,
RESET, or DIR
Time Duration
Symbol
Typ.
1
Unit
ꢀs
STEP minimum, HIGH pulse width
STEP minimum, LOW pulse width
Setup time, input change to STEP
Hold time, input change to STEP
tA
tB
tC
tD
1
ꢀs
200
200
ns
ns
Figure 1. Logic Interface Timing Diagram
Table 1. Stepping Resolution Truth Table
MS1
Step Resolution
Full Step
Half Step
Excitation Mode
L
2 Phase
H
1-2 Phase
Allegro MicroSystems, Inc.
115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3982
DMOS Stepper Motor Driver with Translator
Functional Description
Device Operation. The A3982 is a complete stepper
motor driver with a built-in translator for easy operation
increment is determined by input MS1, as shown in table 1.
Direction Input (DIR). This determines the direction of
rotation of the motor. When low, the direction will be clock-
wise and when high, counterclockwise. Changes to this input
do not take effect until the next STEP rising edge.
with minimal control lines. It is designed to operate bipolar
stepper motors in full- and half-step modes. The currents in
each of the two output full-bridges and all of the N-channel
DMOS FETs are regulated with fixed off-time PMW (pulse
width modulated) control circuitry. At each step, the current
for each full-bridge is set by the value of its external current-
sense resistor (RS1 or RS2), a reference voltage (VREF), and
the output voltage of its DAC (which in turn is controlled by
the output of the translator).
Internal PWM Current Control. Each full-bridge is
controlled by a fixed off-time PWM current control circuit
that limits the load current to a desired value, ITRIP. Ini-
tially, a diagonal pair of source and sink DMOS outputs are
enabled and current flows through the motor winding and
the current sense resistor, RSx. When the voltage across RSx
equals the DAC output voltage, the current sense compara-
tor resets the PWM latch. The latch then turns off either the
source DMOS FET (when in Slow Decay Mode) or the sink
and source DMOS FETs (when in Mixed Decay Mode).
At power-on or reset, the translator sets the DACs and the
phase current polarity to the initial Home state (shown in
figures 2 and 3), and the current regulator to Mixed Decay
Mode for both phases. When a step command signal occurs
on the STEP input, the translator automatically sequences
the DACs to the next level and current polarity. (See table 2
for the current-level sequence.) The step resolution is set by
input MS1, as shown in table 1.
The maximum value of current limiting is set by the selec-
tion of RSx and the voltage at the VREF pin. The transcon-
ductance function is approximated by the maximum value of
current limiting, ITripMAX (A), which is set by
When stepping, if the new output levels of the DACs are
lower than their previous output levels, then the decay mode
for the active full-bridge is set to Mixed. If the new output
levels of the DACs are higher than or equal to their previous
levels, then the decay mode for the active full-bridge is set to
Slow. This automatic current decay selection improves step-
ping performance by reducing the distortion of the current
waveform that results from the back EMF of the motor.
I
TripMAX = VREF /(8 R )
×
S
where RS is the resistance of the sense resistor (Ω) and VREF
is the input voltage on the REF pin (V).
The DAC output reduces the VREF output to the current
sense comparator in precise steps, such that
I
trip = (%ITripMAX /100)
I
TripMAX
RESET Input (RESET). The RESET input sets the
translator to a predefined Home state (shown in figures 2
and 3), and turns off all of the DMOS outputs. All STEP
inputs are ignored until the RESET input is set to high.
×
(See table 2 for %ITripMAX at each step.)
It is critical that the maximum rating (0.5 V) on the SENSE1
and SENSE2 pins is not exceeded.
Step Input (STEP). A low-to-high transition on the STEP
input sequences the translator and advances the motor one
increment. The translator controls the input to the DACs and
Fixed Off-Time. The internal PWM current control cir-
cuitry uses a one-shot circuit to control the duration of time
the direction of current flow in each winding. The size of the that the DMOS FETs remain off. The one shot off-time, tOFF
,
Allegro MicroSystems, Inc.
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3982
DMOS Stepper Motor Driver with Translator
is determined by the selection of an external resistor con-
nected from the ROSC timing pin to ground. If the ROSC
pin is tied to an external voltage > 3 V, then tOFF defaults to
30 μs. The ROSC pin can be safely connected to the VDD
pin for this purpose. The value of tOFF (μs) is approximately
Enable Input (ENABLE). This input turns on or off all
of the DMOS outputs. When set to a logic high, the outputs
are disabled. When set to a logic low, the internal control
enables the outputs as required. The translator inputs STEP,
DIR, and MS1, as well as the internal sequencing logic, all
remain active, independent of the ENABLE input state.
tOFF ≈ ROSC ⁄ 825
Shutdown. In the event of a fault, overtemperature
(excess TJ) or an undervoltage (on VCP), the DMOS out-
puts of the A3982 are disabled until the fault condition is
removed. At power-on, the UVLO (undervoltage lockout)
circuit disables the DMOS outputs and resets the translator
to the Home state.
Blanking. This function blanks the output of the current
sense comparators when the outputs are switched by the
internal current control circuitry. The comparator outputs
are blanked to prevent false overcurrent detection due to
reverse recovery currents of the clamp diodes, and switching
transients related to the capacitance of the load. The blank
time, tBLANK (μs), is approximately
Mixed Decay Operation. The bridge can operate in
Mixed Decay Mode, depending on the step sequence, as
shown in figures 3 thru 5. As the trip point is reached, the
A3982 initially goes into a fast decay mode for 31.25%
of the off-time, tOFF. After that, it switches to Slow Decay
tBLANK ≈ 1 μs
Charge Pump (CP1 and CP2). The charge pump is
used to generate a gate supply greater than that of VBB
for driving the source-side DMOS gates. A 0.1 μF ceramic
capacitor, should be connected between CP1 and CP2. In
addition, a 0.1 μF ceramic capacitor is required between
VCP and VBB, to act as a reservoir for operating the
high-side DMOS gates.
Mode for the remainder of tOFF
.
Synchronous Rectification. When a PWM-off cycle
is triggered by an internal fixed–off-time cycle, load current
recirculates according to the decay mode selected by the
control logic. This synchronous rectification feature turns on
the appropriate FETs during current decay, and effectively
shorts out the body diodes with the low DMOS RDSON. This
reduces power dissipation significantly, and can eliminate
the need for external Schottky diodes in many applications.
Turning off synchronous rectification prevents the reversal of
the load current when a zero-current level is detected.
VREG (VREG). This internally-generated voltage is
used to operate the sink-side DMOS outputs. The VREG
pin must be decoupled with a 0.22 μF ceramic capacitor to
ground. VREG is internally monitored. In the case of a fault
condition, the DMOS outputs of the A3982 are disabled.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3982
DMOS Stepper Motor Driver with Translator
STEP
STEP
100.00
100.00
70.71
70.71
Slow
Mixed
Slow
Mixed
Slow
Mixed
Slow
Phase 1
IOUT1A
Phase 1
IOUT1A
0.00
0.00
Direction = H
(%)
Direction = H
(%)
–70.71
–70.71
–100.00
100.00
70.71
–100.00
100.00
70.71
Slow
Slow
Mixed
Slow
Mixed
Slow
Mixed
Phase 2
Phase 2
IOUT2A
IOUT2A
0.00
0.00
Direction = H
(%)
Direction = H
(%)
Slow
–70.71
–70.71
–100.00
–100.00
Figure 2. Decay Mode for Full-Step Increments
Figure 3. Decay Modes for Half-Step Increments
Table 2. Step Sequencing Settings
Home step position at Step Angle 45º; DIR = H
Phase 1
Current
tripMax
(%)
Phase 2
Current
tripMax
(%)
Full
Half
Step
Angle
(º)
Step Step [% I
#
]
[% I
]
#
1
100.00
70.71
0.00
0.00
70.71
0.0
1
2
3
4
5
6
7
8
45.0
100.00
70.71
90.0
2
3
4
–70.71
–100.00
–70.71
0.00
135.0
180.0
225.0
270.0
315.0
0.00
–70.71
–100.00
–70.71
70.71
Allegro MicroSystems, Inc.
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3982
DMOS Stepper Motor Driver with Translator
Pin List Table
Name
Description
Number
1
OUT2A DMOS Full Bridge 2 Output A
SENSE2 Sense resistor for Bridge 2
2
VBB2
Load supply
3
OUT2B DMOS Full Bridge 2 Output B
ENABLE Logic input
4
5
PGND
PGND
CP1
Power ground
6
Power ground
7
Charge pump capacitor 1
Charge pump capacitor 2
Reservoir capacitor
Regulator decoupling
Logic input
8
CP2
9
VCP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VREG
MS1
RESET Logic input
ROSC
VDD
Timing set
Logic supply
STEP
REF
Logic input
Current trip reference voltage input
PGND
PGND
DIR
Power ground
Power ground
Logic input
1OUT1B DMOS Full Bridge 1 Output B
VBB1 Load supply
SENSE1 Sense resistor for Bridge 1
OUT1A DMOS Full Bridge 1 Output A
Allegro MicroSystems, Inc.
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A3982
DMOS Stepper Motor Driver with Translator
LB Package, 24-Pin Wide Body SOIC
15.40±0.20
4° ±4
24
24
+0.07
–0.06
2.20
0.27
10.30±0.33
7.50±0.10
9.60
A
2
+0.44
–0.43
0.84
0.25
1
1
2
0.65
1.27
PCB Layout Reference View
B
24X
C
SEATING PLANE
GAUGE PLANE
SEATING
PLANE
0.10
C
0.41 ±0.10
1.27
2.65 MAX
0.20 ±0.10
For reference only
Pins 6 and 7, and 18 and 19 internally fused
Dimensions in millimeters
(Reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Terminal #1 mark area
A
B
Reference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Copyright ©2005-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
相关型号：
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