A3983SLP-T [ALLEGRO]
DMOS Microstepping Driver with Translator; DMOS细分驱动器与翻译
| 型号： | A3983SLP-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | DMOS Microstepping Driver with Translator |
| 文件： | 总13页 (文件大小：329K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A3983
DMOS Microstepping Driver with Translator
The A3983 is a complete microstepping motor driver with built-in
translator for easy operation. It is designed to operate bipolar stepper
motors in full-, half-, quarter-, and eighth-step modes, with an output
Package LP
drive capacity of up to 35 V and ±2 A. The A3983 includes a fixed off-
time current regulator which has the ability to operate in Slow or Mixed
decay modes.
GND
CP1
CP2
1
2
24
23
22
21
20
19
18
17
16
15
14
13
ENABLE
OUT2B
VBB2
The translator is the key to the easy implementation of the A3983.
Simply inputting one pulse on the STEP input drives the motor one
microstep. There are no phase sequence tables, high frequency control
lines, or complex interfaces to program. The A3983 interface is an ideal
fit for applications where a complex microprocessor is unavailable or is
overburdened.
VCP
3
VREG
MS1
4
SENSE2
OUT2A
OUT1A
SENSE1
VBB1
5
MS2
6
RESET
ROSC
SLEEP
VDD
7
8
The chopping control in the A3983 automatically selects the current
decay mode (Slow or Mixed). When a signal occurs at the STEP input
pin, the A3983 determines if that step results in a higher or lower
current in each of the motor phases. If the change is to a higher current,
then the decay mode is set to Slow decay. If the change is to a lower
current, then the current decay is set to Mixed (set initially to a fast
decay for a period amounting to 31.25% of the fixed off-time, then
to a slow decay for the remainder of the off-time). This current decay
control scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.
9
OUT1B
DIR
10
11
12
STEP
REF
GND
Approximate Scale 1:1
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation.
Internal circuit protection includes: thermal shutdown with hysteresis,
undervoltage lockout (UVLO), and crossover-current protection.
Special power-on sequencing is not required.
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage,VBB ...................................35 V
Output Current, IOUT.........................................±2 A*
Logic Input Voltage, VIN ..................... –0.3 V to 7 V
Sense Voltage, VSENSE .......................................0.5 V
Reference Voltage, VREF ………..........................4 V
Operating Temperature Range
Ambient, TA ................................. –20°C to 85°C
Junction Temperature, TJ(MAX).....................150°C
Storage Temperature, TS .................... –55°C to 150°C
*Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specified current
rating or a junction temperature of 150°C.
The A3983 is supplied in a low-profile (1.2 mm maximum), 24-pin
TSSOP with exposed thermal pad (package LP). It is also available
in a lead (Pb) free version (suffix –T), with 100% matte tin plated
leadframes.
FEATURES
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Low RDS(ON) outputs
Automatic current decay mode detection/selection
Mixed and Slow current decay modes
Synchronous rectification for low power dissipation
Internal UVLO and thermal shutdown circuitry
Crossover-current protection
Use the following complete part number when ordering:
Part Number Pb-free
Package
Description
A3983SLP
–
24-pin, TSSOP
Exposed thermal pad
A3983SLP-T
Yes
26184.29A
A3983
DMOS Microstepping Driver with Translator
Functional Block Diagram
0.1 μF
0.22 μF
CP1
CP2
VREG
ROSC
VDD
REF
Current
Regulator
Charge
Pump
OSC
VCP
0.1 μF
DMOS Full Bridge
VBB1
DAC
Translator
DAC
OUT1A
OUT1B
PWM Latch
Blanking
Mixed Decay
SENSE1
VBB2
STEP
DIR
Gate
Drive
RS1
DMOS Full Bridge
RESET
Control
Logic
MS1
MS2
OUT2A
OUT2B
PWM Latch
Blanking
Mixed Decay
ENABLE
SLEEP
SENSE2
RS2
VREF
Allegro MicroSystems, Inc.
2
115 Northeast Cutoff, Box 15036
26184.29A
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A3983
DMOS Microstepping Driver with Translator
ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)
2
Characteristics
Output Drivers
Symbol
Test Conditions
Min.
Max.
Units
Typ.
Operating
8
0
–
–
–
35
35
V
V
Load Supply Voltage Range
Logic Supply Voltage Range
Output On Resistance
VBB
VDD
During Sleep Mode
Operating
3.0
–
5.5
0.450
0.370
1.2
1.2
4
V
Source Driver, IOUT = –1.5 A
Sink Driver, IOUT = 1.5 A
Source Diode, IF = –1.5 A
Sink Diode, IF = 1.5 A
fPWM < 50 kHz
0.350
Ω
RDSON
–
0.300
Ω
–
–
–
–
–
–
–
–
–
V
Body Diode Forward Voltage
Motor Supply Current
VF
–
V
–
mA
mA
μA
mA
mA
μA
IBB
Operating, outputs disabled
Sleep Mode
–
2
–
10
fPWM < 50 kHz
–
8
Logic Supply Current
IDD
Outputs off
–
5
Sleep Mode
–
10
Control Logic
VIN(1)
–
–
V
VDD×0.7
–
Logic Input Voltage
VIN(0)
IIN(1)
IIN(0)
–
V
VDD×0.3
–20
<1.0
<1.0
20
μA
μA
VIN = VDD×0.7
VIN = VDD×0.3
Logic Input Current
–20
20
Microstep Select 2
Input Hysteresis
Blank Time
MS2
VHYS(IN)
tBLANK
–
150
0.7
20
23
0
100
300
1
–
500
1.3
40
37
4
kΩ
mV
μs
μs
μs
V
OSC > 3 V
30
30
–
Fixed Off-Time
tOFF
ROSC = 25 kΩ
Reference Input Voltage Range
Reference Input Current
VREF
IREF
–3
–
0
3
μA
%
VREF = 2 V, %ITripMAX = 38.27%
VREF = 2 V, %ITripMAX = 70.71%
VREF = 2 V, %ITripMAX = 100.00%
–
±15
±5
±5
800
Current Trip-Level Error3
–
–
%
errI
tDT
–
–
%
Crossover Dead Time
Protection
100
475
ns
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
TJ
–
165
15
–
–
3
–
°C
°C
V
TJHYS
UVLO
UVHYS
–
VDD rising
2.35
0.05
2.7
0.10
V
1
2
Negative current is defined as coming out of (sourcing from) the specified device pin.
Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
3errI = (ITrip – IProg) ⁄ IProg, where IProg = %ITripMAX
I
.
×
TripMAX
Allegro MicroSystems, Inc.
3
115 Northeast Cutoff, Box 15036
26184.29A
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A3983
DMOS Microstepping Driver with Translator
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic
Symbol
Test Conditions*
Value Units
One-layer PCB, one-sided with copper limited to solder pads
100 ºC/W
One layer PCB, two-sided with copper limited to solder pads and
3.8 in.2 of copper area on each side, connected to GND pins
32 ºC/W
28 ºC/W
RθJA
Package Thermal Resistance
High-K PCB (multilayer with significant copper areas, based on
JEDEC standard)
*In still air. Additional thermal information available on Allegro Web site.
Maximum Power Dissipation, PD(max)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
20
40
60
80
100
120
140
160
180
Temperature (°C)
Allegro MicroSystems, Inc.
4
115 Northeast Cutoff, Box 15036
26184.29A
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A3983
DMOS Microstepping Driver with Translator
t
t
B
A
STEP
t
t
D
C
MS1, MS2,
RESET, or DIR
Time Duration
Symbol
Typ.
1
Unit
μs
STEP minimum, HIGH pulse width
STEP minimum, LOW pulse width
Setup time, input change to STEP
Hold time, input change to STEP
tA
tB
tC
tD
1
μs
200
200
ns
ns
Figure 1. Logic Interface Timing Diagram
Table 1. Microstep Resolution Truth Table
MS1 MS2 Microstep Resolution Excitation Mode
L
H
L
L
L
Full Step
2 Phase
Half Step
1-2 Phase
W1-2 Phase
2W1-2 Phase
H
H
Quarter Step
Eighth Step
H
Allegro MicroSystems, Inc.
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115 Northeast Cutoff, Box 15036
26184.29A
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www.allegromicro.com
A3983
DMOS Microstepping Driver with Translator
Functional Description
Device Operation. The A3983 is a complete microstep-
Microstep Select (MS1 and MS2). Selects the micro-
stepping format, as shown in table 1. MS2 has a 100 kΩ pull-
down resistance. Any changes made to these inputs do not take
effect until the next STEP rising edge.
ping motor driver with a built-in translator for easy operation
with minimal control lines. It is designed to operate bipolar
stepper motors in full-, half-, quarter-, and sixteenth-step
modes. The currents in each of the two output full-bridges
and all of the N-channel DMOS FETs are regulated with
fixed off-time PMW (pulse width modulated) control cir-
cuitry. At each step, the current for each full-bridge is set by
the value of its external current-sense resistor (RS1 or RS2), a
reference voltage (VREF), and the output voltage of its DAC
(which in turn is controlled by the output of the translator).
Direction Input (DIR). This determines the direction of
rotation of the motor. When low, the direction will be clock-
wise and when high, counterclockwise. Changes to this input
do not take effect until the next STEP rising edge.
Internal PWM Current Control. Each full-bridge is
controlled by a fixed off-time PWM current control circuit
that limits the load current to a desired value, ITRIP. Ini-
tially, a diagonal pair of source and sink DMOS outputs are
enabled and current flows through the motor winding and
the current sense resistor, RSx. When the voltage across RSx
equals the DAC output voltage, the current sense compara-
tor resets the PWM latch. The latch then turns off either the
source DMOS FETs (when in Slow Decay Mode) or the sink
and source DMOS FETs (when in Mixed Decay Mode).
At power-on or reset, the translator sets the DACs and the
phase current polarity to the initial Home state (shown in fig-
ures 2 through 5), and the current regulator to Mixed Decay
Mode for both phases. When a step command signal occurs
on the STEP input, the translator automatically sequences the
DACs to the next level and current polarity. (See table 2 for
the current-level sequence.) The microstep resolution is set
by the combined effect of inputs MS1 and MS2, as shown in
table 1.
The maximum value of current limiting is set by the selec-
tion of RSx and the voltage at the VREF pin. The transcon-
ductance function is approximated by the maximum value of
current limiting, ITripMAX (A), which is set by
When stepping, if the new output levels of the DACs are
lower than their previous output levels, then the decay mode
for the active full-bridge is set to Mixed. If the new output
levels of the DACs are higher than or equal to their previous
levels, then the decay mode for the active full-bridge is set
to Slow. This automatic current decay selection improves
microstepping performance by reducing the distortion of
the current waveform that results from the back EMF of the
motor.
ITripMAX = VREF /(8 R )
×
S
where RS is the resistance of the sense resistor (Ω) and VREF
is the input voltage on the REF pin (V).
The DAC output reduces the VREF output to the current
sense comparator in precise steps, such that
RESET Input (RESET). The RESET input sets the
translator to a predefined Home state (shown in figures 2
through 5), and turns off all of the DMOS outputs. All STEP
inputs are ignored until the RESET input is set to high.
Itrip = (%ITripMAX /100)
I
TripMAX
×
(See table 2 for %ITripMAX at each step.)
It is critical that the maximum rating (0.5 V) on the SENSE1
and SENSE2 pins is not exceeded.
Step Input (STEP). A low-to-high transition on the STEP
input sequences the translator and advances the motor one
increment. The translator controls the input to the DACs and
the direction of current flow in each winding. The size of
the increment is determined by the combined state of inputs
MS1 and MS2.
Fixed Off-Time. The internal PWM current control cir-
cuitry uses a one-shot circuit to control the duration of time
that the DMOS FETs remain off. The one shot off-time, tOFF
is determined by the selection of an external resistor con-
nected from the ROSC timing pin to ground. If the ROSC
,
Allegro MicroSystems, Inc.
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115 Northeast Cutoff, Box 15036
26184.29A
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A3983
DMOS Microstepping Driver with Translator
pin is tied to an external voltage > 3 V, then tOFF defaults to
30 μs. The ROSC pin can be safely connected to the VDD
pin for this purpose. The value of tOFF (μs) is approximately
Shutdown. In the event of a fault, overtemperature
(excess TJ) or an undervoltage (on VCP), the DMOS out-
puts of the A3983 are disabled until the fault condition is
removed. At power-on, the UVLO (undervoltage lockout)
circuit disables the DMOS outputs and resets the translator to
the Home state.
tOFF ≈ ROSC ⁄ 825
Blanking. This function blanks the output of the current
sense comparators when the outputs are switched by the
internal current control circuitry. The comparator outputs are
blanked to prevent false overcurrent detection due to reverse
recovery currents of the clamp diodes, and switching tran-
sients related to the capacitance of the load. The blank time,
tBLANK (μs), is approximately
Sleep Mode (SLEEP). To minimize power consumption
when the motor is not in use, this input disables much of the
internal circuitry including the output DMOS FETs, current
regulator, and charge pump. A logic low on the SLEEP pin
puts the A3983 into Sleep mode. A logic high allows normal
operation, as well as start-up (at which time the A3983 drives
the motor to the Home microstep position). When emerging
from Sleep mode, in order to allow the charge pump to stabi-
lize, provide a delay of 1 ms before issuing a Step command.
tBLANK ≈ 1 μs
Charge Pump (CP1 and CP2). The charge pump is
used to generate a gate supply greater than that of VBB
for driving the source-side DMOS gates. A 0.1 μF ceramic
capacitor, should be connected between CP1 and CP2. In
addition, a 0.1 μF ceramic capacitor is required between
VCP and VBB, to act as a reservoir for operating the
high-side DMOS gates.
Mixed Decay Operation. The bridge can operate in
Mixed Decay mode, depending on the step sequence, as
shown in figures 3 thru 5. As the trip point is reached, the
A3983 initially goes into a fast decay mode for 31.25% of
the off-time. tOFF. After that, it switches to Slow Decay mode
for the remainder of tOFF
.
VREG (VREG). This internally-generated voltage is used
to operate the sink-side DMOS outputs. The VREG pin must
be decoupled with a 0.22 μF ceramic capacitor to ground.
VREG is internally monitored. In the case of a fault condi-
tion, the DMOS outputs of the A3983 are disabled.
Synchronous Rectification. When a PWM-off cycle
is triggered by an internal fixed–off-time cycle, load current
recirculates according to the decay mode selected by the
control logic. This synchronous rectification feature turns on
the appropriate FETs during current decay, and effectively
shorts out the body diodes with the low DMOS RDSON. This
reduces power dissipation significantly, and can eliminate
the need for external Schottky diodes in many applications.
Turning off synchronous rectification prevents the reversal of
the load current when a zero-current level is detected.
Enable Input (ENABLE). This input turns on or off all of
the DMOS outputs. When set to a logic high, the outputs are
disabled. When set to a logic low, the internal control enables
the outputs as required. The translator inputs STEP, DIR,
MS1, and MS2, as well as the internal sequencing logic, all
remain active, independent of the ENABLE input state.
Allegro MicroSystems, Inc.
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115 Northeast Cutoff, Box 15036
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A3983
DMOS Microstepping Driver with Translator
STEP
STEP
100.00
70.71
100.00
70.71
Slow
Mixed
Slow
Mixed
Slow
Mixed
Slow
Phase 1
IOUT1A
Phase 1
IOUT1A
0.00
0.00
Direction = H
(%)
Direction = H
(%)
–70.71
–70.71
–100.00
100.00
70.71
–100.00
100.00
70.71
Slow
Slow
Mixed
Slow
Mixed
Slow
Mixed
Phase 2
IOUT2A
Phase 2
IOUT2B
0.00
0.00
Direction = H
(%)
Direction = H
(%)
Slow
–70.71
–70.71
–100.00
–100.00
Figure 2. Decay Mode for Full-Step Increments
Figure 3. Decay Modes for Half-Step Increments
STEP
100.00
92.39
70.71
38.27
Phase 1
IOUT1A
Mixed
Slow
Mixed
Slow
Slow
0.00
Direction = H
(%)
–38.27
–70.71
–92.39
–100.00
100.00
92.39
70.71
38.27
Slow
Phase 2
IOUT2B
Mixed
Slow
Mixed
Slow
Mixed
0.00
Direction = H
(%)
–38.27
–70.71
–92.39
–100.00
Figure 4. Decay Modes for Quarter-Step Increments
Allegro MicroSystems, Inc.
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26184.29A
A3983
DMOS Microstepping Driver with Translator
STEP
100.00
92.39
83.15
70.71
55.56
38.27
Phase 1
IOUT1A
19.51
Slow
Mixed
Slow
Mixed
0.00
Direction = H
(%)
–19.51
–38.27
–55.56
–70.71
–83.15
–92.39
–100.00
100.00
92.39
83.15
70.71
55.56
38.27
Phase 2
IOUT2B
19.51
Mixed
Slow
Mixed
Slow
0.00
Direction = H
(%)
–19.51
–38.27
–55.56
–70.71
–83.15
–92.39
–100.00
Figure 5. Decay Modes for Eighth-Step Increments
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26184.29A
A3983
DMOS Microstepping Driver with Translator
Table 2. Step Sequencing Settings
Home microstep position at Step Angle 45º; DIR = H
Phase 1
Current
tripMax
(%)
Phase 2
Current
tripMax
(%)
Full
Half
1/4
1/8
Step
Angle
(º)
Step Step Step Step [% I
#
]
[% I
]
#
#
#
1
1
1
100.00
98.08
0.00
19.51
0.0
2
11.3
2
3
3
92.39
38.27
22.5
4
83.15
55.56
33.8
1
2
3
4
5
6
7
8
5
70.71
70.71
45.0
6
55.56
83.15
56.3
4
7
38.27
92.39
67.5
8
19.51
98.08
78.8
5
9
0.00
100.00
98.08
90.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
–19.51
–38.27
–55.56
–70.71
–83.15
–92.39
–98.08
–100.00
–98.08
–92.39
–83.15
–70.71
–55.56
–38.27
–19.51
0.00
101.3
112.5
123.8
135.0
146.3
157.5
168.8
180.0
191.3
202.5
213.8
225.0
236.3
247.5
258.8
270.0
281.3
292.5
303.8
315.0
326.3
337.5
348.8
6
92.39
83.15
2
3
4
7
70.71
55.56
8
38.27
19.51
9
0.00
–19.51
–38.27
–55.56
–70.71
–83.15
–92.39
–98.08
–100.00
–98.08
–92.39
–83.15
–70.71
–55.56
–38.27
–19.51
10
11
12
13
14
15
16
19.51
38.27
55.56
70.71
83.15
92.39
98.08
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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26184.29A
A3983
DMOS Microstepping Driver with Translator
Pin List Table
Name
CP1
Description
Charge pump capacitor 1
Charge pump capacitor 2
Reservoir capacitor
Regulator decoupling
Logic input
Number
1
CP2
2
VCP
3
VREG
MS1
4
5
MS2
Logic input
6
RESET
ROSC
SLEEP
VDD
Logic input
7
Timing set
8
Logic input
9
Logic supply
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
STEP
REF
Logic input
Current trip reference voltage input
Ground*
GND
DIR
Logic input
OUT1B
VBB1
SENSE1
OUT1A
OUT2A
SENSE2
VBB2
OUT2B
ENABLE
GND
DMOS Full Bridge 1 Output B
Load supply
Sense resistor for Bridge 1
DMOS Full Bridge 1 Output A
DMOS Full Bridge 2 Output A
Sense resistor for Bridge 2
Load supply
DMOS Full Bridge 2 Output B
Logic input
Ground*
*The two GND pins must be tied together externally by connecting
to the exposed pad ground plane under the device.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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26184.29A
A3983
DMOS Microstepping Driver with Translator
LP Package, 24-Pin TSSOP with Exposed Thermal Pad
Allegro MicroSystems, Inc.
12
115 Northeast Cutoff, Box 15036
26184.29A
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A3983
DMOS Microstepping Driver with Translator
The products described here are manufactured under one or
more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time
to time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability,
or manufacturability of its products. Before placing an order, the
user is cautioned to verify that the information being relied upon is
current.
Allegro products are not authorized for use as critical compo-
nents in life-support devices or systems without express written
approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringement of patents or other
rights of third parties which may result from its use.
Copyright©2005 AllegroMicrosystems, Inc.
Allegro MicroSystems, Inc.
13
115 Northeast Cutoff, Box 15036
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www.allegromicro.com
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ALLEGRO
A3984_08
The A3984 is a complete microstepping motor driver with built-in translator for easy operation.
ALLEGRO
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