ALD1721ESA [ALD]
EPAD⑩ MICROPOWER OPERATIONAL AMPLIFIER; EPAD ™微功耗运算放大器
| 型号： | ALD1721ESA |
| 厂家： | 
ADVANCED LINEAR DEVICES |
| 描述： | EPAD⑩ MICROPOWER OPERATIONAL AMPLIFIER |
| 文件： | 总10页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A
L
D
DVANCED
INEAR
EVICES, INC.
ALD1721E/ALD1721
EPAD™ MICROPOWER OPERATIONAL AMPLIFIER
BENEFITS
KEY FEATURES
• Eliminates manual and elaborate
•
•
•
•
•
•
•
•
•
•
•
EPAD ( Electrically Programmable Analog Device)
User programmable V
trimmer
Computer-assisted trimming
Rail-to-rail input/output
Compatible with standard EPAD Programmer
High precision through in-system circuit precision trimming
system trimming procedures
• Remote controlled automated trimming
• In-System Programming capability
• No external components
• No internal chopper clocking noise
• No chopper dynamic power dissipation
• Simple and cost effective
• Small package size
• Extremely small total functional
volume size
OS
Reduces or eliminates V , PSRR, CMRR and TCV
errors
OS
OS
System level “calibration” capability
Application Specific Programming mode
In-System Programming mode
Electrically programmable to compensate for
external component tolerances
Achieves 0.01pA input bias current and 35µV
input offset voltage simultaneously
Compatible with industry standard pinout
• Low system implementation cost
• Micropower and Low Voltage
•
•
APPLICATIONS
GENERAL DESCRIPTION
• Sensor interface circuits
The ALD1721E/ALD1721 is a monolithic rail-to-rail precision CMOS
operational amplifier with integrated user programmable EPAD (Electri-
callyProgrammableAnalogDevice)basedoffsetvoltageadjustment. The
ALD1721E/ALD1721 operational amplifier is a direct replacement of the
ALD1701 operational amplifier, with the added feature of user-program-
mable offset voltage trimming resulting in significantly enhanced total
system performance and user flexibility. EPAD technology is an exclusive
ALD design which has been refined for analog applications where preci-
sion voltage trimming is necessary to achieve a desired performance. It
utilizes CMOS FETs as in-circuit elements for trimming of offset voltage
bias characteristics with the aid of a personal computer under software
control. Once programmed, the set parameters are stored indefinitely
within the device even after power-down. EPAD offers the circuit designer
a convenient and cost-effective trimming solution for achieving the very
highest amplifier/system performance.
• Transducer biasing circuits
• Capacitive and charge integration circuits
• Biochemical probe interface
• Signal conditioning
• Portable instruments
• High source impedance electrode
amplifiers
• Precision Sample and Hold amplifiers
• Precision current to voltage converter
• Error correction circuits
• Sensor compensation circuits
• Precision gain amplifiers
• Periodic In-system calibration
• System output level shifter
The ALD1721E/ALD1721 operational amplifier features rail-to-rail input
and output voltage ranges, tolerance to over-voltage input spikes of
300mV beyond supply rails, capacitive loading up to 50pF, extremely low
input currents of 0.01pA typical, high open loop voltage gain, useful
bandwidth of 700KHz, slew rate of 0.7 V/µs, and low typical supply current
of 120 uA.
PIN CONFIGURATION
VE1
-IN
1
8
7
6
5
VE2
ORDERING INFORMATION
Operating Temperature Range
+
V
2
-55°C to +125°C
0°C to +70°C
0°C to +70°C
+IN
3
4
OUT
N/C
8-Pin
8-Pin
8-Pin
-
CERDIP
Small Outline
Plastic Dip
V
Package
Package (SOIC)
Package
TOP VIEW
DA, PA, SA PACKAGE
ALD1721E DA
ALD1721 DA
ALD1721E SA
ALD1721 SA
ALD1721E PA
ALD1721 PA
* Contact factory for industrial temperature range
© 1998 Advanced Linear Devices, Inc. 415Tasman Drive, Sunnyvale, California 94089 -1706 Tel: (408) 747-1155 Fax: (408) 747-1286 http://www.aldinc.com
errors introduced by other circuit components, such as resis-
tor or sensor induced voltage errors, can also be corrected.
In this way, the “in-system” circuit output can be adjusted to
a desired level eliminating other trimming components.
FUNCTIONAL DESCRIPTION
TheALD1721E/ALD1721usesEPADsasin-circuitelements
for trimming of offset voltage bias characteristics. Each
ALD1721E/ALD1721 has a pair of EPAD-based circuits
connected such that one circuit is used to adjust V
direction and the other circuit is used to adjust V
other direction.
in one
in the
OS
OS
Functional Description of ALD1721
The ALD1721 is pre-programmed at the factory under stan-
dardoperatingconditionsforminimumequivalentinputoffset
voltage. TheALD1721offerssimilarprogrammablefeatures
as the ALD1721E, but with more limited offset voltage pro-
gram range. It is intended for standard operational amplifier
applications where little or no electrical programming by the
user is necessary.
Functional Description of ALD1721E
While each of the EPAD devices is a monotonically adjust-
ableprogrammabledevice,theV oftheALD1721E canbe
OS
adjusted many times in both directions. Once programmed,
the set V
levels are stored permanently, even when the
OS
device power is removed.
USER PROGRAMMABLE Vos FEATURE
The ALD1721E provides the user with an operational ampli-
fier that can be trimmed with user application-specific pro-
gramming or in-system programming conditions. User appli-
cation-specific circuit programming refers to the situation
wheretheTotalInputOffsetVoltageoftheALD1721E canbe
trimmed with the actual intended operating conditions.
Each ALD1721E/ALD1721 has two pins named VE1 and
VE2 which are internally connected to an internal offset bias
circuit. VE1/VE2 have initial typical values of 1.2 /1.7 Volt.
ThevoltageonthesepinscanbeprogrammedusingtheALD
E100 EPAD Programmer and the appropriate Adapter Mod-
ule. The useful programming range of VE1 and VE2 is 1.2
Volt to 3.0 Volts. VE1 and VE2 pins are programming pins,
used during programming mode. The Programming pin is
used during electrical programming to inject charge into the
internal EPADs. Increases of VE1 decrease the offset volt-
age while increases of VE2 increase the offset voltage of the
operational amplifier. The injected charge is permanently
stored and determines the offset voltage of the operational
amplifier. After programming, VE1 and VE2 terminals must
be left open to settle on a voltage determined by internal bias
currents.
The ALD1721E is pre-programmed at the factory under
standard operating conditions for minimum equivalent input
offset voltage. It also has a guaranteed offset voltage
program range, which is ideal for applications that require
electrical offset voltage programming.
For example, an application circuit may have +6V and -2.5V
power supplies, and the operational amplifier input is biased
at +0.7V, and the average operating temperature is at 55°C.
The circuit can be wired up to these conditions within an
environmental chamber, and the ALD1721E can be inserted
into a test socket connected to this circuit while it is being
During programming, the voltages on VE1 or VE2 are in-
creased incrementally to set the offset voltage of the opera-
tionalamplifiertothedesiredV . NotethatdesiredV can
electrically trimmed. Any error in V
due to these bias
OS
conditions can be automatically zeroed out. The Total V
OS
OS
OS
error is now limited only by the adjustable range and the
be any value within the offset voltage programmable ranges,
and can be either zero, a positive value or a negative value.
stability of V , and the input noise voltage of the operational
OS
amplifier. Therefore, this Total V
error now includes V
OS
This V
value can also be reprogrammed to a different
OS
is traditionally specified; plus the V error contribu-
OS
as V
value at a later time, provided that the useful VE1 or VE2
programming voltage range has not been exceeded. VE1 or
VE2 pins can also serve as capacitively coupled input pins.
OS
OS
tions from PSRR, CMRR, TCV , and noise. Typically this
OS
) is approximately ±35µV for the
total V
ALD1721E.
error term (V
OS
OST
Internally, VE1 and VE2 are programmed and connected
differentially. Temperature drift effects between the two
internal offset bias circuits cancel each other and introduce
less net temperature drift coefficient change than offset
voltage trimming techniques such as offset adjustment with
an external trimmer potentiometer.
The V contribution due to PSRR, CMRR, TCV
and
OS
OS
external components can be large for operational amplifiers
without trimming. Therefore the ALD1721E with EPAD trim-
ming is able to provide much improved system performance
by reducing these other sources of error to provide signifi-
cantly reduced V
OST.
In-System Programming refers to the condition where the
EPAD adjustment is made after the ALD1721E has been
inserted into a circuit board. In this case, the circuit design
must provide for the ALD1721E to operate in normal mode
and in programming mode. One of the benefits of in-system
programming is that not only is the ALD1721E offset voltage
from operating bias conditions accounted for, any residual
While programming, V+, VE1 and VE2 pins may be alter-
nately pulsed with 12V (approximately) pulses generated by
theEPADProgrammer. In-systemprogrammingrequiresthe
ALD1721E/ALD1721 application circuit to accommodate
these programming pulses. This can be accomplished by
adding resistors at certain appropriate circuit nodes. For
more information, see Application Note AN1700.
2
Advanced Linear Devices
ALD1721E/ALD1721
ABSOLUTE MAXIMUM RATINGS
+
Supply voltage, V
13.2V
-0.3V to V +0.3V
600 mW
+
Differential input voltage range
Power dissipation
Operating temperature range PA,SA package
0°C to +70°C
-55°C to +125°C
-65°C to +150°C
+260°C
DA package
Storage temperature range
Lead temperature, 10 seconds
OPERATING ELECTRICAL CHARACTERISTICS
T = 25oC V = ±2.5V unless otherwise specified
A
S
1721E
Typ
1721
Typ
Parameter
Symbol
Min
Max
Min
Max
Unit
Test Conditions
Supply Voltage
V
+
V
±1.0
±5.0
±1.0
±5.0
V
V
S
2.0
10.0
2.0
10.0
Single Supply
Initial Input Offset Voltage1
V
35
±15
50
75
50
±5
50
150
µV
mV
µV
R ≤ 100KΩ
S
OS i
Offset Voltage Program Range 2
∆V
OS
±10
±1
Programmed Input Offset
Voltage Error 3
V
OS
90
90
150
150
At user specified
target offset voltage
Total Input Offset Voltage 4
Input Offset Current 5
Input Bias Current 5
V
50
0.01
0.01
50
0.01
0.01
µV
At user specified
OST
OS
B
target offset voltage
I
I
10
10
pA
pA
T
A
= 25°C
240
240
0°C ≤ T ≤ +70°C
A
10
10
pA
pA
T
A
= 25°C
240
240
0°C ≤ T ≤ +70°C
A
Input Voltage Range 6
V
IR
-0.3
-2.8
5.3
-0.3
-2.8
5.3
V
V
V
V
= +5V
+
+2.8
+2.8
= ±2.5V
S
Input Resistance
R
1014
5
1014
Ω
IN
Input Offset Voltage Drift 7
TCV
OS
7
µV/°C
dB
R
R
≤ 100KΩ
≤ 100KΩ
S
S
Initial Power Supply
Rejection Ratio 8
PSRR
80
80
i
Initial Common Mode
Rejection Ratio 8
CMRR
83
83
dB
R
R
≤ 100KΩ
=100KΩ
i
S
Large Signal Voltage Gain
A
V
32
20
100
32
20
100
V/mV
V/mV
L
0°C ≤ T ≤ +70°C
A
+
R =1MΩ V = 5V
L
0°C ≤ T ≤ +70°C
A
V
low
0.001
4.999
0.01
0.001
4.999
0.01
V
V
O
Output Voltage Range
V
O
high
4.99
2.40
4.99
2.40
V
O
V
O
low
-2.48
2.48
-2.40
-2.48
2.48
-2.40
V
V
R =100KΩ
L
0°C ≤ T ≤ +70°C
A
high
Output Short Circuit Current
I
1
1
mA
SC
\* NOTES 1 through 9, see section titled "Definitions and Design Notes".
ALD1721E/ALD1721
Advanced Linear Devices
3
OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
T = 25oC V = ±2.5V unless otherwise specified
A
S
1721E
Typ
1721
Typ
Parameter
Symbol
Min
Max
Min
Max
Unit
Test Conditions
Supply Current
I
S
120
200
120
200
µA
V
= 0V
IN
No Load
Power Dissipation
Input Capacitance
P
0.6
1
1.00
0.6
1
1.00
mW
pF
V = ±2.5V
S
D
C
C
IN
L
Maximum Load Capacitance
50
50
pF
Equivalent Input Noise Voltage
Equivalent Input Current Noise
Bandwidth
e
55
0.6
700
0.7
55
0.6
700
0.7
nV/√Hz
fA/√Hz
KHz
f = 1KHz
f =10Hz
n
i
n
B
S
400
0.3
400
0.3
W
R
Slew Rate
V/µs
A
= +1
V
R
L
= 10KΩ
Rise time
t
r
0.2
20
0.2
20
µs
R
= 10KΩ
L
Overshoot Factor
%
R
L
= 100KΩ,
C
L
= 50pF
Settling Time
t
s
10
10
µs
0.1%
A
V
= 1,R =100KΩ
L
C
L
= 50pF
T = 25oC V = ±2.5V unless otherwise specified
A
S
1721E
Typ
1721
Typ
Parameter
Symbol
Min
Max
Min
Max
Unit
Test Conditions
Average Long Term Input Offset ∆ V
Voltage Stability 9
0.02
1.2
2.5
0.1
-5
0.02
1.7
1.0
0.1
-5
µV/
OS
∆ time
1000 hrs
Initial VE Voltage
VE1 , VE2
V
i
i
Programmable VE Range
Programmed VE Voltage Error
VE Pin Leakage Current
∆VE1, ∆VE2
1.5
V
e(VE1-VE2)
%
µA
i
eb
4
Advanced Linear Devices
ALD1721E/ALD1721
V = ±2.5V -55°C ≤ T ≤ +125°C unless otherwise specified
S
A
1721E
Typ
1721
Typ
Parameter
Symbol
Min
Max
Min
Max
Unit
mV
nA
Test Conditions
Initial Input offset Voltage
Input Offset Current
Input Bias Current
V
0.5
0.8
R
≤ 100KΩ
OS i
S
I
I
2.0
2.0
2.0
2.0
OS
nA
B
Initial Power Supply
Rejection Ratio 8
PSRR
75
83
50
75
83
50
dB
R
≤ 100KΩ
≤ 100KΩ
= 100KΩ
= 100KΩ
i
S
Initial Common Mode
Rejection Ratio 8
CMRR
dB
R
S
i
Large Signal Voltage Gain
Output Voltage Range
A
15
15
V/mV
R
L
V
V
V
low
-2.47
2.45
-2.40
-2.47
2.45
-2.40
V
V
O
O
high
2.35
2.35
R
L
T = 25oC V = ±5.0V unless otherwise specified
A
S
1721E
Typ
1721
Typ
Parameter
Symbol
Min
Max
Min
Max
Unit
Test Conditions
Initial Power Supply
Rejection Ratio 8
PSRR
CMRR
83
83
83
83
dB
R
R
≤ 100KΩ
≤ 100KΩ
i
S
S
Initial Common Mode
Rejection Ratio 8
dB
i
Large Signal Voltage Gain
Output Voltage Range
A
250
250
V/mV
V
R
R
= 100KΩ
= 100KΩ
V
L
L
V
V
low
-4.98
4.98
-4.90
-4.98
4.98
-4.90
O
O
high
4.90
4.90
Bandwidth
Slew Rate
B
S
1.0
1.0
1.0
1.0
MHz
W
R
V/µs
A
= +1, C = 50pF
V
L
ALD1721E/ALD1721
Advanced Linear Devices
5
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGE AND TEMPERATURE
OUTPUT VOLTAGE SWING AS A FUNCTION
OF SUPPLY VOLTAGE
±6
±5
±4
1000
±25°C ≤ T ≤ +125°C
A
R
= 100KΩ
L
100
±3
10
1
±2
±1
±55°C ≤ T ≤ +125°C
A
R
= 100KΩ
L
0
±2
±4
±6
±8
0
±1
±2
±3
±4
±5
±6
±7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
500
1000
100
+25°C
INPUTS GROUNDED
OUTPUT UNLOADED
-25°C
V
= ±2.5V
S
400
300
200
100
T
= -55°C
A
10
1.0
+70°C
+125°C
0.1
0
0.01
0
±1
±2
±3
±4
±5
±6
-50 -25
0
25
50
75
100
125
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
ADJUSTMENT IN INPUT OFFSET VOLTAGE
AS A FUNCTION OF CHANGE IN VE1 AND VE2
OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF FREQUENCY
10
8
120
100
80
V
T
= ±2.5V
= 25°C
S
A
6
4
VE2
2
0
0
60
40
45
-2
-4
90
135
180
20
0
-6
-8
VE1
-10
-20
0.0
0.25
0.5
0.75
1.0
1.25 1.50
1
10
100
1K
10K 100K
1M
10M
CHANGE IN VE1 AND VE2 (V)
FREQUENCY (Hz)
6
Advanced Linear Devices
ALD1721E/ALD1721
TYPICAL PERFORMANCE CHARACTERISTICS
COMMON MODE INPUT VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE
LARGE - SIGNAL TRANSIENT
RESPONSE
±7
±6
2V/div
V
= ±1.0V
= 25°C
= 100KΩ
= 50pF
S
T
A
T
= 25°C
A
R
C
±5
±4
L
L
±3
±2
±1
0
500mV/div
5µs/div
0
±1
±2
±3
±4
±5
±6
±7
SUPPLY VOLTAGE (V)
OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF LOAD RESISTANCE
SMALL - SIGNAL TRANSIENT
RESPONSE
1000
100
10
100mV/div
V
= ±2.5V
= 25°C
= 100KΩ
= 50pF
S
T
A
R
C
L
L
V
T
= ±2.5V
= 25°C
S
A
20mV/div
2µs/div
1
10K
100K
1M
10M
LOAD RESISTANCE (Ω)
LARGE - SIGNAL TRANSIENT
RESPONSE
DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE
BEFORE AND AFTER EPAD PROGRAMMING
100
80
EXAMPLE B:
AFTER EPAD
EXAMPLE A:
V AFTER EPAD
5V/div
V
= ±2.5V
= 25°C
S
V
OST
PROGRAMMING
TARGET = -750µV
OST
PROGRAMMING
V TARGET = 0.0µV
OST
T
A
V
OST
R
L
C
L
= 100KΩ
= 50pF
60
40
V
BEFORE EPAD
OST
PROGRAMMING
20
0
2V/div
5µs/div
-2500 -2000
-1500
-500
0
500
1000
1500
2000
2500
-1000
TOTAL INPUT OFFSET VOLTAGE (µV)
ALD1721E/ALD1721
Advanced Linear Devices
7
TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
500
400
PSRR = 80 dB
EXAMPLE A:
EPAD PROGRAMMED
V
OS
AT V
= +5V
SUPPLY
300
200
EXAMPLE B:
EPAD
V
OS
PROGRAMMED
AT V
= +8V
SUPPLY
100
0
0
1
2
3
4
5
6
7
8
9
10
SUPPLY VOLTAGE (V)
THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE
500
400
V
= ±5V
SUPPLY
CMRR = 80dB
300
200
EXAMPLE B:
EPAD
EXAMPLE A:
V EPAD PROGRAMMED
V
OS
PROGRAMMED
OS
AT V = 0V
IN
AT V = -4.3V
IN
100
0
EXAMPLE C:
EPAD PROGRAMMED
V
OS
AT V = +5V
IN
-5
-4
-3
-1
0
1
2
3
4
5
-2
COMMON MODE VOLTAGE (V)
EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE
FOR A COMMON MODE VOLTAGE RANGE OF 0.5V
50
40
COMMON MODE VOLTAGE RANGE OF 0.5V
30
20
V
EPAD
OS
PROGRAMMED
AT COMMON MODE
VOLTAGE OF 0.25V
CMRR = 80dB
10
0
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
COMMON MODE VOLTAGE (V)
8
Advanced Linear Devices
ALD1721E/ALD1721
APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING
Examples of applications where accumulated total input offset voltage from various
contributing sources is minimized under different sets of user-specified operating conditions
2500
2000
1500
2500
2000
V
BUDGET AFTER
OS
1500
1000
500
0
EPAD PROGRAMMING
V
BUDGET AFTER
OS
1000
500
0
EPAD PROGRAMMING
+
X
-500
-500
+
X
-1000
-1000
V
BUDGET BEFORE
OS
-1500
-2000
-2500
-1500
-2000
-2500
EPAD PROGRAMMING
V
BUDGET BEFORE
OS
EPAD PROGRAMMING
EXAMPLE B
EXAMPLE A
2500
2000
1500
2500
2000
1500
V
OS
BUDGET AFTER
EPAD PROGRAMMING
V
BUDGET BEFORE
OS
1000
500
0
1000
500
0
EPAD PROGRAMMING
+
X
-500
-500
+
-1000
-1000
X
-1500
-2000
-2500
-1500
-2000
-2500
V
BUDGET AFTER
OS
V
BUDGET BEFORE
OS
EPAD PROGRAMMING
EPAD PROGRAMMING
EXAMPLE C
EXAMPLE D
Total Input V
after EPAD
Device input V
OS
OS
PSRR equivalent V
OS
Programming
+
CMRR equivalent V
OS
T
equivalent V
A
OS
X
Noise equivalent V
OS
External Error equivalent V
OS
ALD1721E/ALD1721
Advanced Linear Devices
9
DEFINITIONS AND DESIGN NOTES:
ADDITIONAL DESIGN NOTES:
A. TheALD1721E/ALD1721isinternallycompensatedforunity
gainstabilityusinganovelschemewhichproducesasinglepole
role off in the gain characteristics while providing more than 70
degrees of phase margin at unity gain frequency. A unity gain
buffer using the ALD1721E/ALD1721 will typically drive 50pF of
external load capacitance.
1. Initial Input Offset Voltage is the initial offset voltage of the
ALD1721E/ALD1721 operational amplifier when shipped from
the factory. The device has been pre-programmed and tested
for programmability.
2. Offset Voltage Program Range is the range of adjustment of
user specified target offset voltage. This is typically an adjust-
ment in either the positive or the negative direction of the input
offset voltage from an initial input offset voltage. The input
offset programming pins, VE1 or VE2, change the input offset
voltage in the negative or positive direction, respectively. User
specified target offset voltage can be any offset voltage within
this programming range.
B. The ALD1721E/ALD1721 has complementary p-channel
and n-channel input differential stages connected in parallel to
accomplish rail-to-rail input common mode voltage range. The
switchingpointbetweenthetwodifferentialstagesis1.5Vbelow
positive supply voltage. For applications such as inverting
amplifier or non-inverting amplifier with a gain larger than 2.5
(5V operation), the common mode voltage does not make
excursions below this switching point. However, this switching
doestakeplaceiftheoperationalamplifierisconnectedasarail-
to-rail unity gain buffer and the design must allow for input offset
voltage variations.
3. Programmed Input Offset Voltage Error is the final offset
voltage error after programming when the Input Offset Voltage
is at target Offset Voltage. This parameter is sample tested.
4. Total Input Offset Voltage is the same as Programmed Input
Offset Voltage, corrected for system offset voltage error. Usu-
ally this is an all inclusive system offset voltage, which also
includes offset voltage contributions from input offset voltage,
C. TheoutputstageconsistsofclassABcomplementaryoutput
drivers. The oscillation resistant feature, combined with the rail-
to-railinputandoutputfeature, makestheALD1721E/ALD1721
an effective analog signal buffer for high source impedance
sensors, transducers, and other circuit networks.
PSRR, CMRR, TCV
and noise. It can also include errors
OS
introduced by external components, at a system level. Pro-
grammed Input Offset Voltage and Total Input Offset Voltage is
not necessarily zero offset voltage, but an offset voltage set to
compensate for other system errors as well. This parameter is
sample tested.
D. The ALD1721E/ALD1721 has static discharge protection.
Care must be exercised when handling the device to avoid
strong static fields that may degrade a diode junction, causing
increased input leakage currents. The user is advised to power
up the circuit before, or simultaneously with, any input voltages
applied and to limit input voltages not to exceed 0.3V of the
power supply voltage levels.
5. The Input Offset and Bias Currents are essentially input
protection diode reverse bias leakage currents. This low input
bias current assures that the analog signal from the source will
not be distorted by it. For applications where source impedance
is very high, it may be necessary to limit noise and hum pickup
through proper shielding.
E. VE1 and VE2 are high impedance terminals, as the internal
bias currents are set very low to a few microamperes to
conserve power. For some applications, these terminals may
need to be shielded from external coupling sources. For ex-
ample, digital signals running nearby may cause unwanted
offset voltage fluctuations. Care during the printed circuit board
layout to place ground traces around these pins and to isolate
them from digital lines will generally eliminate such coupling
effects. In addition, optional decoupling capacitors of 1000pF or
greater value can be added to VE1 and VE2 terminals.
6. Input Voltage Range is determined by two parallel comple-
mentary input stages that are summed internally, each stage
having a separate input offset voltage. While Total Input Offset
Voltage can be trimmed to a desired target value, it is essential
to note that this trimming occurs at only one user selected input
bias voltage. Depending on the selected input bias voltage
relative to the power supply voltages, offset voltage trimming
may affect one or both input stages. For the ALD1721E/
ALD1721, the switching point between the two stages occur at
approximately 1.5V below positive supply voltage.
F. The ALD1721E/ALD1721 is designed for use in low voltage,
micropower circuits. The maximum operating voltage during
normaloperationshouldremainbelow10Voltsatalltimes.Care
shouldbetakentoinsurethattheapplicationinwhichthedevice
is used do not experience any positive or negative transient
voltages that will cause any of the terminal voltages to exceed
this limit.
7. Input Offset Voltage Drift is the average change in Total Input
Offset Voltage as a function of ambient temperature. This
parameter is sample tested.
8. Initial PSRR and initial CMRR specifications are provided as
reference information. After programming, error contribution to
theoffsetvoltagefromPSRRandCMRRissettozerounderthe
specific power supply and common mode conditions, and
becomes part of the Programmed Input Offset Voltage Error.
G. AllinputsorunusedpinsexceptVE1andVE2pinsshouldbe
connected to a supply voltage such as Ground so that they do
not become floating pins, since input impedance at these pins
is very high. If any of these pins are left undefined, they may
cause unwanted oscillation or intermittent excessive current
drain. As these devices are built with CMOS technology, normal
operating and storage temperature limits, ESD and latchup
handling precautions pertaining to CMOS device handling
should be observed.
9. AverageLongTermInputOffsetVoltageStabilityisbasedon
input offset voltage shift through operating life test at 125°C
extrapolated to TA = 25 °C, assuming activation energy of
1.0eV. This parameter is sample tested.
10
Advanced Linear Devices
ALD1721E/ALD1721
相关型号：
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