ALD1721E_11 [ALD]
EPAD® MICROPOWER CMOS OPERATIONAL AMPLIFIER; EPAD®微功耗CMOS运算放大器
| 型号： | ALD1721E_11 |
| 厂家： | 
ADVANCED LINEAR DEVICES |
| 描述： | EPAD® MICROPOWER CMOS OPERATIONAL AMPLIFIER |
| 文件： | 总13页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
A
L
D
DVANCED
INEAR
EVICES, INC.
®
e
EPAD
ALD1721E
®
EPAD MICROPOWER CMOS OPERATIONAL AMPLIFIER
KEY FEATURES
BENEFITS
•
•
•
•
•
•
•
•
•
•
•
EPAD (Electrically Programmable Analog Device)
trimmer
Computer-assisted trimming
Rail-to-rail input/output
Compatible with standard EPAD Programmer
High precision through in-system circuit precision trimming
• Eliminates manual and elaborate
system trimming procedures
• Remote controlled automated trimming
• In-System Programming capability
• No external components
• No internal chopper clocking noise
• No chopper dynamic power dissipation
• Simple and cost effective
• Small package size
• Extremely small total functional
volume size
• Low system implementation cost
• Micropower and Low Voltage
User programmable V
OS
Reduces or eliminates V , PSRR, CMRR and TCV
errors
OS
OS
System level “calibration” capability
Application Specific Programming mode
In-System Programming mode
Electrically programmable to compensate for external
component tolerances
Achieves 0.01pA input bias current and 35µV input offset
voltage simultaneously
•
•
Compatible with industry standard pinout
APPLICATIONS
GENERAL DESCRIPTION
• Sensor interface circuits
The ALD1721E is a monolithic rail-to-rail precision CMOS operational
amplifier with integrated user programmable EPAD (Electrically Program-
mable Analog Device) based offset voltage adjustment. The ALD1721E
operational amplifier is a direct replacement of the ALD1701 operational
amplifier, with the added feature of user-programmable offset voltage
trimming resulting in significantly enhanced total system performance and
user flexibility. EPAD technology is an exclusive ALD design which has
been refined for analog applications where precision voltage trimming is
necessary to achieve a desired performance. It utilizes CMOS FETs as in-
circuit elements for trimming of offset voltage bias characteristics with the
aidofapersonal computerundersoftwarecontrol. Onceprogrammed,the
set parameters are stored indefinitely within the device even after power-
down. EPAD offers the circuit designer a convenient and cost-effective
trimming solution for achieving the very highest amplifier/system perfor-
mance.
• Transducer biasing circuits
• Capacitive and charge integration circuits
• Biochemical probe interface
• Signal conditioning
• Portable instruments
• High source impedance electrode
amplifiers
• Precision Sample and Hold amplifiers
• Precision current to voltage converter
• Error correction circuits
• Sensor compensation circuits
• Precision gain amplifiers
• Periodic In-system calibration
• System output level shifter
The ALD1721E operational amplifier features rail-to-rail input and output
voltage ranges, tolerance to over-voltage input spikes of 300mV beyond
supply rails, capacitive loading up to 50pF, extremely low input currents of
0.01pA typical, high open loop voltage gain, useful bandwidth of 700KHz,
slew rate of 0.7V/µs, and low typical supply current of 120µA.
PIN CONFIGURATION
VE1
-IN
1
8
7
6
5
VE2
+
2
V
ORDERING INFORMATION (“L” suffix denotes lead-free (RoHS))
Operating Temperature Range
+IN
3
4
OUT
N/C
0°C to +70°C
0°C to +70°C
-55°C to +125°C
-
V
8-Pin
8-Pin
8-Pin
Small Outline
Package (SOIC)
Plastic Dip
Package
CERDIP
Package
TOP VIEW
SAL, PAL, DA PACKAGES
ALD1721ESAL
ALD1721EPAL
ALD1721EDA
* N/C Pin is internally connected. Do not connect externally.
* Contact factory for leaded (non-RoHS) or high temperature versions.
Rev 2.1 ©2011 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, CA 94089-1706 Tel: (408) 747-1155 Fax: (408) 747-1286
www.aldinc.com
FUNCTIONAL DESCRIPTION
USER PROGRAMMABLE V
FEATURE
OS
The ALD1721E uses EPADs as in-circuit elements for trim-
ming of offset voltage bias characteristics. Each ALD1721E
has a pair of EPAD-based circuits connected such that one
EachALD1721EhastwopinsnamedVE1andVE2whichare
internally connected to an internal offset bias circuit. VE1/
VE2 have initial typical values of 1.2V/1.7V. The voltage on
these pins can be programmed using the ALD E100 EPAD
ProgrammerandtheappropriateAdapterModule.Theuseful
programming range of VE1 and VE2 is 1.2V to 3.0V.
circuit is used to adjust V
in one direction and the other
OS
circuitisusedtoadjustV intheotherdirection. Whileeach
OS
of the EPAD devices is a monotonically adjustable program-
mable device, the V
of the ALD1721E can be adjusted
OS
many times in both directions. Once programmed, the set
levels are stored permanently, even when the device
VE1 and VE2 pins are programming pins, used during
programming mode to inject charge into the internal EPADs.
Increasing voltage on VE1 decreases the offset voltage
whereas increasing voltage on VE2 increases the offset
voltage of the operational amplifier. The injected charge is
permanently stored and determines the offset voltage of the
operational amplifier. After programming, VE1 and VE2
terminals must be left open to settle on a voltage determined
by internal bias currents.
V
OS
power is removed.
The ALD1721E is pre-programmed at the factory under
standard operating conditions for minimum equivalent input
offset voltage. It also has a guaranteed offset voltage
program range, which is ideal for applications that require
electrical offset voltage programming.
The ALD1721E is an operational amplifier that can be
trimmed with user application-specific programming or in-
system programming conditions. User application-specific
circuit programming refers to the situation where the Total
Input Offset Voltage of the ALD1721E can be trimmed with
the actual intended operating conditions.
During programming, the voltages on VE1 or VE2 are in-
creased incrementally to set the offset voltage of the opera-
tional amplifier to the desired Vos. Note that desired Vos can
be any value within the offset voltage programmable ranges,
and can be zero, a positive value or a negative value. This
V
OS
value can also be reprogrammed to a different value at
a later time, provided that the useful VE1 or VE2 program-
mingvoltagerangehasnotbeenexceeded. VE1orVE2pins
can also serve as capacitively coupled input pins.
For example, an application circuit may have +6V and -2.5V
power supplies, and the operational amplifier input is biased
at +0.7V, and an average operating temperature at 55°C.
The circuit can be wired up to these conditions within an
environmental chamber with the ALD1721E inserted into a
test socket connected to this circuit while it is being electri-
Internally, VE1 and VE2 are programmed and connected
differentially. Temperature drift effects between the two
internal offset bias circuits cancel each other and introduce
less net temperature drift coefficient change than offset
voltage trimming techniques such as offset adjustment with
an external trimmer potentiometer.
cally trimmed. Any error in V
due to these bias conditions
OS
can be automatically zeroed out. The Total V
error is now
OS
limited only by the adjustable range and the stability of V
,
OS
and the input noise voltage of the operational amplifier.
Therefore, this Total V error now includes V as V is
While programming, V+, VE1 and VE2 pins may be alter-
nately pulsed with 12V (approximately) pulses generated by
the EPAD Programmer. In-system programming requires
the ALD1721E application circuit to accommodate these
programming pulses. This can be accomplished by adding
resistors at certain appropriate circuit nodes. For more
information, see Application Note AN1700.
OS
traditionally specified; plus the V
OS
OS
error contributions from
OS
PSRR, CMRR, TCV , and noise. Typically this total V
OS OS
)isapproximately±35µVfortheALD1721E.
errorterm(V
OST
The V
contribution due to PSRR, CMRR, TCV
and
OS
OS
external components can be large for operational amplifiers
without trimming. Therefore the ALD1721E with EPAD trim-
ming is able to provide much improved system performance
by reducing these other sources of error to provide signifi-
cantly reduced V
OST.
In-System Programming refers to the condition where the
EPAD adjustment is made after the ALD1721E has been
inserted into a circuit board. In this case, the circuit design
must provide for the ALD1721E to operate in normal mode
and in programming mode. One of the benefits of in-system
programming is that not only is the ALD1721E offset voltage
from operating bias conditions accounted for, any residual
errors introduced by other circuit components, such as resis-
tor or sensor induced voltage errors, can also be corrected.
In this way, the “in-system” circuit output can be adjusted to
a desired level, eliminating the need for another trimming
function.
ALD1721E
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2 of 13
ABSOLUTE MAXIMUM RATINGS
+
Supply voltage, V
10.6V
-0.3V to V +0.3V
600 mW
+
Differential input voltage range
Power dissipation
Operating temperature range SAL, PAL packages
0°C to +70°C
-55°C to +125°C
-65°C to +150°C
+260°C
DA package
Storage temperature range
Lead temperature, 10 seconds
CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment.
OPERATING ELECTRICAL CHARACTERISTICS
T = 25oC V = ±2.5V unless otherwise specified
A
S
1721E
Typ
Parameter
Symbol
Min
Max
Unit
Test Conditions
Supply Voltage
V
V
±1.0
±5.0
V
V
S
+
2.0
10.0
Single Supply
Initial Input Offset Voltage1
V
35
90
µV
mV
µV
R ≤ 100KΩ
S
OS i
Offset Voltage Program Range 2
∆V
±10
±15
50
OS
Programmed Input Offset
Voltage Error3
V
V
I
90
90
At user specified
OS
target offset voltage
Total Input Offset Voltage 4
Input Offset Current 5
Input Bias Current 5
50
µV
At user specified
OST
target offset voltage
0.01
0.01
10
pA
pA
T
= 25°C
A
OS
240
0°C ≤ T ≤ +70°C
A
I
B
10
pA
pA
T
= 25°C
A
240
0°C ≤ T ≤ +70°C
A
Input Voltage Range 6
V
-0.3
-2.8
5.3
V
V
V
V
= +5V
+
IR
+2.8
= ±2.5V
S
14
Input Resistance
R
IN
10
Ω
Input Offset Voltage Drift 7
TCV
OS
5
µV/°C
dB
R
R
≤ 100KΩ
≤ 100KΩ
S
Initial Power Supply
Rejection Ratio 8
PSRR
80
i
S
Initial Common Mode
Rejection Ratio 8
CMRR
83
dB
R
R
≤ 100KΩ
=100KΩ
i
S
Large Signal Voltage Gain
A
32
20
100
V/mV
V/mV
V
L
0°C ≤ T ≤ +70°C
A
+
R =1MΩ V = 5V
L
0°C ≤ T ≤ +70°C
A
V
V
low
0.001
4.999
0.01
V
V
O
O
Output Voltage Range
high
4.99
2.40
V
V
low
-2.48
2.48
-2.40
V
V
R =100KΩ
L
0°C ≤ T ≤ +70°C
A
O
O
high
Output Short Circuit Current
I
1
mA
SC
* NOTES 1 through 9, see "Definitions and Design Notes" on page 6.
ALD1721E
Advanced Linear Devices
3 of 13
OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
T = 25oC V = ±2.5V unless otherwise specified
A
S
1721E
Typ
Parameter
Symbol
Min
Max
Unit
Test Conditions
Supply Current
I
S
120
200
µA
V
= 0V
IN
No Load
Power Dissipation
Input Capacitance
P
0.6
1
1.00
mW
pF
V = ±2.5V
S
D
C
C
IN
Maximum Load Capacitance
50
pF
L
Equivalent Input Noise Voltage
Equivalent Input Current Noise
Bandwidth
e
55
nV/√Hz
fA/√Hz
KHz
f = 1KHz
f =10Hz
n
i
n
0.6
700
0.7
B
S
400
0.3
W
R
Slew Rate
V/µs
A
= +1
V
R
= 10KΩ
L
Rise time
t
r
0.2
20
µs
R
= 10KΩ
L
Overshoot Factor
%
R
C
= 100KΩ,
L
L
= 50pF
Settling Time
t
s
10
µs
0.1%
A
= 1,R =100KΩ
V
L
C
= 50pF
L
T = 25oC V = ±2.5V unless otherwise specified
A
S
1721E
Typ
Parameter
Symbol
Min
Max
Unit
Test Conditions
Average Long Term Input Offset
Voltage Stability 9
∆ V
0.02
1.2
2.5
0.1
-5
µV/
OS
∆ time
1000 hrs
Initial VE Voltage
VE1 , VE2
V
i
i
Programmable VE Range
Programmed VE Voltage Error
VE Pin Leakage Current
∆VE1, ∆VE2
1.5
V
e(VE1-VE2)
%
µA
i
eb
ALD1721E
Advanced Linear Devices
4 of 13
OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
V = ±2.5V -55°C ≤ T ≤ +125°C unless otherwise specified
S
A
1721E
Typ
Parameter
Symbol
Min
Max
Unit
mV
nA
Test Conditions
Initial Input offset Voltage
Input Offset Current
Input Bias Current
V
0.5
R
S
≤ 100KΩ
OS i
I
I
2.0
2.0
OS
nA
B
Initial Power Supply
Rejection Ratio 8
PSRR
75
83
50
dB
R
S
R
S
R
L
R
L
≤ 100KΩ
≤ 100KΩ
= 100KΩ
= 100KΩ
i
Initial Common Mode
Rejection Ratio 8
CMRR
dB
i
Large Signal Voltage Gain
Output Voltage Range
A
15
V/mV
V
V
V
low
-2.47
2.45
-2.40
V
V
O
O
high
2.35
T = 25oC V = ±5.0V unless otherwise specified
A
S
1721E
Typ
Parameter
Symbol
PSRR
Min
Max
Unit
Test Conditions
Initial Power Supply
Rejection Ratio 8
83
dB
R
R
≤ 100KΩ
≤ 100KΩ
i
S
Initial Common Mode
Rejection Ratio 8
CMRR
83
dB
i
S
Large Signal Voltage Gain
Output Voltage Range
A
250
V/mV
V
R
R
= 100KΩ
= 100KΩ
V
L
V
V
low
-4.98
4.98
-4.90
O
O
L
high
4.90
Bandwidth
Slew Rate
B
S
1.0
1.0
MHz
W
R
V/µs
A
= +1, C = 50pF
V
L
ALD1721E
Advanced Linear Devices
5 of 13
DEFINITIONS AND DESIGN NOTES:
ADDITIONAL DESIGN NOTES:
1. Initial Input Offset Voltage is the initial offset voltage of the
ALD1721Eoperationalamplifierwhenshippedfromthefactory.
The device has been pre-programmed and tested for program-
mability.
A. The ALD1721E is internally compensated for unity gain
stability using a novel scheme which produces a single pole role
off in the gain characteristics while providing more than 70
degrees of phase margin at unity gain frequency. A unity gain
buffer using the ALD1721E will typically drive 50pF of external
load capacitance.
2. Offset Voltage Program Range is the range of adjustment of
user specified target offset voltage. This is typically an adjust-
ment in either the positive or the negative direction of the input
offsetvoltagefromaninitialinputoffsetvoltage. Theinputoffset
programming pins, VE1 or VE2, change the input offset voltage
in the negative or positive direction, respectively. User specified
target offset voltage can be any offset voltage within this
programming range.
B.TheALD1721Ehascomplementaryp-channelandn-channel
input differential stages connected in parallel to accomplish rail-
to-rail input common mode voltage range. The switching point
betweenthetwodifferentialstagesis1.5Vbelowpositivesupply
voltage. For applications such as inverting amplifiers or non-
invertingamplifierswithagainlargerthan2.5(5Voperation),the
common mode voltage does not make excursions below this
switching point. However, this switching does take place if the
operational amplifier is connected as a rail-to-rail unity gain
buffer and the design must allow for input offset voltage varia-
tions.
3. Programmed Input Offset Voltage Error is the final offset
voltage error after programming when the Input Offset Voltage
is at target Offset Voltage. This parameter is sample tested.
4. Total Input Offset Voltage is the same as Programmed Input
Offset Voltage, corrected for system offset voltage error. Usu-
ally this is an all inclusive system offset voltage, which also
includes offset voltage contributions from input offset voltage,
C. The output stage consists of class AB complementary output
drivers. The oscillation resistant feature, combined with the rail-
to-rail input and output feature, makes the ALD1721E an effec-
tive analog signal buffer for high source impedance sensors,
transducers, and other circuit networks.
PSRR, CMRR, TCV
and noise. It can also include errors
OS
introduced by external components, at a system level. Pro-
grammed Input Offset Voltage and Total Input Offset Voltage is
not necessarily zero offset voltage, but an offset voltage set to
compensate for other system errors as well. This parameter is
sample tested.
D. The ALD1721E has static discharge protection. However,
caremustbeexercisedwhenhandlingthedevicetoavoidstrong
static fields that may degrade a diode junction, causing in-
creasedinputleakagecurrents. Theuserisadvisedtopowerup
the circuit before, or simultaneously with, any input voltages
applied and to limit input voltages not to exceed 0.3V of the
power supply voltage levels.
5. The Input Offset and Bias Currents are essentially input
protection diode reverse bias leakage currents. This low input
bias current assures that the analog signal from the source will
not be distorted by it. For applications where source impedance
is very high, it may be necessary to limit noise and hum pickup
through proper shielding.
E. VE1 and VE2 are high impedance terminals, as the internal
biascurrentsaresetverylowtoafewmicroamperestoconserve
power. For some applications, these terminals may need to be
shielded from external coupling sources. For example, digital
signals running nearby may cause unwanted offset voltage
fluctuations. Care during the printed circuit board layout, to
place ground traces around these pins and to isolate them from
digital lines, will generally eliminate such coupling effects. In
addition, optional decoupling capacitors of 1000pF or greater
value can be added to VE1 and VE2 terminals.
6. Input Voltage Range is determined by two parallel comple-
mentary input stages that are summed internally, each stage
having a separate input offset voltage. While Total Input Offset
Voltage can be trimmed to a desired target value, it is essential
to note that this trimming occurs at only one user selected input
bias voltage. Depending on the selected input bias voltage
relative to the power supply voltages, offset voltage trimming
may affect one or both input stages. For the ALD1721E, the
switchingpointbetweenthetwostagesoccursatapproximately
1.5V below positive supply voltage.
F.TheALD1721Eisdesignedforuseinlowvoltage,micropower
circuits. The maximum operating voltage during normal opera-
tion should remain below 10V at all times. Care should be taken
toinsurethattheapplicationinwhichthedeviceisuseddoesnot
experience any positive or negative transient voltages that will
cause any of the terminal voltages to exceed this limit.
7. Input Offset Voltage Drift is the average change in Total Input
Offset Voltage as a function of ambient temperature. This
parameter is sample tested.
8. Initial PSRR and initial CMRR specifications are provided as
reference information. After programming, error contribution to
theoffsetvoltagefromPSRRandCMRRissettozerounderthe
specific power supply and common mode conditions, and
becomes part of the Programmed Input Offset Voltage Error.
G. All inputs or unused pins except VE1 and VE2 pins should be
connectedtoasupplyvoltagesuchasGroundsothattheydonot
becomefloatingpins,sinceinputimpedanceatthesepinsisvery
high. If any of these pins are left undefined, they may cause
unwanted oscillation or intermittent excessive current drain. As
thesedevicesarebuiltwithCMOStechnology,normaloperating
and storage temperature limits, ESD and latchup handling
precautions pertaining to CMOS device handling should be
observed.
9. Average Long Term Input Offset Voltage Stability is based on
input offset voltage shift through operating life test at 125°C
extrapolatedtoTA =25°C, assumingactivationenergyof1.0eV.
This parameter is sample tested.
ALD1721E
Advanced Linear Devices
6 of 13
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGE AND TEMPERATURE
OUTPUT VOLTAGE SWING AS A FUNCTION
OF SUPPLY VOLTAGE
±6
1000
-55°C ≤ T ≤ +125°C
A
±5
±4
R
= 100KΩ
L
100
±3
10
1
±2
±1
-55°C ≤ T ≤ +125°C
A
R
= 100KΩ
L
0
±1
±2
±3
±4
±5
±6
±7
0
±2
±4
±6
±8
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
1000
100
500
400
300
INPUTS GROUNDED
+25°C
OUTPUT UNLOADED
V
= ±2.5V
S
-25°C
10
T
= -55°C
A
1.0
200
100
0
0.1
+125°C
±5
+70°C
0.01
-50 -25
0
25
50
75
100
125
0
±1
±2
±3
±4
±6
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
ADJUSTMENT IN INPUT OFFSET VOLTAGE
AS A FUNCTION OF CHANGE IN VE1 AND VE2
OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF FREQUENCY
10
8
120
100
80
V
T
= ±2.5V
= 25°C
S
A
6
4
VE2
2
0
0
60
40
45
-2
-4
90
135
180
20
0
-6
-8
VE1
-10
-20
0.0
0.25
0.5
0.75
1.0
1.25 1.50
1
10
100
1K
10K 100K
1M
10M
FREQUENCY (Hz)
CHANGE IN VE1 AND VE2 (V)
ALD1721E
Advanced Linear Devices
7 of 13
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd)
COMMON MODE INPUT VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE
OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF LOAD RESISTANCE
1000
100
10
±7
±6
T
= 25°C
A
±5
±4
±3
±2
±1
0
V
T
= ±2.5V
= 25°C
S
A
1
0
±1
±2
±3
±4
±5
±6
±7
10K
100K
1M
10M
SUPPLY VOLTAGE (V)
LOAD RESISTANCE (Ω)
LARGE - SIGNAL TRANSIENT
RESPONSE
LARGE - SIGNAL TRANSIENT
RESPONSE
5V/div
V
T
R
= ±2.5V
S
2V/div
V
T
R
= ±1.0V
= 25°C
= 100KΩ
= 50pF
S
A
L
L
= 25°C
A
= 100KΩ
= 50pF
L
L
C
C
500mV/div
5µs/div
2V/div
5µs/div
SMALL - SIGNAL TRANSIENT
RESPONSE
DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE
BEFORE AND AFTER EPAD PROGRAMMING
100
80
EXAMPLE B:
AFTER EPAD
EXAMPLE A:
V AFTER EPAD
100mV/div
V
T
= ±2.5V
= 25°C
S
A
V
OST
PROGRAMMING
TARGET = -750µV
OST
PROGRAMMING
V TARGET = 0.0µV
OST
V
R
C
= 100KΩ
= 50pF
OST
L
L
60
40
V
BEFORE EPAD
OST
PROGRAMMING
20
0
20mV/div
2µs/div
-2500 -2000
-1500
-500
0
500
1000
1500
2000
2500
-1000
TOTAL INPUT OFFSET VOLTAGE (µV)
ALD1721E
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TYPICAL PERFORMANCE CHARACTERISTICS (cont'd)
TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
500
PSRR = 80 dB
400
300
200
EXAMPLE A:
EPAD PROGRAMMED
V
OS
AT V
= +5V
SUPPLY
EXAMPLE B:
EPAD
V
OS
PROGRAMMED
AT V
= +8V
SUPPLY
100
0
0
1
2
3
4
5
6
7
8
9
10
SUPPLY VOLTAGE (V)
THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE
500
400
V
= ±5V
SUPPLY
CMRR = 80dB
300
200
EXAMPLE B:
EPAD
EXAMPLE A:
V EPAD PROGRAMMED
V
OS
PROGRAMMED
OS
AT V = 0V
IN
AT V = -4.3V
IN
100
0
EXAMPLE C:
EPAD PROGRAMMED
V
OS
AT V = +5V
IN
-5
-4
-3
-1
0
1
2
3
4
5
-2
COMMON MODE VOLTAGE (V)
EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE
FOR A COMMON MODE VOLTAGE RANGE OF 0.5V
50
40
COMMON MODE VOLTAGE RANGE OF 0.5V
30
20
V
EPAD
OS
PROGRAMMED
AT COMMON MODE
VOLTAGE OF 0.25V
CMRR = 80dB
10
0
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
COMMON MODE VOLTAGE (V)
ALD1721E
Advanced Linear Devices
9 of 13
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd)
APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING
Examples of applications where accumulated total input offset voltage from various
contributing sources is minimized under different sets of user-specified operating conditions
2500
2000
1500
2500
2000
V
BUDGET AFTER
OS
1500
1000
500
0
EPAD PROGRAMMING
V
BUDGET AFTER
OS
1000
500
0
EPAD PROGRAMMING
+
X
-500
-500
+
X
-1000
-1000
V
BUDGET BEFORE
OS
-1500
-2000
-2500
-1500
-2000
-2500
EPAD PROGRAMMING
V
BUDGET BEFORE
OS
EPAD PROGRAMMING
EXAMPLE B
EXAMPLE A
2500
2000
1500
2500
2000
1500
V
OS
BUDGET AFTER
EPAD PROGRAMMING
V
BUDGET BEFORE
OS
1000
500
0
1000
500
0
EPAD PROGRAMMING
+
X
-500
-500
+
-1000
-1000
X
-1500
-2000
-2500
-1500
-2000
-2500
V
BUDGET AFTER
OS
V
BUDGET BEFORE
OS
EPAD PROGRAMMING
EPAD PROGRAMMING
EXAMPLE C
EXAMPLE D
Total Input V
after EPAD
Device input V
OS
OS
PSRR equivalent V
OS
Programming
+
CMRR equivalent V
OS
T
equivalent V
OS
A
X
Noise equivalent V
OS
External Error equivalent V
OS
ALD1721E
Advanced Linear Devices
10 of 13
SOIC-8 PACKAGE DRAWING
8 Pin Plastic SOIC Package
E
Millimeters
Inches
Dim
A
Min
Max
Min
Max
1.75
0.25
0.45
0.25
5.00
4.05
0.053
0.069
1.35
0.004
0.014
0.007
0.185
0.140
0.010
0.018
0.010
0.196
0.160
0.10
0.35
0.18
4.69
3.50
A
1
S (45°)
b
C
D-8
E
D
1.27 BSC
0.050 BSC
0.224
e
6.30
0.937
8°
0.248
0.037
8°
5.70
0.60
0°
H
0.024
0°
L
A
ø
S
0.50
0.010
0.020
0.25
A
1
e
b
S (45°)
C
H
L
ø
ALD1721E
Advanced Linear Devices
11 of 13
PDIP-8 PACKAGE DRAWING
8 Pin Plastic DIP Package
E
E
1
Millimeters
Inches
Dim
A
Min
Max
Min
Max
5.08
1.27
2.03
1.65
0.51
0.30
11.68
7.11
8.26
2.79
7.87
3.81
2.03
15°
0.105
0.200
3.81
0.015
0.050
0.035
0.015
0.008
0.370
0.220
0.300
0.090
0.290
0.110
0.040
0°
0.050
0.080
0.065
0.020
0.012
0.460
0.280
0.325
0.110
0.310
0.150
0.080
15°
0.38
1.27
0.89
0.38
0.20
9.40
5.59
7.62
2.29
7.37
2.79
1.02
0°
A
1
2
A
b
b
1
D
c
S
D-8
E
A
2
A
E
1
L
A
1
e
e
b
e
1
L
b
1
S-8
ø
c
ø
e
1
ALD1721E
Advanced Linear Devices
12 of 13
CERDIP-8 PACKAGE DRAWING
8 Pin CERDIP Package
E
E
1
Millimeters
Inches
Dim
A
Min
Max
Min
Max
5.08
0.140
0.200
3.55
1.27
0.97
0.36
0.20
--
D
A
1
2.16
1.65
0.58
0.38
10.29
7.87
8.26
0.050
0.038
0.014
0.008
--
0.085
0.065
0.023
0.015
0.405
0.310
0.325
b
b
1
C
A
1
s
D-8
E
5.59
7.73
0.220
0.290
A
E
1
e
L
1
0.100 BSC
0.300 BSC
L
2.54 BSC
7.62 BSC
3.81
L
2
e
1
b
b
L
5.08
--
0.150
0.200
--
1
L
L
3.18
0.38
--
0.125
0.015
--
1
2
e
1.78
2.49
15°
0.070
0.098
15°
S
Ø
0°
0°
C
ø
e
1
ALD1721E
Advanced Linear Devices
13 of 13
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