ALD1722ESA [ALD]
EPAD⑩ OPERATIONAL AMPLIFIER; EPAD ™运算放大器
| 型号： | ALD1722ESA |
| 厂家： | 
ADVANCED LINEAR DEVICES |
| 描述： | EPAD⑩ OPERATIONAL AMPLIFIER |
| 文件： | 总10页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A
L
D
DVANCED
INEAR
EVICES, INC.
ALD1722E/ALD1722
EPAD™ OPERATIONAL AMPLIFIER
BENEFITS
KEY FEATURES
• Eliminates manual and elaborate
system trimming procedures
• Remote controlled automated trimming
• In-System Programming capability
• No external components
• No internal chopper clocking noise
• No chopper dynamic power dissipation
• Simple and cost effective
• Small package size
• EPAD ( Electrically Programmable Analog Device)
• User programmable V
trimmer
• Computer-assisted trimming
• Rail-to-rail input/output
• Compatible with standard EPAD Programmer
• High precision through in-situ circuit precision trimming
OS
• Reduce or eliminate V , PSRR, CMRR and TCV
errors
OS
OS
• System level “calibration” capability
• In-System Programming capable
• Extremely small total functional
volume size
• Electrically programmable to compensate for external
component tolerances
• Low system implementation cost
• Low power
• Achieve 0.01pA input bias current and 25µV
input offset voltage simultaneously
• Compatible with industry standard pinout
APPLICATIONS
GENERAL DESCRIPTION
The ALD1722E/ALD1722 is a monolithic rail-to-rail precision CMOS
operational amplifier with integrated user programmable EPAD (Electri-
callyProgrammableAnalogDevice)basedoffsetvoltageadjustment. The
ALD1722E/ALD1722 is a direct replacement of the ALD1702 operational
amplifier, with the added feature of user-programmable offset voltage
trimming resulting in significantly enhanced total system performance and
user flexibility. EPAD technology is an exclusive ALD design which has
been refined for analog applications where precision voltage trimming is
necessary to achieve a desired performance. It utilizes CMOS FETs as
in-circuit elements for trimming of offset voltage bias characteristics with
the aid of a personal computer under software control. Once pro-
grammed,thesetparametersarestoredindefinitelywithinthedeviceeven
afterpower-down. EPADoffersthecircuitdesigneraconvenientandcost-
effective trimming solution for achieving the very highest amplifier/system
performance.
• Sensor interface circuits
• Transducer biasing circuits
• Capacitive and charge integration circuits
• Biochemical probe interface
• Signal conditioning
• Portable instruments
• High source impedance electrode
amplifiers
• Precision Sample and Hold amplifiers
• Precision current to voltage converter
• Error correction circuits
• Sensor compensation circuits
• Precision gain amplifiers
• Periodic In-system calibration
• System output level shifter
The ALD1722E/ALD1722 operational amplifier features rail-to-rail input
and output voltage ranges, tolerance to over-voltage input spikes of
300mV beyond supply rails, high capacitive loading up to 4000pF, ex-
tremely low input currents of 0.01pA typical, high open loop voltage gain,
useful bandwidth of 1.5 MHz, slew rate of 2.1 V/µs, and low supply current
of 0.8mA.
PIN CONFIGURATION
VE1
-IN
1
8
7
6
5
VE2
ORDERING INFORMATION
Operating Temperature Range*
+
V
2
-55°C to +125°C
0°C to +70°C
0°C to +70°C
+IN
3
4
OUT
N/C
8-Pin
8-Pin
8-Pin
CERDIP
Small Outline
Plastic Dip
-
V
Package
Package (SOIC)
Package
TOP VIEW
DA, PA, SA PACKAGE
ALD1722E DA
ALD1722 DA
ALD1722E SA
ALD1722 SA
ALD1722E PA
ALD1722 PA
* Contact factory for industrial temperature range
ALD1722E/ALD1722
Advanced Linear Devices
1
FUNCTIONAL DESCRIPTION
Functional Description of ALD1722
The ALD1722E/ALD1722 uses EPADs as in-circuit ele-
ments for trimming of offset voltage bias characteristics.
Each ALD1722E/ALD1722 has a pair of EPAD-based cir-
The ALD1722 is pre-programmed at the factory under stan-
dard operating conditions for minimum equivalent input off-
set voltage.
The ALD1722 offers similar programmable
cuits connected such that one circuit is used to adjust V
OS
features as the ALD1722E, but with more limited offset
voltage program range. It is intended for standard opera-
tional amplifier applications where little or no electrical pro-
gramming by the user is necessary.
in one direction and the other is used to adjust V
other direction.
in the
OS
Functional Description of ALD1722E
While each of the EPAD devices is a monotonically adjust-
able programmable device, the V of the ALD1722E can
USER PROGRAMMABLE Vos FEATURE
OS
be adjusted many times in both directions. Once pro-
grammed, the set V levels are stored permanently, even
Each ALD1722E/ALD1722 has two pins named VE1 and
VE2 which are internally connected to an internal offset bias
circuit. VE1/VE2 have initial typical values of 1.6 Volt. The
voltage on these pins can be programmed using the ALD
E100 EPAD Programmer and the appropriate Adapter Mod-
ule. The useful programming range of VE1 and VE2 is 1.6
Volt to 3.5 Volts. VE1 and VE2 pins are programming pins,
used during programming mode. The Programming pin is
used during electrical programming to inject charge into the
internal EPADs. Increases of VE1 decrease the offset volt-
age while increases of VE2 increase the offset voltage of the
operational amplifier. The injected charge is permanently
stored and determines the offset voltage of the operational
amplifier. After programming, VE1 and VE2 terminals must
be left open to settle on a voltage determined by internal bias
currents.
OS
when the device power is removed.
The ALD1722E provides the user with an operational ampli-
fier that can be trimmed with user application-specific pro-
gramming or in-system programming conditions. User appli-
cation-specific circuit programming refers to the situation
where the Total Input Offset Voltage of the ALD1722E can
be trimmed with the actual intended operating conditions.
The ALD1722E is pre-programmed at the factory under
standard operating conditions for minimum equivalent input
offset voltage. It also has a guaranteed offset voltage
program range, which is ideal for applications that require
electrical offset voltage programming.
For example, an application circuit may have +6V and -2.5V
power supplies, and the operational amplifier input is biased
at +0.7V, and the average operating temperature is at 55°C.
The circuit can be wired up to these conditions within an
environmental chamber, and the ALD1722E can be inserted
into a test socket connected to this circuit while it is being
During programming, the voltages on VE1 or VE2 are
increased incrementally to set the offset voltage of the
operational amplifier to the desired V . Note that desired
OS
V
can be any value within the offset voltage program-
OS
mable ranges, and can be either zero, a positive value or a
negative value. This V value can also be reprogrammed
electrically trimmed. Any error in V
due to these bias
OS
conditions can be automatically zeroed out. The Total V
OS
to a different value at a later time, provided that the useful
VE1 or VE2 programming voltage range has not been
exceeded. VE1 or VE2 pins can also serve as capacitively
coupled input pins.
OS
error is now limited only by the adjustable range and the
stabilityofV , andtheinputnoisevoltageoftheoperational
OS
amplifier. Therefore, this Total V
OS
as V is traditionally specified; plus the V
error now includes V
OS
error contribu-
OS
OS
tions from PSRR, CMRR, TCV , and noise. Typically this
Internally, VE1 and VE2 are programmed and connected
differentially. Temperature drift effects between the two
internal offset bias circuits cancel each other and introduce
less net temperature drift coefficient change than offset
voltage trimming techniques such as offset adjustment with
an external trimmer potentiometer.
OS
) is approximately ± 25µV for the
total V
error term (V
OS
ALD1722E.
OST
The V contribution due to PSRR, CMRR, TCV
and
OS
OS
external components can be large for operational amplifiers
without trimming. Therefore the ALD1722E with EPAD trim-
ming is able to provide much improved system performance
by reducing these other sources of error to provide signifi-
While programming, V+, VE1 and VE2 pins may be alter-
nately pulsed with 12V (approximately) pulses generated by
the EPAD Programmer. In-system programming requires
the ALD1722E/ALD1722 application circuit to accommo-
date these programming pulses. This can be accomplished
by adding resistors at certain appropriate circuit nodes. For
more information, see Application Note AN1700.
cantly reduced V
OST.
In-System Programming refers to the condition where the
EPAD adjustment is made after the ALD1722E has been
inserted into a circuit board. In this case, the circuit design
must provide for the ALD1722E to operate in normal mode
and in programming mode. One of the benefits of in-system
programming is that not only is the ALD1722E offset voltage
from operating bias conditions accounted for, any residual
errors introduced by other circuit components, such as
resistor or sensor induced voltage errors, can also be cor-
rected. In this way, the “in-system” circuit output can be
adjusted to a desired level eliminating other trimming com-
ponents.
2
Advanced Linear Devices
ALD1722E/ALD1722
ABSOLUTE MAXIMUM RATINGS
+
Supply voltage, V
13.2V
+
Differential input voltage range
Power dissipation
-0.3V to V +0.3V
600 mW
Operating temperature range PA,SA package
DA package
Storage temperature range
Lead temperature, 10 seconds
0°C to +70°C
-55°C to +125°C
-65°C to +150°C
+260°C
OPERATING ELECTRICAL CHARACTERISTICS
T = 25oC V = ±2.5V unless otherwise specified
A
S
1722E
Typ
1722
Typ
Parameter
Symbol
Min
Max
Min
Max
Unit
Test Conditions
Supply Voltage
V
V
±2.0
±5.0
±2.0
±5.0
V
V
S
+
4.0
10.0
4.0
10.0
Single Supply
Initial Input Offset Voltage1
V
25
±8
25
50
40
±3
40
90
µV
mV
µV
R ≤ 100KΩ
S
OS i
Offset Voltage Program Range 2
∆V
±5
±0.5
OS
Programmed Input Offset
Voltage Error3
V
V
I
50
50
90
90
At user specified
OS
target offset voltage
Total Input Offset Voltage 4
Input Offset Current5
Input Bias Current5
25
0.01
0.01
40
0.01
0.01
µV
At user specified
OST
target offset voltage
10
10
pA
pA
T
A
= 25°C
OS
280
280
0°C ≤ T ≤ +70°C
A
I
B
10
10
pA
pA
T
A
= 25°C
280
280
0°C ≤ T ≤ +70°C
A
Input Voltage Range 6
V
-0.3
-2.8
5.3
-0.3
-2.8
5.3
V
V
V
V
= +5V; notes 2,5
+
IR
+2.8
+2.8
= ±2.5V
S
14
10
14
10
Input Resistance
R
Ω
IN
Input Offset Voltage Drift 7
TCV
OS
5
7
µV/°C
dB
R
R
≤ 100KΩ
≤ 100KΩ
S
S
Initial Power Supply
Rejection Ratio 8
PSRR
85
85
i
Initial Common Mode
Rejection Ratio 8
CMRR
97
97
dB
R
≤ 100KΩ
i
S
Large Signal Voltage Gain
A
50
250
500
50
250
500
V/mV
V/mV
R
R
=10KΩ
≥ 1MΩ
V
L
L
+
=1MΩ V = 5V
V
V
V
V
low
0.002
4.998
-2.44
2.44
0.01
0.002
4.998
-2.44
2.44
0.01
V
V
V
V
R
O
O
O
O
L
high
low
4.99
2.35
4.99
2.35
0°C ≤ T ≤ +70°C
A
R =10KΩ
L
0°C ≤ T ≤ +70°C
A
Output Voltage Range
-2.35
-2.35
high
Output Short Circuit Current
I
8
8
mA
SC
* NOTES 1 through 9, see section titled "Definitions and Design Notes".
ALD1722E/ALD1722
Advanced Linear Devices
3
OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
T = 25oC V = ±2.5V unless otherwise specified
A
S
1722E
Typ
1722
Typ
Parameter
Symbol
Min
Max
Min
Max
Unit
Test Conditions
Supply Current
I
S
0.8
1.5
0.8
1.5
mA
V
= 0V
IN
No Load
Power Dissipation
P
4.0
1
7.5
4.0
1
7.5
mW
pF
V
= ±2.5V
S
D
Input Capacitance
C
C
IN
L
Maximum Load Capacitance
400
400
pF
pF
Gain = 1
Gain = 5
4000
4000
Input Noise Voltage
Input Current Noise
Bandwidth
e
26
0.6
1.5
2.1
26
0.6
1.5
2.1
nV/√ Hz f = 1KHz
fA/√ Hz f =10Hz
MHz
n
i
n
B
S
1.0
1.4
1.0
1.4
W
R
Slew Rate
V/µs
A
= +1
V
R
= 10KΩ
L
Rise time
t
r
0.2
10
0.2
10
µs
R
= 10KΩ
L
Overshoot Factor
%
R
C
= 10KΩ,
L
L
= 100pF
Settling Time
t
s
8.0
3.0
8.0
3.0
µs
µs
0.01%
0.1%
A
= -1, R = 5KΩ
V
L
C
= 50pF
L
T = 25oC V = ±2.5V unless otherwise specified
A
S
1722E
Typ
1722
Typ
Parameter
Symbol
Min
Max
Min
Max
Unit
Test Conditions
Average Long Term Input Offset
Voltage Stability 9
∆ V
0.02
1.6
2.0
-5
0.02
2.6
0.5
-5
µV/
OS
∆ time
1000 hrs
Initial VE Voltage
VE1
VE2
V
i
i
Programmable VE Range
VE Pin Leakage Current
∆VE1
∆VE2
1.5
V
i
µA
eb
4
Advanced Linear Devices
ALD1722E/ALD1722
V = ±2.5V -55°C ≤ T ≤ +125°C unless otherwise specified
S
A
1722E
Typ
1722
Typ
Parameter
Symbol
Min
Max
Min
Max
Unit
mV
nA
Test Conditions
Initial Input Offset Voltage
Input Offset Current
Input Bias Current
V
0.5
0.7
R
≤ 100KΩ
OS i
S
I
I
2.0
2.0
2.0
2.0
OS
nA
B
Initial Power Supply
Rejection Ratio 8
PSRR
CMRR
85
97
25
85
97
25
dB
R
R
≤ 100KΩ
≤ 100KΩ
i
S
S
Initial Common Mode
RejectionRatio 8
dB
i
Large Signal Voltage Gain
Output Voltage Range
A
10
10
V/mV
R
R
≤ 10KΩ
≤ 10KΩ
V
L
L
V
V
low
-2.4
2.4
-2.3
-2.4
2.4
-2.3
V
V
O
O
high
2.3
2.3
T = 25oC V = ±5.0V unless otherwise specified
A
S
1722E
Typ
1722
Typ
Parameter
Symbol
PSRR
Min
Max
Min
Max
Unit
Test Conditions
Initial Power Supply
Rejection Ratio 8
85
85
dB
R
≤ 100KΩ
i
S
Initial Common Mode
Rejection Ratio 8
CMRR
97
97
dB
R
≤ 100KΩ
i
S
Large Signal Voltage Gain
Output Voltage Range
A
250
250
V/mV
V
R
R
= 10KΩ
= 10KΩ
V
L
L
V
low
high
-4.90
4.93
-4.80
-4.90
4.93
-4.80
O
V
O
4.80
4.80
Bandwidth
Slew Rate
B
1.7
2.8
1.7
MHz
W
S
R
2.8
V/µs
A
= +1, C = 50pF
L
V
ALD1722E/ALD1722
Advanced Linear Devices
5
TYPICAL PERFORMANCE CHARACTERISTICS
COMMON MODE INPUT VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE
OPEN LOOP VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGE AND TEMPERATURE
±7
±6
1000
}
-55°C
+25°C
T
= 25°C
A
±5
±4
}
100
}
+125°C
±3
±2
±1
0
10
1
R = 10KΩ
R = 5KΩ
L
L
0
±1
±2
±3
±4
±5
±6
±7
0
±2
±4
±6
±8
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
1000
100
2.5
2.0
INPUTS GROUNDED
OUTPUT UNLOADED
V
S
= ±2.5V
10
T
A
= -55ºC
1.5
1.0
0.5
0
1.0
-25°C
+25°C
+80°C
+125°C
0.1
0.01
-50 -25
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
0
±1
±2
±3
±4
±5
±6
SUPPLY VOLTAGE (V)
CHANGE IN INPUT OFFSET VOLTAGE AS
A FUNCTION OF CHANGE IN VE1 AND VE2
OPEN LOOP VOLTAGE AS A
FUNCTION OF FREQUENCY
5
4
3
2
120
100
80
VE2
V
T
= ±2.5V
= 25°C
S
A
1
0
0
60
40
45
-1
-2
90
135
180
20
0
-3
-4
-5
VE1
-20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
1
10
100
1K
10K 100K
1M
10M
CHANGE IN VE1 AND VE2 (V)
FREQUENCY (Hz)
6
Advanced Linear Devices
ALD1722E/ALD1722
TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT VOLTAGE SWING AS A
FUNCTION OF SUPPLY VOLTAGE
LARGE - SIGNAL TRANSIENT
RESPONSE
±7
±6
5V/div
±25°C ≤ T ≤ 125°C
A
V
T
R
C
= ±2.5V
= 25°C
= 10KΩ
= 50pF
S
A
L
L
±5
R
L
= 10KΩ
±4
±3
±2
R
L
= 2KΩ
2µs/div
1V/div
±4
SUPPLY VOLTAGE (V)
0
±1
±2
±3
±5
±6
±7
OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF LOAD RESISTANCE
SMALL - SIGNAL TRANSIENT
RESPONSE
1000
100
10
V
T
R
C
= ±2.5V
= 25°C
= 10KΩ
= 50pF
100mV/div
S
A
L
L
V
T
= ±2.5V
= 25°C
S
A
20mV/div
2µs/div
1
1K
10K
100K
1000K
LOAD RESISTANCE (Ω)
DISTRIBUTION OF TOTAL INPUT OFFSET VOLTAGE
BEFORE AND AFTER EPAD PROGRAMMING
100
80
EXAMPLE B:
AFTER EPAD
EXAMPLE A:
V AFTER EPAD
V
OST
PROGRAMMING
TARGET = -750µV
OST
PROGRAMMING
V TARGET = 0.0µV
OST
V
OST
60
40
V
BEFORE EPAD
OST
PROGRAMMING
20
0
-2500 -2000
-1500
-500
0
500
1000
1500
2000
2500
-1000
TOTAL INPUT OFFSET VOLTAGE (µV)
ALD1722E/ALD1722
Advanced Linear Devices
7
TWO EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN SUPPLY VOLTAGE vs. SUPPLY VOLTAGE
500
400
PSRR = 80 dB
EXAMPLE A:
EPAD PROGRAMMED
V
OS
AT V
= +5V
SUPPLY
300
200
EXAMPLE B:
EPAD
V
OS
PROGRAMMED
AT V
= +8V
SUPPLY
100
0
0
1
2
3
4
5
6
7
8
9
10
SUPPLY VOLTAGE (V)
THREE EXAMPLES OF EQUIVALENT INPUT OFFSET VOLTAGE DUE TO
CHANGE IN COMMON MODE VOLTAGE vs. COMMON MODE VOLTAGE
500
400
V
= ±5V
SUPPLY
CMRR = 80dB
300
200
EXAMPLE B:
EPAD
EXAMPLE A:
V EPAD PROGRAMMED
V
OS
PROGRAMMED
OS
AT V = 0V
IN
AT V = -4.3V
IN
100
0
EXAMPLE C:
EPAD PROGRAMMED
V
OS
AT V = +5V
IN
-5
-4
-3
-1
0
1
2
3
4
5
-2
COMMON MODE VOLTAGE (V)
EXAMPLE OF MINIMIZING EQUIVALENT INPUT OFFSET VOLTAGE
FOR A COMMON MODE VOLTAGE RANGE OF 0.5V
50
40
COMMON MODE VOLTAGE RANGE OF 0.5V
30
20
V
EPAD
OS
PROGRAMMED
AT COMMON MODE
VOLTAGE OF 0.25V
CMRR = 80dB
10
0
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
COMMON MODE VOLTAGE (V)
8
Advanced Linear Devices
ALD1722E/ALD1722
APPLICATION SPECIFIC / IN-SYSTEM PROGRAMMING
Examples of applications where accumulated total input offset voltage from various
contributing sources is minimized under different sets of user-specified operating conditions
2500
2000
1500
2500
2000
V
BUDGET AFTER
OS
1500
1000
500
0
EPAD PROGRAMMING
V
BUDGET AFTER
OS
1000
500
0
EPAD PROGRAMMING
+
X
-500
-500
+
X
-1000
-1000
V
BUDGET BEFORE
OS
-1500
-2000
-2500
-1500
-2000
-2500
EPAD PROGRAMMING
V
BUDGET BEFORE
OS
EPAD PROGRAMMING
EXAMPLE B
EXAMPLE A
2500
2000
1500
2500
2000
1500
V
BUDGET AFTER
OS
EPAD PROGRAMMING
V
BUDGET BEFORE
OS
1000
500
0
1000
500
0
EPAD PROGRAMMING
+
X
-500
-500
+
-1000
-1000
X
-1500
-2000
-2500
-1500
-2000
-2500
V
BUDGET AFTER
OS
V
BUDGET BEFORE
OS
EPAD PROGRAMMING
EPAD PROGRAMMING
EXAMPLE D
EXAMPLE C
Total Input V
after EPAD
Device input V
OS
OS
PSRR equivalent V
OS
Programming
+
CMRR equivalent V
OS
T
equivalent V
A
OS
X
Noise equivalent V
OS
External Error equivalent V
OS
ALD1722E/ALD1722
Advanced Linear Devices
9
DEFINITIONS AND DESIGN NOTES:
ADDITIONAL DESIGN NOTES:
1. Initial Input Offset Voltage is the offset voltage of the
ALD1722E/ALD1722 operational amplifier as shipped from the
factory. The device has been pre-programmed and tested for
programmability.
A. The ALD1722E/ALD1722 is internally compensated for unity
gainstabilityusinganovelschemewhichproducesasinglepole
role off in the gain characteristics while providing more than 70
degrees of phase margin at unity gain frequency. A unity gain
buffer using the ALD1722E/ALD1722 will typically drive 400pF
of external load capacitance; in the inverting unity gain configu-
ration, it can drive up to 800pF of load capacitance.
2. Offset Voltage Program Range is the range of adjustment of
user specified target offset voltage. This is typically an adjust-
ment in either the positive or the negative direction of the input
offset voltage from an initial offset voltage. The input offset
programpins, VE1orVE2, changetheinputoffsetvoltageinthe
negativeorpositivedirection,respectively.Userspecifiedtarget
offset voltage can be any offset voltage within this programming
range.
B. The ALD1722E/ALD1722 has complementary p-channel
and n-channel input differential stages connected in parallel to
accomplish rail to rail input common mode voltage range. The
switching point between the two differential stages is 1.5V
above negative supply voltage. For applications such as invert-
ingamplifierornon-invertingamplifierwithagainlargerthan2.5
(5V operation), the common mode voltage does not make
excursions below this switching point. However, this switching
doestakeplaceiftheoperationalamplifierisconnectedasarail-
to-railunitygainbufferandthedesignmustallowforinputoffset
voltage variations.
3. Programmed Input Offset Voltage Error is the final offset
voltage error after programming, when the Input Offset Voltage
is at target Offset Voltage. This parameter is sample tested.
4. Total Input Offset Voltage is the same as Programmed Input
Offset Voltage, corrected for system offset voltage error. Usu-
ally this is an all inclusive system offset voltage, which also
includes offset voltage contributions from input offset voltage,
PSRR, CMRR, TCVos and noise. It can also include errors
introduced by external components, at a system level. Pro-
grammed Input Offset Voltage and Total Input Offset Voltage is
not necessarily zero offset voltage, but an offset voltage set to
compensate for other system errors as well. This parameter is
sample tested.
C. The output stage consists of class AB complementary output
drivers. The oscillation resistant feature, combined with the rail-
to-railinputandoutputfeature, makestheALD1722E/ALD1722
an effective analog signal buffer for high source impedance
sensors, transducers, and other circuit networks.
D. The ALD1722E/ALD1722 has static discharge protection.
However, care must be exercised when handling the device to
avoid strong static fields that may degrade a diode junction,
causing increased input leakage currents. The user is advised
to power up the circuit before, or simultaneously with, any input
voltages applied and to limit input voltages to not exceed 0.3V
of the power supply voltage levels.
5. The Input Offset and Bias Currents are essentially input
protection diode reverse bias leakage currents. This low input
bias current assures that the analog signal from the source will
not be distorted by it. For applications where source impedance
is very high, it may be necessary to limit noise and hum pickup
through proper shielding.
E. VE1 and VE2 are high impedance terminals, as the internal
bias currents are set very low to a few microamperes to
conserve power. For some applications, these terminals may
need to be shielded from external coupling sources. For ex-
ample, digital signals running nearby may cause unwanted
offset voltage fluctuations. Care during the printed circuit board
layout to place ground traces around these pins and to isolate
them from digital lines would generally eliminate such coupling
effects. In addition, optional decoupling capacitors of 1000pF or
greater value can be added to VE1 and VE2 terminals.
6. Input Voltage Range is determined by two parallel comple-
mentary input stages that are summed internally, each stage
having a separate input offset voltage. While Total Input Offset
Voltage can be trimmed to a desired target value, it is essential
to note that this trimming occurs at only one selected input bias
voltage. Dependingontheselectedinputbiasvoltagerelativeto
the power supply voltages, offset voltage trimming may affect
one or both input stages. For the ALD1722E/ALD1722, the
switching point between the two stages occur at approximately
1.5V above the negative supply voltage
F. The ALD1722E/ALD1722 is designed for use in low voltage,
micro-power circuits. The maximum operating voltage during
normaloperationshouldremainbelow10Voltsatalltimes.Care
should be taken to insure that the application in which the
devices are used would not experience any positive or negative
transient voltages that cause any of the terminal voltages to
exceed this limit.
7. Input Offset Voltage Drift is the average change in Total Input
Offset Voltage as a function of ambient temperature. This
parameter is sample tested.
8. Initial PSRR and initial CMRR specifications are provided as
reference information. After programming, error contribution to
theoffsetvoltagefromPSRRandCMRRissettozerounderthe
specific power supply and common mode conditions, and
becomes part of the Programmed Input Offset Voltage Error.
G. All inputs or unused pins except VE1 and VE2 pins should be
connected to a supply voltage such as Ground so that they do
not become floating pins, since input impedance at these pins
is very high. If any of these pins are left undefined, they may
cause unwanted oscillation or intermittent excessive current
drain. As these devices are built with CMOS technology, normal
operating and storage temperature limits, ESD and latchup
handling precautions pertaining to CMOS device handling
should be observed.
9. Average Long Term Input Offset Voltage Stability is based on
input offset voltage shift through operating life test at 125
degrees C extrapolated to Ta = 25 degrees C, assuming
activation energy of 1.0eV. This parameter is sample tested.
10
Advanced Linear Devices
ALD1722E/ALD1722
相关型号：
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