AKD4632-A [AKM]
AK4632 Evaluation board Rev.0; AK4632评估板Rev.0
| 型号： | AKD4632-A |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | AK4632 Evaluation board Rev.0 |
| 文件： | 总48页 (文件大小：654K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AKD4632-A]
AKD4632-A
AK4632 Evaluation board Rev.0
GENERAL DESCRIPTION
AKD4632-A is an evaluation board for the AK4632, 16bit mono CODEC with MIC/SPK/VIDEO amplifier.
The AKD4632-A can evaluate A/D converter and D/A converter separately in addition to loopback mode
(A/D → D/A). AKD4632-A also has the digital audio interface and can achieve the interface with digital
audio systems via opt-connector.
Ordering guide
AKD4632-A
---Evaluation board for AK4632
(Cable for connecting with printer port of IBM-AT, compatible PC and control
software are packed with this. This control software does not support Windows NT.)
FUNCTION
• DIT/DIR with optical input/output
• BNC connector for an external clock input
• 10pin Header for serial control mode
AVDD DVDD SVDD VVDD GND
5V
3.3V
Regulator
Control Data
10pin Header
MIC-Jack
MIC
DSP
BEEP/MIN/MOUT
AOUT
AK4632
10pin Header
SPK-Jack
VIN
Opt In
Opt Out
AK4114
VOUT
Clock
Gen
Figure 1. AKD4632-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
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[AKD4632-A]
Evaluation Board Manual
Operation sequence
1) Set up the power supply lines.
1-1) When AVDD, DVDD, SVDD, VVDD and VCC are supplied from the regulator. (AVDD, DVDD, SVDD,
VVDD and VCC jack should be open.). See “Other jumper pins set up (page 10)”. <default>
[REG]
(red )
= 5V
[AVDD] (orange)
[DVDD] (orange)
[SVDD] (blue)
[VVDD] (blue)
= open
= open
= open
= open
= open
= 0V
: 3.3V is supplied to AVDD of AK4632 from regulator.
: 3.3V is supplied to DVDD of AK4632 from regulator.
: 3.3V is supplied to SVDD of AK4632 from regulator.
: 3.3V is supplied to VVDD of AK4632 from regulator.
: 3.3V is supplied to logic block from regulator.
: for analog ground
[VCC]
(orenge)
[AVSS] (black)
[AGND] (black)
[DGND] (black)
= 0V
= 0V
: for analog ground
: for logic ground
1-2) When AVDD, DVDD, SVDD, VVDD and VCC are not supplied from the regulator. (AVDD, DVDD,
SVDD, VVDD and VCC jack should be junction.) See “Other jumper pins set up (page 10)”.
[REG]
(red)
= “REG” jack should be open.
[AVDD] (orange)
[DVDD] (orange)
[SVDD] (blue)
[VVDD] (blue)
= 2.6 ∼ 3.6V : for AVDD of AK4632 (typ. 3.3V)
= 2.6 ∼ 3.6V : for DVDD of AK4632 (typ. 3.3V)
= 2.6 ∼ 5.25V: for SVDD of AK4632 (typ. 3.3V, 5.0V)
= 2.6 ∼ 5.25V: for VVDD of AK4632 (typ. 3.3V, 5.0V)
= 2.6 ∼ 3.6V : for logic (typ. 3.3V)
[VCC]
(orenge)
[AVSS] (black)
[AGND] (black)
[DGND] (black)
= 0V
= 0V
= 0V
: for analog ground
: for analog ground
: for logic ground
Each supply line should be distributed from the power supply unit.
AVDD and DVDD must be same voltage level.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4632 and AK4114 should be reset once bringing SW1, 2 “L” upon power-up.
Evaluation mode
In case of AK4632 evaluation using AK4114, it is necessary to correspond to audio interface format for
AK4632 and AK4114. About AK4632’s audio interface format, refer to datasheet of AK4632. About
AK4114’s audio interface format, refer to Table 2 in this manual.
Applicable Evaluation Mode
(1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode (Default)
(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI
pin)
→
(3) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or
FCK pin)
(4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode
(5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode
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ASAHI KASEI
[AKD4632-A]
→
(1) Evaluation of loop-back mode (A/D
D/A) : PLL, Master Mode (Default)
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4632 should be set to “0”.
X’tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can be set in X1. X’tal of 12.288MHz
(Default) is set on the AKD4632-A. Set “No.8 of SW3” to “H”.
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) through a RCA
connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1)
and R26 should be properly selected in order to much the output impedance of the clock generator.
JP6
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
MCKI
XTL
EXT 256fs 512fs
1024fs MCKO
DIR
b) Set up jumper pins of BICK clock
Output frequency (16fs/32fs/64fs) of BICK should be set by “BCKO1-0 bit” in the AK4632.
There is no necessity for set up JP19.
JP29
BICK_INV
JP19
BICK_SEL
JP20
BICK
JP27
BICK
DIR ADC
INV THR
INV
THR
64fs
16fs
EXT
32fs
c) Set up jumper pins of FCK clock
JP28
FCK
JP22
FCK_SEL
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4632 is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following.
JP30
SDTI
JP26
4632_SDTI
ADC
ADC
DAC/LOOP
DIR
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ASAHI KASEI
[AKD4632-A]
(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin)
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4632 should be set to “0”.
X’tal of 12.288MHz (Default) is set on the AKD4632-A. In this case, the AK4632 corresponds to PLL reference
clock of 12.288MHz. In this evaluation mode, the output clock from MCKO-pin of the AK4632 is supplied to a
divider (U3: 74VHC4040), BICK and FCK clocks are generated by the divider. Then “MCKO bit” in the
AK4632 is set to “1”. When an external clock through a RCA connector (J8: EXT/BICK) is supplied, select
EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order
to much the output impedance of the clock generator.
JP6
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
MCKI
XTL
EXT 256fs 512fs
1024fs MCKO
DIR
b) Set up jumper pins of BICK clock
JP29
BICK_INV
JP19
BICK_SEL
JP20
BICK
JP27
BICK
DIR ADC
INV THR
INV
THR
64fs
16fs
EXT
32fs
c) Set up jumper pins of FCK clock
JP22
FCK_SEL
JP28
FCK
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4632 is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following.
JP30
SDTI
JP26
4632_SDTI
ADC
ADC
DAC/LOOP
DIR
<KM075602>
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ASAHI KASEI
[AKD4632-A]
→
(3) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or FCK
pin)
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4632 should be set to “1”. JP6 (MCKI) should be open.
b) Set up jumper pins of BICK clock
When an external clock through a RCA connector J8 (EXT/BICK) is supplied, select EXT on JP19
(MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to much the
output impedance of the clock generator.
JP29
BICK_INV
JP17
XTE
JP20
BICK
JP27
BICK
JP21
MCLK_SEL
XTL
EXT
DIR
DIR ADC
INV THR
INV
THR
In this evaluation mode, the selected clock from JP21 (MCLK_SEL) is supplied to a divider (U3: 74VHC4040),
BICK and FCK clocks are generated by the divider. Input frequency of master clock is set up in turn “256fs”,
“512fs”, “1024fs” from left.
JP18
JP18
JP18
MKFS
MKFS
MKFS
256fs
512fs
1024fs MCKO
256fs 512fs
256fs 512fs
1024fs MCKO
1024fs MCKO
And input frequency of BICK is set up in turn “16fs”, “32fs”, “64fs” from left.
JP19
JP19
JP19
BICK_SEL
BICK_SEL
BICK_SEL
64fs 32fs 16fs EXT
64fs 32fs 16fs EXT
64fs 32fs 16fs EXT
<KM075602>
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ASAHI KASEI
[AKD4632-A]
c) Set up jumper pins of FCK clock
When an external clock through a RCA connector J9 (FCK) is supplied, select EXT on JP22 (FCK_SEL). JP24
(EXT2) and R27 should be properly selected in order to much the output impedance of the clock generator.
JP22
JP28
FCK_SEL
FCK
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4632 is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the following.
JP30
SDTI
JP26
4632_SDTI
ADC
ADC
DAC/LOOP
DIR
<KM075602>
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ASAHI KASEI
[AKD4632-A]
(4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4632 should be set to “0”.
JP6
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
MCKI
256fs
512fs1024fs
XTL
EXT
DIR
b) Set up jumper pins of BICK clock
JP19
BICK_SEL
JP29
BICK_INV
JP20
BICK
JP27
BICK
DIR ADC
INV THR
INV
THR
64fs
EXT
32fs 16fs
c) Set up jumper pins of FCK clock
JP24 (EXT2) and R27 should be properly selected in order to much the output impedance of the clock generator.
JP28
FCK
JP22
FCK_SEL
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When D/A converter of the AK4632 is evaluated by using DIR of AK4114, the jumper pins should be set to the
following.
JP30
SDTI
JP26
4632_SDTI
ADC
ADC
DAC/LOOP
DIR
<KM075602>
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ASAHI KASEI
[AKD4632-A]
(5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode
a) Set up jumper pins of MCKI clock
“MCKPD bit” in the AK4632 should be set to “0”.
JP6
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
MCKI
256fs
512fs1024fs
XTL
EXT
DIR
b) Set up jumper pins of BICK clock
JP19
BICK_SEL
JP29
BICK_INV
JP20
BICK
JP27
BICK
DIR ADC
INV THR
INV
THR
64fs
EXT
32fs 16fs
c) Set up jumper pins of FCK clock
JP24 (EXT2) and R27 should be properly selected in order to much the output impedance of the clock generator.
JP28
FCK
JP22
FCK_SEL
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When A/D converter of the AK4632 is evaluated by using DIR of AK4114, the jumper pins should be set to the
following.
JP30
SDTI
JP26
4632_SDTI
ADC
ADC
DAC/LOOP
DIR
<KM075602>
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ASAHI KASEI
[AKD4632-A]
DIP Switch set up
[SW3] (MODE) : Mode Setting of AK4632 and AK4114
ON is “H”, OFF is “L”.
No.
1
2
Name
DIF0
DIF1
ON (“H”)
OFF (“L”)
AK4114 Audio Format Setting
See Table 2
3
CM2
4
5
CM0
CM1
Clock Operation Mode select
See Table 3
6
7
8
OCKS0
OCKS1
M/S
Master Clock Frequency Select
See Table 4
Master mode
Slave mode
Note. When the AK4632 is evaluated Master mode, “No.8 of SW3” is set to “H”.
Table 1. Mode Setting for AK4632 and AK4114
Register setting
for AK4632 Audio
Interface Format
Setting for AK4114 Audio Interface Format
DIF1 bit
DIF0 bit
DIF0
DIF1
DIF2
DAUX
SDTO
0
1
L
L
H
L
L
L
L
H
H
24bit, Left justified
24bit, Left justified
24bit, I2S
16bit, Right justified
24bit, Left justified
24bit, I2S
1
1
0
1
Default
Note. When the AK4632 is evaluated by using DIR/DIT of AK4114, “No.8 of SW3” is set to “L”.
Table 2. Setting for AK4114 Audio Interface Format
Mode
0
1
CM1
0
0
CM0 UNLOCK
PLL
ON
OFF
ON
ON
ON
X'tal
ON(Note)
ON
Clock source SDTO
0
1
-
-
PLL
X'tal
PLL
X'tal
X'tal
RX
DAUX
RX
DAUX
DAUX
0
1
-
ON
ON
ON
2
3
1
1
0
1
Default
ON: Oscillation (Power-up), OFF: STOP (Power-down)
Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off.
Table 3. Clock Operation Mode select
No. OCKS1
MCKO1
256fs
512fs
MCKO2
256fs
256fs
X’tal
256fs
512fs
Default
0
2
0
1
Table 4. Master Clock Frequency Select (Stereo mode)
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ASAHI KASEI
[AKD4632-A]
Other jumper pins set up
1. JP1 (GND)
OPEN
: Analog ground and Digital ground
: Separated.
SHORT
: Common. (The connector “DGND” can be open.) <Default>
2. JP2 (AIN)
OPEN
: Connection between MICOUT pin and AIN pin of the AK4632.
: No connection.
SHORT
: Connection. <Default>
3. JP3 (AVDD_SEL) : AVDD of the AK4632
REG
AVDD
: AVDD is supplied from the regulator (“AVDD” jack should be open). < Default >
: AVDD is supplied from “AVDD ” jack.
4. JP8 (VVDD_SEL) : VVDD of the AK4632
AVDD
VVDD
: AVDD is supplied from “AVDD”. < Default >
: VVDD is supplied from “VVDD ” jack.
5. JP9 (DVDD_SEL) : DVDD of the AK4632
AVDD
DVDD
: DVDD is supplied from “AVDD”. < Default >
: DVDD is supplied from “DVDD ” jack.
6. JP10 (LVC_SEL) : Logic block of LVC is selected supply line.
DVDD
VCC
: Logic block of LVC is supplied from “DVDD”. < Default >
: Logic block of LVC is supplied from “VCC ” jack.
7. JP11 (VCC_SEL) : Logic block is selected supply line.
LVC
VCC
: Logic is supplied from supply line of LVC. < Default >
: Logic block of LVC is supplied from “VCC ” jack.
8. JP4 (SVDD_SEL) : SVDD of the AK4632
REG
SVDD
: SVDD is supplied from the regulator (“SVDD” jack should be open). < Default >
: SVDD is supplied from “SVDD ” jack.
9. JP8 (MCKO_SEL) : Master Clock Frequency is selected clock from MCKO1 or MCKO2 of the AK4114.
MCKO1
MCKO2
: The check from MCKO1 of AK4114 is provided to MCKI of the AK4632. < Default >
: The check from MCKO2 of AK4114 is provided to MCKI of the AK4632.
<KM075602>
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ASAHI KASEI
[AKD4632-A]
The function of the toggle SW
[SW1] (DIR) : Power control of AK4114. Keep “H” during normal operation.
Keep “L” when AK4114 is not used.
[SW2] (PDN) : Power control of AK4632. Keep “H” during normal operation.
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
Serial Control
The AK4632 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2
(CTRL) with PC by 10 wire flat cable packed with the AKD4632-A
CSN
CCLK
Connect
AKD4632
CDTI
PC
10 wire
10pin
10pin Header
flat cable
Connector
Figure 2. Connect of 10 wire flat cable
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ASAHI KASEI
[AKD4632-A]
Analog Input / Output Circuits
(1) Input Circuits
a) MIC Input Circuit
J1
MIC-JACK
6
4
3
JP12
MIC_SEL
AVSS
JACK
RCA
INT
J3
MIC
2
3
1
MR-552LS
AVSS
Figure 3. MIC Input Circuit
(a-1) Analog signal is input to INT pin via J1 connector.
JP12
MIC_SEL
RCA JACK
(a-2) Analog signal is input to INT pin via J3 connector.
JP12
MIC_SEL
RCA JACK
b) VIN Input Circuit
J6
VIN
C29
0.1u
2
3
1
VIN
R23
75
MR-552LS
AVSS
AVSS
Figure 4. VIN Input Circuit
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ASAHI KASEI
[AKD4632-A]
(2) Output Circuits
a) AOUT Output Circuit
C28
R20
220
J5
AOUT
1
2
2
3
1
AOUT
1u
R21
20k
MR-552LS
AVSS
AVSS
Figure 5. AOUT Output Circuit
b) VOUT Output Circuit
C18 1u
JP7 VSAG_SEL
R22
75
J7
1
2
11
00
VOUT
VSAG
VOUT
2
3
1
C17 47u
1
2
11
R41
100k
MR-552LS
00
AVSS
JP5 VOUT_SEL
AVSS
Figure 6. VOUT Output Circuit
(b-1) “DC Output” is output from J7 connector.
JP5
JP7
VOUT_SEL VSAG_SEL
00
11
00 11
(b-2) “SAG Trimming Circuit ” is output from J7 connector.
JP5
JP7
VOUT_SEL VSAG_SEL
00
11
00 11
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ASAHI KASEI
[AKD4632-A]
C) SPK Output Circuit
Note. When mini-jack is inserted or pulled out J2 (SPK-JACK) connector, JP13 (SPP_SEL) and JP14
(SPN_SEL) should be open, or “PMSPK bit” in the AK4632 should be set to “0”.
JP31
Dynamic
J2
R15
10
SPK-JACK
3
4
SVSS
SPP
6
JP13
D1
Dynamic(EXT)
Piez o(EXT)
Dynamic
A
A
K
SPK1
020S16
SVSS
DIODE ZENER
SPP_SEL
JP14
CN5
R
L
D2
Dynamic(EXT)
Piez o(EXT)
Dynamic
2
K
SVSS
SPN
DIODE ZENER
SPN_SEL
1
R17
10
Figure 7. SPK Output Circuit
(C-1) “Dynamic Speaker” of external is evaluated by using J2 (SPK-JACK) connector.
JP13
JP14
JP31
SPP_SEL
SPN_SEL
Dynamic
Dynamic
Dynamic(EXT) Dynamic
Dynamic(EXT)
Piezo(EXT)
Piezo(EXT)
(C-2) “Piezo (Ceramic) Speaker” of external is evaluated by using J2 (SPK-JACK) connector.
JP13
JP14
JP31
Dynamic
SPP_SEL
SPN_SEL
Dynamic
Dynamic(EXT) Dynamic
Dynamic(EXT)
Piezo(EXT)
Piezo(EXT)
<KM075602>
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ASAHI KASEI
[AKD4632-A]
(C-3) Analog signal of SPP/SPN pins are output “Dynamic Speaker” on the evaluation (SPK1).
JP13
JP14
JP31
SPP_SEL
SPN_SEL
Dynamic
Dynamic
Dynamic(EXT) Dynamic
Dynamic(EXT)
Piezo(EXT)
Piezo(EXT)
(3) BEEP/MIN/MOUT Input and Output Circuit
C24
1u
2
1
MOUT
J4
JP15
MIN/MOUT
BEEP/MIN/MOUT
OUT
IN
R16
20k
2
3
1
C25
0.1u
AVSS
MR-552LS
AVSS
C26
1u
JP16
MOUT
MIN
MIN
2
1
BEEP
R19
20k
R18
47k
BEEP/MIN/MOUT
BEEP
AVSS
Figure 8. BEEP/MIN/MOUT Input and Output Circuit
(3-1) Analog signal is input to MIN pin from J4 connector.
JP15
JP16
MIN/MOUT
BEEP/MIN/MOUT
MOUT
MIN
BEEP
IN
OUT
(3-2) Analog signal of MOUT pin is output from J4 connector.
JP15
JP16
MIN/MOUT
BEEP/MIN/MOUT
MOUT
MIN
BEEP
IN
OUT
<KM075602>
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ASAHI KASEI
[AKD4632-A]
(3-3) Analog signal of MOUT pin is input to MIN pin.
JP15
JP16
MIN/MOUT
BEEP/MIN/MOUT
MOUT
MIN
BEEP
IN
OUT
(3-4) Analog signal is input to BEEP pin from J4 connector.
JP15
JP16
BEEP/MIN/MOUT
MIN/MOUT
MOUT
MIN
BEEP
IN
OUT
∗ AKM assumes no responsibility for the trouble when using the above circuit examples.
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ASAHI KASEI
[AKD4632-A]
Control Software Manual
Set-up of evaluation board and control software
1. Set up the AKD4632-A according to previous term.
2. Connect IBM-AT compatible PC with AKD4632-A by 10-line type flat cable (packed with AKD4632-A). Take care
of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”.
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3. Insert the CD-ROM labeled “AKD4632-A Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “akd4632.exe” to set up the control program.
5. Then please evaluate according to the follows.
Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Port Reset” button.
3. Click “Write default” button
Explanation of each buttons
1. [Port Reset] :
2. [Write default] :
3. [All Write] :
4. [Function1] :
5. [Function2] :
6. [Function3] :
7. [Function4] :
8. [Function5]:
Set up the USB interface board (AKDUSBIF-A) when using the board.
Initialize the register of the AK4632.
Write all registers that is currently displayed.
Dialog to write data by keyboard operation.
Dialog to write data by keyboard operation.
The sequence of register setting can be set and executed.
The sequence that is created on [Function3] can be assigned to buttons and executed.
The register setting that is created by [SAVE] function on main window can be assigned to
buttons and executed.
9. [SAVE] :
10. [OPEN] :
11. [Write] :
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the
part that is not defined in the datasheet.
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[AKD4632-A]
Explanation of each dialog
1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data
becomes “H” or “1”. If not, “L” or “0”.
If you want to write the input data to the AK4632, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Input registers address in 2 figures of hexadecimal.
Data Box:
Input registers data in 2 figures of hexadecimal.
If you want to write the input data to the AK4632, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate DATT
There are dialogs corresponding to register of 09h and 0Ah.
Address Box:
Start Data Box:
End Data Box:
Interval Box:
Step Box:
Input registers address in 2 figures of hexadecimal.
Input starts data in 2 figures of hexadecimal.
Input end data in 2 figures of hexadecimal.
Data is written to the AK4632 by this interval.
Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to the AK4632, click [OK] button. If not, click [Cancel] button.
<KM075602>
2005/04
- 18 -
ASAHI KASEI
[AKD4632-A]
4. [SAVE] and [OPEN]
4-1. [SAVE]
All of current register setting values displayed on the main window are saved to the file. The extension of file name is
“akr”.
<Operation flow>
(1) Click [SAVE] Button.
(2) Set the file name and click [SAVE] Button. The extension of file name is “akr”.
4-2. [OPEN]
The register setting values saved by [SAVE] are written to the AK4632. The file type is the same as [SAVE].
<Operation flow>
(1) Click [OPEN] Button.
(2) Select the file (*.akr) and Click [OPEN] Button.
<KM075602>
2005/04
- 19 -
ASAHI KASEI
[AKD4632-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button.
(2) Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
(3) Click [START] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step.
This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file
name is “aks”.
Figure 1. Window of [F3]
<KM075602>
2005/04
- 20 -
ASAHI KASEI
[AKD4632-A]
6. [Function4 Dialog]
The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed.
When [F4] button is clicked, the window as shown in Figure 2 opens.
Figure 2. [F4] window
<KM075602>
2005/04
- 21 -
ASAHI KASEI
[AKD4632-A]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3].
The sequence file name is displayed as shown in Figure 3. ( In case that the selected sequence file name is
“DAC_Stereo_ON.aks”)
Figure 3. [F4] window(2)
(2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name
is “*.ak4”.
[OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the
change.
<KM075602>
2005/04
- 22 -
ASAHI KASEI
[AKD4632-A]
7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to
buttons and then executed. When [F5] button is clicked, the window as shown in Figure 4 opens.
Figure 4. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 5. (In case that the selected file name is
“DAC_Output.akr”)
(2) Click [WRITE] button, then the register setting is executed.
<KM075602>
2005/04
- 23 -
ASAHI KASEI
[AKD4632-A]
Figure 5. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file
name is “*.ak5”.
[OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded.
7-3. Note
(1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be
loaded again in order to reflect the change.
<KM075602>
2005/04
- 24 -
ASAHI KASEI
[AKD4632-A]
MEASUREMENT RESULTS EXAMPLE
1.AK4632 Mode: EXT mode (Slave)
[Measurement condition]
• Measurement unit: ROHDE & SCHWARZ, UPD05
• MCKI: 256fs, 512fs
• BICK: 64fs
• Bit: 16bit
• Sampling Frequency: 8kHz & 16kHz
• Measurement Frequency: 20 ∼ 3.4kHz (fs=8kHz), 20 ∼ 8kHz (fs=16kHz)
• Power Supply: AVDD=DVDD=VVDD=3.3V,SVDD=3.3V/5.0V
• Temperature: Room
• Input Frequency: 1kHz
[Measurement Results]
1.ADC characteristics (MIC Gain = +20dB, IPGA=0dB, ALC1 = OFF, MIC Æ IPGA Æ ADC)
Result
MCKI clock
Sampling Frequency
S/(N+D) (-1dBFS)
D-Range (-60dBFS)
S/N
512fs
256fs
8kHz
16kHz
84.1dB
86.4dB
86.3dB
8kHz
16kHz
84.0dB
86.3dB
86.3dB
84.3dB
88.1dB
88.1dB
84.4dB
85.2dB
88.2dB
2. DAC characteristics (AOUT) (DAC Æ AOUT, DVOL = 0dB)
Result
MCKI clock
Sampling Frequency
S/(N+D) (0dBFS)
D-Range (-60dBFS)
S/N
512fs
256fs
8kHz
16kHz
89.6dB
92.0dB
93.5dB
8kHz
16kHz
89.5dB
92.1dB
93.5dB
91.5dB
94.8dB
95.5dB
90.8dB
94.5dB
95.0dB
3. Speaker-Amp characteristics (DAC Æ MOUT Æ MIN Æ SPP/SPN, ALC2=OFF)
Result
69.6dB
73.5dB
73.2dB
73.8dB
90.4dB
91.7dB
90.6dB
91.0dB
S/(N+D)
SVDD=3.3V
RL=8Ω
SVDD=5.0V
RL=10Ω, CL=3uF
SVDD=3.3V
RL=8Ω
SPKG1-0 = “00” (-0.5dBFS)
SPKG1-0 = “01” (-0.5dBFS)
SPKG1-0 = “10” (-0.5dBFS)
SPKG1-0 = “11” (-0.5dBFS)
SPKG1-0 = “00”
SPKG1-0 = “01”
SPKG1-0 = “10”
SPKG1-0 = “11”
S/N
SVDD=5.0V
RL=10Ω, CL=3uF
4. Loop-back (MIC Æ ADC Æ DAC Æ AOUT)
Result
MCKI clock
Sampling Frequency
S/(N+D) (-1dBFS)
D-Range (-60dBFS)
S/N
512fs
256fs
8kHz
16kHz
83.2dB
85.9dB
86.0dB
8kHz
16kHz
83.4dB
85.9dB
86.0dB
84.2dB
88.4dB
88.4dB
84.2dB
87.0dB
87.0dB
<KM075602>
2005/04
- 25 -
ASAHI KASEI
[AKD4632-A]
2.AK4632 Mode: PLL SLAVE mode
[Measurement condition]
• Measurement unit: ROHDE & SCHWARZ, UPD05
• Bit: 16bit
• Sampling Frequency: 8kHz & 16kHz
• Measurement Frequency: 20 ∼ 3.4kHz (fs=8kHz), 20 ∼ 8kHz (fs=16kHz)
• Power Supply: AVDD=DVDD=SVDD=VVDD=3.3V
• Temperature: Room
• Input Frequency: 1kHz
[Measurement Results]
2-1. PLL Reference clock : BICK or FCK pin
Loop-back (MIC Æ ADC Æ DAC Æ AOUT)
Result
PLL Reference clock
Sampling Frequency
S/(N+D) (-1dBFS)
D-Range (-60dBFS)
S/N
1fs (FCK pin)
16fs (BICK pin)
8kHz
16kHz
78.6dB
86.0dB
85.9dB
8kHz
16kHz
83.8dB
85.9dB
85.8dB
75.3dB
86.5dB
86.5dB
84.7dB
87.7dB
87.6dB
2-2. PLL Reference clock : MCKI pin
Loop-back (MIC Æ ADC Æ DAC Æ AOUT)
Result
12.288MHz
PLL Reference clock
Sampling Frequency
S/(N+D) (-1dBFS)
D-Range (-60dBFS)
S/N
8kHz
16kHz
83.8dB
85.8dB
85.8dB
84.7dB
87.4dB
88.0dB
3.AK4632 Mode: PLL MASTER mode
[Measurement condition]
• Measurement unit: ROHDE & SCHWARZ, UPD05
• MCKI: 12.288MHz
• BICK: 16fs
• Bit: 16bit
• Sampling Frequency: 8kHz & 16kHz
• Measurement Frequency: 20 ∼ 3.4kHz (fs=8kHz), 20 ∼ 8kHz (fs=16kHz)
• Power Supply: AVDD=DVDD=SVDD=VVDD=3.3V
• Temperature: Room
• Input Frequency: 1kHz
[Measurement Results]
Loop-back (MIC Æ ADC Æ DAC Æ AOUT)
Result
8kHz
16kHz
83.3dB
85.0dB
85.0dB
S/(N+D) (-1dBFS)
D-Range (-60dBFS)
S/N
84.2dB
86.9dB
87.0dB
<KM075602>
2005/04
- 26 -
ASAHI KASEI
[AKD4632-A]
4.PLOT DATA (EXT Slave mode)
4-1.ADC (MIC Æ ADC) PLOT DATA
Figure 1. THD+N vs. Input Level
Figure 2. THD+N vs. Input Frequency (Input Level = -1dBFS), C7: Ceramic Condenser
In this case, a ceramic condenser is used as C7 between MICOUT pin as AIN pin on the AKD4632-A.As the performance of
Ceramic condenser is not so good about low frequency signal. Refer to Figure 3 about the performance of AK4632.
<KM075602>
2005/04
- 27 -
ASAHI KASEI
[AKD4632-A]
Figure 3. THD+N vs. Input Frequency (Input Level = -1dBFS), C7: Film Condenser
Figure 4. Linearity
<KM075602>
2005/04
- 28 -
ASAHI KASEI
[AKD4632-A]
Figure 5. Frequency Response (by the board of AKD4632-A)
High pass filter is composed by the input impedance of AIN pin and C7 between MICOUT pin and AIN pin. Refer to
Figure 6 about frequency response of AK4632’s ADC.
Figure 6. Frequency Response (AIN Æ ADC)
<KM075602>
2005/04
- 29 -
ASAHI KASEI
[AKD4632-A]
Figure 7. FFT Plot ( Input level=-1.0dBFS)
Figure 8. FFT Plot ( Input level=-60.0dBFS )
<KM075602>
2005/04
- 30 -
ASAHI KASEI
[AKD4632-A]
Figure 9. FFT Plot ( “0” data input )
<KM075602>
2005/04
- 31 -
ASAHI KASEI
[AKD4632-A]
4-2. DAC (DAC Æ AOUT) PLOT DATA
Figure 10. THD+N vs. Input Level
Figure 11. THD+N vs. Input Frequency (Input Level = 0dBFS)
<KM075602>
2005/04
- 32 -
ASAHI KASEI
[AKD4632-A]
Figure 12. Linearity
Figure 13. Frequency Response
<KM075602>
2005/04
- 33 -
ASAHI KASEI
[AKD4632-A]
Figure 14. FFT Plot ( Input level=0dBFS )
Figure 15. FFT Plot ( Input level=-60.0dBFS )
<KM075602>
2005/04
- 34 -
ASAHI KASEI
[AKD4632-A]
Figure 16. FFT Plot ( “0” data input )
<KM075602>
2005/04
- 35 -
ASAHI KASEI
[AKD4632-A]
4-3. VIDEO PLOT DATA
[Measurement condition]
• Measurement unit: Tektronix VM700T Video Measurement set
• Power Supply: AVDD=DVDD=SVDD=3.3V,VVDD=3.3V
• Temperature: Room
• Input Frequency: 1kHz
4-3-1. S/N
• Measurement Frequency: 100kH ∼ 6MHz
Figure 1. Noise Spectrum
<KM075602>
2005/04
- 36 -
ASAHI KASEI
[AKD4632-A]
4-3-2. SAG
Figure 2. Field Time Distortion (DC Output, SAGC bits = “00”)
Figure 3. Field Time Distortion (SAG Trimming 47µF+ 1.0uF, SAGC bits = “10”)
<KM075602>
2005/04
- 37 -
ASAHI KASEI
[AKD4632-A]
Figure 4. Field Time Distortion (SAG Trimming 100µF+ 2.2uF, SAGC bits = “11”)
4-3-3. Vector
• Input signal: 75% color
Figure 5. 75% Color Vector (SAG Trimming 47µF+ 1.0uF, SAGC bits = “10”)
<KM075602>
2005/04
- 38 -
ASAHI KASEI
[AKD4632-A]
Revision History
Date
Manual
Revision
Board
Revision
Reason
Contents
04/11/24
05/04/05
KM075601
KM075602
0
0
First Edition
Change
“Control Software Manual” chapter is changed by version up
of control software.
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
<KM075602>
2005/04
- 39 -
A
B
C
D
E
REG_IN
T1
TA48033F
JP1
GND
IN
OUT
REG
C3
+
C1
0.1u
C2
0.1u
47u
AVSS
SVSS
E
D
C
B
A
E
D
C
B
A
AVSS
AVSS
CN1
32pin_4
REG
AVDD
T45_O
DVDD
VVDD
AVSS
SVDD
SVSS
DGND
T45_R
T45_O
T45_BU
T45_BK
T45_BU
T45_BK
T45_BK
REG_IN
AVDD
DVDD
VVDD
SVDD
AVSS
SVSS
C4
C5
0.1u
+
2.2u
R1
C6
1u
C7
+
2.2k
0.22u
JP2
AIN
AVSS
U1
R2 10k
C8
4.7n
1
24
23
22
21
20
19
18
17
VCOC
AVDD
AVSS
VVDD
VIN
MIN
SVSS
SVDD
SPP
REG
CN3
24
CN2
REG
AVSS
JP3
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
MIN
AVDD
REG AVDD_SEL
C10
0.1u
+
C9
10u
C11
0.1u
C12
+
L1
10u
SVSS
SVDD
23
1
2
JP4
SVDD_SEL
REG
SVSS
L2
C13
47u
(short)
AVDD
C14
10u
C15
0.1u
AVDD
+
R3
R5
22
+
(short)
1
2
AVSS
AVSS
JP5
SVDD
(short)
AK4632
21
SPP
R4
(short) (open)
C16
+
AVSS
47u
SPN
20
VIN
SPN
VOUT_SEL SAGC00
VOUT
19
AVDD
4632_MCKO
4632_MCKI
SAGC11
2
1
VOUT
VSAG
PDN
MCKO
MCKI
DVSS
C17 47u
SVSS
18
JP8
SAGC00
VVDD
1
AVDD VVDD_SEL
JP6 MCKI
SAGC11
JP7
2
1
17
PDN
L3
(short)
C18 1u
2
VSAG_SEL
AVSS
32pin_1
C19
47u
VVDD
32pin_3
+
R6 51
C20
0.1u
AVSS
AVDD
R7
51
R8
51
R9
51
R10
51
R11
51
R12
470
R13
470
1
2
AVSS
C21
10u
JP9
DVDD
1
AVDD DVDD_SEL
R14
10
L4
(short)
DVDD
LVC
2
C22
47u
DVDD
R40
(short)
JP10
LVC_SEL
+
DVDD
CN4
32pin_2
AVSS
VCC
LVC
JP11
VCC_SEL
VCC(3.3V)
L5
1
D3.3V
2
C23
47u
(short)
VCC
+
Title
Size
AKD4632
Document Number
Rev
0
A3
AK4632
Date:
Sheet
of
Wednesday, August 18, 2004
1
5
A
B
C
D
E
A
B
C
D
E
J1
MIC-JACK
6
JP31
Dynamic
4
3
J2
JP12
MIC_SEL
R15
10
SPK-JACK
E
D
C
B
A
E
D
C
B
A
AVSS
JACK
RCA
SVSS
3
4
INT
SPP
J3
MIC
6
2
3
1
JP13
D1
Dynamic(EXT)
Piezo(EXT)
Dynamic
A
A
K
SPK1
020S16
MR-552LS
AVSS
SVSS
DIODEZENER
SPP_SEL
C24
1u
CN5
R
L
JP14
D2
K
2
1
Dynamic(EXT)
Piezo(EXT)
Dynamic
2
MOUT
J4
JP15
MIN/MOUT
BEEP/MIN/MOUT
OUT
IN
R16
20k
2
3
1
C25
0.1u
SVSS
SPN
DIODEZENER
SPN_SEL
1
AVSS
MR-552LS
R17
10
AVSS
C26
1u
1
JP16
MOUT
MIN
BEEP
MIN
2
R19
20k
R18
47k
BEEP/MIN/MOUT
BEEP
AVSS
C28
R20
220
J5
AOUT
1
2
2
3
1
AOUT
1u
R21
20k
MR-552LS
AVSS
AVSS
J6
VIN
R22
75
C29
0.1u
J7
VOUT
2
3
1
2
3
1
VIN
VOUT
R23
75
R41
100k
MR-552LS
MR-552LS
AVSS
AVSS
AVSS
AVSS
Title
Size
AKD4632
Document Number
Rev
0
A3
Input/Output
Date:
Sheet
of
Wednesday, August 18, 2004
2
5
A
B
C
D
E
A
B
C
D
E
for
74HCU04,74AC74,74VHC4040,74HC14,74HC14,74HC541,74HCT04
D3.3V
12.288MHz
X1
C30
0.1u
C31
0.1u
C32
0.1u
C33
0.1u
C34
0.1u
C35
0.1u
C36
0.1u
E
D
C
B
A
E
D
C
B
A
+
C37
47u
1
2
R24
1M
U2A
U2B
1
2
3
4
74HCU04
74HCU04
JP17
XTE
C38
(open)
C39
(open)
EXT_MCLK
VCC
VCC
JP18
MKFS
U4A
U4B
74AC74
74AC74
256fs
U3
CLK
JP19
512fs
10
11
9
7
6
5
3
2
4
13
12
14
15
1
BICK_SEL
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
2
3
5
12
11
9
1024fs
MCKO
64fs
32fs
16fs
EXT
THR JP20
BICK
D
Q
D
Q
R25
short
RST
JP21
EXT_BICK
EXT_FCK
CLK
CLK
XTL
DIR
EXT
1
2
6
8
INV
DIR_MCLK
Q
Q
U5A
74HC14
MCLK_SEL
Q10
Q11
Q12
JP22
2fs
1fs
74VHC4040
EXT
FCK_SEL
MCKO
J8
EXT/BICK
2
3
1
R26
51
MR-552LS
AVSS
JP23
EXT1
J9
FCK
2
3
1
R27
51
MR-552LS
AVSS
JP24
EXT2
Title
AKD4632
Size
A3
Document Number
Rev
0
CLOCK
Date:
Sheet
of
Wednesday, August 18, 2004
3
5
A
B
C
D
E
A
B
C
D
E
C40 C41
0.1u 0.1u
D3.3V
D3.3V
L6
(short)
R28
10k
D3
E
D
C
B
A
E
D
C
B
A
HSU119
PORT1
VCC
GND
OUT
C42
0.1u
3
2
1
U5B
U5C
C43
10u
4
3
6
5
R29
470
2
1
74HC14
74HC14
D3.3V
TORX141
L
H
C45
0.1u
C44
SW1
DIR
0.1u
C46
0.47u
R30
18k
SW3
U6
DIF0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DIF1
DIF2
CM0
R31
1k
LED1
ERF
U7A
CM1
1
2
36
35
34
33
32
31
30
29
28
27
26
25
1
2
K
A
IPS0
INT0
OCKS0
OCKS1
CM1
D3.3V
OCKS0
OCKS1
M/S
74HC04
NC
OCKS0
RP1
9
8
7
6
5
4
3
2
1
3
DIF0
OCKS1
CM1
CM0
CM1
OCKS0
OCKS1
M/S
4
TEST2
DIF1
NC
5
CM0
CM0
47k
6
PDN
C47
AK4114
(open)
7
DIF2
IPS1
P/SN
XTL0
XTL1
VIN
XTI
X2
11.2896MHz
C48
(open)
8
XTO
9
DAUX
MCKO2
BICK
DAUX
10
11
12
DIR_BICK
SDTO
DIR_SDTI
C49
C50
0.1u
JP25
MCKO_SEL
DIR_FCK
0.1u
MCKO2
DIR_MCLK
MCKO1
1
2
1
2
C51
10u
C52
10u
D3.3V
D3.3V
PORT2
IN
VCC
GND
3
2
1
D3.3V
C53
0.1u
TOTX141
Title
AKD4632
Size
A3
Document Number
Rev
0
DIR/DIT
Date:
Sheet
E
of
4
Wednesday, August 18, 2004
5
A
B
C
D
A
B
C
D
E
U8
LVC
U9
1
19
2
20
10
18
17
16
15
14
13
12
11
E
D
C
B
A
E
D
C
B
A
DIR
VCC
GND
B1
11
12
13
14
15
16
17
18
10
20
9
M/S
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
A8
A7
A6
A5
A4
A3
A2
A1
C54
0.1u
G
8
MCKO
4632_MCKI
DAUX
4632_MCKO
EXT_MCLK
4632_SDTO
RP2
47k
RP3
47k
7
6
5
4
3
2
1
7
6
5
4
3
2
1
A1
A2
A3
A4
A5
A6
A7
A8
7
3
B2
6
JP26
4632_SDTI DAC/LOOP
4
B3
5
4632_SDTI
5
B4
4
ADC
6
B5
3
7
B6
2
JP27
BICK
ADC
EXT_BICK
DIR_BICK
8
B7
4632_BICK
4632_FCK
19
1
GND
G2
G1
DIR
C55
0.1u
9
B8
JP28
FCK
VCC
ADC
DIR
EXT_FCK
DIR_FCK
74LVC245
74LVC541
LVC
JP29
U10A
+
C56
47u
1
2
INV
THR
74HC14
BICK_INV
U11
R32
R34
R36
10k
10k
10k
R33
R35
R37
470
470
470
2
3
4
5
6
7
8
9
18
D3V
CSN
A1
A2
A3
A4
A5
A6
A7
A8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
17
16
15
14
13
12
11
CCLK
CDTI
PDN
4632_MCKI
PORT3
MCLK
BICK
FCK
SDTI
1
2
3
4
5
10
9
8
7
6
PORT4
1
2
3
4
5
10 CSN
VCC
9
8
7
6
CCLK
CDTI
1
19
ROM
G1
G2
R38
10k
74HC541
CTRL
D3V
ADC
DAUX
D3V
JP30
SDTI
R39
10k
D4
HSU119
DIR_SDTI
DIR
U5D
U5E
9
8
11
10
U7D
U2C
U2F
U10B
74HC14
74HC14
5
9
6
13
3
12
9
8
3
5
9
4
L
H
74HC04
74HCU04
74HCU04
74HC14
SW2
PDN
C57
0.1u
U7B
4
U7E
10
U2D
8
U10C
6
U10E
11
13
11
13
10
74HC04
74HC04
74HCU04
74HC14
74HC14
U7C
6
U7F
12
U2E
10
U10D
8
U10F
12
Title
Size
11
5
AKD4632
LOGIC
74HC04
74HC04
74HCU04
74HC14
74HC14
Document Number
Rev
0
A3
Date:
Sheet
E
of
Wednesday, August 18, 2004
5
5
A
B
C
D
A K D 4632-A ꢀL1
A K D 4632-A ꢀL2
A K D 4632-A ꢀL1_SILK
A K D 4632-A ꢀL2_SILK
相关型号：
AKD4641EN-A
16bit stereo CODEC with built-in Microphone-amplifier and 16bit Mono CODEC for Bluetooth Interface.
AKM
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