AKD4633_技术文档

ASAHI KASEI

[AK4633]

AK4633

∆Σ

16-Bit

Mono CODEC with ALC & MIC/SPK-AMP

GENERAL DESCRIPTION

The AK4633 is a 16-bit mono CODEC with Microphone-Amplifier and Speaker-Amplifier. Input circuits

include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit. Output circuits include a

Speaker-Amplifier and Mono Line Output. The AK4633 suits a moving picture of Digital Still Camera and

etc. This speaker-Amplifier supports a Piezo Speaker. The AK4633 is housed in a space-saving 24-pin

QFN package.

FEATURE

1. 16-Bit Delta-Sigma Mono CODEC

2. Recording Function

• 1ch Mono Input

• 1^stMIC Amplifier: 0dB, 6dB, 10dB, 14dB, 17dB, 20dB, 26dB or 32dB

• 2^ndAmplifier with ALC: +36dB ∼ -54dB, 0.375dB Step, Mute

• ADC Performance (MIC-Amp= +20dB): S/(N+D): 84dB, DR, S/N: 85dB

• Wind Noise Reduction

• Notch Filter

3. Playback Function

• Digital ALC (Automatic Level Control): +36dB ∼ -54dB, 0.375dB Step, Mute

• Mono Line Output Performance: S/(N+D): 85dB, S/N: 93dB

• Mono Speaker-Amp

- Speaker-Amp Performance: S/(N+D): 60dB (150mW@ 8Ω)

Output Noise Level: -87dBV

- BTL Output

- Output Power: 400mW @ 8Ω

• Beep Input

4. Power Management

5. Flexible PLL Mode:

• Frequencies:

11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin)

1fs (FCK pin)

16fs, 32fs or 64fs (BICK pin)

6. EXT Mode:

• Frequencies: 256fs, 512fs or 1024fs (MCKI pin)

7. Sampling Rate:

• PLL Slave Mode (FCK pin) : 7.35kHz ~ 48kHz

• PLL Slave Mode (BICK pin) : 7.35kHz ~ 48kHz

• PLL Slave Mode (MCKI pin):

8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz

• PLL Master Mode:

8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz

• EXT Slave Mode/EXT Master Mode:

7.35kHz~ 48kHz (256fs), 7.35kHz ~ 26kHz (512fs), 7.35kHz ~ 13kHz (1024fs)

8. Output Master Clock Frequency: 256fs

9. Serial µP Interface: 3-wire

10. Master / Slave Mode

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ASAHI KASEI

[AK4633]

11. Audio Interface Format: MSB First, 2’s compliment

• ADC: DSP Mode, 16bit MSB justified, I²S

• DAC: DSP Mode, 16bit MSB justified, 16bit LSB justified, I²S

12. Ta = -40 ∼ 85°C

13. Power Supply

• AVDD: 2.2 ∼ 3.6V (typ. 3.3V)

• DVDD: 1.6 ∼ 3.6V (typ. 3.3V)

• SVDD: 2.2 ∼ 4.0V (typ. 3.3V)

14. Power Supply Current: 12mA (All Power ON)

15. Package: 24pin QFN(4mmx4mm)

Block Diagram

AVDD

AVSS

VCOM

DVDD

DVSS

PMMP

MPI

MIC Power

Supply

PMADC

MIC/MICP

A/D

HPF

Mic

PDN

MIC-Amp

0dB /+6dB/+10dB/+14dB/+17dB

+20dB / +26dB / +32dB

PMPFIL

Audio

I/F

HPF

BICK

FCK

2 Band

EQ

PMAO

VOL

(ALC)

AOUT

SDTO

SDTI

Line Out

Speaker

PMDAC

MCKO

MCKI

PMPLL

PMSPK

SPP

SPN

D/A

PLL

VCOC

CSN

Control

Register

CCLK

CDTI

PMBP

BEEP/MICN

SVDD

SVSS

Figure 1. AK4633 Block Diagram

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ASAHI KASEI

[AK4633]

Ordering Guide

AK4633VN

AKD4633

−40 ∼ +85°C

24pin QFN (0.5mm pitch)

Evaluation board for AK4633

Pin Layout

19

20

21

12

11

10

9

SVSS

SVDD

AOUT

BICK

FCK

SDTO

SDTI

CDTI

CCLK

AK4633VN

22

23

24

BEEP/MICN

MPI

Top View

8

7

MIC/MICP

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[AK4633]

Interchange with AK4631

1. Function

Function

AVDD

DVDD

SVDD

AK4631

AK4633

2.6V ∼ 3.6V

2.6V ∼ 5.25V

2.2V ∼ 3.6V

1.6V ∼ 3.6V

2.2V ∼ 4.0V

MIC Input

MIC Power Output Voltage

MIC-Amp

Single-end

0.75 x AVDD

0dB/+20dB/+26dB/+32dB

Single-end / differential

0.8 x AVDD

0dB/+6dB/+10dB/+14dB

+17dB/+20dB/+26dB/+32dB

Yes

HPF for Wind Noise Reduction

Notch Filter

No

Yes

ALC for Input Signal

Input Volume

Analog ALC

+27.5dB ∼ -8dB, 0.5dB Step

Digital ALC (Note 1)

+36dB ∼ -54dB, 0.375dB Step

(Note 1)

ALC for Output Signal

Output Volume

Speaker-Amp block

+12dB ∼ -115dB, 0.5dB Step

Digital Block (Note 1)

+36dB ∼ -54dB, 0.375dB Step

(Note 1)

Maximum Output for SPK-Amp

(using Piezo Speaker)

MCKI Pull-down Resistance

Package

8.5Vpp@SVDD=5V

6.33Vpp@SVDD=3.8V

Yes

No (Delete MCKPD bit )

24pin QFN 4.0mm x 4.0mm

28pin QFN 5.2mm x 5.2mm

41pin BGA 4.0mm x 4.0mm

Note 1. ALC and Volume circuits are shared by input and output. Therefore, it is impossible to use ALC and Volume

function at same time for both recording and playback mode.

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[AK4633]

2. Register Map

(1) AK4631

Addr

Register Name

D7

0

SPPS

0

PLL3

0

D6

PMVCM

0

BEEPS

AOPSN

PLL2

0

ROTM

ALC2

REF6

IPGA6

OVOL6

0

D5

PMBP

0

ALC2S

MGAIN1

PLL1

FS3

ZTM1

ALC1

REF5

IPGA5

OVOL5

RFS5

D4

PMSPK

0

D3

PMAO

M/S

D2

D1

D0

PMADC

PMPLL

MGAIN0

ALC1A

DIF0

00H Power Management 1

01H Power Management 2

02H Signal Select 1

03H Signal Select 2

04H Mode Control 1

05H Mode Control 2

06H Timer Select

07H ALC Mode Control 1

08H ALC Mode Control 2

09H Input PGA Control

0AH Digital Volume Control

0BH ALC2 Mode Control

PMDAC

MCKPD

MPWR

BEEPA

BCKO0

FS2

WTM0

LMAT0

REF2

PMMIC

MCKO

MICAD

ALC1M

DIF1

DACA

SPKG1

PLL0

MSBS

ZTM0

ZELM

REF4

IPGA4

OVOL4

RFS4

DACM

SPKG0

BCKO1

BCKP

WTM1

LMAT1

REF3

IPGA3

OVOL3

RFS3

FS1

FS0

DVTM

LTM1

RATT

REF1

IPGA1

OVOL1

RFS1

LTM0

LMTH

REF0

IPGA0

OVOL0

RFS0

0

OVOL7

0

IPGA2

OVOL2

RFS2

(2) AK4633

Addr

Register Name

D7

D6

PMVCM

0

BEEPS

AOPS

PLL2

FCKO

0

ALC2

IREF6

IVOL6

OVOL6

D5

PMBP

0

DACS

MGAIN1

PLL1

D4

PMSPK

0

DACA

SPKG1

PLL0

MSBS

ZTM0

ZELMN

IREF4

IVOL4

OVOL4

OREF4

VOL4

MDIF

D3

PMAO

M/S

D2

PMDAC

0

D1

0

MCKO

MGAIN2 MGAIN0

PFDAC

DIF1

D0

PMADC

PMPLL

00H Power Management 1

01H Power Management 2

02H Signal Select 1

PMPFIL

0

SPPSN

PFSDO

PLL3

ADRST

0

PMMP

BEEPA

BCKO0

FS2

WTM0

LMAT0

IREF2

IVOL2

OVOL2

OREF2

VOL2

EQ1

03H Signal Select 2

SPKG0

BCKO1

BCKP

WTM1

LMAT1

IREF3

IVOL3

OVOL3

OREF3

VOL3

EQ2

ADCPF

DIF0

FS0

04H Mode Control 1

05H Mode Control 2

06H Timer Select

07H ALC Mode Control 1

08H ALC Mode Control 2

09H Digital Volume Control

0AH Digital Volume Control

0BH ALC Mode Control 3

0DH ALC LEVEL

FS3

FS1

ZTM1

ALC1

IREF5

IVOL5

OVOL5

OREF5

VOL5

SMUTE

RFST1

RGAIN0

IREF1

IVOL1

OVOL1

OREF1

VOL1

HPF

RFST0

LMTH0

IREF0

IVOL0

OVOL0

OREF0

VOL0

HPFAD

0

IREF7

IVOL7

OVOL7

RGAIN1 LMTH1

VOL7

VOL6

DATT0

0EH Signal Select 3

DATT1

10H - 1FH

Digital Filter Setting

hatching Register bits changed from the AK4631.

Register bits added from the AK4631.

Bold

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ASAHI KASEI

[AK4633]

3. Register Setting

(1) When PLL reference clock is input from FCK or BICK pin, the setting of FS3-0 bits is changed as shown in the

following table.

Sampling Frequency

Mode

FS3 bit

FS2 bit

FS1 bit

FS0 bit

Range

0

1

0

1

0

Don’t care

0

1

2

Don’t care

7.35kHz ≤ fs ≤ 12kHz

12kHz < fs ≤ 24kHz

24kHz < fs ≤ 48kHz

N/A

Others

ALL of modes are changed from AK4631.

(2) In EXT Slave Mode, the setting of FS3-0 bits is changed as shown in the following table.

.

Mode

FS3-2 bits

FS1 bit

FS0 bit

MCKI Input

Frequency

Sampling Frequency

Range

Don’t care

0

1

0

1

256fs

1024fs

512s

0

1

2

3

0

1

7.35kHz ≤ fs ≤ 48kHz

7.35kHz < fs ≤ 13kHz

7.35kHz < fs ≤ 26kHz

7.35kHz ≤ fs ≤ 48kHz

256fs

Hatching parts are the setting changed from AK4631.

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ASAHI KASEI

No. Pin Name

[AK4633]

PIN / FUNCTION

I/O

O

Function

Common Voltage Output Pin, 0.45 x AVDD

Bias voltage of ADC inputs and DAC outputs.

Analog Ground Pin

1

VCOM

2

3

AVSS

-

AVDD

Analog Power Supply Pin

Output Pin for Loop Filter of PLL Circuit

This pin should be connected to AVSS with one resistor and capacitor in series.

Power-Down Mode Pin

4

VCOC

O

5

“H”: Power up, “L”: Power down reset and initialize the control register.

AK4633 should always be reset upon power-up.

PDN

I

6

CSN

I

Chip Select Pin

7

CCLK

CDTI

SDTI

SDTO

FCK

Control Data Clock Pin

8

I/O Control Data Input Pin / Output pin

9

I

Audio Serial Data Input Pin

Audio Serial Data Output Pin

10

11

12

13

14

15

16

17

18

19

20

21

22

O

I/O Frame Clock Pin

BICK

DVDD

DVSS

MCKI

MCKO

SPP

I/O Audio Serial Data Clock Pin

-

Digital Power Supply Pin

Digital Ground Pin

External Master Clock Input Pin

Master Clock Output Pin

I

O

-

Speaker Amp Positive Output Pin

Speaker Amp Negative Output Pin

Speaker Amp Ground Pin

SPN

SVSS

SVDD

AOUT

BEEP

MICN

MPI

-

Speaker Amp Power Supply Pin

Mono Line Output Pin

O

I

Beep Signal Input Pin

(MDIF bit = “0”)

(MDIF bit = “1”)

I

Microphone Negative Input Pin for Differential Input

MIC Power Supply Pin for Microphone

Microphone Input Pin for Single Ended input

Microphone Positive Input Pin for Differential Input

23

24

O

I

MIC

(MDIF bit = “0”)

(MDIF bit = “1”)

MICP

I

Note: All input pins except analog input pins (MIC/MICP and BEEP/MICN pins) should not be left floating.

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ASAHI KASEI

[AK4633]

Handling of Unused Pin

The unused I/O pins should be processed appropriately as below.

Classification

Analog

Pin Name

Setting

MIC/MICP, BEEP/MICN, MPI, AOUT,

SPP, SPN, VCOC

These pins should be open.

MCKI, SDTI

These pins should be connected to DVSS.

These pins should be connected to DVSS, or should

be pulled-down/pulled-up by about 100kΩ resister .

These pins should be open.

FCK, BICK (Note)

Digital

MCKO, SDTO

(Note) When the AK4633 is used by the slave mode (M/Sbit=“0”), these pins should be connected to DVSS. When the

AK4633 is used by the master mode (M/Sbit=“1”), these pins should be pulled-down or pulled-up by about 100kΩ

resistor.

ABSOLUATE MAXIMUM RATING

(AVSS, DVSS, SVSS=0V; Note 2)

Parameter

Symbol

AVDD

DVDD

SVDD

∆GND1

∆GND2

IIN

min

−0.3

-

max

4.6

0.3

Units

V

Power Supplies:

Analog

Digital

Speaker-Amp

|AVSS – DVSS| (Note 3)

|AVSS – SVSS| (Note 3)

-

0.3

V

Input Current, Any Pin Except Supplies

Analog Input Voltage (Note 5)

-

±10

mA

V

VINA

VIND

Ta

Tstg

Pd

−0.3

−40

−65

-

AVDD+0.3

DVDD+0.3

85

Digital Input Voltage (Note 6)

V

Ambient Temperature (powered applied)

Storage Temperature

Maximum Power Dissipation (Note 4)

°C

mW

150

650

Note 2. All voltages with respect to ground.

Note 3. AVSS, DVSS and SVSS must be connected to the same analog ground plane.

Note 4. In case that PCB wiring density is 100%. This power is the AK4633 internal dissipation that does not include

power of externally connected speaker.

Note 5. BEEP/MICN, MIC/MICP pins

Note 6. PDN, CSN, CCLK, CDTI, SDTI, FCK, BICK, MCKI pins

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

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ASAHI KASEI

[AK4633]

RECOMMENDED OPERATING CONDITIONS

(AVSS, DVSS, SVSS=0V; Note 2)

Parameter

Symbol

AVDD

DVDD

min

2.2

1.6

2.2

-

typ

3.3

-

max

3.6

4.0

0.3

Units

V

Power Supplies Analog

(Note 7)

Digital

Speaker-Amp

Difference

SVDD

DVDD - AVDD

DVDD - SVDD

-

V

Note 2. All voltages with respect to ground.

Note 7. The power up sequence between AVDD, DVDD and SVDD is not critical. It is not permit to power DVDD off

only when AVDD or SVDD is powered up. When the power supplies except DVDD are partially powered OFF,

the AK4633 must be reset by bringing PDN pin “L” after these power supplies are powered ON again. If AVDD is

powered off when DVDD is powered up, the PMADC bit should be set to “0” before AVDD is powered off.

* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

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ASAHI KASEI

[AK4633]

ANALOG CHRACTERISTICS

(Ta=25°C; AVDD, DVDD, SVDD=3.3V; AVSS=DVSS=SVSS=0V; fs=8kHz, BICK=64fs; Signal Frequency=1kHz;

16bit Data; Measurement frequency=20Hz ∼ 3.4kHz; EXT Slave Mode; unless otherwise specified)

Parameter

min

typ

max

Units

MIC Amplifier : MDIF bit = “0”; (Single-ended input)

Input Resistance

Gain

20

-

30

0

20

26

32

6

10

14

17

40

-

kΩ

dB

(MGAIN2-0 bits = “000”)

(MGAIN2-0 bits = “001”)

(MGAIN2-0 bits = “010”)

(MGAIN2-0 bits = “011”)

(MGAIN2-0 bits = “100”)

(MGAIN2-0 bits = “101”)

(MGAIN2-0 bits = “110”)

(MGAIN2-0 bits = “111”)

MIC Amplifier : MDIF bit = “1”; (Full-differential input)

Input Voltage

(Note 8)

-

0.228

0.114

0.057

1.14

0.721

0.455

0.322

Vpp

(MGAIN2-0 bits = “001”)

(MGAIN2-0 bits = “010”)

(MGAIN2-0 bits = “011”)

(MGAIN2-0 bits = “100”)

(MGAIN2-0 bits = “101”)

(MGAIN2-0 bits = “110”)

(MGAIN2-0 bits = “111”)

MIC Power Supply: MPI pin

Output Voltage

Load Resistance

Load Capacitance

(Note 9)

2.38

2

-

2.64

-

2.90

-

30

V

kΩ

pF

ADC Analog Input Characteristics: MIC Æ ADC, MIC Gain=20dB, IVOL=0dB, ALC1bit = “0”

Resolution

-

0.168

72

75

-

0.198

84

85

16

0.228

-

Bits

Vpp

dB

Input Voltage (MIC Gain=20dB,Note 10)

S/(N+D)

D-Range

S/N

(−1dBFS) (Note 11)

(−60dBFS)

DAC Characteristics:

Resolution

16

Bits

Mono Line Output Characteristics: AOUT pin, DAC → AOUT, R_L=10kΩ

Output Voltage (Note 12)

1.78

73

83

10

-

1.98

85

93

-

2.18

-

Vpp

dB

kΩ

pF

S/(N+D)

D-Range

S/N

(0dBFS) (Note 11)

(-60dBFS)

Load Resistance

Load Capacitance

-

30

Speaker-Amp Characteristics: DAC Æ SPP/SPN pins, ALC2 bit = “0”, R_L=8Ω, BTL, SVDD=3.3V

2.54

3.20

40

-

-75

-

8

3.17

4.00

60

3.80

4.80

-

Vpp

dB

SPKG1-0 bits = “00” (-4.1dBFS)

SPKG1-0 bits = “01” (-4.1dBFS)

As 150mW output power

As 400mW output power

SPKG1-0 bits = “00”

SPKG1-0 bits = “01”

SPKG1-0 bits = “10”

Output Voltage

S/(N+D)

20

dB

Output Noise

Level

-87

-85

-83

-

dBV

Ω

Load Resistance

Load Capacitance

-

30

pF

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ASAHI KASEI

[AK4633]

Parameter

Min

typ

max

Units

Speaker-Amp Characteristics: DAC Æ SPP/SPN pins, ALC2=OFF, C_L=3µF, R_serial=10Ω x 2, BTL, SVDD=3.8V

SPKG1-0 bits = “11”

Output Voltage

-

6.33

-

Vpp

(-4.1dBFS)

SPKG1-0 bits = “11”

(-4.1dBFS)

S/(N+D) (Note 13)

-

60

-

dB

Output Noise Level (Note 13) SPKG1-0 bits = “11”

Load Impedance (Note 14)

Load Capacitance

-

50

-

-81

-

3

dBV

Ω

µF

BEEP Input: BEEP pin, External Input Resistance= 20kΩ

Maximum Input Voltage (Note 15)

Output Voltage (Input Voltage=0.6Vpp)

BEEP Æ SPP/SPN (SPKG1-0 bits = “00”)

BEEP Æ AOUT

-

1.98

-

Vpp

0.625

0.25

1.25

0.50

1.875

0.75

Vpp

Power Supplies

Power Up (PDN = “H”)

All Circuit Power-up: (Note 17)

AVDD+DVDD

fs=8kHz

fs=48kHz

-

8

11

-

17

mA

SVDD: Speaker-Amp Normal Operation (SPPSN bit = “1”, No Output)

SVDD=3.3V

Power Down (PDN = “L”) (Note 18)

AVDD+DVDD+SVDD

-

4

12

mA

-

1

100

µA

Note 8. It is a differential value of plus and minus input pin. Each input pins should be connected to the AC coupling

capacitance serially. The differential input is not permission when MGAIN2-0 bits are “000”. The Maximum

input voltage of MICP and MICN pins are proportional to AVDD voltage. Vin= |(MICP) − (MICN)| = 0.069 x

AVDD (max)@MGAIN2-0 bits = “001”,

0.035 x AVDD (max)@MGAIN2-0 bits = “010”, 0.017 x AVDD (max)@MGAIN2-0 bits = “011”,

0.346 x AVDD (max)@MGAIN2-0 bits = “100”, 0.218 x AVDD (max)@MGAIN2-0 bits = “101”,

0.138 x AVDD (max)@MGAIN2-0 bits = “110”, 0.098 x AVDD (max)@MGAIN2-0 bits = “111”,

ADC function is not assumed for using the exceeded input voltage.

Note 9. Output Voltage is proportional to AVDD voltage. Vout = 0.8 x AVDD (typ).

Note 10. Input Voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ).

Note 11. When a PLL reference clock is FCK pin in PLL Slave Mode, S/(N+D):MICÆADC is 75dB (typ) and

S/(N+D):DACÆAOUT is 75dB(typ).

Note 12. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).

Note 13. In case of measuring between SPP pin and SPN pin directly.

Note 14. Load impedance is total impedance of series resistance and piezo speaker impedance at 1kHz in Figure 41. Load

capacitance is capacitance of piezo speaker. When piezo speaker is used, 10Ω or more series resistors should be

connected at both SPP and SPN pins, respectively.

Note 15. The maximum input voltage of the BEEP is proportional to AVDD voltage and external input resistance (Rin).

Vout = 0.6 x AVDD x Rin/20kΩ(max).

Note 16. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).

Note 17. In case of PLL Master Mode (MCKI=12.288MHz) and PMMP = PMADC = PMDAC = PMPFIL = PMSPK =

PMVCM = PMPLL = MCKO = PMAO = PMBP = PMMP = M/S =“1”. In this case, the output current of MPI

pin is 0mA.

When the AK4633 is EXT mode (PMPLL = MCKO = M/S = “0”), “AVDD+DVDD” is typically 6mA@fs=8kHz,

9mA@fs=48kHz.

Note 18. All digital inputs pins are fixed to DVDD or DVSS.

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ASAHI KASEI

[AK4633]

FILTER CHRACTERISTICS

(Ta = 25°C; AVDD =2.2 ∼ 3.6V, DVDD =1.6 ∼ 3.6V, SVDD =2.2 ∼ 4.0V; fs=8kHz)

Parameter

Symbol

min

typ

max

Units

ADC Digital Filter (Decimation LPF):

Passband

(Note 19) ±0.16dB

−0.66dB

PB

0

-

4.7

-

3.5

3.6

4.0

-

3.0

-

kHz

dB

−1.1dB

−6.9dB

Stopband

Passband Ripple

(Note 19)

SB

PR

-

±0.1

Stopband Attenuation

SA

GD

∆GD

73

-

16

0

-

dB

1/fs

µs

Group Delay

(Note 20)

Group Delay Distortion

DAC Digital Filter (Decimation LPF):

Passband

(Note 19)

±0.16dB

−0.54dB

−1.0dB

−6.7dB

PB

0

-

4.7

-

3.5

3.6

4.0

-

3.0

-

Stopband

Passband Ripple

(Note 19)

SB

PR

-

kHz

dB

-

±0.1

Stopband Attenuation

SA

GD

∆GD

73

-

16

0

-

dB

1/fs

µs

Group Delay

(Note 20)

Group Delay Distortion

DAC Digital Filter + Analog Filter:

Frequency Response: 0 ∼ 3.4kHz

FR

-

±1.0

-

dB

Note 19. The passband and stopband frequencies are proportional to fs (system sampling rate).

For example, ADC is PB=3.6kHz (@-1.0dB)= 0.45 x fs. A reference of frequency response is 1kHz.

Note 20. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the

16-bit data of a channel from the input register to the output register of the ADC.

For the DAC, this time is from setting the 16-bit data of a channel from the input register to the output of analog

signal.

In case of selected the path through the programming filter (1^stHPF + 2-band Equalizer + ALC), the Group

Delay should be increased to 2/fs without the phase changing by IIR filter.

DC CHRACTERISTICS

(Ta = 25°C; AVDD =2.2 ∼ 3.6V, DVDD =1.6 ∼ 3.6V, SVDD =2.2 ∼ 4.0V)

Parameter

Symbol

min

typ

max

Units

V

High-Level Input Voltage

(DVDD ≥ 2.2V)

(DVDD < 2.2V)

(DVDD ≥ 2.2V)

(DVDD < 2.2V)

(Iout=−80µA)

VIH

70%DVDD

80%DVDD

-

Low-Level Input Voltage

VIL

-

30%DVDD

20%DVDD

High-Level Output Voltage

Low-Level Output Voltage

Input Leakage Current

VOH

VOL

Iin

DVDD−0.4

-

V

(Iout= 80µA)

-

0.4

±10

-

µA

MS0447-E-03

2006/04

- 12 -

ASAHI KASEI

[AK4633]

SWITING CHARACTERISTICS

(Ta = 25°C; AVDD =2.2 ∼ 3.6V, DVDD =1.6 ∼ 3.6V, SVDD =2.2 ∼ 4.0V; C_L=20pF)

Parameter

Symbol

min

typ

max

Units

PLL Master Mode (PLL Reference Clock = MCKI pin) (Figure 2)

MCKI Input: Frequency

Pulse Width Low

Pulse Width High

MCKO Output:

fCLK

tCLKL

tCLKH

11.2896

0.4/fCLK

-

27.0

MHz

ns

-

ns

Frequency

fMCK

dMCK

fFCK

-

40

-

256 x fFCK

-

kHz

%

Duty Cycle except fs=29.4kHz,32kHz

fs=29.4kHz, 32kHz (Note 21)

FCK Output: Frequency

Pulse width High

50

33

-

60

-

%

8

48

kHz

(DIF1-0 bits = “00” and FCKO bit = “1”)

Duty Cycle

tFCKH

-

tBCK

-

ns

(DIF1-0 bits ≠ “00” or FCKO bit = “0”)

BICK: Period (BCKO1-0 = “00”)

(BCKO1-0 = “01”)

dFCK

tBCK

dBCK

-

50

-

%

ns

%

1/16fFCK

1/32fFCK

1/64fFCK

50

(BCKO1-0 = “10”)

Duty Cycle

Audio Interface Timing

DSP Mode: (Figure 3, Figure 4)

FCK “↑” to BICK “↑” (Note 22)

FCK “↑” to BICK “↓” (Note 23)

BICK “↑” to SDTO (BCKP = “0”)

BICK “↓” to SDTO (BCKP = “1”)

SDTI Hold Time

tDBF

tBSD

tSDH

tSDS

0.5 x tBCK -40

0.5 x tBCK

0.5 x tBCK + 40

ns

0.5 x tBCK -40

0.5 x tBCK

0.5 x tBCK +40

-70

50

-

70

-

SDTI Setup Time

50

-

Except DSP Mode: (Figure 5)

BICK “↓” to FCK Edge

FCK to SDTO (MSB)

tBFCK

tFSD

-40

-70

-

40

70

ns

(Except I²S mode)

BICK “↓” to SDTO

SDTI Hold Time

tBSD

tSDH

tSDS

-70

50

-

70

-

ns

SDTI Setup Time

50

-

MS0447-E-03

2006/04

- 13 -

ASAHI KASEI

[AK4633]

Parameter

Symbol

min

typ

max

Units

PLL Slave Mode (PLL Reference Clock: FCK pin) (Figure 6,Figure 7)

FCK: Frequency

DSP Mode: Pulse Width High

Except DSP Mode: Duty Cycle

BICK: Period

fFCK

tFCKH

duty

7.35

8

-

48

kHz

ns

tBCK-60

45

1/fFCK-tBCK

55

%

tBCK

1/64fFCK

0.4 x tBCK

1/16fFCK

ns

Pulse Width Low

Pulse Width High

tBCKL

tBCKH

-

ns

PLL Slave Mode (PLL Reference Clock: BICK pin) (Figure 6,Figure 7)

FCK: Frequency

DSP Mode: Pulse width High

fFCK

tFCKH

duty

7.35

8

48

kHz

ns

tBCK-60

-

1/fFCK-tBCK

Except DSP Mode: Duty Cycle

BICK: Period (PLL3-0 = “0001”)

(PLL3-0 = “0010”)

45

-

55

-

%

tBCK

tBCKL

tBCKH

-

1/16fFCK

ns

-

1/32fFCK

-

ns

(PLL3-0 = “0011”)

Pulse Width Low

-

1/64fFCK

-

ns

0.4 x tBCK

-

ns

Pulse Width High

-

ns

PLL Slave Mode (PLL Reference Clock: MCKI pin) (Figure 8)

MCKI Input: Frequency

Pulse Width Low

Pulse Width High

MCKO Output:

fCLK

fCLKL

fCLKH

11.2896

0.4/fCLK

-

27.0

MHz

ns

-

ns

Frequency

fMCK

dMCK

fFCK

-

256 x fFCK

-

kHz

%

Duty Cycle except fs=29.4kHz, 32kHz

fs=29.4kHz, 32kHz (Note 21)

FCK: Frequency

40

-

50

33

-

60

-

%

8

48

kHz

DSP Mode: Pulse width High

Except DSP Mode: Duty Cycle

BICK: Period

tFCKH

duty

tBCK-60

45

-

1/fFCK-tBFCK

ns

%

ns

-

55

tBCK

1/64fFCK

0.4 x tBCK

-

1/16fFCK

Pulse Width Low

tBCKL

tBCKH

-

Pulse Width High

-

Audio Interface Timing

DSP Mode: (Figure 9, Figure 10)

FCK “↑” to BICK “↑” (Note 22)

FCK “↑” to BICK “↓” ()

tFCKB

tBFCK

tBSD

tSDH

tSDS

0.4 x tBCK

-

ns

BICK “↑” to FCK “↑” (Note 22)

BICK “↓” to FCK “↑” ()

BICK “↑” to SDTO (BCKP = “0”)

BICK “↓” to SDTO (BCKP = “1”)

SDTI Hold Time

-

50

80

-

SDTI Setup Time

-

Except DSP Mode: (Figure 12)

FCK Edge to BICK “↑” (Note 24)

BICK “↑” to FCK Edge (Note 24)

FCK to SDTO (MSB) (Except I²S mode)

BICK “↓” to SDTO

tFCKB

tBFCK

tFSD

tBSD

tSDH

tSDS

50

-

50

-

80

-

ns

SDTI Hold Time

SDTI Setup Time

-

MS0447-E-03

2006/04

- 14 -

ASAHI KASEI

[AK4633]

Parameter

Symbol

min

typ

max

Units

EXT Slave Mode (Figure 11)

MCKI Frequency: 256fs

512fs

fCLK

tCLKL

tCLKH

fFCK

1.8816

3.7632

7.5264

0.4/fCLK

7.35

2.048

12.288

MHz

ns

4.096

13.312

1024fs

8.192

13.312

Pulse Width Low

Pulse Width High

FCK Frequency (MCKI = 256fs)

(MCKI = 512fs)

(MCKI = 1024fs)

Duty Cycle

-

ns

8

-

48

26

13

55

-

kHz

%

fFCK

7.35

fFCK

7.35

duty

45

BICK Period

tBCK

tBCKL

tBCKH

312.5

130

-

ns

BICK Pulse Width Low

Pulse Width High

-

ns

130

-

ns

Audio Interface Timing (Figure 12)

FCK Edge to BICK “↑” (Note 24)

BICK “↑” to FCK Edge (Note 24)

FCK to SDTO (MSB) (Except I²S mode)

BICK “↓” to SDTO

tFCKB

tBFCK

tFSD

50

-

ns

80

-

tBSD

tSDH

tSDS

-

SDTI Hold Time

50

SDTI Setup Time

-

MS0447-E-03

2006/04

- 15 -

ASAHI KASEI

[AK4633]

Parameter

Symbol

min

typ

max

Units

EXT Master Mode (Figure 2)

MCKI Frequency: 256fs

512fs

fCLK

tCLKL

tCLKH

fFCK

dFCK

tBCK

dBCK

1.8816

2.048

12.288

MHz

ns

3.7632

4.096

13.312

1024fs

7.5264

8.192

13.312

Pulse Width Low

Pulse Width High

FCK Frequency (MCKI = 256fs)

(MCKI = 512fs)

0.4/fCLK

-

0.4/fCLK

-

ns

7.35

8

48

26

13

-

kHz

%

7.35

8

(MCKI = 1024fs)

Duty Cycle

7.35

-

50

BICK: Period (BCKO1-0 bit= “00”)

(BCKO1-0 bit= “01”)

(BCKO1-0 bit= “10”)

Duty Cycle

1/16fFCK

1/32fFCK

1/64fFCK

50

-

ns

-

ns

-

ns

-

%

Audio Interface Timing

DSP Mode: (Figure 3, Figure 4)

FCK “↑” to BICK “↑” (Note 22)

FCK “↑” to BICK “↓” (Note 23)

BICK “↑” to SDTO (BCKP bit= “0”)

BICK “↓” to SDTO (BCKP bit= “1”)

SDTI Hold Time

tDBF

tBSD

tSDH

tSDS

0.5 x tBCK -40

0.5 x tBCK

0.5 x tBCK + 40

ns

0.5 x tBCK -40

0.5 x tBCK

0.5 x tBCK +40

-70

50

-

70

-

SDTI Setup Time

50

-

Except DSP Mode: (Figure 5)

BICK “↓” to FCK Edge

FCK to SDTO (MSB)

tBFCK

tFSD

-40

-70

-

40

70

ns

(Except I²S mode)

BICK “↓” to SDTO

SDTI Hold Time

tBSD

tSDH

tSDS

-70

50

-

70

-

ns

SDTI Setup Time

50

-

Note 21. Duty Cycle = (the width of “L” ) / (the period of clock) × 100

Note 22. MSBS, BCKP bits = “00” or “11”

Note 23. MSBS, BCKP bits = “01” or “10”

Note 24. BICK rising edge must not occur at the same time as FCK edge.

MS0447-E-03

2006/04

- 16 -

ASAHI KASEI

[AK4633]

Parameter

Symbol

min

typ

max

Units

Control Interface Timing:

CCLK Period

tCCK

tCCKL

tCCKH

tCDS

200

80

40

150

50

-

ns

CCLK Pulse Width Low

Pulse Width High

-

CDTI Setup Time

-

CDTI Hold Time

tCDH

tCSW

tCSS

-

CSN “H” Time

-

CSN “↓“ to CCLK “↑“

CCLK “↑“ to CSN “↑“

CCLK “↓“ to CDTI (at Read Command)

CSN “↑“ to CDTI (Hi-Z) (at Read Command)

-

tCSH

-

tDCD

tCCZ

70

-

Reset Timing

PDN Pulse Width

(Note 25)

(Note 26)

tPD

150

-

ns

PMADC “↑“ to SDTO valid

ADRST bit = “0”

ADRST bit = “1”

tPDV

-

1059

291

-

1/fs

Note 25. The AK4633 can be reset by the PDN pin = “L”.

Note 26. This is the count of FCK “↑“ from the PMADC = “1”.

MS0447-E-03

2006/04

- 17 -

ASAHI KASEI

[AK4633]

Timing Diagram

1/fCLK

VIH

VIL

MCKI

tCLKH

dFCK

tCLKL

dFCK

1/fFCK

50%DVDD

FCK

1/fMCK

MCKO

50%DVDD

tMCKOH

tMCKOL

dMCK = tMCKOL x fMCK x 100%

Figure 2. Clock Timing (PLL/EXT Master mode) (MCKO isn’t available at EXT Master Mode)

FCK

50%DVDD

tBCK

tDBF

dBCK

BICK

(BCKP = "0")

50%DVDD

BICK

(BCKP = "1")

tBSD

SDTO

50%DVDD

MSB

tSDH

tSDS

VIH

VIL

SDTI

MSB

Figure 3. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “0”)

MS0447-E-03

2006/04

- 18 -

ASAHI KASEI

[AK4633]

FCK

50%DVDD

tBCK

tDBF

dBCK

BICK

(BCKP = "1")

50%DVDD

BICK

(BCKP = "0")

tBSD

SDTO

50%DVDD

MSB

tSDH

tSDS

VIH

VIL

SDTI

MSB

Figure 4. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “1”)

50%DVDD

FCK

tBFCK

dBCK

BICK

SDTO

SDTI

50%DVDD

tFSD

tBSD

tSDS

tSDH

VIH

VIL

Figure 5. Audio Interface Timing (PLL/EXT Master mode & Except DSP mode)

MS0447-E-03

2006/04

- 19 -

ASAHI KASEI

[AK4633]

1/fFCK

VIH

VIL

FCK

tFCKH

tBCKH

tBFCK

tBCK

VIH

VIL

BICK

(BCKP = "0")

tBCKL

VIH

VIL

BICK

(BCKP = "1")

Figure 6. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = 0)

1/fFCK

VIH

FCK

VIL

tFCKH

tBCKH

tBFCK

tBCK

VIH

VIL

BICK

(BCKP = "1")

tBCKL

VIH

VIL

BICK

(BCKP = "0")

Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = FCK or BICK pin & DSP mode; MSBS = 1)

MS0447-E-03

2006/04

- 20 -

ASAHI KASEI

[AK4633]

1/fCLK

VIH

VIL

MCKI

tCLKH

tCLKL

1/fFCK

VIH

VIL

FCK

tFCKH

tFCKL

tBCK

VIH

VIL

BICK

tBCKH

tBCKL

1/fMCK

50%DVDD

MCKO

tMCKOH

tMCKOL

dMCK = tMCKOL x fMCK x 100%

Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode)

MS0447-E-03

2006/04

- 21 -

ASAHI KASEI

[AK4633]

tFCKH

VIH

VIL

FCK

tFCKB

VIH

VIL

BICK

(BCKP = "0")

VIH

VIL

BICK

(BCKP = "1")

tBSD

SDTO

SDTI

50%DVDD

MSB

tSDH

tSDS

VIH

VIL

MSB

Figure 9. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 0)

tFCKH

VIH

FCK

VIL

tFCKB

VIH

VIL

BICK

(BCKP = "1")

VIH

VIL

BICK

(BCKP = "0")

tBSD

SDTO

50%DVDD

MSB

tSDS

tSDH

VIH

VIL

SDTI

MSB

Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1)

- 22 -

MS0447-E-03

2006/04

ASAHI KASEI

[AK4633]

1/fCLK

VIH

VIL

MCKI

tCLKH

tCLKL

1/fFCK

VIH

VIL

FCK

tFCKH

tBCKH

tFCKL

tBCKL

tBCK

VIH

VIL

BICK

Figure 11. Clock Timing (EXT Slave mode)

VIH

FCK

VIL

tBFCK

tFCKB

VIH

VIL

BICK

SDTO

SDTI

tFSD

tBSD

50%DVDD

MSB

tSDS

tSDH

VIH

VIL

Figure 12. Audio Interface Timing (PLL, EXT Slave mode & Except DSP mode)

MS0447-E-03

2006/04

- 23 -

ASAHI KASEI

[AK4633]

VIH

CSN

VIL

tCSS

tCCKL

tCCKH

VIH

VIL

CCLK

CDTI

tCCK

tCDH

tCDS

VIH

VIL

C1

C0

R/W

Figure 13. WRITE Command Input Timing

tCSW

VIH

VIL

CSN

tCSH

VIH

VIL

CCLK

CDTI

VIH

VIL

D2

D1

D0

Figure 14. WRITE Data Input Timing

MS0447-E-03

2006/04

- 24 -

ASAHI KASEI

[AK4633]

VIH

VIL

CSN

VIH

VIL

CCLK

CDTI

tCCZ

tDCD

50%

DVDD

D3

D2

D1

D0

Figure 15 . Read Data Output Timing

PMADC

bit

tPDV

SDTO

50%DVDD

Figure 16. Power Down & Reset Timing 1

tPD

PDN

VIL

Figure 17. Power Down & Reset Timing 2

MS0447-E-03

2006/04

- 25 -

ASAHI KASEI

[AK4633]

OPERATION OVERVIEW

System Clock

There are the following four clock modes to interface with external devices (Table 1 and Table 2).

Mode

PMPLL bit M/S bit

PLL3-0 bit

Table 4

Figure

Figure 18

PLL Master Mode

PLL Slave Mode 1

(PLL Reference Clock: MCKI pin)

PLL Slave Mode 2

(PLL Reference Clock: FCK or BICK pin)

1

0

Table 4

Figure 19

Figure 20

1

0

EXT Slave Mode

EXT Master Mode

0

1

X

Figure 21

Figure 22

Table 1. Clock Mode Setting (X: Don’t care)

Mode

MCKO bit

MCKO pin

MCKI pin

BICK pin

FCK pin

Master Clock

Input for PLL

(Note 27)

0

1

16fs/32fs/64fs

Output

1fs

Output

“L” Output

PLL Master Mode

256fs Output

Master Clock

Input for PLL

(Note 27)

0

1

“L” Output

PLL Slave Mode 1

(PLL Reference Clock: MCKI pin)

16fs/32fs/64fs

Input

1fs

Input

256fs Output

PLL Slave Mode 2

(PLL Reference Clock: FCK or BICK pin)

16fs/32fs/64fs

Input

1fs

Input

0

GND

“L” Output

256fs/

512fs/

1024fs

Input

256fs/

512fs/

1024fs

Input

1fs

Input

≥ 32fs

Input

EXT Slave Mode

EXT Master Mode

32fs/64fs

Output

1fs

Output

0

“L” Output

Note 27. 11.2896MHz/12MHz/12.288MHz/13.5MHz/24MHz/27MHz

Table 2. Clock pins state in Clock Modes

MS0447-E-03

2006/04

- 26 -

ASAHI KASEI

[AK4633]

Master Mode/Slave Mode

The M/S bit selects either master or slave modes. M/S bit = “1” selects master mode and “0” selects slave mode. When the

AK4633 is power-down mode (PDN pin = “L”) and exits reset state, the AK4633 is slave mode. After exiting reset state,

the AK4633 goes master mode by changing M/S bit = “1”.

When the AK4633 is used by master mode, FCK and BICK pins are a floating state until M/S bit becomes “1”. FCK and

BICK pins of the AK4633 should be pulled-down or pulled-up by about 100kΩ resistor externally to avoid the floating

state.

M/S bit

Mode

0

1

Slave Mode

Master Mode

Default

Table 3. Select Master/Salve Mode

PLL Mode

When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the

PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK4633 is supplied to a stable clocks after

PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes.

1) Setting of PLL Mode

PLL

Reference

Clock Input

R and C of VCOC

pin(Note 28)

PLL

Lock

Time

(max)

PLL3 PLL2 PLL1 PLL0

Input

Frequency

Mode

bit

C[F]

R[Ω]

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FCK pin

BICK pin

MCKI pin

N/A

1fs

16fs

32fs

6.8k

10k

220n

4.7n

10n

160ms

2ms

Default

64fs

2ms

11.2896MHz

12.288MHz

12MHz

24MHz

13.5MHz

27MHz

40ms

12

13

Others

1

10n

Others

Note 28. The tolerance of R is ±5%, C is ±30%.

Table 4. Setting of PLL Mode (*fs: Sampling Frequency)

2) Setting of sampling frequency in PLL Mode.

When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS2-0 bits as

defined in Table 5.

Mode

0

1

2

3

4

5

6

7

10

11

14

15

Others

FS3 bit

FS2 bit

FS1 bit

FS0 bit

Sampling Frequency

8kHz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Default

12kHz

16kHz

24kHz

7.35kHz

11.025kHz

14.7kHz

22.05kHz

32kHz

48kHz

29.4kHz

44.1kHz

N/A

Others

Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1”

MS0447-E-03

2006/04

- 27 -

ASAHI KASEI

[AK4633]

When PLL2 bit is “0”(PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS3-2 bits

(Table 6).

FS3 bit

FS2 bit

Sampling Frequency

Range

Mode

FS1 bit

FS0 bit

0

1

0

1

0

Don’t care

0

1

2

Don’t care

Default

7.35kHz ≤ fs ≤ 12kHz

12kHz < fs ≤ 24kHz

24kHz < fs ≤ 48kHz

N/A

Others

Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1”

PLL Unlock State

1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)

In this mode, after PMPLL bit = “0” Æ “1” and until PLL locked , “L” are output from BICK and FCK pins and invalid

frequency clock is output from MCKO pin when MCKO bit is “1”. If MCKO bit is “0”, “L” is output from MCKO pin.

( Table 7)

In case that sampling frequency is changed, setting PMPLL bit to “0” once a time could be prevent BICK and FCK pins

output to “L” from unstable clocks.

MCKO pin

MCKO bit = “0” MCKO bit = “1”

PLL State

BICK pin

FCK pin

Invalid

256fs Output

Invalid

“L” Output

See Table 9

Invalid

“L” Output

1fs Output

After that PMPLL bit “0” Æ “1”

PLL Unlock

PLL Lock

“L” Output

Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)

2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)

In this mode, an invalid clock is output from MCKO pin after PMPLL bit = “0” Æ “1” or sampling frequency is changed.

After that, 256fs clock is output from MCKO pin while PLL is locked. However, the normal data couldn’t output from

ADC and DAC while PLL is unlocked. For DAC, the output signal should be muted by setting “0” to DACA and DACM

bits in Addr=02H.

MCKO pin

PLL State

MCKO bit = “0”

“L” Output

MCKO bit = “1”

Invalid

After that PMPLL bit “0” Æ “1”

PLL Unlock

Invalid

“L” Output

PLL Lock

256fs Output

“L” Output

Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)

MS0447-E-03

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ASAHI KASEI

[AK4633]

PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)

When an external clock (11.2896MHz, 12MHz , 12.288MHz, 13.5MHz, 24MHz or 27MHz) is input to MCKI pin, the

MCKO, BICK and FCK clocks are generated by an internal PLL circuit. The MCKO output frequency is fixed to 256fs,

the output is enabled by MCKO bit. The BICK is selected among 16fs, 32fs or 64fs, by BCKO1-0 bits (Table 9).

As the DSP mode, the FCK pin is output as 50% duty or 1 BICK period high output by FCK bit (Note 11). In addition to

DSP mode, FCK bit should be set to “0”.

When BICK output frequency is 16fs, the audio interface format supports only Mode 0 (DSP Mode).

11.2896MHz, 12MHz, 12.288MHz

13.5MHz, 24MHz, 27MHz

AK4633

DSP or P

µ

MCKI

256fs

16fs, 32fs, 64fs

1fs

MCKO

BICK

FCK

MCLK

BCLK

FCK

SDTI

SDTO

SDTI

SDTO

Figure 18. PLL Master Mode

BICK Output

Frequency

Mode

BCKO1

BCKO0

0

1

2

3

0

1

0

1

0

1

16fs

32fs

64fs

N/A

Default

Table 9. BICK Output Frequency at PLL Master Mode

Mode

0

1

FCKO

FCK Output

Duty = 50%

High Width = 1/fBCK

0

1

Default

fBCK is the output frequency of BICK

Table 10. FCK Output at PLL Master Mode and DSP Mode

MS0447-E-03

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ASAHI KASEI

[AK4633]

PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)

A reference clock of PLL is selected among the input clocks to MCKI, BICK or FCK pin. The required clock to the

AK4633 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits. When BICK input frequency

is 16fs, the audio interface format supports only Mode 0(DSP Mode).

a) PLL reference clock: MCKI pin

BICK and FCK inputs should be synchronized with MCKO output. The phase between MCKO and FCK dose not

matter. Sampling frequency can be selected by FS3-0 bits(Table 5).

11.2896MHz, 12MHz, 12.288MHz

13.5MHz, 24MHz, 27MHz

AK4633

DSP or µP

MCKI

256fs

MCLK

BCLK

FCK

MCKO

BICK

FCK

16fs, 32fs, 64fs

1fs

SDTI

SDTO

SDTI

SDTO

Figure 19. PLL Slave Mode1 (PLL Reference Clock: MCKI pin)

b) PLL reference clock: BICK or FCK pin

In case of using BICK or FCK as PLL reference clock, the sampling frequency corresponds to 7.35kHz to 48kHz by

FS3-0 bits(Table 6).

AK4633

MCKO

DSP or µP

MCKI

16fs, 32fs, 64fs

BCLK

FCK

BICK

FCK

1fs

SDTI

SDTO

SDTI

SDTO

Figure 20. PLL Slave Mode 1 (PLL Reference Clock: FCK or BICK pin)

The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC or Programmable

Filter are in operation (PMADC bit = “1” or PMDAC bit = “1” or PMPFIL bit = “1”). If these clocks are not provided, the

AK4633 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic

internally. If the external clocks are not present, the ADC, DAC and Programmable Filter should be in the power-down

mode (PMADC bit =PMDAC bit = PMPFIL bit = “0”).

MS0447-E-03

2006/04

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ASAHI KASEI

[AK4633]

EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)

When PMPLL bit is “0” and M/S bit is “0”, the AK4633 becomes EXT slave mode. Master clock is input from MCKI pin,

the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks

required to operate are MCKI (256fs, 512fs or 1024fs), BICK (≥32fs) and FCK (fs). The master clock (MCKI) should be

synchronized with FCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by

FS3-0 bits ( Table 11).

Mode

FS3-2 bits

FS1 bit

FS0 bit

MCKI Input

Frequency

Sampling Frequency

Range

Don’t care

0

1

0

1

256fs

1024fs

512s

Default

0

1

2

3

0

1

7.35kHz ≤ fs ≤ 48kHz

7.35kHz < fs ≤ 13kHz

7.35kHz < fs ≤ 26kHz

7.35kHz < fs ≤ 48kHz

256fs

Table 11. Setting MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)

External Slave Mode does not support Mode 0 (DSP Mode) of Audio Interface Format.

The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.

When the out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output

through AOUT amp at fs=8kHz is shown in Table 12.

S/N

MCKI

(fs=8kHz, 20kHzLPF + A-weighted)

256fs

512fs

1024fs

84dB

92dB

Table 12. Relationship between MCKI and S/N of AOUT

The external clocks (MCKI, BICK and FCK) should always be present whenever the ADC or DAC or Programmable

Filter are in operation (PMADC bit = “1” or PMDAC bit = “1” or PMPFIL bit = “1”). If these clocks are not provided, the

AK4633 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic

internally. If the external clocks are not present, the ADC, DAC and Programmable Filter should be in the power-down

mode (PMADC bit =PMDAC bit = PMPFIL bit = “0”).

AK4633

MCKO

DSP or µP

256fs, 512fs or 1024fs

MCKI

BICK

FCK

MCLK

BCLK

FCK

32fs, 64fs

1fs

SDTI

SDTO

SDTI

SDTO

Figure 21. EXT Slave Mode

MS0447-E-03

2006/04

- 31 -

ASAHI KASEI

[AK4633]

EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)

When PMPLL bit is “0” and M/S bit is “1”, the AK4633 becomes clock master mode(EXT Master Mode). Master clock is

input from MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or

1024fs). The input frequency of MCKI is selected by FS3-0 bits (Table 11). The output frequency of BICK is selected to

32fs or 64fs by setting BCKO1-0 bit (Table 14). FCK bit should be set to “0”.

Mode

FS3-2 bits

FS1 bit

FS0 bit

MCKI Input

Frequency

Sampling Frequency

Range

Don’t care

0

1

0

1

256fs

1024fs

512s

Default

0

1

2

3

0

1

7.35kHz ≤ fs ≤ 48kHz

7.35kHz < fs ≤ 13kHz

7.35kHz < fs ≤ 26kHz

7.35kHz < fs ≤ 48kHz

256fs

Table 13. Setting MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “1”)

External Master Mode does not support Mode 0 (DSP Mode) of Audio Interface Format.

MCKI should always be present whenever the ADC or DAC or Programmable Filter is in operation (PMADC bit = “1” or

PMDAC bit = “1” or PMPFIL bit = “1”). If MCKI is not provided, the AK4633 may draw excess current and it is not

possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC, DAC

and Programmable Filter should be in the power-down mode (PMADC bit =PMDAC bit = PMPFIL bit = “0”).

AK4633

MCKO

DSP or µP

256fs, 512fs or 1024fs

MCKI

BICK

FCK

MCLK

BCLK

FCK

32fs, 64fs

1fs

SDTI

SDTO

SDTI

SDTO

Figure 22. EXT Master Mode

BICK Output

Frequency

Mode

BCKO1

BCKO0

0

1

2

3

0

1

0

1

0

1

N/A

32fs

64fs

N/A

Default

Table 14. BICK Output Frequency at EXT Master Mode

MS0447-E-03

2006/04

- 32 -

ASAHI KASEI

[AK4633]

Audio Interface Format

Four types of data formats are available and are selected by setting the DIF1-0 bits (Table 15). In all modes, the serial data

is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. FCK and

BICK are output from AK4633 in master mode, but must be input to AK4633 in slave mode.

In Mode 1-3, the SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising edge.

Mode

DIF1

DIF0

SDTO (ADC)

DSP Mode

SDTI (DAC)

DSP Mode

LSB justified

MSB justified

BICK

≥ 16fs

≥ 32fs

Figure

0

1

2

3

0

1

0

1

0

1

Table 16

Figure 23

Figure 24

Figure 25

MSB justified

Default

I²S compatible I²S compatible

Table 15. Audio Interface Format

In Mode0 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits.

When BCKP bit is “0”, SDTO data is output by rising edge of BICK, SDTI data is latched by falling edge of BICK.

When BCKP bit is “1”, SDTO data is output by falling edge of BICK, SDTI data is latched by rising edge of BICK.

MSB data position of SDTO and SDTI can be shifted by MSBS bit. The shifted period is a half of BICK.

MSBS bit BCKP bit

Audio Interface Format

Figure 26

0

1

0

1

0

1

Default

Figure 27

Figure 28

Figure 29

Table 16. Audio Interface Format in Mode 0

If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, “−1” at 16bit data is converted to “−1” at

8-bit data. And when the DAC playbacks this 8-bit data, “−1” at 8-bit data will be converted to “−256” at 16-bit data and

this is a large offset. This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit

data.

FCK

0

1

2

3

8

9

10 11

12

13 14

15

0

1

2

3

8

9

10 11

12

13 14

15

0

1

BICK(32fs)

SDTO(o)

15 14

8

7

6

5

4

3

2

1

0

15

13

SDTI(i)

15 14

5

2

13

Don’t Care

0

1

2

3

14

15 16

17

18

31

0

1

2

3

14

15 16

17

18

31

0

1

BICK(64fs)

SDTO(o)

15 14 13

2

1

0

15

Don’t Care

15:MSB, 0:LSB

15 14

1

0

Don’t Care

SDTI(i)

Data

1/fs

Figure 23. Mode 1 Timing

MS0447-E-03

2006/04

- 33 -

ASAHI KASEI

[AK4633]

FCK

0

1

2

8

9

10 11

12

13 14

15

0

1

2

8

9

10 11

12

13 14

15

0

1

BICK(32fs)

SDTO(o)

15 14

8

7

6

5

4

3

2

1

0

15

SDTI(I)

15 14

5

2

Don’t Care

0

1

2

3

14

15 16

17

18

31

0

1

2

3

14

15 16

17

18

31

0

1

BICK(64fs)

SDTO(o)

15 14 13 13

2

1

0

15

SDTI(i)

15 14 13 13

15:MSB, 0:LSB

Don’t Care

Data

1/fs

Figure 24. Mode 2 Timing

FCK

0

1

2

3

4

9

10 11

12

13 14

15

0

1

2

3

4

9

10 11

12

13 14

15

0

1

BICK(32fs)

SDTO(o)

15

13

7

6

5

4

3

2

1

0

14

SDTI(i)

15 14 13

7

6

3

0

1

2

3

4

14

15 16

17

18

31

0

1

2

3

4

14

15 16

17

18

31

0

1

BICK(64fs)

SDTO(o)

15 14

2

1

0

13

15 14 13

15:MSB, 0:LSB

Don’t Care

SDTI(i)

Data

1/fs

Figure 25. Mode 3 Timing

MS0447-E-03

2006/04

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ASAHI KASEI

[AK4633]

FCK

15

0

1

8

9

10

11

12 13

14 15

0

1

8

9

10

11

12 13

14 15

0

2

BICK(16fs)

SDTO(o)

0

15

8

7

6

5

4

3

2

1

0

15

8

7

6

5

4

3

2

1

0

14

SDTI(i)

15

0

1

8

14

15 16

17

18 29

30 31

0

1

8

9

10

11

12 13

30 31

0

2

BICK(32fs)

SDTO(o)

15

8

2

1

0

15

8

2

1

0

14

0

SDTI(i)

Don’t Care

1/fs

15:MSB, 0:LSB

Figure 26. Mode 0 Timing (BCKP = “0”, MSBS = “0”)

FCK

15

0

1

8

9

10

11

12 13

14 15

0

1

8

9

10

11

12 13

14 15

0

2

BICK(16fs)

SDTO(o)

0

15

8

7

6

5

4

3

2

1

0

15

8

7

6

5

4

3

2

1

0

14

SDTI(i)

15

0

1

8

14

15 16

17

18 29

30 31

0

1

8

9

10

11

12 13

30 31

0

2

BICK(32fs)

SDTO(o)

15

8

2

1

0

15

8

2

1

0

14

0

SDTI(i)

Don’t Care

1/fs

15:MSB, 0:LSB

Figure 27. Mode 0 Timing (BCKP = “1”, MSBS = “0”)

MS0447-E-03

2006/04

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ASAHI KASEI

[AK4633]

FCK

15

0

1

8

9

10

11

12 13

14 15

0

1

8

9

10

11

12 13

14 15

0

2

BICK(16fs)

SDTO(o)

0

15

8

7

6

5

4

3

2

1

0

15

8

7

6

5

4

3

2

1

0

14

SDTI(i)

15

0

1

8

14

15 16

17

18 29

30 31

0

1

8

9

10

11

12 13

30 31

0

2

BICK(32fs)

SDTO(o)

15

8

2

1

0

15

8

2

1

0

14

0

SDTI(i)

Don’t Care

1/fs

15:MSB, 0:LSB

Figure 28. Mode 0 Timing (BCKP = “0”, MSBS = “1”)

FCK

15

0

1

8

9

10

11

12 13

14 15

0

1

8

9

10

11

12 13

14 15

0

2

BICK(16fs)

SDTO(o)

0

15

8

7

6

5

4

3

2

1

0

15

8

7

6

5

4

3

2

1

0

14

SDTI(i)

15

0

1

8

14

15 16

17

18 29

30 31

0

1

8

9

10

11

12 13

30 31

0

2

BICK(32fs)

SDTO(o)

15

8

2

1

0

15

8

2

1

0

14

0

SDTI(i)

Don’t Care

1/fs

15:MSB, 0:LSB

Figure 29. Mode 0 Timing (BCKP = “1”, MSBS = “1”)

MS0447-E-03

2006/04

- 36 -

ASAHI KASEI

[AK4633]

System Reset

Upon power-up, reset the AK4633 by bringing the PDN pin = “L”. This ensures that all internal registers reset to their

initial values.

The ADC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The initialization cycle

time is selected by ADRST bit (Table 17). During the initialization cycle, the ADC digital data outputs of both channels

are forced to a 2's compliment, “0”. The ADC output reflects the analog input signal after the initialization cycle is

complete. The DAC does not require an initialization cycle.

(Note) The initial data of ADC has the offset data that depends on the condition of the microphone and the cut-off

frequency of HPF. If this offset isn’t small, the longer initialization cycle should be selected as ADRSTbit=“0” in

order to prevent the offset data. Or, do not use the initial data of ADC.

Init Cycle

ADRST bit

Cycle

1059/fs

291/fs

fs = 8kHz

132.4ms

36.4ms

fs = 16kHz

66.2ms

fs = 48kHz

22.1ms

6.1ms

0

1

18.2ms

Table 17. Initialization cycle of ADC

MIC Gain Amplifier

The AK4633 has a Gain Amplifier for Microphone input. This gain is selected by MGAIN2-0 bits. The typical input

impedance is 30kΩ.

MGAIN2 bit MGAIN1 bit MGAIN0 bit

Input Gain

0dB

+20dB

+26dB

+32dB

+6dB

+10dB

+14dB

+17dB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Default

Table 18. Input Gain

MS0447-E-03

2006/04

- 37 -

ASAHI KASEI

[AK4633]

MIC Power

The MPI pin supplies power for the Microphone. This output voltage scales with 0.8 x AVDD (typ) and the load

resistance is minimum 2kΩ. Don’t connect the capacitor directly to MPI pin

AK4633

MIC-Power

MPI pin

≥ 2k

Audio

I/F

MIC pin

BICK pin

FCK pin

A/D HPF

STDO pin

MIC-Amp

Figure 30. MIC Block Circuit

MIC Differential Input

The MIC input becomes an differential input when MDIF bit is “1”. The input pins are MIC and MICP pins. At this time,

the MICP pin couldn’t be used for an BEEP input. When MDIF bit is “1”, the PMBP, BEEPA and BEEPS bits should be

set to “0”.

AK4633

MIC-Power

MPI pin

1k

MICP pin

BICK pin

FCK pin

STDO pin

Audio

I/F

MICN pin

A/D HPF

MIC-Amp

1k

Figure 31. MIC Differential Input Circuit

MS0447-E-03

2006/04

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ASAHI KASEI

[AK4633]

Digital Block

Digital Block is composed as Figure 32.The recording and playback single paths are selected by ADCPF bit, PFDAC bit

and PFSDO bit (Figure 32~ Figure 35, Table 19)

PMADC bit

SDTI

ADC

1st Order

HPFAD bit

HPF

“1”

“0”

ADCPF bit

PMPFIL bit

HPF bit

1st Order

HPF

2 Band

EQ2-1 bits

EQ

ALC

(Volume)

“0”

“1”

“0”

PFSDO bit

PFDAC bit

PMDAC bit

DATT

SDTO

SMUTE

DAC

(1) ADC : Include the Digital Filter(LPF) for ADC as shown in “FILTER CHRACTERISTICS”.

(2) DAC : Include the Digital Filter(LPF) for DAC as shown in “FILTER CHRACTERISTICS”.

(3) HPF : High Pass Filter. Enable to use for a Wind-Noise Reduction Filter. (See “Programmable Filter”)

(4) EQ : using for an Equalizer or Notch Filter. (See “Programmable Filter”)

(5) Volume : Digital Volume with ALC function. (See “Digital Volume” or “ALC”)

(6) DATT : 4 steps Digital Volume for playback path.( See “Output Digital Volume2”)

(7) SMUTE : Soft mute.

Figure 32. Digital block path

MS0447-E-03

2006/04

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ASAHI KASEI

[AK4633]

Mode

ADCPF bit

PFDAC bit

PFSDO bit

Figure

Recoding Main Mode

Playback Main Mode

Loop Back Mode

1

0

1

0

1

0

1

Figure 33

Figure 34

Figure 35

Table 19. Recode/Playback Mode

2nd Order

2 Band

ALC

(Volume)

ADC

DAC

HPF

EQ

SMUTE

DATT

Figure 33. The path at ADCPF bit = “1”, PFDAC bit = “0” and PFSDO bit = “1” (Default)

1st Order

ADC

HPF

2 Band

1st Order

ALC

(Volume)

DAC

SMUTE

DATT

EQ

HPF

Figure 34. The path at ADCPF bit = “0”, PFDAC bit = “1” and PFSDO bit = “0”

2nd Order

2 Band

ALC

(Volume)

ADC

DAC

HPF

EQ

SMUTE

DATT

Figure 35. The path at ADCPF bit = “1”, PFDAC bit = “1” and PFSDO bit = “1”

MS0447-E-03

2006/04

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ASAHI KASEI

[AK4633]

Digital Programmable Filter

The AK4633 have 2steps of 1st order HPF and 2 band Equalizer for recording and playback path (Figure 32).

(1) High Pass Filter (HPF)

Normally, this HPF is used for a Wind-Noise Reduction Filter. This is composed with 2 steps of 1st order HPF. The

coefficient of both HPF is same and should be set by F1A13-0 bits and F1B13-0 bits. The HPF of ADC could be ON/OFF

by HPFAD bit, and the HPF before 2 band EQ could be ON/Off by setting HPF bit. When the HPF is OFF, the audio data

passes this block by 0dB . The coefficient should be set when HPFAD bit = HPF bit = “0” or PMADC bit = PMPFIL bit

= “0”. After changing the coefficient, the HPF starts with 3/fs (max) delay time after (HPFAD bit and PMADC bit) or

(HPF bit and PMPFIL bit) are set to “1”. The waiting time is not necessity for setting HPFAD bit, HPF bit, PMADC bit

and PMPFIL bit to “1” after setting the coefficient.

fs: Sampling frequency

fc: Cut-off frequency

Register setting (Note 29)

HPF: F1A[13:0] bits =A, F1B[13:0] bits =B

(MSB=F1A13, F1B13; LSB=F1A0, F1B0)

1

1− tan (πfc/fs)

1 + tan (πfc/fs)

A =

,

B =

1 + tan (πfc/fs)

The cut-off frequency should be set as below.

fc/fs ≥ 0.0001 (fc min = 1.6Hz at 16kHz)

(2) 2 band Equalizer

This could be used as Equalizer or notch filter. 2 band Equalizer (EQ1 and EQ2) are ON/OFF independently by EQ1 bit

and EQ2 bit. When Equalizer is OFF, the audio data passes this block by 0dB. The coefficient of EQ1 should be set by

E1A15-0 bits, E1B15-0 bits and E1C15-0 bits, the coefficient of EQ2 should be set by E2A15-0 bits, E2B15-0 bits and

E2C15-0 bits. The EQ1 coefficient should be set when EQ1 bit = “0” or PMPFIL bit = “0”, the EQ2 coefficient should be

set when EQ2 bit = “0” or PMPFIL bit = “0”. After changing the coefficient, the Equalizer starts with 3/fs (max) delay

time after (EQ1 bit and PMPFIL bit) or (EQ2 bit and PMPFIL bit) are set to “1”. The waiting time is not necessity for

setting EQ1 bit, EQ2 bit and PMPFIL bit to “1” after setting the coefficient.

fs: Sampling frequency

fo: Center frequency

fb: Band width of 3dB gain difference from center frequency

K : Gain ( -1 ≤ K < 3 )

Register setting(Note 29)

EQ1: E1A[15:0] bits =A, E1B[15:0] bits =B, E1C[15:0] bits =C

EQ2: E2A[15:0] bits =A, E2B[15:0] bits =B, E2C[15:0] bits =C

(MSB=E1A15, E1B15, E1C15, E2A15, E2B15, E2C15 ; LSB= E1A0, E1B0, E1C0, E2A0, E2B0, E2C0)

2

tan (πfb/fs)

1 − tan (πfb/fs)

1 + tan (πfb/fs)

−

C =

A = K x

,

B = cos(2π fo/fs) x

,

1 + tan (πfb/fs)

The center frequency should be set as below.

fo/fs < 0.497

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When the gain of K is set to “-1”, these Equalizers work as notch filter. If the difference between two center frequencies

of these notch filters is small, the center frequency will differ from the frequency that is calculated by the above equation.

Then, the difference between the actual two center frequencies is smaller that the difference between the two calculated

center frequencies. It is required to adjust the center frequencies when these are calculated. The frequency response can be

confirmed by the control soft that is attached in the demo board kit. If the two center frequencies are near, the actual center

frequencies should be confirmed by this software.

e.g.) Sampling frequency = 44.1kHz, the center frequencies of 2 band notch fitters are 6000Hz and 6500Hz, and the band

width is 200Hz.

When the coefficients that are calculated by fo = 6000Hz and 6500Hz is used, the actual center frequencies are 6017Hz

and 6476Hz. When the coefficients that are calculated by fo = 5984Hz and 6522Hz is used, the actual center frequencies

are 6000Hz and 6500Hz.

Note 29. [changing real number to binary number for the filter coefficient setting upon is as below]

X=( the real filter coefficient setting upon) x 2¹³

Round off the X value to the decimal point and change it to binary number.

The MSB bit of each filter coefficient setting register is a sign bit.

Input Digital volume (Manual mode)

When ADCPF bit = “1” and ALC1 bit = “0”, ALC block becomes an input digital volume (manual mode). The digital

volume’s gain is set by IVOL7-0 bits as shown in Table 20. The IVOL7-0 bits value are reflected to this input volume at

zero cross or zero cross time out. The zero crossing timeout period is set by ZTM1-0 bits.

IVOL7-0bits

GAIN(0dB)

Step

F1H

F0H

EFH

:

92H

91H

90H

:

+36.0

+35.625

+35.25

:

+0.375

0.0

0.375dB

Default

-0.375

:

2H

1H

-53.625

-54.0

MUTE

0H

Table 20. Input Digital Volume Setting

When writing to the IVOL7-0 bits continually, the control register should be written by an interval more than zero

crossing timeout. If not, zero crossing counter could be reset at each time and volume is not be changed. However, it could

be ignored when writing a same register value as the last time. At this time, zero crossing counter has not been reset, so it

should be written by an interval less than zero crossing timeout.

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Output Digital volume (Manual mode)

When ADCPF bit = “0” and ALC2 bit = “0”, ALC block become an output digital volume (manual mode). The digital

volume’s gain is set by OVOL7-0 bits as shown in Table 21. The OVOL7-0 bits value are reflected to this output volume

at zero cross or zero cross time out. The zero crossing timeout period is set by ZTM1-0 bits.

OVOL7-0bits

GAIN(0dB)

Step

F1H

F0H

EFH

:

92H

91H

90H

:

+36.0

+35.625

+35.25

:

+0.375

0.0

0.375dB

Default

-0.375

:

2H

1H

-53.625

-54.0

MUTE

0H

Table 21. Output Digital Volume Setting

When writing to the OVOL7-0 bits continually, the control register should be written by an interval more than zero

crossing timeout. If not, zero crossing counter could be reset at each time and volume is not be changed. However, It

could be ignored when writing a same register value as the last time. At this time, zero crossing counter has not been reset,

so it should be written by an interval less than zero crossing timeout.

Output Digital Volume2

AK4633 has 4 steps output volume in addition to the volume setting by OVOL7-0 bits. This volume is set by DATT1-0

bits as shown in Table 22.

DATT1-0bits

GAIN(0dB)

Step

0H

1H

2H

3H

0.0

-6.0

-12.0

-18.1

Default

6.0dB

Table 22. Output Digital Volume2 Setting

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ALC Operation

ALC Operation works in ALC block. When ADCPF bit = “1”, ALC operation is enable for recording path. When

ADCPF bit = “0”, ALC operation is enable for playback path. The ON/OFF of ALC operation for recording is controlled

by ALC1 bit and the ON/OFF of ALC operation for playback is controlled by ALC2 bit.

1. ALC Limiter Operation

When the ALC limiter is enabled, and output exceeds the ALC limiter detection level (Table 23), the volume value is

attenuated by the amount defined in LMAT1-0 bits(Table 24) automatically.

When the ZELMN bit = “0”(zero crossing detection valid), the VOL value is changed by ALC limiter operation at the

zero crossing point or zero crossing timeout. Zero crossing timeout period is set by ZTM1-0 bit that in common with ALC

recovery zero crossing timeout period’s setting (Table 25).

When the ZELMN bit = “1” (zero crossing detection invalid), VOL value has been changed immediately (period: 1/fs) by

ALC limiter operation. The attenuation for limiter operation is fixed to 1 step and not controlled by setting LMAT1-0 bits.

After finishing the attenuation operation, if ALC bit does not change to “0”, the operation repeats when the output signal

level exceeds the ALC limiter detection level.

LMTH1 LMTH0 ALC Limiter Detection Level ALC Recovery Waiting Counter Reset Level

0

1

0

1

0

1

ALC Output ≥ −2.5dBFS

ALC Output ≥ −4.1dBFS

ALC Output ≥ −6.0dBFS

ALC Output ≥ −8.5dBFS

−2.5dBFS > ALC Output ≥ −4.1dBFS

−4.1dBFS > ALC Output ≥ −6.0dBFS

−6.0dBFS > ALC Output ≥ −8.5dBFS

−8.5dBFS > ALC Output ≥ −12dBFS

Default

Table 23. ALC Limiter Detection Level / Recovery Waiting Counter Reset Level

ALC1 Limiter ATT Step

LMAT1

LMAT0

ALC1 Output ALC1 Output ALC1 Output ALC1 Output

≥ LMTH

≥ FS

≥ FS + 6dB

≥ FS + 12dB

0

1

0

1

0

1

2

1

2

4

2

1

2

4

1

2

8

Default

Table 24. ALC Limiter ATT Step Setting

Zero Crossing Timeout Period

ZTM1

ZTM0

8kHz

16ms

32ms

64ms

128ms

16kHz

8ms

16ms

32ms

64ms

44.1kHz

2.9ms

5.8ms

11.6ms

23.2ms

0

1

0

1

0

1

128/fs

256/fs

512/fs

1024/fs

Default

Table 25. ALC Zero Crossing Timeout Period Setting

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2. ALC Recovery Operation

The ALC recovery operation waits for the WTM1-0 bits(Table 26) to be set after completing the ALC limiter operation.

If the input signal does not exceed “ALC recovery waiting counter reset level” (Table 23) during the wait time, the ALC

recovery operation is done. The VOL value is automatically incremented by RGAIN1-0 bits (Table 27) up to the set

reference level(Table 28, Table 29) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 25).

The ALC recovery operation is done at a period set by WTM1-0 bits.

For example, when the current VOL value is 30H and RGAIN1-0 bits are set to “01”(2 steps), VOL is changed to 32H by

the auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the VOL value

exceeds the reference level (IREF7-0 or OREF5-0), the VOL values are not increased.

When

“ALC recovery waiting counter reset level (LMTH1-0) ≤ Output Signal < ALC limiter detection level (LMTH1-0)”

during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When

“ALC recovery waiting counter reset level (LMTH1-0) > Output Signal”,

the waiting timer of ALC recovery operation starts.

The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation

becomes faster than a normal recovery operation. When large noise is input to microphone instantaneously, the quality of

small level in the large noise can be improved by this fast recovery operation. The speed of first recovery operation is set

by RFST1-0 bits(Table 30).

ALC Recovery Operation Waiting Period

WTM1

WTM0

8kHz

16ms

32ms

64ms

128ms

16kHz

8ms

16ms

32ms

64ms

44.1kHz

2.9ms

5.8ms

11.6ms

23.2ms

0

1

0

1

0

1

128/fs

256/fs

512/fs

1024/fs

Default

Table 26. ALC Recovery Operation Waiting Period

RGAIN1

RGAIN0

GAIN STEP

0.375dB

0

1

0

1

0

1

2

3

4

Default

0.750dB

1.125dB

1.500dB

Table 27. ALC Recovery GAIN Step

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IREF7-0bits

GAIN(0dB)

Step

F1H

F0H

EFH

:

+36.0

+35.625

+35.25

:

C5H

:

+19.5

:

Default

0.375dB

92H

91H

90H

:

+0.375

0.0

-0.375

:

2H

1H

0H

-53.625

-54.0

MUTE

Table 28. Reference Level at ALC Recovery operation for recoding

OREF5-0bits

GAIN(0dB)

Step

3CH

3BH

3AH

:

+36.0

+34.5

+33.0

:

28H

:

+6.0

:

Default

1.5dB

25H

24H

23H

:

+1.5

0.0

-1.5

:

2H

1H

0H

-51.0

-52.5

-54.0

Table 29. Reference Level at ALC Recovery operation for playback

RFST1 bit

RFST0 bit

Recovery Speed

4 times

0

1

0

1

0

1

Default

8 times

16times

N/A

Table 30. First Recovery Speed Setting

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3. The Volume at the ALC Operation

The current volume value at the ALC operation is reflected by VOL7-0 bits. It is enable to check the current volume value

with reading the register value of VOL7-0 bits.

VOL7-0bits

GAIN(0dB)

0EH

0FH

10H

:

+36.0

+35.625

+35.25

:

3AH

:

+19.5

:

6DH

6EH

6FH

:

+0.375

0.0

-0.375

:

FDH

FEH

FFH

-53.625

-54.0

MUTE

Table 31. Value of VOL7-0 bits

4. Example of the ALC Operation for Recording Operation

Table 32 shows the examples of the ALC setting for mic recording.

fs=8kHz

Operation

fs=16kHz

Operation

Register Name Comment

Data

01

0

LMTH

ZELM

Limiter detection Level

Limiter zero crossing detection

Zero crossing timeout period

Recovery waiting period

*WTM1-0 bits should be the same data

as ZTM1-0 bits

01

0

−4.1dBFS

Enable

16ms

−4.1dBFS

Enable

16ms

ZTM1-0

00

01

WTM1-0

00

16ms

01

16ms

IREF7-0

IVOL7-0

LMAT1-0

RGAIN1-0

ALC

Maximum gain at recovery operation

Gain of IVOL

Limiter ATT step

Recovery GAIN step

ALC enable

C5H

11

00

1

19.5dB

1/2/4/8 step

1 step

C5H

11

00

1

19.5dB

1/2/4/8 step

1 step

Enable

FRSL1-0

Speed of Fast Recovery

00

4 times

10

4times

Table 32. Example of the ALC Setting (Recording)

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5. Example of the ALC Operation for Playback Operation

Table 33 shows the examples of the ALC setting for playback operation.

fs=8kHz

fs=16kHz

Operation

Register Name Comment

Data

01

0

Operation

Data

01

0

LMTH

ZELM

Limiter detection Level

−4.1dBFS

Enable

16ms

−4.1dBFS

Enable

16ms

Limiter zero crossing detection

Zero crossing timeout period

Recovery waiting period

*WTM1-0 bits should be the same data

as ZTM1-0 bits

ZTM1-0

00

01

WTM1-0

00

16ms

01

16ms

OREF5-0

OVOL7-0

LMAT1-0

RGAIN1-0

ALC

Maximum gain at recovery operation

Gain of IVOL

Limiter ATT step

Recovery GAIN step

ALC enable

28

91

11

00

1

+6dB

0dB

1/2/4/8 step

1 step

Enable

4 times

28

91

11

00

1

+6dB

0dB

1/2/4/8 step

1 step

Enable

4 times

FRSL1-0

Speed of Fast Recovery

00

Table 33. Example of the ALC Setting (Playback)

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The following registers should not be changed during the ALC operation. These bits should be changed after the ALC

operation is finished by ALC1 = ALC2 bits =“0” or PMPFIL bit = “0”.

• LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, IREF7-0/OREF7-0, ZELM, RFST1-0

Example:

Limiter = Zero crossing Enable

Manual Mode

Recovery Cycle = 16ms@8kHz

Limiter and Recovery Step = 1

WR (ZTM1-0, WTM1-0)

WR (IREF7-0/OREF5-0)

WR (IVOL7-0/OVOL7-0)

Maximum Gain = +19.5dB

Limiter Detection Level = −4.1dBFS

ALC1 bit = “1”

*1

(1) Addr=06H, Data=00H

(2) Addr=08H, Data=C5H

(3) Addr=09H, Data=C5H

WR (RGAIN1, LMTH1,RFST1-0)

WR (LMAT1-0, RGAIN0, ZELMN, LMTH0)

WR (ALC1= “1”)

*2

ALC Operation

(4) Addr=0BH, Data=28H

(5) Addr=07H, Data=21H

Note : WR : Write

*1: The value of volume at starting should be the same or smaller than REF’s.

*2: When setting ALC1 bit or ALC2 bit to “0”, the operation is shifted to manual mode after passing the zero crossing

time set by ZTM1-0 bits.

Figure 36. Registers set-up sequence at ALC operation

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SOFTMUTE

Soft mute operation is performed in the digital input domain. When the SMUTE bit goes to “1”, the input signal is

attenuated by −∞ (“0”) during the cycle of 245/fs (31msec@fs=8kHz). When the SMUTE bit is returned to “0”, the mute

is cancelled and the input attenuation gradually changes to 0dB during the cycle of 245/fs (31msec@fs=8kHz). If the soft

mute is cancelled within the cycle of 245/fs (31msec@fs=8kHz), the attenuation is discontinued and returned to 0dB. The

soft mute for Playback operation is effective for changing the signal source without stopping the signal transmission.

SMUTE bit

245/fs

(1)

245/fs

0dB

(3)

Attenuation

-∞

GD

(2)

Analog Output

Figure 37. Soft Mute Function

(1) The input signal is attenuated by −∞ (“0”) during the cycle of 245/fs (31msec@fs=8kHz).

(2) Analog output corresponding to digital input has the group delay (GD).

(3) If the soft mute is cancelled within the cycle of 245/fs (31msec@fs=8kHz), the attenuation is discounted and returned

to 0dB within the same cycle.

BEEP Input

When the PMBP bit is set to “1”, the beep input is powered-up. When the BEEPS bit is set to “1”, the input signal from the

BEEP pin is output to Speaker-Amp. When the BEEPA bit is set to “1”, the input signal from the BEEP pin is output to the

mono line output amplifier. The external resister Ri adjusts the signal level of BEEP input. Table 34 shows the typical

gain example at R_i= 20kΩ. This gain is in inverse proportion to R_iIt should be set MDIF bit to “1” expect PMBP bit =

BEEPA bit = BEEPS bit = “0”.

Rf

Ri

-

+

BEEP

Figure 38. Block Diagram of BEEP pin

SPKG1-0 bits

BEEP Æ SPP/SPN Gain

BEEP Æ AOUT Gain

00

01

10

11

+8dB

+10dB

+12dB

+14dB

0dB

Table 34. BEEP Input Gain at R_i= 20kΩ

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Mono Line Output (AOUT pin)

A signal of DAC is output from AOUT pin. When the DACA bit is “0”, this output is OFF. The load resistance is

10kΩ(min). When PMAO bit is “0” and AOPS bit is “0”, the mono line output enters power-down and is pulled down by

100Ω(typ). When ADPS bit is “1”, the mono line output enters power-save mode. If PMAO bit is controlled at AOPS bit

= “1”, POP noise will be reduced at power-up and down. Then, this line should be pulled down by 20kΩ of resister after

C-coupling shown in Figure 39. This rising and falling time is max 300 ms at C=1.0µF . When PMAO bit is “1” and

AOPS bit is “0”, the mono line output enters power-up state.

1µF

220Ω

AOUT

20kΩ

Figure 39. AOUT external circuit in case of using POP Reduction function

AOUT Control Sequence in case of using POP Reduction Circuit

(2 )

(5 )

P M A O b it

A O P S b it

(1 )

(3 )

(4 )

(6 )

A O U T p in

N o rm a l O u tp u t

≥ 3 0 0 m s

≥

3 0 0 m s

(1) Set AOPS bit = “1”. Mono line output enters the power-save mode.

(2) Set PMAO bit = “1”. Mono line output exits the power-down mode.

AOUT pin rises up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1µF.

(3) Set AOPS bit = “0” after AOUT pin rises up. Mono line output exits the power-save mode.

Mono line output is enabled.

(4) Set AOPS bit = “1”. Mono line output enters power-save mode.

(5) Set PMAO bit = “1”. Mono line output enters power-down mode.

AOUT pin falls down to AVSS. Fall time is 200ms (max 300ms) at C=1µF.

(6) Set AOPS bit = “0” after AOUT pin falls down. Mono line output exits the power-save mode.

Figure 40. Mono Line Output Control Sequence in case of using POP Reduction function

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Speaker Output

The power supply voltage for Speaker-Amp SVDD can be set to from 2.2V to 4.0V. However, SVDD should be set to

from 2.6V to 3.6V, when 8Ω dynamic speaker is connected. If SVDD is more than 3.6V when 8Ω dynamic speaker is

connected to the AK4633, the output of Speaker-Amp should be restricted in consideration of maximum power

dissipation.

The output signal from DAC is input to the Speaker-amp. This Speaker-amp is a mono output controlled by BTL and the

gain of Speaker-Amp is set by SPKG1-0 bits. The output voltage depends on AVDD and SPKG1-0 bits.

SPK-AMP Output Level[Vpp]

DAC =-4.1dBFS (Note 30)

Gain

(Note 31)

SPKG1-0 bits

00

01

10

11

3.17

4.00

5.03

6.33

0dB

+2dB

+4dB

+6dB

Note 30. AVDD=3.3V. The output level is proportional to AVDD.

Note 31. The Gain with a reference of SPKG1-0 bits = “00”.

Note 32. The setting of SPKG1-0 bits = “01” is recommend when 8Ω dynamic speaker is connected.

The SPK-Amp Power is 250mW at 8Ω Load Resistance and 4.0Vpp output level.

Table 35. SPK-Amp Output Voltage and Gain

When a piezo speaker is used, resistances more than 10Ω should be inserted between SPP/SPN pins and speaker in series,

respectively, as shown in Figure 41. Zener diodes should be inserted between speaker and GND as shown in Figure 41, in

order to protect SPK-Amp of AK4633 from the power that the piezo speaker outputs when the speaker is pressured. Zener

diodes of the following Zener voltage should be used.

92% of SVDD ≤ Zener voltage of Zener diodo(ZD of Figure 41) ≤ SVDD+0.3V

Ex) In case of SVDD = 3.8V : 3.5V ≤ ZD ≤ 4.1V

For example, Zener diode which Zener voltage is 3.9V(Min 3.7V, Max 4.1V) can be used.

ZD

SPK-Amp

≥10Ω

SPP

SPN

≥10Ω

ZD

Figure 41. Circuit of Speaker Output (using a piezo speaker)

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Speaker-Amp can be powered-up/down by controlling the PMSPK bit. When the PMSPK bit is “0”, the SPP and SPN

pins are placed in a Hi-Z state.

When the PMSPK bit is “1” and SPPSN bit is “0”, the Speaker-amp enters power-save-mode. In this mode, the SPP pin is

placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage.

When the PMSPK bit is “1” and PDN pin is controlled from “L” to “H”, the SPP and SPN pins rise up from

power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage. Because

the SPP and SPN pins rise up at power-save-mode, this mode can reduce pop noise. When the AK4633 is powered-down,

pop noise can be also reduced by first entering power-save-mode.

PMSPKbit

SPPSNbit

SPPpin

SPNpin

Hi-Z

SVDD/2

>0

SVDD/2

>t1(Note)

Hi-Z

(Note)

SPPSN bit should be set to “1” at more than 1ms after PMSPK bit is set to “1”. But, when BEEP Input Amp and Speaker

Amp are powered-up at the same time, SPPSN bit should be set to “1” after BEEP Input become stable. When the

resistance and capacitance of BEEP pin are R=20kΩ, C=0.1µF, 10ms(=5τ) is required for BEEP Input to become stable.

Figure 42. Power-up/Power-down Timing for Speaker-Amp

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Serial Control Interface

Internal registers may be written and read by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this

interface consists of a 2-bit Chip address (2bits, fixed to “10”), Read/Write, Register address (MSB first, 5bits) and

Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the

falling edge. It is available for writing the data on the rising edge of CSN. When reading operation, CDTI pin has become

an output mode at the falling edge of 8th CCLK and outputs D7-D0. The output finishes on the rising edge of CSN. The

CDTI pin is placed in a Hi-Z state except outputting data at read operation mode. The clock speed of CCLK is 5MHz

(max). The value of internal registers is initialized at PDN pin = “L”.

Note 33. It is available for reading the address 00H~0BH and 0DH~0FH. When reading the address 0CH and 10H ∼ 1FH,

the register values are invalid.

CSN

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

CCLK

CDTI

R/W

C1 C0

“1” “0”

A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

C1-C0: Chip Address (C1 = “1”, C0 = “0”); Fixed to “10”

R/W: READ/WRITE (“1”: WRITE, “0”: READ)

A4-A0: Register Address

D7-D0: Control data

Figure 43. Serial Control I/F Timing

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Register Map

Addr

Register Name

D7

PMPFIL

0

SPPSN

PFSDO

PLL3

ADRST

0

D6

PMVCM

0

BEEPS

AOPS

PLL2

FCKO

0

ALC2

IREF6

IVOL6

OVOL6

LMTH1

0

D5

PMBP

0

DACS

MGAIN1

PLL1

FS3

ZTM1

ALC1

IREF5

IVOL5

OVOL5

OREF5

0

D4

PMSPK

0

D3

PMAO

M/S

D2

PMDAC

0

PMMP

BEEPA

BCKO0

FS2

WTM0

LMAT0

IREF2

IVOL2

OVOL2

OREF2

0

D1

0

MCKO

MGAIN2 MGAIN0

PFDAC

DIF1

D0

PMADC

PMPLL

00H Power Management 1

01H Power Management 2

02H Signal Select 1

03H Signal Select 2

04H Mode Control 1

05H Mode Control 2

06H Timer Select

07H ALC Mode Control 1

08H ALC Mode Control 2

09H Digital Volume Control

0AH Digital Volume Control

0BH ALC Mode Control 3

0CH Reserved

DACA

SPKG1

PLL0

MSBS

ZTM0

ZELMN

IREF4

IVOL4

OVOL4

OREF4

0

SPKG0

BCKO1

BCKP

WTM1

LMAT1

IREF3

IVOL3

OVOL3

OREF3

0

ADCPF

DIF0

FS0

RFST0

LMTH0

IREF0

IVOL0

OVOL0

OREF0

0

FS1

RFST1

RGAIN0

IREF1

IVOL1

OVOL1

OREF1

0

IREF7

IVOL7

OVOL7

RGAIN1

0

0DH ALC LEVEL

0EH Signal Select 3

0FH Reserved

VOL7

DATT1

0

VOL6

DATT0

0

VOL5

SMUTE

0

VOL4

MDIF

0

VOL3

EQ2

0

VOL2

EQ1

0

VOL1

HPF

0

VOL0

HPFAD

0

10H E1 Co-efficient 0

11H E1 Co-efficient 1

12H E1 Co-efficient 2

13H E1 Co-efficient 3

14H E1 Co-efficient 4

15H E1 Co-efficient 5

16H E2 Co-efficient 0

17H E2 Co-efficient 1

18H E2 Co-efficient 2

19H E2 Co-efficient 3

1AH E2 Co-efficient 4

1BH E2 Co-efficient 5

1CH HPF Co-efficient 0

1DH HPF Co-efficient 1

1EH HPF Co-efficient 2

1FH HPF Co-efficient 3

E1A7

E1A15

E1B7

E1B15

E1C7

E1C15

E2A7

E2A15

E2B7

E2B15

E2C7

E2C15

F1A7

0

E1A6

E1A14

E1B6

E1B14

E1C6

E1C14

E2A6

E2A14

E2B6

E2B14

E2C6

E2C14

F1A6

0

E1A5

E1A13

E1B5

E1B13

E1C5

E1C13

E2A5

E2A13

E2B5

E2B13

E2C5

E2C13

F1A5

F1A13

F1B5

F1B13

E1A4

E1A12

E1B4

E1B12

E1C4

E1C12

E2A4

E2A12

E2B4

E2B12

E2C4

E2C12

F1A4

F1A12

F1B4

E1A3

E1A11

E1B3

E1B11

E1C3

E1C11

E2A3

E2A11

E2B3

E2B11

E2C3

E2C11

F1A3

F1A11

F1B3

E1A2

E1A10

E1B2

E1B10

E1C2

E1C10

E2A2

E2A10

E2B2

E2B10

E2C2

E2C10

F1A2

F1A10

F1B2

E1A1

E1A9

E1B1

E1B9

E1C1

E1C9

E2A1

E2A9

E2B1

E2B9

E2C1

E2C9

F1A1

F1A9

F1B1

F1B9

E1A0

E1A8

E1B0

E1B8

E1C0

E1C8

E2A0

E2A8

E2B0

E2B8

E2C0

E2C8

F1A0

F1A8

F1B0

F1B8

F1B7

0

F1B6

0

F1B12

F1B11

F1B10

PDN pin = “L” resets the registers to their default values.

Note 34. Unused bits must contain a “0” value.

Note 35. When reading address 0CH and 10H to 1FH, the values are invalid.

Note 36. Address 0DH is a read only register. Writing access to 0DH does not effect the operation.

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ASAHI KASEI

[AK4633]

Register Definitions

Addr Register Name

D7

PMPFIL

0

D6

PMVCM

0

D5

PMBP

0

D4

PMSPK

0

D3

PMAO

0

D2

PMDAC

0

D1

0

D0

PMADC

0

00H

Power Management 1

Default

PMADC: ADC Block Power Control

0: Power down (Default)

1: Power up

When the PMADC bit changes from “0” to “1”, the initialization cycle (1059/fs=133ms@8kHz when ADRST

bit = “0”) starts. After initializing, digital data of the ADC is output.

PMDAC: DAC Block Power Control

0: Power down (Default)

1: Power up

PMAO: Mono Line Out Power Control

0: Power down (Default)

1: Power up

PMSPK: Speaker Block Power Control

0: Power down (Default)

1: Power up

PMBP: BEEP In Power Control

0: Power down (Default)

1: Power up

Even if PMBP bit is “0”, the path is still connected between BEEP and AOUT/SPK-Amp. BEEPS and BEEPA

bits should be set to “0” to disconnect these paths.

PMVCM: VCOM Block Power Control

0: Power down (Default)

1: Power up

PMPFIL: Programmable Filter Block(HPF/2 Band EQ/ALC) Control

0: Power down (Default)

1: Power up

Each block can be powered-down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are

powered-down.

When PMPLL and MCKO bits and all bits in 00H address are “0”, all blocks are powered-down. The registers remain

unchanged.

When any of the blocks are powered-up, the PMVCM bit must be set to “1”. When PMPLL and MCKO bits and all

bits in 00H address are “0”, PMVCM bit can write to “0”.

When BEEP signal is output from Speaker-Amp (Signal path: BEEP pin Æ SPP/SPN pins) or Mono Lineout-Amp

(Signal path: BEEP pin Æ AOUT pin) only, the clocks may not be present. When ADC, DAC, ALC1 or ALC2 is in

operation, the clocks must always be present.

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[AK4633]

Addr

01H

Register Name

Power Management 2

Default

D7

0

D6

0

D5

0

D4

0

D3

M/S

0

D2

0

D1

MCKO

0

D0

PMPLL

0

PMPLL: PLL Block Power Control Select

0: PLL is Power down and External is selected. (Default)

1: PLL is Power up and PLL Mode is selected.

MCKO: Master Clock Output Enable

0: “L” Output (Default)

1: 256fs Output

M/S: Master/Slave Mode Select

0: Slave Mode(Default)

1: Master Mode

Addr Register Name

D7

SPPSN

0

D6

BEEPS

0

D5

DACS

0

D4

DACA

0

D3

0

D2

PMMP

0

D1

D0

MGAIN2 MGAIN0

02H

Signal Select 1

Default

0

1

MGAIN2, MGAIN0: MIC-Amp Gain Control (Table 18)

MGAIN1 bit is D5 bit of 03H. Default: “001H” (+20.0dB)

PMMP: Power Supply Control for Microphone

0: OFF (Default)

1: ON

When PMADC bit is “1”, PMMP bit is enabled.

DACA: Switch Control from DAC to Mono Line Output

0: OFF (Default)

1: ON

When PMAO bit is “1”, DACA bit is enabled. When PMAO bit is “0”, the AOUT pin go to AVSS.

DACS: Switch Control from DAC to Speaker-Amp

0: OFF (Default)

1: ON

When DACS bit is “1”, DAC output signal is input to Speaker-Amp.

BEEPS: Switch Control from BEEP pin to Speaker-Amp

0: OFF (Default)

1: ON

When BEEPS bit is “1”, BEEP signal is input to Speaker-Amp.

SPPSN: Speaker-Amp Power-Save Mode

0: Power-Save Mode (Default)

1: Normal Operation

When SPPSN bit is “0”, Speaker-Amp is in power-save mode. In this mode, SPP pin goes to Hi-Z and SPN pin

is outputs SVDD/2 voltage. When PMSPK bit = “1”, SPPSN bit is enabled. After the PDN pin is set to “H”,

Speaker-Amp is in power-down mode since PMSPK bit is “0”.

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[AK4633]

Addr Register Name

D7

PFSDO

1

D6

AOPS

0

D5

MGAIN1

0

D4

D3

D2

BEEPA

0

D1

PFDAC

0

D0

ADCPF

1

03H

Signal Select 2

Default

SPKG1 SPKG0

0

ADCPF : Select the input signal to Programmable Filter/ALC

0: SDTI

1: Output from ADC (Default)

PFDAC : Select the input signal to DAC

0: SDTI (Default)

1: Output from programmable Filter/ALC

BEEPA: Switch Control from beep signal to mono line output amp

0: OFF (Default)

1: ON

When PMAO bit is “1”, BEEPA bit is enabled. When PMAO bit is “0”, the AOUT pin go to AVSS.

SPKG1-0: Select Speaker-Amp Output Gain ( Table 35)

Default: “00”

DACS

DAC

SPK

BEEPS

BEEP

DACA

BEEPA

AOUT

Figure 44. Speaker and Mono Lineout-Amps switch control

MGAIN1: MIC-Amp Gain Control (Table 18)

MGAIN2, MGAIN0 bit is D1,D2 bit of 02H. Default: “001H” (+20.0dB)

AOPS: Mono Line Output Power-Save Mode

0: Normal Operation (Default)

1: Power Save Mode

Power-save mode is enable at AOPS bit = “1”. POP noise at power-up/down can be reduced by changing at

AOPS bit = “1” (Figure 40).

PFSDO : Select the output signal from SDTO

0: Output from ADC (+ 1^stHPF)

1: Output from Programmable Filter/ALC(Default)

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[AK4633]

Addr Register Name

D7

PLL3

0

D6

PLL2

0

D5

PLL1

0

D4

PLL0

0

D3

D2

D1

DIF1

1

D0

DIF0

0

04H

Mode Control 1

Default

BCKO1 BCKO0

0

DIF1-0: Audio Interface Format (Table 15)

Default: “10” (MSB justified)

BCKO1-0: Select BICK output frequency at Master Mode (Table 9)

Default: “00” (16fs)

PLL3-0: Select input frequency at PLL mode (See Table 4)

Default: “0000” (FCK pin)

Addr Register Name

D7

ADRST

0

D6

FCKO

0

D5

FS3

0

D4

MSBS

0

D3

BCKP

0

D2

FS2

0

D1

FS1

0

D0

FS0

0

05H

Mode Control 2

Default

FS3-0: Setting of Sampling Frequency (Table 5 and Table 6) and MCKI Frequency (See Table 11)

These bits are selected to sampling frequency at PLL mode and MCKI frequency at EXT mode.

Default: “0000”

BCKP, MSBS: “00” (Default) (Table 16)

FCKO: Select FCK output frequency at Master Mode (Table 10)

“0” (Default)

ADRST: Select ADC initialization cycle

0: 1059/fs (Default)

1: 291/fs

Addr Register Name

D7

0

D6

0

D5

ZTM1

0

D4

ZTM0

0

D3

WTM1

0

D2

WTM0

0

D1

RFST1

0

D0

RFST0

0

06H

Timer Select

Default

WTM1-0: ALC1 Recovery Waiting Period (Table 26)

A period of recovery operation when any limiter operation does not occur during the ALC1 operation.

Default is “00”.

ZTM1-0: ALC1 Zero crossing timeout Period (Table 25)

When the IPGA perform zero crossing or timeout, the IPGA value is changed by the µP WRITE operation,

ALC1 recovery operation. Default is “00”.

FRSL1-0: ALC First recovery Speed(Table 30)

Default: “00”(4times)

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[AK4633]

Addr Register Name

D7

0

D6

ALC2

0

D5

ALC1

0

D4

D3

D2

D1

RGAIN0

0

D0

LMTH0

1

07H

ALC Mode Control 1

Default

ZELMN LMAT1 LMAT0

0

LMTH1-0: ALC Limiter Detection Level / Recovery Waiting Counter Reset Level (Table 23)

LMTH1 bit is D6 bit of 0BH. Default: “01”.

RGAIN1-0: ALC Recovery Gain Step(Table 27)

RGAIN1 bit is D7 bit of 0BH. Default: “00”

LMAT1-0: ALC Limiter ATT Step(Table 24)

Default: “00”

ZELMN: Enable zero crossing detection at ALC Limiter operation

0: Enable (Default)

1: Disable

ALC1: ALC Enable for Recording

0: Recording ALC Disable (Default)

1: Recording ALC Enable

ALC2: ALC Enable for Playback

0: Playback ALC Disable (Default)

1: Playback ALC Enable

Addr Register Name

08H ALC Mode Control 2

Default

D7

IREF7

1

D6

IREF6

1

D5

IREF5

0

D4

IREF4

0

D3

IREF3

0

D2

IREF2

1

D1

IREF1

0

D0

IREF0

1

IREF7-0: Reference value at Recording ALC Recovery Operation. 0.375dB step, 242 Level (Table 28)

Default: “C5H” (+19.5dB)

Addr Register Name

Input Digital Volume Control

Default

D7

IVOL7

1

D6

IVOL6

0

D5

IVOL5

0

D4

IVOL4

1

D3

IVOL3

0

D2

IVOL2

0

D1

IVOL1

0

D0

IVOL0

1

09H

IVOL7-0: Input Digital Volume; 0.375dB step, 242 Level (Table 20)

Default: “91H” (0.0dB)

Addr Register Name

0AH Digital Volume Control

Default

D7

D6

D5

D4

OVOL4

1

D3

D2

D1

D0

OVOL0

1

OVOL7 OVOL6 OVOL5

OVOL3 OVOL2 OVOL1

1

0

OVOL7-0: Output Digital Volume; 0.375dB step, 242 Level (Table 21)

Default: “91H” (0.0dB)

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[AK4633]

Addr Register Name

0BH ALC Mode Control 3

Default

D7

RGAIN1

0

D6

LMTH1

0

D5

OREF5

1

D4

OREF4

0

D3

OREF3

1

D2

OREF2

0

D1

OREF1

0

D0

OREF0

0

OREF5-0: Reference value at Playback ALC Recovery Operation. 0.375dB step, 50 Level (Table 29)

Default: “28H” (+6.0dB)

RGAIN1-0: ALC Recovery Gain Step(Table 27)

RGAIN1 bit is D1 bit of 07H. Default: “00”

Addr Register Name

Input Digital Volume Control

Default

D7

VOL7

-

D6

VOL6

-

D5

VOL5

-

D4

VOL4

-

D3

VOL3

-

D2

VOL2

-

D1

VOL1

-

D0

VOL0

-

0DH

VOL7-0: Current ALC volume value; 0.375dB step, 242 Level. Read operation only(Table31)

Addr Register Name

0EH Mode Control 3

Default

D7

DATT1

0

D6

DATT0

0

D5

SMUTE

0

D4

MDIF

0

D3

EQ2

0

D2

EQ1

0

D1

HPF

1

D0

HPFAD

1

HPFAD: HPF after ADC Enable

0: Disable

1: Enable(Default)

When HPFAD bit = “0”, HPFAD block is through (0dB).

HPF: HPF Enable in Filter block that PMPFIL bit is controlled.

0: Disable

1: Enable(Default)

When HPF bit = “0”, HPF block is through (0dB).

EQ1: Equalizer1(EQ1) Enable

0: Disable (Default)

1: Enable

When EQ1 bit is “1”, the settings of EQA15-0, EQB15-0 and EQC15-0 bits are enabled. When EQ1 bit is “0”,

EQ1 block is through (0dB).

EQ2: Equalizer2(EQ2) Enable

0: Disable (Default)

1: Enable

When EQ2 bit is “1”, the settings of EQA15-0, EQB15-0 and EQC15-0 bits are enabled. When EQ2 bit is “0”,

EQ2 block is through (0dB).

SMUTE: soft mute control

0: Normal Operation (Default)

1: DAC outputs soft-muted

MDIF: MIC Input Type Select

0: Single-ended input (MIC pin Input: Default)

1: Full-differential input (MIC pin and BEEP/MICP pin Input)

When MDIF bit = “1”, it must be set PMBP bit = BEEPA bit = BEEPS bit = “0”.

DATT1-0: Output Digital Volume2; 6dB step, 4 Level (Table 22)

Default: “00H” (0.0dB)

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[AK4633]

Addr Register Name

10H E1 Co-efficient 0

11H E1 Co-efficient 1

12H E1 Co-efficient 2

13H E1 Co-efficient 3

14H E1 Co-efficient 4

15H E1 Co-efficient 5

16H E2 Co-efficient 0

17H E2 Co-efficient 1

18H E2 Co-efficient 2

19H E2 Co-efficient 3

1AH E2 Co-efficient 4

1BH E2 Co-efficient 5

Default

D7

D6

D5

D4

D3

D2

D1

D0

E1A7

E1A15

E1B7

E1B15

E1C7

E1C15

E2A7

E2A15

E2B7

E2B15

E2C7

E2C15

0

E1A6

E1A14

E1B6

E1B14

E1C6

E1C14

E2A6

E2A14

E2B6

E2B14

E2C6

E2C14

0

E1A5

E1A13

E1B5

E1B13

E1C5

E1C13

E2A5

E2A13

E2B5

E2B13

E2C5

E2C13

0

E1A4

E1A12

E1B4

E1B12

E1C4

E1C12

E2A4

E2A12

E2B4

E2B12

E2C4

E2C12

0

E1A3

E1A11

E1B3

E1B11

E1C3

E1C11

E2A3

E2A11

E2B3

E2B11

E2C3

E2C11

0

E1A2

E1A10

E1B2

E1B10

E1C2

E1C10

E2A2

E2A10

E2B2

E2B10

E2C2

E2C10

0

E1A1

E1A9

E1B1

E1B9

E1C1

E1C9

E2A1

E2A9

E2B1

E2B9

E2C1

E2C9

0

E1A0

E1A8

E1B0

E1B8

E1C0

E1C8

E2A0

E2A8

E2B0

E2B8

E2C0

E2C8

0

E1A15-0, E1B15-0, E1C15-0: Coefficient for Equalizer 1(16bit x3)

Default: “0000H”

E2A15-0, E2B15-0, E2C15-0: Coefficient for Equalizer 2 (16bit x3)

Default: “0000H”

Addr Register Name

1CH HPF Co-efficient 0

Default

D7

F1A7

0

D6

F1A6

0

D5

F1A5

0

D4

F1A4

1

D3

F1A3

0

D2

F1A2

1

D1

F1A1

1

D0

F1A0

0

Addr Register Name

1DH HPF Co-efficient 1

Default

D7

0

D6

0

D5

F1A13

0

D4

F1A12

1

D3

F1A11

1

D2

F1A10

1

D1

F1A9

1

D0

F1A8

1

Addr Register Name

1EH HPF Co-efficient 2

Default

D7

F1B7

0

D6

F1B6

0

D5

F1B5

1

D4

F1B4

0

D3

F1B3

1

D2

F1B2

0

D1

F1B1

1

D0

F1B0

1

Addr Register Name

1FH HPF Co-efficient 3

Default

D7

0

D6

0

D5

F1B13

0

D4

F1B12

1

D3

F1B11

1

D2

F1B10

1

D1

F1B9

1

D0

F1B8

0

F1A13-0, F1B13-0: FIL1 (Wind-noise Reduction Filter) Coefficient Setting Enable (14bit x 2)

Default: F1A13-0 bits = 0x1F16, F1B13-0 bits = 0x1E2B

fc = 75Hz@fs=8kHz, 150Hz@fs=16kHz

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[AK4633]

SYSTEM DESIGN

Figure 45 shows the system connection diagram for the AK4633. An evaluation board [AKD4633] is available which

demonstrates the optimum layout, power supply arrangements and measurement results.

Single Ended input

20k

Analog Supply

2.2∼4.0V

10µ

C

R

220

1µ

2.2k

+

0.1µ

1µ

R2

R1

1

18

VCOM

SPN

SPP

+

2.2µ

Speaker

0.1µ

2 AVSS

17

0.1µ

ZD2

ZD1

Analog Supply

3

MCKO 16

15

AVDD

Dynamic SPK :

R1,R2 : Short

ZD1,ZD2 : Open

Peizo SPK :

Cp Rp

Top View

+

2.2∼3.6V

10µ

4

5

VCOC

PDN

MCKI

R1,R2 : 10

ZD1,ZD2 : Required

Ω

DVSS 14

DVDD 13

6 CSN

0.1µ

10

DSP or µP

Figure 45. Typical Connection Diagram

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[AK4633]

Differential Input

20k

1k

Analog Supply

2.2∼4.0V

10µ

220

1µ

1k

+

0.1µ

1µ

R2

1

18

17

VCOM

SPN

SPP

+

2.2µ

Speaker

0.1µ

R1

2 AVSS

0.1µ

ZD2

ZD1

Analog Supply

3

MCKO 16

15

AVDD

Dynamic SPK :

R1,R2 : Short

ZD1,ZD2 : Open

Peizo SPK :

Cp Rp

Top View

+

2.2∼3.6V

10µ

4

5

VCOC

PDN

MCKI

R1,R2 : 10Ω

ZD1,ZD2 : Required

DVSS 14

DVDD 13

6 CSN

0.1µ

10

DSP or µP

Figure 46. Typical Connection Diagram

Note:

- AVSS, DVSS and SVSS of the AK4633 should be distributed separately from the ground of external

controllers.

- If AVDD and DVDD are separated, DVDD should be set from 1.6V to 3.6V.

- All digital input pins should not be left floating.

- When the AK4633 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.

- When the AK4633 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in

Table 36.

PLL

Reference

Clock Input

Rp and Cp of

VCOC pin

PLL3 PLL2 PLL1 PLL0

Input

Frequency

PLL Lock

Time (max)

Mode

bit

Cp[F]

Rp[Ω]

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

FCK pin

BICK pin

MCKI pin

N/A

1fs

16fs

32fs

6.8k

10k

220n

4.7n

10n

160ms

2ms

Default

64fs

2ms

11.2896MHz

12.288MHz

12MHz

24MHz

13.5MHz

27MHz

40ms

12

13

Others

1

10n

Others

Table 36. Setting of PLL Mode (*fs: Sampling Frequency)

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[AK4633]

1. Grounding and Power Supply Decoupling

The AK4633 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and SVDD are

usually supplied from the system’s analog supply. If AVDD, DVDD and SVDD are supplied separately, the correct

power up sequence should be observed. AVSS, DVSS and SVSS of the AK4633 should be connected to the analog

ground plane. System analog ground and digital ground should be connected together near to where the supplies are

brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4633 as possible, with the small

value ceramic capacitor being the nearest.

2. Voltage Reference

VCOM is a signal ground of this chip. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor attached

to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All

signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the

AK4633.

3. Analog Inputs

The Mic and Beep inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp for the Mic

input and 0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage (approx. 0.45 x AVDD).

Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2πRC). The AK4633 can accept

input voltages from AVSS to AVDD.

4. Analog Outputs

The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and

a negative full scale for 8000H(@16bit). Mono output from the MOUT pin and Mono Line Output from the AOUT pin

are centered at 0.45 x AVDD (typ). The Speaker-Amp output is centered at SVDD/2.

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ASAHI KASEI

[AK4633]

CONTROL SEQUENCE

Clock Set up

When ADC, DAC and Programmable Filter are used, the clocks must be supplied.

1. In case of PLL Master Mode

Example:

Audio I/F Format: DSP Mode, BCKP = MSBS = “0”

BICK frequency at Master Mode: 64fs

Input Master Clock Select at PLL Mode: 13.5MHz

MCKO : Enable

Power Supply

PDN pin

(1)

Sampling Frequency:16kHz

(2)

(3)

PMVCM bit

(Addr:00H, D6)

(1) Power Supply & PDN pin = “L” Æ “H”

(4)

MCKO bit

(Addr:01H, D1)

(2)Addr:01H, Data:08H

Addr:04H, Data:C8H

Addr:05H, Data:02H

PMPLL bit

(Addr:01H, D0)

(5)

MCKI pin

Input

(3)Addr:00H, Data:40H

(4)Addr:01H, Data:0BH

M/S bit

(Addr:01H, D3)

40msec(max)

(6)

(9)

BICK pin

FCK pin

Output

(7)

1msec (max)

MCKO, BICK and FCK output

40msec(max)

(8)

MCKO pin

Figure 47. Clock Set Up Sequence (1)

(1) After Power Up, PDN pin = “L” → “H”

“L” time (1) of 150ns or more is needed to reset the AK4633.

(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period.

(3) Power Up VCOM: PMVCM bit = “0” → “1”

VCOM should first be powered-up before the other block operates.

(4) In case of using MCKO output: MCKO bit = “1”

In case of not using MCKO output: MCKO bit = “0”

(5) PLL lock time is 40ms(max) after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external

source.

(6) The AK4633 starts to output the FCK and BICK clocks after the PLL becomes stable. The normal operation of

the block which a clock is necessary for becomes possible.

(7) The invalid frequencies are output from FCK and BICK pins during this period.

(8) The invalid frequency is output from MCKO pin during this period.

(9) The normal clock is output from MCKO pin after the PLL is locked.

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[AK4633]

2. When the external clock (FCK or BICK pin) is used in PLL Slave mode.

Example:

Audio I/F Format : DSP Mode, BCKP = MSBS = “0”

PLL Reference clock: BICK

BICK frequency: 64fs

Sampling Frequency: 16kHz

Power Supply

(1)

4fs of

(1) Power Supply & PDN pin = “L” Æ “H”

PDN pin

(3)

(2)

PMVCM bit

(2) Addr:04H, Data:30H

Addr:05H, Data:01H

(Addr:00H, D6)

PMPLL bit

(Addr:01H, D0)

(3) Addr:00H, Data:40H

(4) Addr:01H, Data:01H

BICK and FCK input

FCK pin

BICK pin

Input

(4)

Internal Clock

(5)

Figure 48. Clock Set Up Sequence (2)

(1)After Power Up: PDN pin “L” → “H”

“L” time (1) of 150ns or more is needed to reset the AK4633.

(2) DIF1-0, FS3-0, PLL3-0, MSBS and BCKP bits should be set during this period.

(3)Power Up VCOM: PMVCM bit = “0” → “1”

VCOM should first be powered up before the other block operates.

(4)PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clocks (FCK or BICK pin) are

supplied. PLL lock time is 160ms(max) when PLL reference clock is FCK, and PLL lock time is 2ms(max) when

PLL reference clock is BICK.

(5)Normal operation starts after the PLL is locked.

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[AK4633]

3. When the external clock (MCKI pin) is used in PLL Slave mode.

Example:

Audio I/F Format: DSP Mode, BCKP = MSBS = “0”

BICK frequency at Master Mode: 64fs

Input Master Clock Select at PLL Mode: 13.5MHz

MCKO : Enable

Sampling Frequency:16kHz

Power Supply

(1) Power Supply & PDN pin = “L” Æ “H”

(1)

PDN pin

(2)

(3)

(2)Addr:04H, Data:C8H

Addr:05H, Data:02H

PMVCM bit

(Addr:00H, D6)

(4)

PMPLL bit

(Addr:01H, D0)

(5)

(3)Addr:00H, Data:40H

(4)Addr:01H, Data:03H

MCKO output start

MCKI pin

Input

40msec(max)

(6)

MCKO pin

(7)

Output

Input

(8)

BICK pin

FCK pin

BICK and FCK input start

Figure 49. Clock Set Up Sequence (3)

(1) After Power Up: PDN pin “L” → “H”

“L” time (1) of 150ns or more is needed to reset the AK4633.

(2) DIF1-0, PLL3-0, FS3-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period.

(3) Power Up VCOM: PMVCM bit = “0” → “1”

VCOM should first be powered up before the other block operates.

(4) PLL Power Up: PMVCM bit “0” → “1”

(5) PLL lock time is 40ms(max) after the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin)

is supplied..

(6) The normal clock is output from MCKO after PLL is locked.

(7) The invalid frequency is output from MCKO during this period.

(8) BICK and FCK clocks should be synchronized with MCKO clock.

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ASAHI KASEI

[AK4633]

4. EXT Slave Mode

Example

Audio I/F Format:MSB justified (ADC and DAC)

Input MCKI frequency: 1024fs

Sampling Frequency:16kHz

MCKO: Disable

Power Supply

(1)

PDN pin

(1) Power Supply & PDN pin = “L” Æ “H”

(2)

(3)

PMVCM bit

(Addr:00H, D6)

(2) Addr:04H, Data:02H

Addr:05H, Data:02H

(4)

"L"

PMPLL bit

(Addr:01H, D0)

(5)

MCKI pin

Input

(3) Addr:00H, Data:40H

FCK pin

BICK pin

MCKI, BICK and FCK input

Figure 50. Clock Set Up Sequence (4)

(1)After Power Up: PDN pin “L” → “H”

“L” time (1) of 150ns or more is needed to reset the AK4633.

(2)DIF1-0 and FS1-0 bits should be set during this period.

(3)Power Up VCOM: PMVCM bit = “0” → “1”

VCOM should first be powered up before the other block operates.

(4)Power down PLL: PMPLL bit = “0”

(5)Normal operation starts after the MCKI, FCK and BICK are supplied.

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ASAHI KASEI

[AK4633]

MIC Input Recording

FS3-0 bits

(Addr:05H,

D5,D2-0)

XXXX

(1)

ADRST bit

(Addr:05H, D7)

X

MIC Control

001

1XX

XXH

2XH

(Addr:02H, D2-0)

(2)

ALC1 Control 1

XXH

(Addr:06H)

(3)

ALC1 Control 2

(Addr:08H)

(4)

IVOL7-0 bits

(Addr:09H)

XXH

(5)

ALC1 Control 3

XXH

(Addr:07H)

(6)

Signal Select

(Addr:03H)

XXH

81H

(7)

Filter Co-ef

(Addr:10H-1F)

XX....X

(8)

Filter Select

(Addr:0EH D3-0)

XXX1

(9)

ALC1 State

ALC1 Disable

ALC1 Enable

PMADC bit

(Addr:00H, D0)

(10)

(11)

PMPFIL bit

(Addr:00H, D7)

291/fs or 1059/fs

ADC Internal

State

Power Down

Normal State Power Down

Initialize

Figure 51. MIC Input Recording Sequence

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ASAHI KASEI

[AK4633]

Example:

PLL Master Mode

Audio I/F Format:DSP Mode, BCKP=MSBS=“0”

Sampling Frequency: 16kHz

Pre MIC AMP:+20dB

MIC Power On

ADC Initialize time : 291/fs

ALC1 setting:Refer to Table 32

HPFAD, HPF : ON (fc=150Hz)

2 band EQ : OFF

(1) Addr:05H, Data:82H

(2) Addr:02H, Data:05H

(3) Addr:06H, Data:14H

(4) Addr:08H, Data:C5H

(5) Addr:09H, Data:C5H

(6) Addr:07H, Data:2DH

(7) Addr:03H, Data:81H

(8-1) Addr:1CH, Data:16H

(8-2) Addr:1DH, Data:1FH

(8-3) Addr:1EH, Data:2BH

(8-4) Addr:1FH, Data:1EH

(9) Addr:0EH, Data:03H

(10) Addr:00H, Data:C1H

Recording

(11) Addr:00H, Data:40H

Figure 52. MIC Input Recording Sequence Example

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ASAHI KASEI

[AK4633]

This sequence is an example of ALC1 setting at fs=16kHz. If the parameter of the ALC1 is changed, please refer to

“Table 32. Example of the ALC Setting (Recording)“

At first, clocks should be supplied according to “Clock Set Up” sequence.

(1) Set up a sampling frequency (FS3-0 bit) and ADC initialization cycle. When the AK4633 is PLL mode,

Programmable Filter and ADC should be powered-up in consideration of PLL lock time after a sampling

frequency is changed.

(2) Set up MIC input (Addr: 02H)

(3) Set up Timer Select for ALC1 (Addr: 06H)

(4) Set up REF value for ALC1 (Addr: 08H)

(5) Set up IVOL value at start ALC1 (Addr: 09H)

(6) Set up LMTH0, RGAIN0, LMAT1-0, ZELM and ALC1 bits (Addr: 07H)

(7) Set up path of programmable filter: PFSDO bit = ADCPF bit = “1”

(8) Set up coefficient of programmable filter (HPF/EQ): Addr: 10H ∼ 1FH

(9) Set up ON/OFF of programmable filter (HPF/EQ)

HPFAD bit should be set to “1”.

(10) Power Up programmable filter and ADC: PMPFIL bit = PMADC bit = “0” → “1”

The initialization cycle time of ADC is 1059/fs=66ms@fs=16kHz when ADRST bit = “0”,

and 291/fs=18ms@fs=16kHz when ADRST bit = “1”. The ALC1 starts at IVOL value set by (5).

(11) Power Down programmable filter and ADC: PMPFIL bit = PMADC bit = “1” → “0”

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[AK4633]

Speaker-amp Output

FS3-0 bits

XXXX

(Addr:05H,

D5,D2-0)

(1)

(13)

DACS bit

(Addr:02H, D3)

(2)

ALC2 Control 1

XXH

(Addr:06H)

(3)

ALC2 Control 2

XXH

(Addr:10H)

(4)

OVOL7-0 bits

XXH

(Addr:0AH)

(5)

ALC2 Control 3

XXH

4XH

(Addr:07H)

(6)

Signal Select

XXXXXXXX

XX....X

000XX010

XX....X

(Addr:03H)

(7)

Filter Co-ef

(Addr:10H-1F)

(8)

Filter Select

(Addr:0EH D3-0)

XXX1

XX11

(9)

ALC2 State

ALC2 Disable

ALC2 Enable

PMPFIL bit

(Addr:00H, D7)

(14)

PMDAC bit

(Addr:00H, D2)

(10)

PMSPK bit

(Addr:00H, D4)

(11)

SPPSN bit

(Addr:02H, D7)

(12)

SPP pin

SPN pin

Hi-Z

Normal Output

Hi-Z

SVDD/2 Normal Output SVDD/2 Hi-Z

Figure 53. Speaker-Amp Output Sequence

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[AK4633]

Example:

PLL Master Mode

Audio I/F Format:DSP Mode, BCKP=MSBS=“0”

Sampling Frequency: 16kHz

SPKG1-0 bits = “01”

ALC2 : ON

ALC2 setting:Refer to Table 33

HPF : ON (fc=150Hz)

2 band EQ : OFF

(1) Addr:05H, Data:02H

(2) Addr:02H, Data:20H

(3) Addr:06H, Data:14H

(4) Addr:0BH, Data:28H

(5) Addr:0AH, Data:91H

(6) Addr:07H, Data:4DH

(7) Addr:03H, Data:0AH

(8-1) Addr:1CH, Data:16H

(8-2) Addr:1DH, Data:1FH

(8-3) Addr:1EH, Data:2BH

(8-4) Addr:1FH, Data:1EH

(9) Addr:0EH, Data:03H

(10) Addr:00H, Data:D4H

(11) Addr:02H, Data:A0H

Playback

(12) Addr:02H, Data:20H

(13) Addr:02H, Data:00H

(14) Addr:00H, Data:40H

Figure 54. Speaker-Amp Output Sequence Example

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[AK4633]

This sequence is an example of ALC2 setting at fs=16kHz. If the parameter of the ALC2 is changed, please refer to

“Table 33. Example of the ALC Setting (Playback)”.

At first, clocks should be supplied according to “Clock Set Up” sequence.

(1) Set up a sampling frequency (FS3-0 bits). When the AK4633 is PLL mode, DAC and Speaker-Amp should be

powered-up in consideration of PLL lock time after a sampling frequency is changed.

(2) Set up the path of “DAC Æ SPK-Amp”: DACS bit: “0” → “1”

(3) Set up the ALC2 Timer (Addr: 06H)

(4) Set up the REF value of ALC2 (Addr: 08H)

(5) Set up OVOL value at start ALC2 (Addr: 10H), RGAIN1 and LMTH1

(6) Set up LMTH0, RGAIN0, LMAT1-0, ZELM and ALC2 bits (Addr: 07H)

(7) Set up path of programmable filter and SPK-Amp gain:

PFDAC bit = “1”, ADCPF bit = “0”, SPKG1-0 bits = “XX”

(8) Set up coefficient of programmable filter (HPF/EQ): Addr: 10H ∼ 1FH

(9) Set up ON/OFF of programmable filter (HPF/EQ)

HPF bit is recommended to “1”.

(10) Power Up DAC, SPK and programmable filter:

PMDAC bit = PMSPK bit = PMPFIL bit = “0” → “1”

(11) Exit Speaker power-save-mode: SPPSN bit = “0” → “1”

SPPSN bit should be set to “1” at more than 1ms after PMSPK bit is set to “1”.

(12) Enter Speaker power-save-mode: SPPSN bit = “1” → “0”

(13) Disable the path of “DAC Æ SPK-Amp”: DACS bit = “1” → “0”

(14) Power Down DAC, Speaker and programmable filter: PMDAC bit = PMSPK bit = PMPFIL bit = “1” → “0”

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ASAHI KASEI

[AK4633]

BEEP signal output from Speaker-Amp

Example:

(1) Addr:00H, Data:70H

Clocks can be stopped.

CLOCK

PMBP bit

(Addr:00H, D2)

(2) Addr:02H, Data:40H

(3) Addr:02H, Data:C0H

BEEP Signal Output

(1)

(5)

PMSPK bit

(Addr:00H, D4)

(2)

(6)

BEEPS bit

(Addr:02H, D6)

(3)

SPPSN bit

(Addr:02H, D7)

(4) Addr:02H, Data:40H

(4)

SPP pin

SPN pin

Hi-Z

Normal Output

Hi-Z

(5) Addr:00H, Data:40H

(6) Addr:02H, Data:00H

Hi-Z

SVDD/2 Normal Output SVDD/2 Hi-Z

Figure 55. “BEEP-Amp Æ Speaker-Amp” Output Sequence

The clock is not needed to supply when only BEEP-Amp and Speaker-Amp are operating.

(1) Power Up BEEP-Amp and Speaker-Amp: PMBP bit = PMSPK bit = “0” → “1”

(2) Enable the path of “BEEP Æ SPK-Amp”: BEEPS bit = “0” → “1”

(3) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”

“(4)” time depends on the time constant of external resistor and capacitor connected to BEEP pin. If

Speaker-Amp output is enabled before input of BEEP-Amp becomes stable, pop noise may occur.

e.g. R=20k, C=0.1µF: Recommended wait time is more than 5τ = 10ms.

(4) Enter the power-save-mode of Speaker-Amp: SPPSN bit = “1” → “0”

(5) Power Down BEEP-Amp and Speaker-Amp: PMBP bit = PMSPK bit = “1” → “0”

(6) Disable the path of “BEEP Æ SPK-Amp”: BEEPS bit = “1” → “0”

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ASAHI KASEI

[AK4633]

MONO LINEOUT

Example:

PLL, Master Mode

Audio I/F Format :DSP Mode, BCKP=MSBS= “0”

Sampling Frequency: 16kHz

Digital Volume: 0dB

FS3-0 bits

XXXX

(Addr:05H,

D5, D2-0)

(1)

(1) Addr:05H, Data:02H

(2) Addr:02H, Data:10H

(3) Addr:03H, Data:02H

(4) Addr:07H, Data:00H

(5) Addr:0AH, Data:91H

(6) Addr:03H, Data:42H

(7) Addr:00H, Data:CCH

(8) Addr:03H, Data:02H

Playback

(11)

DACA bit

(Addr:02H, D4)

(2)

(3)

ADCPF bit

(Addr:03H, D0)

0

0 or 1

PFDAC bit

(Addr:03H, D1)

0 or 1

1

0

(4)

ALC2 bit

(Addr:07H, D6)

(5)

OVOL7-0 bits

(Addr:0AH, D7-0)

XXH

AOPS bit

(Addr:03H, D6)

(6)

(8)

(9)

(12)

PMDAC bit

(Addr:00H, D2)

(7)

(10)

PMPFIL bit

(9) Addr:03H, Data:42H

(10) Addr:00H, Data:40H

(11) Addr:02H, Data:00H

(12) Addr:03H, Data:02H

(Addr:00H, D7)

PMAO bit

(Addr:00H, D3)

>300 ms

Normal Output

AOUT pin

Figure 56. Mono Lineout Sequence

This sequence is an example of Digital Output Volume at manual mode.

At first, clocks should be supplied according to “Clock Set Up” sequence.

(1) Set up a sampling frequency (FS3-0 bits).

DAC should be powered-up in consideration of PLL lock time.

(2) Set up the path of “DAC Æ Mono Line Amp”: DACA bit: “0” → “1”

(3) Set up the path: ADCPF bit = “0”, PFDAC bit = “1”

(4) Disable ALC2: ALC2 bit = “0”

(5) Set up the digital volume (Addr: 0AH)

(6) Enter the power-save-mode of AOUT: AOPS bit: “0” → “1”

(7) Power Up DAC, programming filter and mono lineout.

PMDAC bit = PMPFIL bit = PMAO bit = “0” → “1”

AOUT pin powers up at rise edge. The rise time is 300ms(max) when C = 1µF.

(8) Exit the power-save-mode of AOUT: AOPS bit: “1” → “0”

The setting should be down after AOUT pin rises up. After the setting, the signal is output from AOUT pin.

(9) Enter the power-save-mode of AOUT: AOPS bit: “0” → “1”

(10)Power Down DAC, programmable filter and mono lineout.

PMDAC bit = PMPFIL bit = PMAO bit = “1” → “0”

AOUT pin powers up at fall edge. The fall time is 300ms(max) when C = 1µF.

(11)Disable the path of “DAC Æ Mono Line Amp”: DACA bit: “1” → “0”

(12)Exit the power-save-mode of AOUT: AOPS bit: “1” → “0”

The setting should be down after the AOUT pin fall down.

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ASAHI KASEI

[AK4633]

Stop of Clock

Master clock can be stopped when ADC, DAC and programmable filter don’t operate.

1. PLL Master Mode

Example:

Audio I/F Format: DSP Mode, BCKP = MSBS = “0”

BICK frequency at Master Mode : 64fs

Input Master Clock Select at PLL Mode : 11.2896MHz

Sampling Frequency:8kHz

(1)

PMPLL bit

(Addr:01H, D0)

(1) (2) Addr:01H, Data:08H

Stop an external MCKI

(2)

MCKO bit

(Addr:01H, D1)

"H" or "L"

(3)

External MCKI

Input

Figure 57. Clock Stopping Sequence (1)

(1) Power down PLL: PMPLL bit = “1” → “0”

(2) Stop MCKO clock: MCKO bit = “1” → “0”

(3) Stop an external master clock.

2. PLL Slave Mode (FCK or BICK pins)

Example

Audio I/F Format : DSP Mode, BCKP = MSBS = “0”

PLL Reference clock: BICK

(1)

PMPLL bit

(Addr:01H,D0)

BICK frequency: 64fs

Sampling Frequency: 8kHz

(2)

External BICK

External FCK

Input

(1) Addr:01H, Data:04H

(2)

(2) Stop the external clocks

Figure 58. Clock Stopping Sequence (2)

(1) Power down PLL: PMPLL bit = “1” → “0”

(2) Stop the external BICK and FCK clocks.

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ASAHI KASEI

[AK4633]

3. PLL Slave Mode (MCKI pin)

Example

(1)

Audio I/F Format : DSP Mode, BCKP = MSBS = “0”

PLL Reference clock: MCKI

PMPLL bit

(Addr:01H, D0)

BICK frequency: 64fs

Sampling Frequency: 8kHz

(1)

MCKO bit

(Addr:01H, D1)

(1) Addr:01H, Data:00H

(2)

External MCKI

Input

(2) Stop the external clocks

Figure 59. Clock Stopping Sequence (3)

(1) Power down PLL: PMPLL bit = “1” → “0”

Stop MCKO output: MCKO bit = “1” → “0”

(2) Stop the external master clock.

4. EXT Slave Mode

Example

(1)

Audio I/F Format :MSB justified(ADC and DAC)

Input MCKI frequency:1024fs

External MCKI

Input

Sampling Frequency:8kHz

(1)

External BICK

External FCK

Input

(1) Addr:01H, Data:00H

(2) Stop the external clocks

Figure 60. Clock Stopping Sequence (4)

(1) Stop the external MCKI, BICK and FCK clocks.

Power down

If the clocks are supplied, power down VCOM (PMVCM bit: “1” → “0”) after all blocks except for VCOM are

powered-down and a master clock stops. The AK4633 is also powered-down by PDN pin = “L”. When PDN pin = “L”,

the registers are initialized.

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ASAHI KASEI

[AK4633]

Package

24pin QFN (Unit: mm)

4.0 ± 0.1

2.4 ± 0.15

13

18

12

19

24

A

Exposed

Pad

7

0.40 ± 0.1

6

1

B

PIN #1 ID

(0.35 x 45 )

0.23 ± 0.05

M

0.10

0.08

0.5

Note) The exposed pad on the bottom surface of the package must be open or connected to GND.

Material & Lead finish

Package molding compound:

Lead frame material:

Epoxy

Cu

Lead frame surface treatment:

Solder (Pb free) plate

MS0447-E-03

2006/04

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ASAHI KASEI

[AK4633]

MARKING

4633

XXXX

1

XXXX: Date code (4 digit)

Pin #1 indication

Revision History

Date (YY/MM/DD) Revision Reason

Page

Contents

05/12/26

06/04/28

00

03

First Edition

Error Correct

40

41

Table 19 : PDSDO bit → PFSDO bit

2 Band Equalizer : The Coefficient of C is corrected.

[Before correct]

1 − tan (πfb/fs)

C =

1 + tan (πfb/fs)

[After correct]

1 − tan (πfb/fs)

−

C =

1 + tan (πfb/fs)

Add

Explanation

Add

42

2 Band Equalizer : The note is added when these

equalizer are used as notch filters

53, 75 Speaker-Amp Control Sequence

The wait time from PMSPK bit = “1” to SPPSN bit is

Explanation

“1” is added.

Error Correct

54

Serial control interface

Bit6 in Figure 43 : A2 → A1

MS0447-E-03

2006/04

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ASAHI KASEI

[AK4633]

IMPORTANT NOTICE

• These products and their specifications are subject to change without notice. Before considering any

use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized

distributor concerning their current status.

• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the

application or use of any information contained herein.

• Any export of these products, or devices or systems containing them, may require an export license

or other official approval under the law and regulations of the country of export pertaining to customs

and tariffs, currency exchange, or strategic materials.

• AKM products are neither intended nor authorized for use as critical components in any safety, life

support, or other hazard related device or system, and AKM assumes no responsibility relating to any

such use, except with the express written consent of the Representative Director of AKM. As used

here:

a. A hazard related device or system is one designed or intended for life support or maintenance of

safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its

failure to function or perform may reasonably be expected to result in loss of life or in significant

injury or damage to person or property.

b. A critical component is one whose failure to function or perform may reasonably be expected to

result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or

system containing it, and which must therefore meet very high standards of performance and

reliability.

• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of,

or otherwise places the product with a third party to notify that party in advance of the above content

and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability

for and hold AKM harmless from any and all claims arising from the use of said product in the

absence of such notification.

MS0447-E-03

2006/04

- 82 -


型号：	AKD4633
厂家：	ASAHI KASEI MICROSYSTEMS
描述：	16-Bit Mono CODEC with ALC & MIC/SPK-AMP 16位单声道编解码器与ALC ＆ MIC / SPK- AMP 解码器编解码器
文件：	总82页 (文件大小：662K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AKD4633 [AKM]

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