AK4385_06 [AKM]
108dB 192kHz 24-Bit 2ch ツヒ DAC; 108分贝192kHz的24位双声道ツヒDAC
| 型号： | AK4385_06 |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | 108dB 192kHz 24-Bit 2ch ツヒ DAC |
| 文件： | 总23页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AK4385]
AK4385
∆Σ
108dB 192kHz 24-Bit 2ch
DAC
GENERAL DESCRIPTION
The AK4385 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit
architecture for its modulator the AK4385 delivers a wide dynamic range while preserving linearity for
improved THD+N performance. The AK4385 has full differential SCF outputs, removing the need for AC
coupling capacitors and increasing performance for systems with excessive clock jitter. The 24 Bit word
length and 192kHz sampling rate make this part ideal for a wide range of applications including
DVD-Audio. The AK4385 is offered in a space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
On chip SCF
Digital de-emphasis for 32k, 44.1k and 48kHz sampling
Soft mute
Digital Attenuator (Linear 256 steps)
I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I2S
Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
THD+N: -94dB
Dynamic Range: 108dB
High Tolerance to Clock Jitter
Power supply: 4.75 to 5.25V
Very Small Package: 16pin TSSOP (6.4mm x 5.0mm)
AK4381 Pin Compatible
MCLK
VDD
VSS
Clock
Divider
De-emphasis
Control
CSN
µP
Interface
CCLK
CDTI
DZFL
DZFR
AOUTL+
AOUTL-
8X
∆Σ
SCF
SCF
LRCK
Modulator
Audio
Data
Interface
Interpolator
BICK
SDTI
AOUTR+
AOUTR-
8X
∆Σ
Interpolator
Modulator
PDN
MS0246-E-01
2006/01
- 1 -
ASAHI KASEI
[AK4385]
Ordering Guide
AK4385ET
AK4385VT
AKD4385
-20 ∼ +85°C
-40 ∼ +85°C
Evaluation Board for AK4385
16pin TSSOP (0.65mm pitch)
16pin TSSOP (0.65mm pitch)
Pin Layout
MCLK
BICK
SDTI
LRCK
DZFL
DZFR
VDD
1
2
3
16
15
14
13
12
11
10
9
4
VSS
Top
View
AOUTL+
PDN
CSN
5
AOUTL-
AOUTR+
AOUTR-
6
7
8
CCLK
CDTI
PIN/FUNCTION
No. Pin Name
I/O
I
Function
Master Clock Input Pin
1
MCLK
An external TTL clock should be input on this pin.
Audio Serial Data Clock Pin
Audio Serial Data Input Pin
L/R Clock Pin
2
3
4
5
BICK
SDTI
LRCK
PDN
I
I
I
I
Power-Down Mode Pin
When at “L”, the AK4385 is in the power-down mode and is held in reset.
The AK4385 must be reset once upon power-up.
Chip Select Pin
6
7
8
9
10
11
12
13
14
15
16
CSN
CCLK
CDTI
AOUTR-
AOUTR+
AOUTL-
AOUTL+
VSS
I
I
I
O
O
O
O
-
Control Data Input Pin
Control Data Input Pin in serial mode
Rch Negative Analog Output Pin
Rch Positive Analog Output Pin
Lch Negative Analog Output Pin
Lch Positive Analog Output Pin
Ground Pin
Power Supply Pin
Rch Data Zero Input Detect Pin
Lch Data Zero Input Detect Pin
VDD
DZFR
DZFL
-
O
O
Note: All input pins should not be left floating.
MS0246-E-01
2006/01
- 2 -
ASAHI KASEI
[AK4385]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Power Supply
Input Current (any pins except for supplies)
Input Voltage
Ambient Operating Temperature
(Powered applied)
Symbol
VDD
IIN
VIND
Ta
min
-0.3
-
-0.3
-20
-40
-65
max
6.0
±10
Units
V
mA
V
°C
°C
VDD+0.3
AK4385ET
AK4385VT
85
85
150
Ta
Tstg
Storage Temperature
°C
Note: 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Symbol
min
typ
max
Units
Power Supply
VDD
4.75
5.0
5.25
V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0246-E-01
2006/01
- 3 -
ASAHI KASEI
[AK4385]
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;
Measurement frequency=20Hz ∼ 20kHz; RL ≥4kΩ; unless otherwise specified)
Parameter
min
typ
max
Units
Resolution
24
Bits
Dynamic Characteristics
THD+N
(Note 3)
0dBFS
fs=44.1kHz
BW=20kHz
fs=96kHz
BW=40kHz
fs=192kHz
BW=40kHz
-94
-44
-92
-41
-92
-41
108
108
110
0.2
-84
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
-60dBFS
0dBFS
-60dBFS
0dBFS
-
-
-
-
-
-60dBFS
Dynamic Range (-60dBFS with A-weighted)
S/N (A-weighted)
(Note 4)
(Note 5)
100
100
90
Interchannel Isolation (1kHz)
Interchannel Gain Mismatch
DC Accuracy
0.5
Gain Drift
Output Voltage
Load Resistance
100
±2.75
-
ppm/°C
Vpp
kΩ
(Note 6)
(Note 7)
±2.55
4
±2.95
Power Supplies
Power Supply Current (VDD)
17
20
10
27
32
100
mA
mA
µA
Normal Operation (PDN = “H”, fs≤96kHz)
Normal Operation (PDN = “H”, fs=192kHz)
Power-Down Mode (PDN = “L”)
(Note 8)
Notes: 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
4. 100dB at 16bit data.
5. S/N does not depend on input bit length.
6. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF,
AOUT (typ.@0dB)=(AOUT+)-(AOUT-)=±2.75Vpp × VREF/5.
7. For AC-load. 4kΩ for DC-load.
8. All digital inputs including clock pins (MCLK, BICK and LRCK) are held VDD or VSS.
MS0246-E-01
2006/01
- 4 -
ASAHI KASEI
[AK4385]
SHARP ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; VDD = 4.75 ∼ 5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “0”)
Parameter
Digital filter
Passband
Symbol
min
typ
max
Units
PB
0
-
24.1
20.0
-
kHz
kHz
kHz
dB
dB
1/fs
±0.05dB (Note 9)
-6.0dB
22.05
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 9)
SB
PR
SA
GD
± 0.02
54
-
(Note 10)
19.3
-
Digital Filter + SCF
Frequency Response 20.0kHz fs=44.1kHz
40.0kHz fs=96kHz
FR
FR
FR
-
-
-
-
-
-
dB
dB
dB
± 0.2
± 0.3
+0.1/-0.6
80.0kHz fs=192kHz
Notes: 9. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data
of both channels to input register to the output of analog signal.
SLOW ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “1”)
Parameter
Digital Filter
Symbol
min
typ
max
Units
Passband
±0.04dB
-3.0dB
(Note 11)
(Note 11)
PB
0
-
8.1
-
kHz
kHz
kHz
dB
18.2
Stopband
SB
PR
SA
GD
39.2
Passband Ripple
± 0.005
Stopband Attenuation
Group Delay
72
-
dB
(Note 10)
19.3
-
1/fs
Digital Filter + SCF
Frequency Response
FR
FR
FR
-
-
-
+0/-5
+0/-4
-
-
-
dB
dB
dB
fs=44.kHz
fs=96kHz
fs=192kHz
20.0kHz
40.0kHz
80.0kHz
+0.1/-5
Note: 11. The passband and stopband frequencies scale with fs.
For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
DC CHARACTERISTICS
(Ta=25°C; VDD=4.75 ∼ 5.25V)
Parameter
Symbol
VIH
VIL
VOH
VOL
Iin
min
2.2
-
typ
max
-
0.8
-
0.4
± 10
Units
V
V
V
V
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout=-80µA)
Low-Level Output Voltage
Input Leakage Current
-
-
-
VDD-0.4
(Iout=80µA)
-
-
-
µA
MS0246-E-01
2006/01
- 5 -
ASAHI KASEI
[AK4385]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=4.75 ∼ 5.25V)
Parameter
Master Clock Frequency
Symbol
fCLK
dCLK
min
2.048
40
typ
11.2896
max
36.864
60
Units
MHz
%
Duty Cycle
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
fsn
fsd
8
48
96
kHz
kHz
kHz
%
60
fsq
120
45
192
55
Duty Cycle
Duty
Audio Interface Timing
BICK Period
Normal Speed Mode
Double/Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fs
1/64fs
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
BICK rising to LRCK Edge
LRCK Edge to BICK rising
SDTI Hold Time
(Note 12)
(Note 12)
SDTI Setup Time
Control Interface Timing
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Reset Timing
tCSH
PDN Pulse Width
(Note 13)
tPD
150
ns
Notes: 12. BICK rising edge must not occur at the same time as LRCK edge.
13. The AK4385 can be reset by bringing PDN= “L”.
MS0246-E-01
2006/01
- 6 -
ASAHI KASEI
[AK4385]
Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
BICK
VIL
tBCK
VIH
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
BICK
SDTI
VIL
tBLR
tLRB
VIH
VIL
tSDS
tSDH
VIH
VIL
Serial Interface Timing
MS0246-E-01
2006/01
- 7 -
ASAHI KASEI
[AK4385]
VIH
VIL
CSN
tCSS
tCCKL tCCKH
VIH
VIL
CCLK
CDTI
tCDS tCDH
C0
VIH
VIL
C1
R/W
A4
WRITE Command Input Timing
tCSW
VIH
VIL
CSN
tCSH
VIH
VIL
CCLK
CDTI
VIH
VIL
D3
D2
D1
D0
WRITE Data Input Timing
tPD
PDN
VIL
Power-down Timing
MS0246-E-01
2006/01
- 8 -
ASAHI KASEI
[AK4385]
OPERATION OVERVIEW
System Clock
The external clocks, which are required to operate the AK4385, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is set
automatically. (Table 2~4).After exiting reset (PDN = “↑”), the AK4385 is in Auto Setting Mode. In Auto Setting Mode
(ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes
the appropriate frequency (Table 6), it is not necessary to set DFS0/1.
All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4385 is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4385 may draw excess current and may fall into unpredictable
operation. This is because the device utilizes dynamic refreshed logic internally. The AK4385 should be reset by PDN=
“L” after threse clocks are provided. If the external clocks are not present, the AK4385 should be in the power-down
mode (PDN= “L”). After exiting reset at power-up etc., the AK4385 is in the power-down mode until MCLK and LRCK
are input.
DFS1
DFS0
Sampling Rate (fs)
Default
0
0
1
0
1
0
Normal Speed Mode
8kHz~48kHz
60kHz~96kHz
120kHz~192kHz
Double Speed Mode
Quad Speed Mode
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
fs
MCLK
512fs
BICK
64fs
8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz 2.0480MHz
256fs
384fs
768fs
1152fs
32.0kHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz
N/A
N/A
2.8224MHz
3.0720MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
fs
MCLK
BICK
64fs
128fs
192fs
256fs
384fs
88.2kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz
96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK
fs
MCLK
BICK
64fs
128fs
192fs
176.4kHz 22.5792MHz 33.8688MHz 11.2896MHz
192.0kHz 24.5760MHz 36.8640MHz 12.2880MHz
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MS0246-E-01
2006/01
- 9 -
ASAHI KASEI
[AK4385]
MCLK
Sampling Speed
Normal
512fs
256fs
128fs
768fs
384fs
192fs
Double
Quad
Table 5. Sampling Speed (Auto Setting Mode: Default)
LRCK
fs
MCLK (MHz)
Sampling Speed
128fs
192fs
256fs
384fs
512fs
768fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
Normal
22.5792
24.5760
33.8688
36.8640
-
-
-
-
-
-
-
-
Double
Quad
-
-
22.5792
24.5760
33.8688
36.8640
-
-
-
-
Table 6. System Clock Example (Auto Setting Mode)
Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-2 as shown in Table 7 can select five serial
data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK.
Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode DIF2 DIF1 DIF0 SDTI Format
BICK
≥32fs
≥40fs
≥48fs
≥48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
0
1
2
3
0
0
0
0
0
0
1
1
0
1
0
1
16bit LSB Justified
20bit LSB Justified
24bit MSB Justified
24bit I2S Compatible
Default
4
1
0
0
24bit LSB Justified
Figure 2
≥48fs
Table 7. Audio Data Formats
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15 14
6
5
4
3
2
1
0
0
15 14
6
5
4
3
2
1
0
0
15 14
0
1
14
15
16
17
31
0
1
14
15
16
17
31
0
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15 14
Don’t care
15 14
15:MSB, 0:LSB
Lch Data
Rch Data
MS0246-E-01
2006/01
- 10 -
ASAHI KASEI
[AK4385]
Figure 1. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
0
1
BICK
(64fs)
SDTI
Mode 1
Don’t care
19
0
0
Don’t care
Don’t care
19
0
0
19:MSB, 0:LSB
Don’t care
SDTI
Mode 4
23 22 21 20 19
23 22 21 20 19
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1,4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDTI
23 22
23:MSB, 0:LSB
1
0
Don’t care
23 22
1
0
Don’t care
23 22
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
0
1
23 22
23:MSB, 0:LSB
Don’t care
23 22
1
0
Don’t care
23
Lch Data
Figure 4. Mode 3 Timing
Rch Data
MS0246-E-01
2006/01
- 11 -
ASAHI KASEI
[AK4385]
De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled
with DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off.
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
Default
48kHz
32kHz
Table 8. De-emphasis Filter Control (Normal Speed Mode)
Output Volume
The AK4385 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing
levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition
time of 1 level and all 256 levels is shown in Table 9.
Sampling Speed
Transition Time
255 to 0
1 Level
4LRCK
8LRCK
16LRCK
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
1020LRCK
2040LRCK
4080LRCK
Table 9. ATT Transition Time
MS0246-E-01
2006/01
- 12 -
ASAHI KASEI
[AK4385]
Zero Detection
The AK4385 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input
data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pin
of both channels go to “L” at 2~3/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both channels go
to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect function can
be disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the polarity of DZF
pin.
Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by
-∞ during ATT_DATA×ATT transition time (Table 9) from the current ATT level. When the SMUTE bit is returned to
“0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT
transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE bit
(1)
(1)
ATT Level
Attenuation
(3)
-∞
GD
GD
(2)
AOUT
(4)
8192/fs
DZF pin
Notes:
(1) ATT_DATA×ATT transition time (Table 9). For example, in Normal Speed Mode, this time is 1020LRCK cycles
(1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 5. Soft Mute and Zero Detection
MS0246-E-01
2006/01
- 13 -
ASAHI KASEI
[AK4385]
System Reset
The AK4385 should be reset once by bringing PDN= ”L” upon power-up. The AK4385 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4385 is in the
power-down mode until MCLK and LRCK are input.
Power-down
The AK4385 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z).
Figure 6 shows an example of the system timing at the power-down and power-up.
PDN
Internal
State
Normal Operation
Power-down
Normal Operation
D/A In
(Digital)
“0” data
GD
GD
(1)
(1)
(3)
(6)
(2)
(3)
D/A Out
(Analog)
(4)
Clock In
MCLK, LRCK, BICK
Don’t care
DZFL/DZFR
External
MUTE
(5)
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN = “L”).
Figure 6. Power-down/up Sequence Example
MS0246-E-01
2006/01
- 14 -
ASAHI KASEI
[AK4385]
Reset Function
When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to
VCOM voltage and DZF pin goes to “H”. Figure 7 shows the example of reset by RSTN bit.
RSTN bit
3~4/fs (6)
2~3/fs (6)
Internal
RSTN bit
Internal
State
Normal Operation
Digital Block Power-down
“0” data
Normal Operation
D/A In
(Digital)
GD
GD
(1)
(1)
(3)
(2)
(4)
(3)
D/A Out
(Analog)
Clock In
MCLK,LRCK,BICK
Don’t care
2/fs(5)
DZF
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage (VDD/2).
(3) Click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN “1”.
Figure 7. Reset Sequence Example
MS0246-E-01
2006/01
- 15 -
ASAHI KASEI
[AK4385]
Mode Control Interface
Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists
of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first,
5bits) and Control Data (MSB first, 8bits). AK4385 latches the data on the rising edge of CCLK, so data should clocked
in on the falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max).
PDN = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers are
not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 8. Control I/F Timing
*AK4385 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4385 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
Register Map
Addr
Register Name
D7
D6
0
D5
0
D4
D3
D2
D1
D0
00H Control 1
ACKS
DIF2
DIF1
DIF0
PW
RSTN
01H Control 2
02H Control 3
03H Lch ATT
04H Rch ATT
DZFE
0
ATT7
ATT7
DZFM
0
ATT6
ATT6
SLOW
0
ATT5
ATT5
DFS1
0
ATT4
ATT4
DFS0
0
ATT3
ATT3
DEM1
DZFB
ATT2
ATT2
DEM0
0
ATT1
ATT1
SMUTE
0
ATT0
ATT0
Notes:
For addresses from 05H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default
values.
All data can be written to the register even if PW or RSTN bit is “0”.
MS0246-E-01
2006/01
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ASAHI KASEI
[AK4385]
Register Definitions
Addr
Register Name
D7
ACKS
1
D6
0
D5
0
D4
DIF2
0
D3
DIF1
1
D2
DIF0
0
D1
PW
1
D0
RSTN
1
00H Control 1
default
0
0
RSTN: Internal timing reset control
0: Reset. All registers are not initialized.
1: Normal Operation
When MCLK frequency or DFS changes, the click noise can be reduced by RSTN bit.
PW: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation
DIF2-0: Audio data interface formats (see Table 7)
Initial: “010”, Mode 2
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0
are ignored. When this bit is “0”, DFS1-0 set the sampling speed mode.
Addr
Register Name
D7
DZFE
0
D6
DZFM
0
D5
SLOW
0
D4
DFS1
0
D3
DFS0
0
D2
DEM1
0
D1
DEM0
1
D0
SMUTE
0
01H Control 2
default
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis Response (see Table 8)
Initial: “01”, OFF
DFS1-0: Sampling speed control
00: Normal speed
01: Double speed
10: Quad speed
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise
occurs.
SLOW: Slow Roll-off Filter Enable
0: Sharp Roll-off Filter
1: Slow Roll-off Filter
DZFE: Data Zero Detect Enable
0: Disable
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are
always “L”.
MS0246-E-01
2006/01
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ASAHI KASEI
[AK4385]
DZFM: Data Zero Detect Mode
0: Channel Separated Mode
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at both
channels are continuously zeros for 8192 LRCK cycles.
Addr
Register Name
D7
0
D6
0
D5
0
D4
0
D3
0
D2
DZFB
0
D1
0
D0
0
02H Control 3
default
0
0
0
0
0
0
0
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
03H Lch ATT
04H Rch ATT
ATT7
ATT7
ATT6
ATT6
ATT5
ATT5
ATT4
ATT4
ATT3
ATT3
ATT2
ATT2
ATT1
ATT1
ATT0
ATT0
default
1
1
1
1
1
1
1
1
ATT = 20 log10 (ATT_DATA / 255) [dB]
00H: Mute
SYSTEM DESIGN
Figure 9 shows the system connection diagram. An evaluation board (AKD4385) is available in order to allow an easy
study on the layout of a surrounding circuit.
Master Clock
64fs
MCLK
BICK
SDTI
DZFL
1
2
3
4
5
6
7
8
16
DZFR 15
VDD 14
Analog
Supply 5V
24bit Audio Data
fs
+
10u
0.1u
LRCK
PDN
VSS 13
AK4385
Reset & Power down
AOUTL+ 12
Lch
LPF
Lch
MUTE
Lch Out
Rch Out
CSN
AOUTL-
AOUTR+
AOUTR-
11
10
9
Micro-
controller
CCLK
Rch
LPF
Rch
MUTE
CDTI
Digital Ground
Analog Ground
Figure 9. Typical Connection Diagram
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins should not be left floating.
MS0246-E-01
2006/01
- 18 -
ASAHI KASEI
[AK4385]
1. Grounding and Power Supply Decoupling
VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling
capacitor, especially 0.1µF ceramic capacitor for high frequency should be placed as near to VDD as possible. The
differential Voltage between VDD and VSS pins set the analog output range.
2. Analog Outputs
The analog outputs are full-differential outputs and 0.55 x VDD Vpp (typ) centered around the internal common voltage
(about AVDD/2). The differential outputs are summed externally, VAOUT=(AOUT+)-(AOUT-) between AOUT+ and
AOUT-. If the summing gain is 1, the output range is 5.5Vpp (typ @VREFH=5V). The bias voltage of the external
summing circuit is supplied externally. The input data format is 2’s complement. The output voltage (VAOUT) is a positive
full scale for 7FFFFF (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H
(@24bit).
The internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma
modulator beyond the audio passband. DC offset on AOUT+/- is eliminated without AC coupling since the analog
outputs are differential. Figure 10 and 11 show the example of external op-amp circuit summing the differential outputs.
4.7k
4.7k
AOUT-
AOUT+
R1
R1
470p
Vop
3300p
4.7k
Analog
Out
4.7k
Vop
470p
1k
0.1u
BIAS
47u
When R1=200
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
Ω
1k
When R1=180
Ω
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Figure 10. External 2nd order LPF Circuit Example (using op-amp with single power supply)
4.7k
4.7k
AOUT-
AOUT+
R1
R1
470p
+Vop
3300p
4.7k
Analog
Out
4.7k
-Vop
470p
When R1=200Ω
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
When R1=180
Ω
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Figure 11. External 2nd order LPF Circuit Example (using op-amp with dual power supplies)
MS0246-E-01
2006/01
- 19 -
ASAHI KASEI
[AK4385]
PACKAGE
16pin TSSOP (Unit: mm)
*5.0 0.1
1.05 0.05
±
±
16
9
A
8
1
0.22 0.1
±
0.65
0.17 0.05
±
0.13 M
Detail A
0.1 0.1
±
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10
°
Package & Lead frame material
Package molding compound:
Lead frame material:
Epoxy
Cu
Lead frame surface treatment:
Solder(Pb free) plate
MS0246-E-01
2006/01
- 20 -
ASAHI KASEI
[AK4385]
MARKING (AK4385VT)
AKM
4385VT
XXYYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
3) Marketing Code : 4385VT
4) Asahi Kasei Logo
MS0246-E-01
2006/01
- 21 -
ASAHI KASEI
[AK4385]
MARKING (AK4385ET)
AKM
4385ET
XXYYY
5) Pin #1 indication
6) Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
7) Marketing Code : 4385ET
8) Asahi Kasei Logo
MS0246-E-01
2006/01
- 22 -
ASAHI KASEI
[AK4385]
Revision History
Date (YY/MM/DD) Revision Reason
Page
2
Contents
03/07/02
06/01/11
00
01
First Edition
Spec Addition
Ordering Guide
AK4385ET was added.
22
MARKING
AK4385ET was added.
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
MS0246-E-01
2006/01
- 23 -
相关型号：
AK4388KT
D/A Converter, 1 Func, Serial Input Loading, PDSO16, 6.40 X 5 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, TSSOP-16
AKM
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