AK4388AET [AKM]
192kHz 24-Bit 2ch ΔΣ DAC; 192kHz的24位双声道DAC ΔΣ
| 型号： | AK4388AET |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | 192kHz 24-Bit 2ch ΔΣ DAC |
| 文件： | 总18页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
[AK4388A]
AK4388A
192kHz 24-Bit 2ch ΔΣ DAC
GENERAL DESCRIPTION
The AK4388A offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit
architecture for its modulator, the AK4388A delivers a wide dynamic range while preserving linearity for
improved THD+N performance. The AK4388A integrates a combination of SCF and CTF filters increasing
performance for systems with excessive clock jitter. The 24 Bit word length and 192kHz sampling rate
make this part ideal for a wide range of applications including DVD-Audio. The AK4388A is offered in a
space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranges from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
SCF with High Tolerance to Clock Jitter
Single Ended Output Buffer
Digital de-emphasis
Soft mute
I/F format: 24-Bit MSB justified, 24/16-Bit LSB justified or I2S
Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)
256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
THD+N: -90dB
Dynamic Range: 106dB
Power supply: 4.5 to 5.5V
Very Small Package: 16pin TSSOP (6.4mm x 5.0mm)
AK4384 Parallel Mode Compatible
MCLK
VDD
VSS
DEM
SMUTE
ACKS
DIF0
DIF1
Clock
Divider
De-emphasis
Control
Control
Port
VCOM
DZF
8X
ΔΣ
SCF
LPF
AOUTL
AOUTR
Interpolator
LRCK
Modulator
Audio
Data
Interface
BICK
SDTI
8X
ΔΣ
SCF
LPF
Interpolator
Modulator
RSTN
MS1008-E-02
2010/09
- 1 -
[AK4388A]
■Ordering Guide
AK4388AET
-20°C ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for the AK4388A
AKD4388A
■ Pin Layout
MCLK
BICK
SDTI
DZF
DEM
VDD
VSS
1
2
3
16
15
14
13
12
11
10
9
LRCK
RSTN
SMUTE
ACKS
DIF0
4
Top
View
5
VCOM
AOUTL
6
7
8
AOUTR
DIF1
■ Compatibility with AK4384, AK4388
1. Function
Functions
THD+N
Output Voltage
Slow Roll-Off Filter
Mode Setting
AK4384
-94dB
3.4Vpp
AK4388
-90dB
3.2Vpp
AK4388A
Å
Å
Å
Å
Å
Å
Available
Serial/Parallel
Not Available
Not Available
Parallel
Available
DEM in Parallel control
24/16-Bit I2S
24-Bit MSB justified
24/16-Bit LSB justified
1 pin
24-Bit I2S
24-Bit MSB justified
Audio Format in Parallel control
Å
Zero Data Detect Pin
2 pins
MCLK, LRCK, BICK
Clock Stop (RSTN pin= “H”)
Not Available
Not Available
Available
2. Pin Configuration
AK4388/A
MCLK
BICK
SDTI
LRCK
RSTN
SMUTE
ACKS
DIF0
AK4384
MCLK
BICK
SDTI
LRCK
Pin# Pin# AK4384
AK4388/A
DZF
DEM (pd)
VDD
VSS
VCOM
AOUTL
AOUTR
DIF1 (pu)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DZFL
DZFR
VDD
VSS
VCOM
AOUTL
AOUTR
P/S (pu)
PDN
SMUTE/CSN
ACKS/CCLK
DIF0/CDTI
: Deference between AK4384
* pu: Pull-up, pd: Pull-down
MS1008-E-02
2010/09
- 2 -
[AK4388A]
PIN/FUNCTION
No. Pin Name
I/O
I
Function
Master Clock Input Pin
1
MCLK
An external TTL clock must be input on this pin.
Audio Serial Data Clock Pin
Audio Serial Data Input Pin
L/R Clock Pin
2
3
4
5
BICK
SDTI
LRCK
RSTN
I
I
I
I
Reset Mode Pin
When at “L”, the AK4388A is in power-down mode and is held in reset. The
AK4388A must always be reset upon power-up.
Soft Mute Pin
“H”: Enable, “L”: Disable
Auto Setting Mode Pin
6
7
8
SMUTE
ACKS
DIF0
I
I
I
“L”: Manual Setting Mode, “H”: Auto Setting Mode
Audio Data Interface Format Pin
9
DIF1
I
Audio Data Interface Format Pin (Internal pull-up pin)
Rch Analog Output Pin
Lch Analog Output Pin
10
11
12
AOUTR
AOUTL
VCOM
O
O
O
Common Voltage Pin, VDD/2
Normally connected to VSS with a 10μF electrolytic cap.
Ground Pin
13
14
VSS
VDD
-
-
Power Supply Pin
4.5V~5.5V
15
DEM
I
De-emphasis Mode Pin (Internal pull-down pin)
When at “H”, the de-emphasis filter is available.
Zero Input Detect Pin
16
DZF
O
Note: All input pins except pull-up and pull-down pins must not be left floating.
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Power Supply
Input Current (any pins except for supplies)
Input Voltage
Ambient Operating Temperature
Storage Temperature
Symbol
VDD
IIN
VIND
Ta
min
-0.3
-
-0.3
-20
-65
max
6.0
±10
Units
V
mA
V
°C
°C
VDD+0.3
85
150
Tstg
Note 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Symbol
min
typ
max
Units
Power Supply
VDD
4.5
5.0
5.5
V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1008-E-02
2010/09
- 3 -
[AK4388A]
ANALOG CHARACTERISTICS
(Ta = 25°C; VDD = 5.0V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement
frequency = 20Hz ∼ 20kHz; RL ≥5kΩ; unless otherwise specified)
Parameter
min
typ
max
Units
Resolution
24
Bits
Dynamic Characteristics
THD+N
(Note 2)
0dBFS
–60dBFS
0dBFS
–60dBFS
0dBFS
–60dBFS
fs=44.1kHz
BW=20kHz
fs=96kHz
BW=40kHz
fs=192kHz
BW=40kHz
–90
–42
–90
–39
–85
–39
106
106
100
0.2
–80
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
-
-
-
-
-
Dynamic Range (-60dBFS with A-weighted)
S/N (A-weighted)
Interchannel Isolation (1kHz)
Interchannel Gain Mismatch
DC Accuracy
(Note 3)
(Note 4)
98
98
90
0.5
Gain Drift
Output Voltage
Load Resistance
100
3.20
-
ppm/°C
Vpp
kΩ
(Note 5)
(Note 6)
2.95
5
3.45
Load Capacitance
25
pF
Power Supplies
Power Supply Current (VDD)
16
18
60
-
27
160
mA
mA
µA
Normal Operation (RSTN pin = “H”, fs ≤ 96kHz)
Normal Operation (RSTN pin = “H”, fs = 192kHz)
Power-Down Mode (RSTN pin = “L”)
(Note 7)
Note 2. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
Note 3. 100dB at 16bit data.
Note 4. S/N does not depend on input bit length.
Note 5. Full-scale voltage (0dB). Output voltage scales with the voltage of VDD, AOUT (typ.@0dB) = 3.20Vpp ×
VDD/5.
Note 6. For AC-load.
Note 7. The DIF1 pin is held to VDD and the other all digital inputs including clock pins (MCLK, BICK and LRCK) are
held to VSS.
MS1008-E-02
2010/09
- 4 -
[AK4388A]
FILTER CHARACTERISTICS
(Ta = 25°C; VDD = 4.5 ∼ 5.5V; fs = 44.1kHz)
Parameter
Symbol
min
typ
max
Units
Digital filter (DEM = OFF)
PB
0
-
24.1
20.0
-
kHz
kHz
kHz
dB
dB
1/fs
Passband
±0.05dB (Note 8)
–6.0dB
22.05
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 8)
SB
PR
SA
GD
± 0.02
54
-
(Note 9)
19.3
-
De-emphasis Filter (DEM = ON)
De-emphasis Error
(DC referenced)
fs = 32kHz
fs = 44.1kHz
fs = 48kHz
-
-
-
-
-
-
–1.5/0
–0.2/+0.2
0/+0.6
dB
dB
dB
Digital Filter + LPF (DEM = OFF)
Frequency Response 20.0kHz fs=44.1kHz
40.0kHz fs=96kHz
FR
FR
FR
-
-
-
-
-
-
dB
dB
dB
±0.2
±0.3
+0.1/-0.6
80.0kHz fs=192kHz
Note 8. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535×fs
(@±0.05dB), SB=0.546×fs.
Note 9. Calculated delay time caused by digital filter. This time is measured from setting the 16/24bit data of both
channels to input register to the output of the analog signal.
MS1008-E-02
2010/09
- 5 -
[AK4388A]
DC CHARACTERISTICS
(Ta = 25°C; VDD = 4.5 ∼ 5.5V)
Parameter
Symbol
VIH
VIL
VOH
VOL
Iin
min
2.2
-
typ
max
-
0.8
-
0.4
± 10
Units
V
V
V
V
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout = –80µA)
Low-Level Output Voltage
Input Leakage Current (Note 10)
-
-
-
VDD-0.4
(Iout = 80µA)
-
-
-
µA
Note 10. Except for the DIF1 and DEM pins. The DIF1 pin has internal pull-up resistor, the DEM pin has internal
pull-down resistor, nominally 100kΩ. (typ. 100kΩ)
SWITCHING CHARACTERISTICS
(Ta = 25°C; VDD = 4.5 ∼ 5.5V; CL = 20pF)
Parameter
Master Clock Frequency
Symbol
fCLK
dCLK
min
2.048
40
typ
11.2896
max
36.864
60
Units
MHz
%
Duty Cycle
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
fsn
fsd
8
48
96
kHz
kHz
kHz
%
32
fsq
120
45
192
55
Duty Cycle
Audio Interface Timing
BICK Period
Duty
Normal Speed Mode
Double/Quad Speed Mode
BICK Pulse Width Low
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fs
1/64fs
30
ns
ns
ns
ns
ns
ns
ns
ns
Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
SDTI Hold Time
30
20
20
20
(Note 11)
(Note 11)
20
SDTI Setup Time
Reset Timing
RSTN Pulse Width
(Note 12)
tRST
150
ns
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. The AK4388A can be reset by bringing RSTN pin = “L” → “H”.
MS1008-E-02
2010/09
- 6 -
[AK4388A]
■ Timing Diagram
1/fCLK
VIH
VIL
MCLK
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
VIL
LRCK
BICK
tBCK
VIH
VIL
tBCKH
tBCKL
Figure 1. Clock Timing
VIH
LRCK
BICK
SDTI
VIL
tBLR
tLRB
VIH
VIL
tSDS
tSDH
VIH
VIL
Figure 2. Serial Interface Timing
tRST
RSTN
VIL
Figure 3. Power-down Timing
MS1008-E-02
2010/09
- 7 -
[AK4388A]
OPERATION OVERVIEW
■ System Clock
The external clocks, which are required to operate the AK4388A, are MCLK, LRCK and BICK. The master clock
(MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital
interpolation filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting
Mode (ACKS pin = “L”, Normal Speed Mode), the frequency of MCLK is set automatically (Table 1). In Auto Setting
Mode (ACKS pin = “H”), as MCLK frequency is detected automatically (Table 2), and the internal master clock becomes
the appropriate frequency (Table 3).
LRCK
fs
MCLK
512fs
BICK
64fs
256fs
384fs
768fs
1152fs
32.0kHz
8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz 2.0480MHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz
N/A
N/A
2.8224MHz
3.0720MHz
Table 1. System Clock Example (Manual Setting Mode, ACKS pin = “L”, Normal Speed Mode)
MCLK
1152fs
Mode
Normal
Normal
Double
Quad
Sampling Rate
8kHz~32kHz
8kHz~48kHz
32kHz~96kHz
120kHz~192kHz
512fs
256fs
128fs
768fs
384fs
192fs
Table 2. Sampling Speed (Auto Setting Mode, ACKS pin = “H”)
LRCK
fs
MCLK (MHz)
128fs
-
-
-
-
-
192fs
-
-
-
-
-
256fs
8.1920
11.2896
12.2880
22.5792
24.5760
-
384fs
12.2880
16.9344
18.4320
33.8688
36.8640
-
512fs
16.3840
22.5792
24.5760
768fs
24.5760 36.8640
33.8688
36.8640
1152fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
22.5792
24.5760
33.8688
36.8640
-
-
Table 3. System Clock Example (Auto Setting Mode, ACKS pin = “H”)
When MCLK= 256fs/384fs, the Auto Setting Mode supports sampling rate of 32kHz~96kHz (Table 2). When the
sampling rate is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK=
512fs/768fs.
ACKS pin
MCLK
256fs/384fs/512fs/768fs
256fs/384fs
DR,S/N
106dB
103dB
106dB
L
H
H
512fs/768fs
Table 4. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
MS1008-E-02
2010/09
- 8 -
[AK4388A]
■ Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-1 as shown in Table 5 can select four serial
data modes. The DIF1 pin is internal pull-up pin. In all modes the serial data is MSB-first, 2’s compliment format and is
latched on the rising edge of BICK.
Mode
0
DIF1 DIF0 SDTI Format
BICK
≥32fs
≥48fs
Figure
Figure 4
L
L
L
H
L
16bit LSB justified
24bit LSB justified
24bit MSB justified
16/24bit I2S Compatible
1
2
3
Figure 5
Figure 6
Figure 7
H
H
≥48fs
H
≥48fs or 32fs
Table 5. Audio Data Formats
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15 14
6
5
4
3
2
1
0
0
15 14
6
5
4
3
2
1
0
0
15 14
0
1
14
15
16
17
31
0
1
14
15
16
17
31
0
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15:MSB, 0:LSB
15 14
Don’t care
15 14
Lch Data
Rch Data
Figure 4. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
0
1
BICK
(64fs)
SDTI
Mode 1
23
22 21 20
23 22 21 20
Don’t care
19
0
Don’t care
19
0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 5. Mode 1 Timing
MS1008-E-02
2010/09
- 9 -
[AK4388A]
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDTI
Mode 2
23 22
23:MSB, 0:LSB
1
0
Don’t care
23 22
1
0
Don’t care
23 22
Lch Data
Rch Data
Figure 6. Mode 2 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
Mode 3
1
0
Don’t care
23 22
1
0
Don’t care
23
23 22
23:MSB, 0:LSB
Lch Data
Figure 7. Mode 3 Timing
Rch Data
■ De-emphasis Filter
A digital de-emphasis filter is built-in (tc = 50/15µs). The DEM pin is internal pull-down pin. The digital de-emphasis
filter is enabled by setting the DEM pin to “H”. Refer to “FILTER CHARACTERISTICS” regarding the gain error when
the de-emphasis filter is enabled. In case of double speed mode (MCLK=256fs/384fs) and quad speed mode
(MCLK=128fs/192fs), the digital de-emphasis filter is always off.
DEM pin
De-emphasis Filter
1
0
ON
(default)
OFF
Table 6. De-emphasis Filter Control (Normal Speed Mode)
MS1008-E-02
2010/09
- 10 -
[AK4388A]
■ Zero Detection
When the input data at both channels are continuously zeros for 8192 LRCK cycles, the DZF pin goes to “H”. The DZF
pin immediately returns to “L” if input data of both channels are not zero (Figure 8).
■ Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE pin goes to “H”, the output signal is attenuated by
-∞ in 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation
gradually changes to 0dB in 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles, the
attenuation is discontinued and returned to 0dB in the same cycle. The soft mute is effective for changing the signal
source without stopping the signal transmission.
SMUTE pin
1024/fs
(1)
1024/fs
0dB
(3)
Attenuation
-∞
GD
GD
(2)
AOUT
(4)
8192/fs
DZF pin
Notes:
(1) 1024LRCK cycles (1024/fs) at input data is attenuated to -∞.
(2) The analog output corresponding to the digital input has group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞, the attenuation is discontinued and returned to ATT level by
the same cycle.
(4) When the input data at both channels are continuously zeros for 8192 LRCK cycles, the DZF pin goes to “H”. The
DZF pin immediately returns to “L” if input data are not zero.
Figure 8. Soft Mute and Zero Detection
MS1008-E-02
2010/09
- 11 -
[AK4388A]
■ System Reset
The AK4388A must be reset once by bringing the RSTN pin = “L” upon power-up. The AK4388A is powered up and the
internal timing starts clocking by LRCK “↑” after exiting reset by MCLK. The AK4388A is in reset state until LRCK is
input.
■ Power ON/OFF timing
The AK4388A is placed in the power-down mode by bringing the RSTN pin “L” and the registers are initialized. The
analog outputs go to VCOM (VDD/2). Since click noise occurs at the edge of the RSTN signal, the analog output should
be muted externally if click noise aversely affects system application.
Power
RSTN pin
Internal
State
(2)
Normal Operation
Reset
DAC In
(Digital)
(2)
“0”data
“0”data
GD
(1)
GD
(3)
(3)
DAC Out
(Analog)
(5)
DZF
External
Mute
(4)
Mute ON
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are VCOM (VDD/2) in power-down mode.
(3) Click noise occurs at the edge of RSTN signal. This noise is output even if “0” data is input.
(4) Mute the analog output externally if the click noise (3) influences the system application.
The timing example is shown in this figure.
(5) DZF pins are “L” in the power-down mode (RSTB pin = “L”).
Figure 9. Power-down/up Sequence Example
MS1008-E-02
2010/09
- 12 -
[AK4388A]
■ Reset Function (MCLK, LRCK or BICK stop)
When the MCLK, LRCK or BICK stops, the digital circuit of the AK4388A is placed in power-down mode. When the
MCLK, LRCK and BICK are restarted, power-down mode is released and the AK4388A returns to normal operation
mode.
RSTN pin
Internal
Digital Circuit Power-down
Power-down
Power-down
Normal Operation
Normal Operation
State
D/A In
(Digital)
(2)
GD
GD
(1)
(1)
(4)
(3)
(3)
VCOM
D/A Out
(Analog)
(3)
(5)
<Case1:MCLK Stop>
Clock In
MCLK, BICK, LRCK
MCLK Stop
(5)
External
MUTE
<Case2:LRCK Stop>
Clock In
MCLK, BICK, LRCK
LRCK Stop
External
MUTE
(5)
(5)
(5)
<Case3:BICK Stop>
Clock In
MCLK, BICK, LRCK
BICK Stop
External
MUTE
(5)
(5)
(5)
Notes.
(1) The analog output corresponding to a specific digital input has group delay (GD).
(2) Digital data can be stopped. The click noise, after MCLK, LRCK and BICK are input again, can be reduced by
inputting the “0” data during this period.
(3) Click noise occurs within 20usec or 20usec +3 ~ 4LRCK from the riding edge (“↑”) of the RSTN pin or MCLK
inputs. Click noise also occurs within 20usec when MCLK, LRCK or BICK is stopped.
(4) The analog output becomes idle voltage when MCLK is stopped. It becomes VCOM voltage if LRCK or BICK is
stopped when MCLK is input.
(5) Mute the analog output externally if click noise (3) adversely affect system performance.
Figure 10. Clock Stop Sequence
MS1008-E-02
2010/09
- 13 -
[AK4388A]
SYSTEM DESIGN
Figure 11 shows the system connection diagram. An evaluation board (AKD4388A) is available for fast evaluation as
well as suggestions for peripheral circuitry.
Optional External
Mute Circuits
Master Clock
64fs
MCLK
BICK
SDTI
DZF
1
2
3
4
5
6
7
8
16
DEM 15
VDD 14
VSS 13
Analog
Supply 5V
24bit Audio Data
fs
+
10u
0.1u
LRCK
RSTN
SMUTE
ACKS
AK4388A
10u
+
Reset & Power down
VCOM 12
Lch Out
Rch Out
AOUTL
AOUTR
DIF1
11
10
9
Mode
Setting
DIF0
Digital Ground
Analog Ground
Figure 11. Typical Connection Diagram
Notes:
- LRCK = fs, BICK=64fs.
- When AOUT drives capacitive load, a resistor must be connected in series between AOUT and capacitive load.
- All input pins except DIF1 and DEM pins must not be left floating.
MS1008-E-02
2010/09
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[AK4388A]
1. Grounding and Power Supply Decoupling
VDD and VSS are supplied from analog supply and must be separated from system digital supply. Decoupling capacitor,
especially 0.1μF ceramic capacitor, for high frequency should be placed as near to VDD as possible. The differential
voltage between VDD and VSS pins set the analog output range.
2. Analog Outputs
The analog outputs are single-ended and centered on the VCOM voltage. The output signal range is typically 3.20Vpp
(typ@VDD=5V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the
delta-sigma modulator beyond the audio passband. The output voltage is a positive full scale for 7FFFFFH (@24bit) and
a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage for 000000H (@24bit).
The analog outputs have DC offsets of VCOM + a few mV. This DC offsets on analog outputs are eliminated by AC
coupling. Figure 12 shows an example of the external LPF with 3.20Vpp (1.13Vrms) output. Figure 13 shows an
example of the external LPF with 2Vrms output.
AK4388A
10u
220
Analog
Out
AOUT
3.2Vpp (1.13Vrms)
2.2nF
22k
fc=328.8kHz, g=-0.064dB at 40kHz
Figure 12. External 1st order LPF Circuit Example (simple)
390p
3.9k
3.9k
3.3k
+Vop
AK4388A
AOUT
Analog
Out
10u
2.7k
5.93Vpp (2.09Vrms)
-Vop
22k
390p
fc=125.8kHz, Q=0.752, g=0.058dB at 40kHz
Figure 13. External 2nd order LPF Circuit Example (using op-amp with dual power supplies)
MS1008-E-02
2010/09
- 15 -
[AK4388A]
PACKAGE
16pin TSSOP (Unit: mm)
1.1 (max)
*5.0±0.1
16
9
A
8
1
0.65
0.22±0.1
0.17±0.05
M
0.13
Detail A
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Epoxy
Cu
Lead frame surface treatment:
Solder (Pb free) plate
MS1008-E-02
2010/09
- 16 -
[AK4388A]
MARKING (AK4388AET)
AKM
4388AET
XXYYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
3) Marketing Code : 4388AET
4) Asahi Kasei Logo
REVISION HISTORY
Date (YY/MM/DD) Revision Reason
Page
10
Contents
08/09/19
08/10/17
00
01
First Edition
Description
Addition
■ De-emphasis Filter
“In case of double speed and quad speed mode,
the digital de-emphasis filter is always off.” was
added.
10/09/28
02
Specification
Change
16
PACKAGE
The package dimension was changed.
MS1008-E-02
2010/09
- 17 -
[AK4388A]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
MS1008-E-02
2010/09
- 18 -
相关型号：
AK4388KT
D/A Converter, 1 Func, Serial Input Loading, PDSO16, 6.40 X 5 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, TSSOP-16
AKM
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