AK4386VT-E2 [AKM]
D/A Converter, 24-Bit, 2 Func, PDSO16;
| 型号： | AK4386VT-E2 |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | D/A Converter, 24-Bit, 2 Func, PDSO16 光电二极管 转换器 |
| 文件： | 总16页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AK4386]
AK4386
100dB 96kHz 24-Bit 2ch DS DAC
GENERAL DESCRIPTION
The AK4386 is a 24bit low voltage & low power stereo DAC. The AK4386 uses the Advanced Multi-Bit DS
architecture, this architecture achieves DR=100dB at 3V operation. The AK4386 integrates a
combination of SCF and CTF filters increasing performance for systems with excessive clock jitter. The
AK4386 is suitable for the portable audio system like MP3 and the home audio systems like STB and TV,
etc as low power and small package. The AK4386 is offered in a space saving 16pin TSSOP package.
FEATURES
o Sampling Rate: 8kHz
o 24-Bit 8 times FIR Digital Filter
~
96kHz
o SCF with high tolerance to clock jitter
o Single-ended output buffer
o Digital de-emphasis for 44.1kHz sampling
o I/F Format: 24-Bit MSB justified, 16/24-Bit LSB justified, I2S Compatible
o Master Clock:
512/768/1024/1536fs for Half Speed (8kHz
256/384/512/768fs for Normal Speed (8kHz
128/192/256/384fs for Double Speed (48kHz
~
~
24kHz)
48kHz)
96kHz)
~
o CMOS Input Level
o THD+N: 86dB
-
o DR, S/N: 100dB(@VDD=3.0V)
o Power Supply: 2.2 to 3.6V
o Ta =
o 16pin TSSOP
-40 ~ 85°C
TEST
PDN
DEM
MCLK
VDD
VSS
Clock
Divider
De-emphasis
Control
DFS1
DFS0
VCOM
8X
DS
SCF
CTF
LOUT
ROUT
LRCK
BICK
SDTI
Audio
Data
Interface
Interpolator
Modulator
8X
DS
SCF
CTF
Interpolator
Modulator
DIF1
DIF0
MS0280-E-00
2003/12
- 1 -
ASAHI KASEI
[AK4386]
n Ordering Guide
AK4386VT
AKD4386
- 40 ~ +85°C
Evaluation Board for AK4386
16pin TSSOP (0.65mm pitch)
n Pin Layout
MCLK
TEST
DIF1
1
2
3
16
15
14
13
12
11
10
9
BICK
SDTI
LRCK
PDN
VDD
VSS
4
Top View
VCOM
LOUT
ROUT
DIF0
5
6
7
8
DFS0
DFS1
DEM
MS0280-E-00
2003/12
- 2 -
ASAHI KASEI
No. Pin Name
[AK4386]
PIN/FUNCTION
I/O Function
1
2
3
4
MCLK
BICK
SDTI
I
I
I
I
Master Clock Input Pin
Audio Serial Data Clock Pin
Audio Serial Data Input Pin
LRCK
Input Channel Clock Pin
Full Power Down Mode Pin
“L” : Power down, “H” : Power up
5
PDN
I
6
7
DFS0
DFS1
I
I
Sampling Speed Select 0 Pin
Sampling Speed Select 1 Pin
De-emphasis Filter Enable Pin
“L” : OFF, “H” : ON (De-emphasis of fs=44.1kHz is enable.)
Audio Interface Format 0 Pin
8
9
DEM
DIF0
I
I
10 ROUT
11 LOUT
O
O
Rch Analog Output Pin
Lch Analog Output Pin
Common Voltage Output Pin, 0.55 ´ VDD
12 VCOM
O
Normally connected to VSS with a 4.7mF (min. 1mF, max. 10mF) electrolytic
capacitor.
13 VSS
14 VDD
15 DIF1
-
-
I
Ground Pin
Power Supply Pin, 2.2 ~ 3.6V
Audio Interface Format 1 Pin
TEST Pin
16 TEST
I
This pin should be connected to VDD.
Note: All digital input pins should not be left floating.
n Handling of Unused Pin
The unused output pins should be processed appropriately as below.
Classification
Analog
Pin Name
LOUT, ROUT
Setting
This pin should be open.
MS0280-E-00
2003/12
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ASAHI KASEI
[AK4386]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Symbol
VDD
IIN
min
- 0.3
-
max
4.6
±10
Units
V
Power Supply
Input Current, Any Pin Except Supplies
Digital Input Voltage
mA
V
VIND
Ta
Tstg
- 0.3
- 40
- 65
VDD+0.3
85
Ambient Temperature (Powered applied)
Storage Temperature
°C
°C
150
Note 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Symbol
min
typ
max
Units
Power Supply
VDD
2.2
3.0
3.6
V
Note 1. All voltages with respect to ground.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0280-E-00
2003/12
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ASAHI KASEI
[AK4386]
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=3.0V; VSS=0V; fs=44.1kHz, 96kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data;
Measurement frequency=20Hz ~ 20kHz at fs=44.1kHz, 20Hz ~ 40kHz at fs=96kHz; unless otherwise specified)
Parameter
min
typ
max
Units
Dynamic Characteristics:
Resolution
THD+N
24
- 76
-
-
-
Bits
dB
dB
dB
dB
dB
dB
dB
0dBFS
- 60dBFS
0dBFS
fs=44.1kHz
BW=20kHz
fs=96kHz
- 86
- 37
- 84
- 34
100
100
100
- 60dBFS
BW=40kHz
DR
S/N
(- 60dBFS with A-weighted)
92
92
80
(A-weighted)
Interchannel Isolation
DC Accuracy:
Interchannel Gain Mismatch
Gain Drift
Output Voltage
Load Resistance
Load Capacitance
0.2
100
2.0
0.5
-
2.15
dB
ppm/°C
Vpp
kW
(Note 2)
(Note 3)
1.85
10
25
pF
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”, fs=44.1kHz)
Normal Operation (PDN pin = “H”, fs=96kHz)
Power Save mode (PDN pin = “H”, MCLK Stop)
Full Power-down mode (PDN pin = “L”)
6
9
mA
mA
mA
mA
6.5
1.5
10
10
2.5
50
(Note 4)
Note 2. Full-scale voltage (0dB). Output voltage scales with the voltage of VDD, Vout = 0.67 ´ VDD (typ).
Note 3. For AC-load.
Note 4. All digital input pins are fixed to VDD or VSS.
MS0280-E-00
2003/12
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ASAHI KASEI
[AK4386]
FILTER CHARACTERISTICS
(Ta=25°C; VDD=2.2 ~ 3.6V; fs=44.1kHz; DEM=OFF)
Parameter
Symbol
min
typ
max
Units
DAC Digital Filter:
Passband
(Note 5) ±0.05dB
- 6.0dB
PB
0
-
24.1
20.0
-
kHz
kHz
kHz
dB
dB
1/fs
22.05
Stopband
(Note 5)
SB
PR
SA
GD
Passband Ripple
Stopband Attenuation
Group Delay
±0.01
64
-
(Note 6)
(Note 7)
24.0
-
Digital Filter + SCF + CTF:
Frequency Response 0 ~ 20kHz
~ 40kHz
FR
-
-
±0.5
±1.0
-
-
dB
dB
Note 5. The passband and stopband frequencies scale with fs (system sampling rate).
Note 6. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data
of both channels to input register to the output of analog signal.
Note 7. At fs=96kHz.
DC CHARACTERISTICS
(Ta=25°C; VDD=2.2 ~ 3.6V)
Parameter
Symbol
min
typ
max
Units
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
VIH
VIL
Iin
70%VDD
-
-
-
-
V
V
-
-
30%VDD
±10
mA
MS0280-E-00
2003/12
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ASAHI KASEI
[AK4386]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=2.2 ~ 3.6V)
Parameter
Symbol
min
typ
max
Units
Master Clock Frequency
Half Speed Mode (512/768/1024/1536fs)
Normal Speed Mode (256/384/512/768fs)
Double Speed Mode (128/192/256/384fs)
Duty Cycle
fCLK
fCLK
fCLK
dCLK
4.096
2.048
6.144
40
36.864
36.864
36.864
60
MHz
MHz
MHz
%
LRCK Frequency
Half Speed Mode
(DFS1-0 = “10”)
fsh
fsn
8
8
24
48
96
55
kHz
kHz
kHz
%
Normal Speed Mode (DFS1-0 = “00”)
Double Speed Mode (DFS1-0 = “01”)
Duty Cycle
fsd
48
45
dCLK
Audio Interface Timing
BICK Period
Half Speed Mode
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
1/128fs
1/128fs
1/64fs
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
Normal Speed Mode
Double Speed Mode
BICK Pulse Width Low
Pulse Width High
70
BICK “• ” to LRCK Edge
LRCK Edge to BICK “• ”
SDTI Hold Time
(Note 8)
(Note 8)
40
tLRB
40
tSDH
tSDS
40
SDTI Setup Time
40
Power-Down & Reset Timing
PDN Pulse Width
(Note 9)
tPD
4 ´ C
ms
Note 8. BICK rising edge must not occur at the same time as LRCK edge.
Note 9. The AK4386 can be reset by bringing PDN pin = “L”.
The PDN pulse width is proportional to the value of the capacitor (C) connected to VCOM pin. tPD = 4 ´ C.
When C = 4.7mF, tPD is 19ms(min).
The value of the capacitor (C) connected with VCOM pin should be 1mF £ C £ 10mF.
When the states of DIF1-0 pins change, the AK4386 should be reset by PDN pin.
MS0280-E-00
2003/12
- 7 -
ASAHI KASEI
[AK4386]
n Timing Diagram
1/fCLK
VIH
VIL
MCLK
tCLKH
tCLKL
1/fs
VIH
VIL
LRCK
BICK
tBCK
VIH
VIL
tBCKH
tBCKL
Clock Timing
VIH
VIL
LRCK
tBLR
tLRB
VIH
VIL
BICK
SDTI
tSDS
tSDH
VIH
VIL
Audio Interface Timing
tPD
PDN
VIL
Power Down & Reset Timing
MS0280-E-00
2003/12
- 8 -
ASAHI KASEI
[AK4386]
OPERATION OVERVIEW
n System Clock
The external clocks, which are required to operate the AK4386, are MCLK, BICK and LRCK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta•sigma modulator. The MCLK frequency is detected from the relation between MCLK and LRCK
automatically. The Half speed, the Normal speed and the Double speed mode are selected with the DFS1-0 pins (Table 1).
The sampling speed mode is set depending on the MCLK frequency automatically for Auto mode (DFS1 pin = DFS0 pin
= “H”) (Table 2).
The AK4386 is automatically placed in the power save mode when MCLK stops in the normal operation mode (PDN pin
= “H”), and the analog output becomes the VCOM voltage. After MCLK is input again, the AK4386 is powered up. After
exiting reset at power-up etc., the AK4386 is in the power-down mode until MCLK and LRCK are input.
When the states of DIF1-0 pins change in the normal operation mode, the AK4386 should be reset by PDN pin.
Mode
Normal Speed
Double Speed
Half Speed
Auto
DFS1
L
L
H
H
DFS0
fs
MCLK Frequency
256/384/512/768fs
128/192/256/384fs
512/768/1024/1536fs
Table 2
L
H
L
8 ~ 48kHz
48 ~ 96kHz
8 ~ 24kHz
8 ~ 96kHz
H
Table 1. System Clock Example
MCLK Frequency
512/768fs
128/192/256/384fs
1024/1536fs
Sampling Speed Mode
Normal Speed
fs
8 ~ 48kHz
48 ~ 96kHz
8 ~ 24kHz
Double Speed
Half Speed
Table 2. Auto Mode
n Audio Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF1-0 pins as shown in Table 3 can select four
serial data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of
BICK. Mode 3 can be used for 16bit I2S Compatible format by zeroing the unused LSBs at BICK ³ 48fs or BICK = 32fs.
Mode
DIF1
L
L
H
H
DIF0
L
H
L
H
SDTI Format
16bit, LSB justified
24bit, LSB justified
24bit, MSB justified
16/24bit, I2S Compatible
BICK
³ 32fs
³ 48fs
Figure
0
1
2
3
Figure 1
Figure 2
Figure 3
Figure 4
³ 48fs
³ 48fs or 32fs
Table 3. Audio Interface Format
MS0280-E-00
2003/12
- 9 -
ASAHI KASEI
[AK4386]
LRCK
0
1
2
3
9 10 11 12 13 14 15 0
1
2
3
9 10 11 12 13 14 15 0 1
BICK(32fs)
SDTI(i)
15 14 13
7
6
5
4
3
2
1
0 15 14 13
7
6
5
4
3
2
1
0 15
0
1
2
3
17 18 19 20
31 0
1
2
3
17 18 19 20
31 0
1
BICK(64fs)
SDTI(i)
Don't Care 15 14 13 12
SDTI-15:MSB, 0:LSB
1
0
Don't Care 15 14 13 12
Rch Data
1
0
Lch Data
Figure 1. Mode 0 Timing
LRCK
0
1
2
8
9
24
31 0
1
2
8
9
24
31 0 1
BICK(64fs)
SDTI(i)
Don't Care 23
23:MSB, 0:LSB
8
1
0
Don't Care 23
8
1 0
Lch Data
Rch Data
Figure 2. Mode 1 Timing
LRCK
0
1
2
20 21 22 23 24
31 0
1
2
20 21 22 23 24
31 0 1
BICK(64fs)
SDTI(i)
23 22
4
3
2
1
0
Don't Care 23 22
4
3
2
1
0
Don't Care 23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
21 22 23 24 25
0
1
2
21 22 23 24 25
0
1
BICK(64fs)
SDTI(i)
23 22
4
3
2
1
0
Don't Care 23 22
4
3
2
1
0
Don't Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
MS0280-E-00
2003/12
- 10 -
ASAHI KASEI
[AK4386]
n De-emphasis Filter
The AK4386 includes the digital de-emphasis filter (tc=50/15ms) by IIR filter. This filter corresponds to 44.1kHz
sampling. The de-emphasis filter is enabled by setting DEM pin “H”. In case of Half speed and Double speed mode, the
digital de•emphasis filter is always off.
Mode
DFS1 pin DFS0 pin DEM pin
De-emphasis Filter
L
L
L
H
H
H
L
L
H
L
H
H
L
H
*
*
L
H
OFF
ON
OFF
OFF
OFF
Normal Speed
Double Speed
Half Speed
Auto
ON (Note)
Table 4. De-emephasis Filter (*: Don’t care)
Note. The digital de-emphasis filter corresponds to 44.1kHz sampling.
In case of Half speed and Double speed mode, the digital de•emphasis filter is always off.
n Power-down
The AK4386 is placed in the power-down mode by bringing PDN pin = “L”. and the digital filter is reset at the same time.
This reset should always be done after power up.
When PDN pin = “L”, DAC outputs go to Hi-Z. Also, the internal power down is automatically done when MCLK stops
during operating (PDN pin =“H”), and the analog outputs go to the VCOM voltage. MCLK pin should be fixed to “H” or
“L” when MCLK stops.
Mode
PDN pin
L
MCLK
Don’t care
Supplied
DAC Output
Hi-Z
Normal Output
VCOM Voltage
State
Full Power Down
Normal
0
1
2
H
Not Supplied
Power Save
Table 5. Power down mode
MS0280-E-00
2003/12
- 11 -
ASAHI KASEI
[AK4386]
(1) Power down by PDN pin
PDN
(1)
Internal
State
Normal Operation
Power-down
Normal Operation
D/A In
(Digital)
“0” data
GD
GD
(2)
(2)
(4)
(3)
(4)
D/A Out
(Analog)
Clock In
MCLK, BICK, LRCK
(5)
Don’t care
External
MUTE
(6)
Mute ON
Notes:
(1) PDN pin should be “L” for 19ms or more when an electrolytic capacitor 4.7mF is attached between VCOM pin and
VSS.)
(2) The analog output corresponding to digital input has the group delay (GD).
(3) When PDN pin = “L”, the analog output is Hi-Z.
(4) Click noise occurs in 3 ~ 4LRCK at both edges (• ¯) of PDN signal. This noise is output even if “0” data is input.
(5) The external clocks (MCLK, BICK and LRCK) can be stopped in the power down mode (PDN pin = “L”).
(6) Please mute the analog output externally if the click noise (4) influences system application. The timing example
is shown in this figure.
Figure 5. Power-down/up sequence example 1
MS0280-E-00
2003/12
- 12 -
ASAHI KASEI
[AK4386]
(2) Power save by MCLK stop (PDN pin = “H”)
(1)
PDN pin
Internal
State
Power-down
Power-down
Normal Operation
Power-save
Normal Operation
D/A In
(Digital)
(3)
GD
GD
(2)
(2)
(4)
(5)
(4)
Hi-Z
VCOM
D/A Out
(Analog)
(4)
(5)
Clock In
MCLK, BICK, LRCK
MCLK Stop
External
MUTE
(6)
(6)
Notes:
(1) PDN pin should be “L” for 19ms or more when an electrolytic capacitor 4.7mF is attached between VCOM pin and
VSS.)
(2) The analog output corresponding to digital input has the group delay (GD).
(3) The digital data can be stopped. The click noise after MCLK is input again by inputting the “0” data to this section
can be reduced.
(4) Click noise occurs in 3 ~ 4LRCK at both edges (• ¯) of PDN signal, MCLK inputs and MCLK stops. This noise is
output even if “0” data is input.
(5) The external clocks (BICK and LRCK) can be stopped in the power down mode (MCLK stop).
(6) Please mute the analog output externally if the click noise (4) influences system application. The timing example
is shown in this figure.
Figure 6. Power-down/up sequence example 2
MS0280-E-00
2003/12
- 13 -
ASAHI KASEI
[AK4386]
SYSTEM DESIGN
Figure 7 shows the system connection diagram. An evaluation board is available which demonstrates application circuits,
the optimum layout, power supply arrangements and measurement results.
Master Clock
64fs
1
2
3
4
5
6
7
8
MCLK
BICK
SDTI
TEST 16
DIF1 15
VDD 14
VSS 13
Analog Supply
2.2 to 3.6V
24bit Audio Data
fs
+
10u
0.1u
4.7u
LRCK
PDN
AK4386
+
Reset & Power down
VCOM 12
LOUT 11
ROUT 10
(C)
DFS0
DFS1
Lch Out
Rch Out
Mode
Setting
DIF0
DEM
9
Digital Ground
Analog Ground
Note:
- VSS of the AK4386 should be distributed separately from the ground of external digital devices (MPU, DSP etc.).
- When AOUT drive some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- The value of the capacitor connected to VCOM pin should be 1mF £ C £ 10mF.
- All digital input pins should not be left floating.
Figure 7. Typical Connection Diagram
1. Grounding and Power Supply Decoupling
The AK4386 requires careful attention to power supply and grounding arrangements. VDD is usually supplied from the
analog supply in the system. System analog ground and digital ground should be connected together near to where the
supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4386 as possible,
with the small value ceramic capacitor being the closest.
2. Voltage Reference
The differential Voltage between VDD and VSS sets the analog output range. VCOM is used as a common voltage of the
analog signal. VCOM pin is a signal ground of this chip. An electrolytic capacitor about 4.7mF should be attached
between VCOM pin and VSS. No load current may be drawn from VCOM pin. Especially, the ceramic capacitor should
be connected to this pin as near as possible.
3. Analog Outputs
The analog outputs are single-ended and centered around the VCOM voltage (0.55 ´ VDD). The output signal range is
typically 2.0Vpp (typ@VDD=3.0V). The internal switched-capacitor filter and continuous-time filter attenuate the noise
generated by the delta-sigma modulator beyond the audio passband. The output voltage is a positive full scale for
7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage (0.55 ´ VDD) for
000000H (@24bit).
DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV.
MS0280-E-00
2003/12
- 14 -
ASAHI KASEI
[AK4386]
PACKAGE
16pin TSSOP (Unit: mm)
5.0
1.10max
16
9
A
8
1
0.22 0.1
±
0.17 0.05
±
0.65
0.1 0.1
±
Detail A
Seating Plane
0.10
0 10
~
°
n Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0280-E-00
2003/12
- 15 -
ASAHI KASEI
[AK4386]
MARKING
AKM
4386VT
XXYYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
3) Marketing Code : 4386VT
IMPORTANT NOTICE
· These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
· AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
· Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
· AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
a. A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
b. A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
· It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for
and hold AKM harmless from any and all claims arising from the use of said product in the absence of
such notification.
MS0280-E-00
2003/12
- 16 -
相关型号：
AK4388KT
D/A Converter, 1 Func, Serial Input Loading, PDSO16, 6.40 X 5 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, TSSOP-16
AKM
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