HSDL7001 [AGILENT]
IR 3/16 Encode/Decode IC; IR 3/16编码/解码IC
| 型号： | HSDL7001 |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | IR 3/16 Encode/Decode IC |
| 文件： | 总8页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IR 3/16 Encode/Decode IC
Technical Data
HSDL-7001-2500 pc, tape
and reel
HSDL-7001#100-100pc,
50/tube
Features
• Compliant with IrDA 1.0
Physical Layer Specs
• Interfaces with IrDA 1.0
Compliant IR Transceivers
• Used in Conjunction with
Standard 16550 UART
• Transmits/Receives either
1.63 µs or 3/16 Pulse Mode
• Internal or External Clock
Modes
• Programmable Baud Rate
• 2.7-5.5 V Operation
Description
Schematic
The HSDL-7001 modulates and
demodulates electrical pulses
from Hewlett-Packard’s
TXD
IR_TXD
SIR
ENCODE
HSDL-1001 Infrared transceiver
module and other IrDA-compliant
transceivers. The HSDL-7001 can
be used with a microcontroller/
microprocessor that has a serial
communication interface (UART).
Prior to communication, the
processor selects the transmis-
sion baud rate. Serial data is then
transmitted or received at the
prescribed data rate.
/NRST
RCD
IR_RCV
SIR
DECODE
INT_CLOCK
A0
A1
CLOCK
DIVIDE
A2
• 16 Pin SOIC Package
16XCLK
The HSDL-7001 consists of two
state machines – the SIR (Serial
InfraRed) Encode and SIR Decode
blocks. It also contains a
sequential block Clock Divide
which synthesizes the required
internal signal.
Applications
• Interfaces with IR
Transceivers in:
- Computer Applications:
Notebook Computers
Sub-notebooks
Desktop PCs
PDAs
Printers
Dongle or other RS-232
adapter
- Telecom Applications:
Modems
Fax Machines
Pagers
PULSEMOD
CLK_SEL
Pin Out
The HSDL-7001 can be placed
into the Internal Clock Mode or
External Clock Mode. An external
crystal is needed for the Internal
Clock Mode. In applications
where the external 16XCLK
signal is provided, a crystal is not
needed.
1
16
15
14
13
12
11
10
9
V
16XCLK
CC
2
OSCIN
TXD
3
OSCOUT
POWERDN
PULSEMOD
IR_TXD
RCV
4
A0
5
A1
Phones
6
- Handheld Data Collection:
Industrial
Medical
A2
There are two data transmission
modes. Data can be transmitted
and received in either a standard
3/16 modulation mode or a
1.63 µs pulse mode.
7
IR_RCV
CLK_SEL
8
Transportation
NRST
GND
2
I/O Pinout List
Pin
Name
Type
Function
1
16XCLK
(SIXTNCK)
DIGIN
Positive edge triggered input clock that is set to 16 times the data
transmission baud rate. The encode and decode schemes require this
signal. The signal is usually tied to a UART’s BAUDOUT signal. The
16XCLK may be provided by application circuitry if BAUDOUT is not
available. This signal is required when the internal clock is not used.
2
3
/TXD
RCV
DIGIN
Negative edge triggered input signal that is normally tied to the SOUT
signal of the UART (serial data to be transmitted). Data is modulated
and output as IR_TXD.
DIGOUT Output signal normally tied to SIN signal of a UART (received serial
data). RCV is the demodulated output of IR_RVC.
4
5
6
7
A0
A1
A2
DIGIN
DIGIN
DIGIN
DIGIN
Clock Multiplex Signal
Clock Multiplex Signal
Clock Multiplex Signal
Used to activate either the Internal or External Clock. A high on this
line activates the External clock (16XCLK) and a low activates the
Internal clock. When the External clock is activated, the internal
oscillator is put in POWERDOWN MODE.
CLK_SEL
8
9
GND
/NRST
Chip Ground
DIGIN
DIGIN
Active low signal used to reset the IrDA-SIR ENCODE & DECODE
state machine. This signal can be tied to POR (Power On Reset) or V
Input from SIR optoelectronics. Input signal is a 3/16th or 1.6 µs pulse
.
CC
10
/IR_RCV
which is demodulated to generate RCV output signal.
11
12
IR_TXD
PULSEMOD
DIGOUT This is the modulated TXD signal.
DIGIN
(with
A high level on this input puts the chip into the monoshot transmit
mode. In this mode, when there is a negative transition on the TXD
pulldown) input, a rising edge on the internal transmit modulation state machine
will activate a high pulse on IR_TXD for 6 crystal clock cycles. With a
3.6864 MHz crystal, this corresponds to 1.63 µs. This mode cannot be
used in conjunction with the 16XCLK clock. It is meant to be used with
the external crystal clock. By default, this input pin is pulled to GND.
13
POWERDN
DIGIN
(with
A high on this input puts only the internal oscillator cell (OSCII) in
POWERDOWN MODE. The cell is normally not powered down.
pulldown)
14
15
16
OSCOUT
OSCIN
ANAOUT Oscillator Output
ANAIN
Oscillator Input
Power
V
CC
Note: There are two methods of putting the internal oscillator cell in POWERDOWN MODE. Whenever the CLKSEL Pin is asserted
high (External clock selected) the oscillator cell is automatically put in powerdown mode, or whenever the POWERDN Pin is asserted
high.
3
Table 1. Selection of Internal Clock Rate from Crystal Oscillator
Selected Clock Rate (bps)
A2
0
0
A1
0
0
A0
0
1
Crystal Freq. Division
Divided by 2
115200
57600
Divided by 4
19200
9600
38400
0
0
1
1
1
0
0
1
0
Divided by 12
Divided by 24
Divided by 6
4800
2400
TEST PURPOSE
1
1
1
0
1
1
1
0
1
Divided by 48
Divided by 96
No division
Package Dimensions
–A–
NOTES:
1. DIMENSIONS A AND B ARE DATUMS
AND T IS A DATUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
3. CONTROLLING DIMENSION: MILLIMETER.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
9
8
φ
P
0.25 (0.010) M B M
–B–
8 PL.
16
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
1
MILLIMETERS
INCHES
1
DIM. MIN.
MAX.
10.00
4.00
1.75
0.49
1.25
MIN.
MAX.
0.393
0.157
0.068
0.019
0.049
G
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
R X 45°
C
K
J
–T–
SEATING
PLANE
F
M
G
J
1.27 BSC
0.060 BSC
D
16 PL.
0.19
0.10
0°
0.25
0.25
7°
0.008
0.004
0°
0.009
0.009
7°
φ
0.25 (0.010) M
T B S A S
K
M
P
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
R
R
4
Encoding Scheme
16 CYCLES
16 CYCLES
16 CYCLES
16 CYCLES
16XCLK
TXD
7 CS
IRTXD
3 CS
The encoding scheme relies on a
clock being present, which is set
to 16 times the data transmission
baud rate (16XCLX). The encoder
sends a pulse for every space or
“0” that is sent on the TXD line.
On a high to low transition of the
TXD line, the generation of the
pulse is delayed for 7 clock cycles
of the 16XCLK before the pulse is
set high for 3 clock cycles (or
3/16th of a bit time) and then
subsequently pulled low. This
generates a 3/16th bit time pulse
centered around the bit of
information (“0”) that is being
transmitted.
For consecutive spaces, pulses
with a 1 bit time delay are gener-
ated in series. If a logic 1 (mark)
is sent then the encoder does not
generate a pulse.
Decoding Scheme
16 CYCLES
16 CYCLES
16 CYCLES
16 CYCLES
16XCLK
IRRXD
RXD
3 CS
arrival of a pulse. This pulse
needs to be stretched to
Note 1: The stretched pulse must
be at least 3/4 of a bit time in
duration to be correctly inter-
preted by a UART.
The IrDA-SIR (Serial InfraRed)
decoding modulation method can
be thought of as a pulse stretch-
ing scheme.
accommodate 1 bit time (or 16
16XCLK cycles). Every pulse that
is received is translated into a “0”
or space on the RXD line equal to
1 bit time.
Note 2: It is recommended that
TXD remains high when not
transmitting. This ensures the
LED is off and will not interfere
with signal reception.
Every high to low transition of
the IR_RXD line signifies the
5
Monoshot Operation
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CRYSTAL
CLK
INT CLK
(DIVBY2)
TXD
INTERNAL
IRTXD
OUTPUT
6 CRYSTAL CYCLES
IRTXD
(MONOSHOT)
The figure above illustrates the
With a 3.6864 MHz clock, this
corresponds to a pulse of 1.63 µs.
The duration of this pulse is
independent of the code A2,
A1,A0 and is always 6 clock
cycles of the crystal, corre-
sponding to the monoshot
operation.
operation of the monoshot when
the internal clock is set to divide
by 2 mode, i.e., when A2=0,
A1=0, and A0=0. A rising edge
on the internal modulation state
machine (IRTXD OUTPUT), will
cause the output on the IRTXD to
go up for 6 crystal clock cycles.
6
Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Output Current
Symbol
Min.
-65
-40
Max.
+150
+85
100
0.46
V + 0.5
CC
Units
°C
°C
mA
W
V
V
V
T
S
T
A
I
-100
O
[1]
Power Dissipation
Input/Output Voltage
P
MAX
[2]
V /V
-0.5
-0.5
I
O
Power Supply Voltage
Electrostatic Protection
V
7.0
4000
CC
V
ESD
Notes:
1. Maximum power dissipation is given for Rth = 140 C/W (SO 16 Plastic).
2. All pins are protected from damage to static discharge by internal diode clamps to
and GND.
V
CC
Switching Specifications
(V = 2.7 to 5.5 V, T = -20 to +85°C)
CC
A
Parameter
Propagation Delay Time
Symbol
Min. Typ.
Max. Units
Conditions
[1]
t
pd
80
11.6
24
ns
ns
[2]
Output Rise Time
t
rise
3.7
10
7.25
16
V
= 5.5 V, CL = 50 pF
= 2.7 V, CL = 50 pF
= 5.5 V, CL = 50 pF
= 2.7 V, CL = 50 pF
CC
V
CC
[3]
Output Fall Time
t
fall
4.4
11
8.35
16
11.2
26
ns
V
CC
V
CC
Output Capacitance on Output
Pads Used for Simulation
C
OUT
50
pF
Notes:
1. Propagation Delay Time in the output buffer is the time taken from the input passing V /2 to the time of the output reaching
CC
V
/2 with 50 pF as the output load.
CC
2. The Output Rise Time is the time taken for the outputs (RCV, IR_TXD) to rise from 10% of the original value to 90% of the final
value.
3. The Output Fall Time is the time taken for the outputs (RCV, IR_TXD) to fall from 90% of the original value to 10% of the final
value.
7
Recommended Operating Conditions
(V = 2.7 to 5.5 V, T = -20 to +85°C)
CC
A
Parameter
Symbol
Min.
2.7
0.0
Typ.
5
Max. Units Conditions
Supply Voltage
Input Voltage
V
5.5
V
V
CC
V
I
V
CC
Ambient Temperature
High Level Input Voltage
Low Level Input Voltage
Output High Voltage
T
-20
+85
V
CC
°C
V
V
A
V
0.7 V
IH
CC
V
0
2.2
0.3 V
IL
CC
V
OH
V
V
CC
= 2.7 V
ioh = 2 mA
V = 2.7 V
CC
iol = 2 mA
V = 5.5 V
CC
ioh = 2 mA
V = 5.5 V
CC
Output Low Voltage
V
0.5
V
V
V
OL
Output High Voltage
V
OH
4.5
Output Low Voltage
V
OL
0.5
iol = 2 mA
Static Power Dissipation
Dynamic Power Dissipation
Static Current Consumption
Dynamic Current Consumption
P
0.44
0.11
11
5.4
80
40
0.61
0.15
16.5
8.1
110
54
3
3
mW
mW
mW
mW
µA
µA
mA
mA
V
= 5.5 V
= 2.7 V
= 5.5 V
= 2.7 V
= 5.5 V
= 2.7 V
= 5.5 V
= 2.7 V
STAT
CC
V
CC
P
V
DYN
CC
V
CC
I
V
STAT
CC
V
CC
I
2
2
V
DYN
CC
V
CC
[1]
Max Clk Frequency (16XCLK)
Minimum Pulse Width (IR_TXD)
f
2
MHz
ns
ns
16XCLK
[2]
t
t
1630
1630
mpw
mpw
Pulse Width on Monoshot
(IR_TXD and IR_RCV)
Value of Pulldown Resistor Used on
POWERDOWN & PULSEMOD Input Pins
Trigger Low Level Input Voltage
(For /NRST Input Pin)
1710
152
1730
256
R
114
KΩ
V
DWN
VIL_TRIG
VIH_TRIG
0.7
1.9
1.7
0.8
1.95
1.85
3.4
0.9
2.00
1.9
3.60
V
= 2.7 V
= 5.5 V
= 2.7 V
= 5.5 V
CC
V
CC
Trigger High Level Input Voltage
(For /NRST Input Pin)
V
V
CC
3.25
V
CC
Notes:
1. IrDA Parameters. The Max Clk Frequency represents the maximum clock frequency to drive the HSDL-7001’s internal state
machine. Under normal circumstances, the clock input should not exceed 16* 115.2 Kbps or 1.8432 MHz. This product can
operate at higher clock rates, but the above is the recommended rate.
2. The Minimum Pulse Width (t
) represents the minimum pulse width of the encoded IR_TXD pulse (and the IR_RCV pulse). As
mpw
per the IrDA specifications, the minimum pulse width of the IR_TXD and IR_RCV pulses should be 3*(1/1.8432 MHz) or 1.63 µs.
Application Circuits
HSDL-7001 Connection to UART
HSDL-1001
TXD
HSDL-7001
UART 16550
IR_TXD
IR_RCV
TXD
RCV
SOUT
SIN
RCV
16XCLK
NRST
BAUDOUT
10 kΩ
V
CC
0.1 µF
HSDL-7001 Connected to Microcontroller
HSDL-1001
HSDL-7001
MICROCONTROLLER
TXD
RCV
IR_TXD
IR_RCV
TXD
RCV
SDO
SDI
A0
A1
A2
I01
I02
I03
I04
I05
I06
CLK_SEL
PULSEMOD
POWERDN
15 pF
OSCIN
F = 3.6864 MHz
10 MΩ
NRST
OSCOUT
10 kΩ
15 pF
V
CC
0.1 µF
NOTE: POWERDN CAN BE USED AS A BASIC CHIP SELECT.
THE HSDL-7001 WILL NOT BE ABLE TO RECEIVE OR TRANSMIT DATA WHILE POWERDN IS ASSERTED.
www.hp.com/go/ir
For technical assistance or the location of
your nearest Hewlett-Packard sales office,
distributor or representative call:
Americas/Canada: 1-800-235-0312 or
408-654-8675
Far East/Australasia: Call your local HP
sales office.
Japan: (81 3) 3335-8152
Europe: Call your local HP sales office.
Data subject to change.
Copyright © 1999 Hewlett-Packard Co.
Obsoletes 5965-5150E (11/96)
5968-7456E (8/99)
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