HSDL-3209-021 [AGILENT]
IrDA Data Compliant Low Power 115.2 kbit/s Infrared Transceiver; IrDA数据标准低功率115.2 kbit / s的红外收发器
| 型号： | HSDL-3209-021 |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | IrDA Data Compliant Low Power 115.2 kbit/s Infrared Transceiver |
| 文件： | 总16页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Agilent HSDL-3209
IrDA Data Compliant Low Power
115.2 kbit/s Infrared Transceiver
Specifications version 1.4 Low
Power from 9.6 kbit/s to 115.2
kbit/s with extended link
distance and it is IEC 825-
Class 1 eye safe.
Features
• Fully Compliant to IrDA 1.4 Low
Power Specification from 9.6
kbit/s to 115.2 kbit/s
Description
• Miniature Package
- Height : 1.60 mm
- Width : 7.00 mm
- Depth : 2.80 mm
The HSDL-3209 can be
The HSDL-3209 is an ultra-
small low cost infrared
transceiver module that
shutdown completely to
achieve very low power
consumption. In the shutdown
mode, the PIN diode will be
inactive and thus producing
very little photocurrent even
under very bright ambient
light. Such features are ideal
for battery operated handheld
products.
provides the interface between
logic and infrared (IR) signals
for through air, serial, half-
duplex IR data link. It is
designed to interface to input/
output logic circuits as low as
1.5V. The module is compliant
to IrDA Physical Layer
• Guaranteed Temperature
Performance, -25 to +70 °C
- Critical parameters are
guaranteed over temperature &
supply voltage
• Low Power Consumption
- Complete shutdown of TXD,
RXD, and PIN diode
Functional Block Diagram
• Vcc Supply 2.4 to 3.6 Volts
Vcc
• Interface to Input/Output Logic
CX2
CX1
Circuits as Low as 1.5V
• LED Stuck-High Protection
Vcc (6)
GND (7)
• Designed to Accommodate Light
Loss with Cosmetic Windows
• IEC 825-Class 1 Eye Safe
SD (4)
Receiver
Applications
RXD (2)
• Mobile Telecom
- Mobile Phones
- Pagers
IOVcc (5)
- Smart Phone
IOVcc
Vled
HSDL-3209
• Data Communication
- PDAs
CX4
R1
- Portable Printers
TXD (3)
Transmitter
• Digital Imaging
- Digital Cameras
- Photo-Imaging Printers
LEDA (1)
• Electronic Wallet
CX3
Figure 1. Functional Block Diagram
Order Information
Part Number
Packaging Type
Package
Quantity
HSDL-3209-021
Tape and Reel
Front View
2500
I/O Pins Configuration Table
Pin
Symbol Description
I/O Type
Function
1
LED A
LED Anode
Input
Tied through external resistor, R1, to VLED from 2.4V to 4.5V.
Please refer to Table 1 for VLED versus Series Resistor, R1.
2
RXD
Receive Data
Output,
Active Low
This pin is capable of driving a standard CMOS or TTL load.
No external pull-up or pull down resistor is required. It is in
tri-state mode when the transceiver is in shutdown mode.
3
4
5
TXD
SD
Transmit Data
Shutdown
Input,
Active High
This pin is used to transmit serial data when SD pin is low.
If held high longer than ~ 50µs, the LED will be turned off.
The transceiver is in shutdown mode if this pin is high
Input,
Active High
IOVcc
Input/Output
ASIC Vcc
Input/Output
Active High
Connect to ASIC logic controller Vcc Voltage as low as 1.5V.
6
7
Vcc
Supply Voltage Supply Voltage
Ground Ground
Regulated, 2.4 to 3.6 Volts.
Connect to system ground.
GND
Recommended Application Circuit Components
Component
Recommended Value
Note
R1
15Ω 5%, 0.0625 Watt for 2.4 ≤ Vled ≤ 2.7V
27Ω 5%, 0.0625 Watt for 2.7 < Vled ≤ 3.6V
36Ω 5%, 0.0625 Watt for 3.6 < Vled ≤ 4.5V
CX1, CX4
CX2, CX3
Notes:
0.47 µF 20%, X7R Ceramic
6.8 µF 20%, X7R Ceramic or Tantalum
1
1
1. CX1, CX2, CX3 and CX4 must be placed within 0.7 cm of the HSDL-3209 to obtain optimum noise immunity.
CAUTIONS: The CMOS inherent to the design of this component increases the component’s
susceptibility to damage from the electrostatic discharge (ESD). It is advised that normal
static precautions be taken in handling and assembly of this component to prevent
damage and/or degradation which may be induced by ESD
2
Absolute Maximum Ratings
For implementations where case to ambient thermal resistance is ≤ 50°C/W.
Parameter
Symbol
TS
Min.
-40
-25
0
Max.
+100
85
Units
°C
°C
V
Notes
Storage Temperature
Operating Temperature
LED Anode Voltage
Supply Voltage
TA
VLEDA
VCC
6.5
0
6.5
V
Input/Output Voltage
Input Voltage : SD
Input Voltage : TXD
DC LED Transmit Current
Peak LED Transmit Current
IOVCC
VI(SD)
0
VCC
V
0
IOVCC
IOVCC
50
V
VI(TXD)
ILED (DC)
ILED (PK)
0
V
mA
mA
250
2
Notes:
2. ≤ 20% duty cycle, ≤ 90 ms pulse width.
Recommended Operating Conditions
Parameter
Symbol Min.
Typ. Max.
70
Units
Conditions
Operating Temperature
Supply Voltage
TA
-25
°C
V
VCC
IOVCC
VIH
2.4
3.6
Input/Output Voltage
1.5
VCC
V
Logic Input Voltage for
TXD/SD
Logic High
Logic Low
IOVcc-0.2
IOVcc
V
The minimum input logic
voltage should not be
lower than 1.5V
VIL
0
0.4
V
Receiver Input Irradiance Logic High
EIH
0.0081
500
mW/cm2
For in-band signals
≤ 115.2kbit/s
[3]
[3]
µW/cm2
Logic Low
EIL
1.0
For in-band signals
LED (Logic High)
ILEDA
50
mA
Current Pulse Amplitude
Receiver Data Rate
9.6
115.2
kbit/s
Ambient Light
See IrDA Serial Infrared Physical Layer Link Specification, Appendix A for ambient levels
Notes:
3. An in-band optical signal is a pulse/sequence where the peak wavelength, λp, is defined as 850 ≤ λp ≤ 900 nm, and the pulse characteristics are
compliant with the IrDA Serial Infrared Physical Layer Link Specification v1.4.
3
Electrical & Optical Specifications
Specifications (Min. & Max. values) hold over the recommended operating conditions unless otherwise noted.
Unspecified test conditions may be anywhere in their operating range. All typical values (Typ.) are at 25°C with Vcc set to
3.0V and IOVcc set to 1.8V unless otherwise noted.
Parameter
Receiver
Symbol
Min.
Typ.
Max.
Units
Conditions
Viewing Angle
2θ
½
30
°
Peak Sensitivity Wavelength
RXD Output Voltage
880
nm
λp
Logic High
Logic Low
VOH
IOVcc-0.2
IOVcc
0.4
V
IOH = -200 µA,
EI ≤ 1.0 µW/cm2
VOL
0
1
V
IOL = 200 µA,
EI ≥ 8.1 µW/cm2
[4]
RXD Pulse Width (SIR)
tPW (SIR)
4.0
µs
ns
µs
µs
θ ≤ 15°, CL =9 pF
½
RXD Rise and Fall Times
tr, tf
tL
60
50
CL =9 pF
[5]
Receiver Latency Time
Receiver Wake Up Time [6]
tW
100
Transmitter
Radiant Intensity
IEH
4
14
mW/sr ILEDA= 50 mA,
θ ≤ 15°, VTXD ≥ VIH
½
TA=25 °C, IOVcc = 1.8V
Viewing Angle
2θ
30
60
10
°
½
Peak Wavelength
875
35
nm
λp
∆λ½
IH
Spectral Line Half Width
TXD Input Current
nm
High
Low
0.02
VI ≥ VIH
µA
IL
-10
1.4
-0.02 10
50
0 ≤ VI ≤ VIL
µA
mA
nA
µs
LED Current
On
IVLED
VI(TXD) ≥ VIH
VI(SD) ≥ VIH
tPW (TXD) = 1.6 µs at
115.2 kbit/s
Shutdown
IVLED
200
1.8
Optical Pulse Width (SIR)
tPW (SIR)
1.6
[7]
Maximum Optical PW
tPW(max.)
100
µs
ns
V
TXD Rise and fall Time (Optical)
LED Anode On State Voltage
tr, tf
600
1.8
tpw(TXD) = 1.6 µs
ILEDA=50mA,
VI(TXD) ≥ VIH
VON(LEDA)
1.55
Transceiver
[8]
Supply Current
Shutdown
Idle
ICC1
ICC2
1
VSD ≥ VIH, TA=25°C
VI(TXD) ≤ VIL, EI = 0
µA
µA
100
Notes:
2
2
4. For in-band signals from 9.6kbit/s to 115.2 kbit/s, where 9µW/cm ≤ EI ≤ 500mW/cm .
5. Latency time is defined as the time from the last TxD light output pulse until the receiver has recovered full sensitivity
6. Receiver wake up time is measured from Vcc power on or SD pin high to low transition to a valid RXD output.
7. The maximum optical PW is the maximum time the LED remains on when the TXD is constantly high. This is to prevent long turn on time of the LED
for eye safety protection.
8. For V > 3V and IOV < 1.8V, I can exceed 15uA.
cc
cc
CC1
4
tpw
tpw
VOH
90%
50%
10%
LED ON
LED OFF
90%
50%
10%
VOL
tf
tr
tr
tf
Figure 2. RXD output waveform.
Figure 3. LED optical waveform.
SD
TXD
RX
LIGHT
LED
RXD
tpw (MAX.)
tRW
Figure 4. TXD “stuck on” protection waveform.
Figure 5. Receiver wakeup time waveform.
SD
TXD
TX
LIGHT
tTW
Figure 6. TXD wakeup time waveform.
Average VLED_A vs Average ILED
Average LOP vs Average ILED
1.75
1.70
1.65
1.60
35
30
25
20
15
1.55
1.50
1.45
1.40
10
5
0
10.0E-3
30.0E-3
50.0E-3
70.0E-3
90.0E-3
110.0E-3
10.0E-3
30.0E-3
50.0E-3
70.0E-3
90.0E-3
110.0E-3
Average ILED (A)
Average ILED (A)
Figure 8. V
vs. I
LED
LOP
Figure 7. V vs. I
LED
LED
5
HSDL-3209 Package Outline with Mechanical Dimensions
Mounting Centre
3.50
7.00
5.10
0.95
0.95
R1.10
R1.10
PCB solder
pad length
PCB
GND
Vcc
LEDA RXD
SD
IOVcc
TXD
0.60 0.05 (7x)
0.95 0.05 (6x)
Notes :
1. ALL DIMENSIONS IN MILLIMETERS (mm).
2. DIMENSION TOLERANCE IS 0.2mm UNLESS OTHERWISE SPECIFIED.
6
HSDL-3209 Tape and Reel Dimensions
4.0 0.1
2.0 0.1
Unit: mm
1.75 0.1
+0.1
0
1.5
POLARITY
Pin 7: GND
7.5 0.1
16.0 0.2
Pin 1: LEDA
0.3 0.05
7.35 0.1
2.93 0.1
1.78 0.1
4.0 0.1
Progressive Direction
Empty
Parts Mounted
Leader
(400mm min)
(40mm min)
Empty
(40mm min)
Option #
021
"B" "C" Quantity
330
2500
80
Unit: mm
Detail A
2.0 0.5
13.0 0.5
B
C
R1.0
LABEL
21 0.8
Detail A
+2
16.4
0
2.0 0.5
7
Moisture Proof Packaging
Baking Conditions:
All HSDL-3209 options are
shipped in moisture proof
package. Once opened,
moisture absorption begins.
This part is compliant to
JEDEC Level 4.
If the parts are not stored in
dry conditions, they must be
baked before reflow to prevent
damage to the parts.
Baking should only be done
once.
Package Temperature
Time
Units in A Sealed
Mositure-Proof
Package
In Reel
In Bulk
60°C
100°C
125°C
150°C
≥ 48 hours
≥ 4 hours
≥ 2 hours
≥ 1 hours
Package Is
Opened (Unsealed)
Recommended Storage Conditions:
Time from unsealing to soldering:
Environment
less than 30 deg C, and
less than 60% RH ?
After removal from the bag,
the parts should be soldered
within 72 hours if stored at
the recommended storage
conditions. If times longer than
72 hours are needed, the parts
must be stored in a dry box.
Yes
Package Is
Opened less
Yes
No Baking
Is Necessary
than 72 hours ?
Storage
10°C to 30°C
Temperature
No
Relative Humidity
below 60% RH
No
Perform Recommended
Baking Conditions
8
Recommended Reflow Profile
MAX 260C
255
R3
R4
230
220
200
R2
180
60 sec
MAX
Above 220 C
160
R5
R1
120
80
25
0
100
P2
SOLDER PASTE DRY
150
200
250
300
50
P1
HEAT
UP
P3
t-TIME
(SECONDS)
P4
COOL DOWN
SOLDER
REFLOW
Process Zone
Symbol
P1, R1
P2, R2
DT
Maximum ∆T/∆time
4°C/s
Heat Up
25°C to 160°C
160°C to 200°C
Solder Paste Dry
Solder Reflow
0.5°C/s
P3, R3
P3, R4
200°C to 255°C (260°C at 10 seconds max)
255°C to 200°C
4°C/s
-6°C/s
Cool Down
P4, R5
200°C to 25°C
-6°C/s
The reflow profile is a
Process zone P2 should be of
sufficient time duration (60 to
120 seconds) to dry the solder
paste. The temperature is
raised to a level just below the reduced to a point below the
liquidus point of the solder,
usually 200°C (392°F).
excessive, resulting in the
formation of weak and
unreliable connections. The
temperature is then rapidly
straight-line representation of
a nominal temperature profile
for a convective reflow solder
process. The temperature
profile is divided into four
process zones, each with
different DT/Dtime
temperature change rates. The
DT/Dtime rates are detailed in
the above table. The
solidus temperature of the
solder, usually 200°C (392°F),
to allow the solder within the
connections to freeze solid.
Process zone P3 is the solder
reflow zone. In zone P3, the
temperature is quickly raised
above the liquidus point of
solder to 255°C (491°F) for
optimum results. The dwell
time above the liquidus point
Process zone P4 is the cool
down after solder freeze. The
cool down rate, R5, from the
liquidus point of the solder to
25°C (77°F) should not exceed
temperatures are measured at
the component to printed
circuit board connections.
In process zone P1, the PC
board and HSDL-3209
of solder should be between 20 6°C per second maximum. This
and 60 seconds. It usually
takes about 20 seconds to
limitation is necessary to allow
the PC board and HSDL-3209
castellation pins are heated to
a temperature of 160°C to
activate the flux in the solder
paste. The temperature ramp
up rate, R1, is limited to 4°C
per second to allow for even
heating of both the PC board
and HSDL-3209 castellations.
assure proper coalescing of the castellations to change
solder balls into liquid solder
and the formation of good
solder connections. Beyond a
dwell time of 60 seconds, the
intermetallic growth within the
solder connections becomes
dimensions evenly, putting
minimal stresses on the HSDL-
3209 transceiver.
9
Appendix A: SMT Assembly Application Note
1.0 Solder Pad, Mask and Metal Stencil Aperture
METAL STENCIL
FOR SOLDER
PASTE PRINTING
STENCIL
APERTURE
SOLDER
MASK
PCBA
Stencil and PCBA
1.1 Recommended Land Pattern
C
L
Mounting
Center
0.10
1.75
0.775
fiducial
0.60
0.95
1.9
Unit: mm
2.85
10
1.2 Recommended Metal Solder
Stencil Aperture
Apertures as
per land
Dimensions
It is recommended that only a
0.152 mm (0.006 inches) or a
0.127 mm (0.005 inches) thick
stencil be used for solder
paste printing. This is to
ensure adequate printed solder
paste volume and no shorting.
See the table below the
t
w
drawing for combinations of
metal stencil aperture and
metal stencil thickness that
should be used.
l
Aperture size (mm)
Stencil Thickness, t (mm)
0.152 mm
Length, l (mm)
2.60 0.05
Width, w (mm)
0.55 0.05
Aperture opening for shield
pad is 2.7 mm x 1.25 mm as
per land pattern.
0.127 mm
3.00 0.05
0.55 0.05
1.3 Adjacent Land Keepout and
Solder Mask Areas
7.2
Adjacent land keep-out is the
maximum space occupied by
the unit relative to the land
pattern. There should be no
other SMD components within
this area. The minimum solder
resist strip width required to
avoid solder bridging adjacent
pads is 0.2 mm. It is
0.2
2.6
3.0
Solder mask
recommended that two fiducial
crosses be place at midlength
of the pads for unit alignment.
Units: mm
Note: Wet/Liquid Photo-
Imageable solder resist/mask is
recommended.
11
Appendix B: PCB Layout Suggestion
The HSDL 3209 is a shieldless
part and hence does not
contain a shield trace unlike
the other transceivers. The
following PCB layout
guidelines should be followed
to obtain a good PSRR and EM
immunity resulting in good
electrical performance. Things
to note:
Top layer
Connect the metal shield & module
ground pin to bottom ground layer
Layer 2
Critical ground plane zone. Do not connect
directly to the module ground pin
Layer 3
Keep data bus away from critical ground
plane zone
1. The ground plane should be
continuous under the part.
Bottom layer
(GND)
2. VLED can be connected to
either unfiltered or
unregulated power supply. If
VLED and Vcc share the
same power supply, CX3
need not be used and the
connections for CX1 and
CX2 should be before the
current limiting resistor R1.
CX1 is generally a ceramic
capacitor of low inductance
providing a wide frequency
response while CX2 and
CX3 are tantalum capacitors
of big volume and fast
The area underneath the
module at the second layer,
and 3cm in all direction
around the module is defined
as the critical ground plane
zone. The ground plane should
be maximized in this zone.
Refer to application note
AN1114 or the Agilent IrDA
Data Link Design Guide for
details. The layout below is
based on a 2-layer PCB.
frequency response. The use
of a tantalum capacitor is
more critical on the VLED
line, which carries a high
current. CX4 is an optional
ceramic capacitor, similar to
CX1, for the IOVcc line.
3. Preferably a multi-layered
board should be used to
provide sufficient ground
plane. Use the layer
Bottom View
Top View
underneath and near the
transceiver module as Vcc,
and sandwich that layer
between ground connected
board layers. Refer to the
diagram below for an
example of a 4 layer board,
12
Appendix C: General Application
Guide for the HSDL-3209
Speaker
Audio
DSP
Core
Interface
Description The HSDL-3209, a
low-cost and ultra-small form
factor infrared transceiver, is
designed to address the mobile
computing market such as
PDAs, as well as small
embedded mobile products
such as digital cameras and
cellular phones. It is fully
compliant to IrDA 1.4 low
power specification from 9.6
kb/s to 115.2 kb/s, and
Microphone
ASIC
Controller
RF
Interface
Transceiver
Mod /De-
Modulator
IR
Microcontroller
User
Interface
HSDL-3209
supports HP-SIR and TV
Mobile Phone Platform
Remotes modes. The design of
the HSDL-3209 also includes
the following unique features:
Figure 9. Mobile phone platform
LCD
Panel
- Low passive component
count.
- Shutdown mode for low
power consumption
requirement.
RAM
IR
CPU for embedded
application
HSDL-3209
Selection of Resistor R1
Resistor R1 should be selected
to provide the appropriate
peak pulse LED current over
different ranges of Vcc as
shown on page 2 under
“Recommended Application
Circuit Components”.
ROM
Touch
Panel
PCMCIA
Controller
RS232C
Driver
COM
Port
PDA Platform
Interface to Recommended I/O
chips The HSDL-3209’s TXD
data input is buffered to allow
for CMOS drive levels. No
peaking circuit or capacitor is
required. Data rate from 9.6
kb/s up to 115.2 kb/s is
Figure 10. PDA platform
available at the RXD pin.
Figure 10 shows how the IrDA
port fits into a mobile phone
and PDA platform.
The link distance testing was
done using typical HSDL-3209
units with SMC’s FDC37C669
and FDC37N769 Super I/O
controllers. An IrDA link
distance of up to 50 cm was
demonstrated.
13
IR Transparent Window
Appendix D: Window Designs for
HSDL-3209
OPAQUE MATERIAL
Optical Port Dimensions for HSDL-
3209
To ensure IrDA compliance,
some constraints on the height
and width of the window exist.
The minimum dimensions
ensure that the IrDA cone
angles are met without
vignetting. The maximum
dimensions minimize the
effects of stray light. The
minimum size corresponds to a
cone angle of 30° and the
maximum size corresponds to
a cone angle of 60°.
Y
IR Transparent Window
OPAQUE MATERIAL
X
K
Z
A
In the figure above, X is the
width of the window, Y is the
height of the window and Z is
the distance from the HSDL-
3208 to the back of the
D
window. The distance from the
center of the LED lens to the
center of the photodiode lens,
K, is 5.1mm. The equations for The depth of the LED image
is 15° and the maximum is
computing the window
dimensions are as follows:
inside the HSDL-3208, D, is
3.17mm. ‘A’ is the required
half angle for viewing. For
30°. Assuming the thickness of
the window to be negligible,
the equations result in the
X = K + 2*(Z+D)*tanA
Y = 2*(Z+D)*tanA
IrDA compliance, the minimum following tables and graphs:
Module Depth
(z) mm
Aperture Width (x, mm)
Aperture height (y, mm)
The above equations assume
that the thickness of the
Max
8.76
min
6.80
Max
3.66
Min
1.70
2.33
2.77
3.31
3.84
4.38
4.91
5.45
5.99
6.52
window is negligible compared
to the distance of the module
from the back of the window
(Z). If they are comparable, Z’
replaces Z in the above
0
1
2
3
4
5
6
7
8
9
9.92
7.33
4.82
11.07
12.22
13.38
14.53
15.69
16.84
18.00
19.15
7.87
5.97
8.41
7.12
equation. Z’ is defined as
8.94
8.28
Z’=Z+t/n
9.48
9.43
where ‘t’ is the thickness of
the window and ‘n’ is the
refractive index of the window
material.
10.01
10.55
11.09
11.62
10.59
11.74
12.90
14.05
Aperture Width (X) vs Module Depth
25
20
15
10
5
Xmax
Xmin
0
0
1
2
3
4
5
6
7
8
9
Module Depth (z) mm
Aperture Height(Y) vs Module Depth
16
14
12
10
8
6
4
Ymax
Ymin
2
0
0
1
2
3
4
5
6
7
8
9
Module Depth (z) mm
Window Material
The recommended plastic
materials for use as a cosmetic
window are available from
General Electric Plastics.
Almost any plastic material
will work as a window
material. Polycarbonate is
recommended. The surface
finish of the plastic should be
smooth, without any texture.
An IR filter dye may be used
in the window to make it look
black to the eye, but the total
optical loss of the window
should be 10% or less for best
optical performance. Light loss
should be measured at 875
nm.
Recommended Plastic Materials:
Material #
Lexan 141
Light Transmission
Haze
1%
Refractive Index
1.586
88%
85%
85%
Lexan 920A
Lexan 940A
1%
1.586
1%
1.586
Note: 920A and 940A are more flame retardant than 141.
Recommended Dye: Violet #21051 (IR transmissant above 625 nm)
Shape of the Window
While this will not completely
eliminate the lens effect of the
front curved surface, it will
The following drawings show
the effects of a curved window
on the radiation pattern. In
From an optics standpoint, the
window should be flat. This
ensures that the window will
not alter either the radiation
pattern of the LED, or the
receive pattern of the
significantly reduce the effects. all cases, the center thickness
The amount of change in the
radiation pattern is dependent
upon the material chosen for
the window, the radius of the
of the window is 1.5 mm, the
window is made of
polycarbonate plastic, and the
distance from the transceiver
photodiode.
front and back curves, and the to the back surface of the
If the window must be curved
for mechanical or industrial
distance from the back surface
to the transceiver. Once these
window is 3 mm.
design reasons, place the same items are known, a lens design
curve on the back side of the
window that has an identical
radius as the front side.
can be made which will
eliminate the effect of the
front surface curve.
Flat Window
Curved Front and Back
Curved Front, Flat Back
(First choice)
(Second choice)
(Do not use)
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semiconductors
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Data subject to change.
Copyright © 2004 Agilent Technologies, Inc.
August 19, 2004
5989-1520EN
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