HCPL-5301 [AGILENT]
Intelligent Power Module and Gate Drive Interface Optocouplers; 智能功率模块和门驱动接口光电耦合器
| 型号： | HCPL-5301 |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | Intelligent Power Module and Gate Drive Interface Optocouplers |
| 文件： | 总15页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
H
Intelligent Power Module and
Gate Drive Interface Optocouplers
HCPL-4506
HCPL-0466
HCNW4506
Technical Data
Features
Applications
• IPM Isolation
• Isolated IGBT/MOSFET Gate
Drive
• AC and Brushless DC Motor
Drives
gation delay difference between
devices make these optocouplers
excellent solutions for improving
inverter efficiency through
• Performance Specified for
Common IPM Applications
over Industrial Temperature
Range: -40°C to 100°C
• Fast Maximum Propagation
Delays
reduced switching dead time.
An on chip 20 kΩ output pull-up
resistor can be enabled by short-
ing output pins 6 and 7, thus
eliminating the need for an
external pull-up resistor in
common IPM applications. Speci-
fications and performance plots
are given for typical IPM
• Industrial Inverters
tPHL = 400 ns
t
PLH = 550 ns
Description
• Minimized Pulse Width
Distortion (PWD = 450 ns)
• 15 kV/µs Minimum Common
Mode Transient Immunity at
The HCPL-4506 and HCPL-0466
contain a GaAsP LED while the
HCNW4506 contains an AlGaAs
LED. The LED is optically
coupled to an integrated high gain
photo detector. Minimized propa-
VCM = 1500 V
applications.
• CTR > 44% at IF = 10 mA
• Safety Approval
UL Recognized - 2500 V rms
for 1 minute (5000 V rms for
1 minute for HCNW4506 and
HCPL-4506 Option 020) per
UL1577
Functional Diagram
Truth Table
LED
ON
VO
L
NC
1
2
8
7
V
V
CC
20 kΩ
CSA Approved
OFF
H
ANODE
L
VDE 0884 Approved
-VIORM = 630 V peak for
HCPL-4506 Option 060
-VIORM = 1414 V peak for
HCNW4506
3
4
6
5
CATHODE
NC
V
O
GND
SHIELD
BSI Certified (HCNW4506)
Selection Guide
Operating Temperature
TA [°C]
Single Channel Packages
8-Pin DIP
(300 Mil)
Small Outline
SO-8
Widebody
(400 Mil)
Min.
-40
Max.
100
Hermetic*
HCPL-4506
HCPL-0466
HCNW4506
-55
125
HCPL-5300
HCPL-5301
*Technical data for these products are on separate HP publications.
The connection of a 0.1 µF bypass capacitor between pins 5 and 8 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
1-49
5965-3603E
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-4506#XXX
020 = UL 5000 V rms/1 Minute Option*
060 = VDE 0884 VIORM = 630 V peak Option*
300 = Gull Wing Surface Mount Option†
500 = Tape and Reel Packaging Option
*For HCPL-4506 only. Combination of Option 020 and
Option 060 is not available.
†Gull wing surface mount option applies to through
hole parts only.
Option data sheets are available. Contact your Hewlett-Packard sales representative or authorized
distributor for information.
Package Outline Drawings
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
TYPE NUMBER
OPTION CODE*
DATE CODE
HP XXXXZ
YYWW
U R
4
UL
1
2
3
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
0.254
5° TYP.
- 0.051
+ 0.003)
- 0.002)
(0.010
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
0.65 (0.025) MAX.
1.080 ± 0.320
(0.043 ± 0.013)
* MARKING CODE LETTER FOR OPTION NUMBERS.
"L" = OPTION 020
"V" = OPTION 060
2.54 ± 0.25
(0.100 ± 0.010)
OPTION NUMBERS 300 AND 500 NOT MARKED.
Figure 1. HCPL-4506 Outline Drawing (Standard DIP Package).
PAD LOCATION (FOR REFERENCE ONLY)
9.65 ± 0.25
(0.380 ± 0.010)
1.016 (0.040)
1.194 (0.047)
8
7
6
5
4.826
(0.190)
TYP.
6.350 ± 0.25
(0.250 ± 0.010)
9.398 (0.370)
9.906 (0.390)
1
3
2
4
0.381 (0.015)
0.635 (0.025)
1.194 (0.047)
1.778 (0.070)
1.780
(0.070)
MAX.
9.65 ± 0.25
(0.380 ± 0.010)
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
+ 0.076
4.19
(0.165)
0.254
MAX.
- 0.051
+ 0.003)
- 0.002)
(0.010
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
0.635 ± 0.130
(0.025 ± 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
Figure 2. HCPL-4506 Gull Wing Surface Mount Option #300 Outline Drawing.
1-50
8
1
7
2
6
5
4
5.842 ± 0.203
(0.236 ± 0.008)
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
3
0.381 ± 0.076
(0.016 ± 0.003)
1.270
(0.050)
BSG
0.432
(0.017)
7°
5.080 ± 0.127
(0.200 ± 0.005)
45° X
3.175 ± 0.127
(0.125 ± 0.005)
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.152 ± 0.051
(0.006 ± 0.002)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.305
(0.012)
MIN.
Figure 3. HCPL-0466 Outline Drawing (8-Pin Small Outline Package).
Pin Location (for reference only)
11.00
(0.433)
11.15 ± 0.15
MAX.
(0.442 ± 0.006)
9.00 ± 0.15
(0.354 ± 0.006)
7
6
5
8
TYPE NUMBER
DATE CODE
HP
HCNWXXXX
YYWW
1
3
2
4
10.16 (0.400)
TYP.
1.55
(0.061)
MAX.
7° TYP.
+ 0.076
- 0.0051
+ 0.003)
- 0.002)
0.254
(0.010
5.10
(0.201)
MAX.
3.10 (0.122)
3.90 (0.154)
0.51 (0.021) MIN.
2.54 (0.100)
TYP.
1.78 ± 0.15
(0.070 ± 0.006)
0.40 (0.016)
0.56 (0.022)
DIMENSIONS IN MILLIMETERS (INCHES).
Figure 4a. HCNW4506 Outline Drawing (8-Pin Widebody Package).
11.15 ± 0.15
(0.442 ± 0.006)
PAD LOCATION (FOR REFERENCE ONLY)
7
6
5
4
8
1
6.15
(0.242)
TYP.
9.00 ± 0.15
(0.354 ± 0.006)
12.30 ± 0.30
(0.484 ± 0.012)
2
3
0.9
(0.035)
1.3
(0.051)
1.55
(0.061)
MAX.
12.30 ± 0.30
(0.484 ± 0.012)
11.00
MAX.
(0.433)
4.00
(0.158)
MAX.
1.78 ± 0.15
(0.070 ± 0.006)
1.00 ± 0.15
(0.039 ± 0.006)
0.75 ± 0.25
(0.030 ± 0.010)
+ 0.076
0.254
2.54
(0.100)
BSC
- 0.0051
+ 0.003)
- 0.002)
(0.010
DIMENSIONS IN MILLIMETERS (INCHES).
7° NOM.
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
Figure 4b. HCNW4506 Outline Drawing (8-Pin Widebody Package with Gull Wing Surface Mount Option 300).
1-51
Solder Reflow Temperature Profile
260
240
220
∆T = 145°C, 1°C/SEC
∆T = 115°C, 0.3°C/SEC
200
180
160
140
120
100
80
∆T = 100°C, 1.5°C/SEC
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10
11
12
TIME – MINUTES
Note: Use of nonchlorine activated fluxes is recommended.
Regulatory Information
CSA
BSI
The devices contained in this data
sheet have been approved by the
following organizations:
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
Certification according to
BS451:1994
(BS EN60065:1994);
BS EN60950:1992
UL
VDE
(BS7002:1992) and
EN41003:1993 for Class II
applications (HCNW4506 only).
Recognized under UL 1577,
Component Recognition
Program, File E55361.
Approved according to VDE
0884/06.92 (HCNW4506 and
HCPL-4506 Option 060 only).
InsulationandSafetyRelatedSpecifications
8-PinDIP
Widebody
(300 Mil) SO-8 (400Mil)
Parameter
Symbol
Value
Value
Value
Units
Conditions
MinimumExternal
AirGap(External
Clearance)
L(101)
7.1
4.9
9.6
mm
Measuredfrominputterminals
tooutputterminals,shortest
distancethroughair.
MinimumExternal
Tracking(External
Creepage)
L(102)
7.4
4.8
10.0
1.0
mm
mm
Measuredfrominputterminals
tooutputterminals,shortest
distancepathalongbody.
MinimumInternal
PlasticGap
(InternalClearance)
0.08
0.08
Throughinsulationdistance,
conductortoconductor,usually
the direct distance between the
photoemitterandphotodetector
insidetheoptocouplercavity.
MinimumInternal
Tracking(Internal
Creepage)
NA
200
IIIa
NA
200
IIIa
4.0
200
IIIa
mm
Measuredfrominputterminals
tooutputterminals, along
internalcavity.
TrackingResistance
(Comparative
TrackingIndex)
CTI
Volts DIN IEC 112/VDE 0303 Part 1
IsolationGroup
MaterialGroup
(DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
1-52
VDE 0884 Insulation Related Characteristics
(HCPL-4506 OPTION 060 ONLY)
Description
Symbol
Characteristic
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms
for rated mains voltage ≤ 450 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
I-IV
I-III
55/100/21
2
V
630
V peak
V peak
IORM
V
IORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
VPR
VPR
1181
945
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
V
IORM x 1.5 = VPR, Type and sample test,
V peak
V peak
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
V
6000
IOTM
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 18, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
TS
IS,INPUT
PS,OUTPUT
175
230
600
≥ 109
°C
mA
mW
Insulation Resistance at TS, V = 500 V
RS
Ω
IO
VDE 0884 Insulation Related Characteristics (HCNW4506 ONLY)
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 600 V rms
for rated mains voltage ≤ 1000 V rms
Climatic Classification
Symbol Characteristic Units
I-IV
I-III
55/100/21
2
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
V
1414
V peak
V peak
IORM
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
VPR
VPR
2652
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test,
2121
8000
V peak
V peak
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
V
IOTM
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 18, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
TS
150
400
700
≥ 109
°C
mA
mW
IS,INPUT
PS,OUTPUT
Insulation Resistance at TS, V = 500 V
RS
Ω
IO
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
1-53
Absolute Maximum Ratings
Parameter
Storage Temperature
Symbol
TS
Min.
-55
-40
Max.
125
100
25
50
1.0
5
Units
°C
°C
mA
mA
A
Operating Temperature
TA
Average Input Current[1]
IF(avg)
IF(peak)
IF(tran)
VR
Peak Input Current[2] (50% duty cycle, ≤ 1 ms pulse width)
Peak Transient Input Current (<1 µs pulse width, 300 pps)
Reverse Input Voltage (Pin 3-2)
HCPL-4506, HCPL-0466
HCNW4506
Volts
3
Average Output Current (Pin 6)
Resistor Voltage (Pin 7)
Output Voltage (Pin 6-5)
Supply Voltage (Pin 8-5)
Output Power Dissipation[3]
Total Power Dissipation[4]
IO(avg)
V7
VO
VCC
PO
PT
15
VCC
30
30
100
145
mA
Volts
Volts
Volts
mW
-0.5
-0.5
-0.5
mW
Lead Solder Temperature (HCPL-4506)
Lead Solder Temperature (HCNW4506)
Infrared and Vapor Phase Reflow Temperature
(HCPL-0466 and Option 300)
260°C for 10s, 1.6 mm below seating plane
260°C for 10 s (up to seating plane)
See Package Outline Drawings Section
Recommended Operating Conditions
Parameter
Power Supply Voltage
Output Voltage
Input Current (ON)
Input Voltage (OFF)
Operating Temperature
Symbol
Min.
4.5
0
10
-5
Max.
30
30
20
0.8
100
Units
VCC
VO
IF(on)
Volts
Volts
mA
V
VF(off)
TA
*
-40
°C
*Recommended VF(OFF) = -3 V to 0.8 V for HCNW4506.
Electrical Specifications
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter
Symbol Min. Typ.* Max. Units
Test Conditions
IF = 10 mA, VO = 0.6 V
IF = 10 mA, VO = 0.6 V
IO = 2.4 mA
VO = 0.8 V, IO = 0.75 mA
VF = 0.8 V
VF = 0.8 V, VO = Open
IF = 10 mA, VO = Open
HCPL-4506 IF = 10 mA
HCPL-0466
Fig. Note
Current Transfer Ratio
Low Level Output Current
Low Level Output Voltage
Input Threshold Current
High Level Output Current
High Level Supply Current
Low Level Supply Current
Input Forward Voltage
CTR
IOL
VOL
ITH
IOH
ICCH
ICCL
VF
44
4.4
90
9.0
0.3
1.5
5
0.6
0.6
1.5
%
mA
V
mA
µA
mA
mA
V
5
5,6
0.6
5.0
50
1.3
1.3
1.8
5
7
14
14
14
8
9
1.6
1.85
HCNW4506
Temperature Coefficient
of Forward Voltage
∆VF/∆T
-1.6
mV/°C HCPL-4506 IF = 10 mA
A
HCPL-0466
-1.3
HCNW4506
Input Reverse Breakdown
Voltage
BVR
CIN
5
3
V
HCPL-4506 IR = 100 µA
HCPL-0466
HCNW4506
Input Capacitance
60
pF
HCPL-4506 f = 1 MHz,
HCPL-0466 V = 0 V
F
72
20
0.014
HCNW4506
TA = 25°C
Internal Pull-up Resistor
Internal Pull-up Resistor
Temperature Coefficient
RL
∆RL/∆T
14
25
kΩ
kΩ/°C
10,11
A
*All typical values at 25°C, VCC = 15 V.
†VF(off) = -3 V to 0.8 V for HCNW4506.
1-54
Switching Specifications (RL= 20 kΩ External)
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter
Symbol Min. Typ.* Max. Units
Test Conditions
Fig. Note
Propagation Delay
Time to Low
Output Level
Propagation Delay
Time to High
tPHL
IF(on) = 10 mA,
VF(off) = 0.8 V,
VCC = 15.0 V,
VTHLH = 2.0 V,
VTHHL = 1.5 V
10,
12,
14-17 14
9,
12,
30
200 400
100
ns
ns
CL = 100 pF
CL = 10 pF
tPLH
270 400 550
ns
CL = 100 pF
Output Level
130
CL = 10 pF
Pulse Width
Distortion
PWD
200 450
ns
ns
CL = 100 pF
18
15
Propagation Delay tPLH-tPHL -150 200 450
Difference Between
Any 2 Parts
Output High Level
Common Mode
Transient Immunity
Output Low Level
Common Mode
|CMH|
|CML|
15
15
30
30
kV/µs IF = 0 mA,
VCC = 15.0 V,
CL = 100 pF,
VCM = 1500 V
11
16
17
VO > 3.0 V
P-P
T = 25°C
kV/µs IF = 10 mA
A
VO < 1.0 V
Transient Immunity
Switching Specifications (RL = Internal Pull-up)
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter
Symbol Min. Typ.* Max. Units
Test Conditions
Fig. Note
Propagation Delay
Time to Low
Output Level
tPHL
20
200 400
ns
IF(on) = 10 mA, VF(off) = 0.8 V,
VCC = 15.0 V, CL = 100 pF,
VTHLH = 2.0 V, VTHHL = 1.5 V
10, 9-12,
13
14
Propagation Delay
Time to High
Output Level
Pulse Width
Distortion
tPLH
220 450 650
250 500
ns
PWD
ns
ns
18
15
Propagation Delay tPLH-tPHL -150 250 500
Difference Between
Any 2 Parts
Output High Level
Common Mode
Transient Immunity
Output Low Level
Common Mode
Transient Immunity
|CMH|
|CML|
PSR
30
30
kV/µs IF = 0 mA,
VCC = 15.0 V,
CL = 100 pF,
VCM = 1500 V ,
11
16
17
14
VO > 3.0 V
P-P
T = 25°C
kV/µs IF = 16 mA,
A
VO < 1.0 V
Power Supply
Rejection
1.0
VP-P
Square Wave, tRISE, tFALL
> 5 ns, no bypass capacitors
*All typical values at 25°C, VCC = 15 V.
†VF(off) = -3 V to 0.8 V for HCNW4506.
1-55
Package Characteristics
Over recommended temperature (TA = -40°C to 100°C) unless otherwise specified.
Parameter
Sym. Min. Typ.* Max. Units
TestConditions
Fig. Note
Input-OutputMomentary
Withstand Voltage†
V
2500
5000
5000
V rms HCPL-4506
RH < 50%,
t = 1 min.
TA = 25°C
6, 7, 8
ISO
HCPL-0466
HCNW4506
Option020
6, 8, 13
HCNW4506
6, 8
6
Resistance
(Input-Output)
RI-O
1012
Ω
HCPL-4506
HCPL-0466
VI-O = 500 Vdc
f = 1 MHz
1012 1013
0.6
HCNW4506
Capacitance
(Input-Output)
CI-O
pF
HCPL-4506
HCPL-0466
6
0.5
HCNW4506
*All typical values at 25°C, VCC = 15 V.
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if
applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance
Voltage,” publication number 5963-2203E.
Notes:
8. For option 020, in accordance with
UL 1577, each optocoupler is proof
tested by applying an insulation test
voltage ≥ 6000 V rms for 1 second
(leakage detection current limit, II-O
≤ 5 µA). This test is performed before
the 100% Production test for partial
discharge (method b) shown in the
VDE 0884 Insulation Related
Characteristics Table, if applicable.
9. Pulse: f = 20 kHz, Duty Cycle = 10%.
10. The internal 20 kΩ resistor can be
used by shorting pins 6 and 7
14. Use of a 0.1 µF bypass capacitor
connected between pins 5 and 8 can
improve performance by filtering
power supply line noise.
15. The difference between tPLH and tPHL
between any two devices under the
same test condition. (See IPM Dead
Time and Propagation Delay
1. Derate linearly above 90°C free-air
temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 90°C free-air
temperature at a rate of 1.6 mA/°C.
3. Derate linearly above 90°C free-air
temperature at a rate of 3.0 mW/°C.
4. Derate linearly above 90°C free-air
temperature at a rate of 4.2 mW/°C.
5. CURRENT TRANSFER RATIO in
percent is defined as the ratio of
output collector current (IO) to the
forward LED input current (IF) times
100.
6. Device considered a two-terminal
device: Pins 1, 2, 3, and 4 shorted
together and Pins 5, 6, 7, and 8
shorted together.
7. In accordance with UL 1577, each
optocoupler is proof tested by
applying an insulation test voltage
≥ 3000 V rms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
This test is performed before the
100% Production test shown in the
VDE 0884 Insulation Related
Specifications section.)
16. Common mode transient immunity in
a Logic High level is the maximum
tolerable dVCM/dt of the common
mode pulse, VCM, to assure that the
output will remain in a Logic High
state (i.e., VO > 3.0 V).
17. Common mode transient immunity in
a Logic Low level is the maximum
tolerable dVCM/dt of the common
mode pulse, VCM, to assure that the
output will remain in a Logic Low
state (i.e., VO < 1.0 V).
together.
11. Due to tolerance of the internal
resistor, and since propagation delay
is dependent on the load resistor
value, performance can be improved
by using an external 20 kΩ 1% load
resistor. For more information on
how propagation delay varies with
load resistance, see Figure 12.
12. The RL = 20 kΩ, CL = 100 pF load
represents a typical IPM (Intelligent
Power Module) load.
18. Pulse Width Distortion (PWD) is
defined as |tPHL - tPLH| for any given
device.
13. See Option 020 data sheet for more
information.
Characteristics Table, if applicable.
1-56
10
1.05
1.00
0.95
0.90
20.0
15.0
10.0
5.0
V
V
= 0.8 V
F
= V = 4.5 V OR 30 V
CC
O
8
6
4
4.5 V
30 V
I
V
= 10 mA
F
V
= 0.6 V
O
= 0.6 V
O
2
0
0.85
0.80
100 °C
25 °C
-40 °C
0
20
– TEMPERATURE – °C
20
T – TEMPERATURE – °C
A
0
5
10
15
20
-40 -20
0
40
60 80 100
-40 -20
0
40
60 80 100
I
– FORWARD LED CURRENT – mA
T
F
A
Figure 5. Typical Transfer
Characteristics.
Figure 6. Normalized Output Current
vs. Temperature.
Figure 7. High Level Output
Current vs. Temperature.
100
1000
T
= 25°C
A
T
= 25 °C
A
100
10
10
1
I
F
I
F
+
V
+
F
V
–
F
–
1.0
0.1
0.1
0.01
0.01
0.001
0.001
0.8
1.0
1.2
1.4
1.6
1.8
2.0
1.10 1.20
1.30
1.40
1.50
1.60
V
– INPUT FORWARD VOLTAGE – V
V
– FORWARD VOLTAGE – VOLTS
F
F
Figure 8. HCPL-4506 and HCPL-0466
Input Current vs. Forward Voltage.
Figure 9. HCNW4506 Input Current
vs. Forward Voltage.
1
8
7
20 k
Ω
0.1 µF
20 kΩ
I
=10 mA
5 V
F(ON)
+
+
2
3
4
I
–
f
V
= 15 V
t
t
r
CC
f
V
–
O
6
5
V
OUT
90%
10%
90%
10%
C *
L
V
V
THHL
THLH
SHIELD
*TOTAL LOAD CAPACITANCE
t
t
PLH
PHL
Figure 10. Propagation Delay Test Circuit.
1-57
V
1
2
8
7
CM
0.1 µF
20 kΩ
V
δV
δt
CM
∆t
20 kΩ
I
F
=
+
OV
V
= 15 V
CC
–
A
B
∆t
3
4
6
5
V
OUT
100 pF*
V
O
V
V
CC
+
–
SWITCH AT A: I = 0 mA
SHIELD
F
V
FF
*100 pF TOTAL
CAPACITANCE
V
O
OL
SWITCH AT B: I = 10 mA
F
+
V
= 1500 V
CM
Figure 11. CMR Test Circuit. Typical CMR Waveform.
500
400
300
200
100
500
400
300
200
100
800
I
V
= 10 mA
F
I
V
= 10 mA
F
= 15 V
CC
= 15 V
CC
CL = 100 pF
RL = 20 kΩ
(INTERNAL)
I
V
= 10 mA
= 15 V
CL = 100 pF
RL = 20 kΩ (EXTERNAL)
F
CC
CL = 100 pF
= 25 °C
600
400
200
T
A
t
t
t
t
PLH
PHL
t
t
PLH
PHL
PLH
PHL
20
– TEMPERATURE – °C
20
T – TEMPERATURE – °C
A
20
RL – LOAD RESISTANCE – K Ω
-40 -20
0
40
60 80 100
-40 -20
0
40
60 80 100
0
10
30
40
50
T
A
Figure 12. Propagation Delay with
External 20 kΩ RL vs. Temperature.
Figure 13. Propagation Delay with
Internal 20 kΩ RL vs. Temperature.
Figure 14. Propagation Delay vs. Load
Resistance.
1400
500
1400
1200
1000
800
I
V
= 10 mA
= 15 V
I
= 10 mA
V
= 15 V
CC
F
F
t
t
PLH
PHL
CL = 100 pF
RL = 20 kΩ
T
CL = 100 pF
RL = 20 kΩ
CC
RL = 20 kΩ
= 25°C
1200
1000
800
T
= 25°C
T = 25°C
A
A
400
300
200
100
A
t
t
t
t
PLH
PHL
PLH
PHL
600
600
400
400
200
0
200
0
0
100
200
300
400
500
5
10
15
20
25
30
0
5
10
15
20
CL – LOAD CAPACITANCE – pF
I
– FORWARD LED CURRENT – mA
V
– SUPPLY VOLTAGE – V
F
CC
Figure 15. Propagation Delay vs. Load
Capacitance.
Figure 16. Propagation Delay vs.
Supply Voltage.
Figure 17. Propagation Delay vs. Input
Current.
1-58
HCNW4506
(mW)
HCPL-4506 OPTION 060
1000
800
700
600
500
400
300
P
P
I
(mW)
S
S
1
2
8
7
900
800
700
600
500
400
300
200
I
(mA)
(mA)
S
S
20 kΩ
C
LEDP
3
4
6
5
C
LEDN
(230)
200
SHIELD
100
0
100
0
0
25
50 75 100 125 150 175
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – °C
T
– CASE TEMPERATURE – °C
T
S
S
Figure 20. Optocoupler Input to
Output Capacitance Model for
Unshielded Optocouplers.
Figure 18. Thermal Derating Curve, Dependence of Safety Limiting Value with
Case Temperature per VDE 0884.
1
2
8
7
20 kΩ
C
LEDP
1
2
8
7
C
LED02
C
20 kΩ
0.1 µF
20 kΩ
LED01
+
+5 V
310 Ω
CMOS
V
= 15 V
–
CC
3
4
6
5
C
LEDN
3
4
6
5
V
OUT
SHIELD
100 pF
SHIELD
*100 pF TOTAL
CAPACITANCE
Figure 21. Optocoupler Input to
Output Capacitance Model for
Shielded Optocouplers.
Figure 19. Recommended LED Drive Circuit.
1
2
8
7
20
20 kΩ
I
I
TOTAL*
CLEDP
kΩ
C
LED02
C
I
LEDP
F
310 Ω
C
1
2
8
7
LED01
+5 V
I
CLED01
V
OUT
20 kΩ
0.1 µF
20 kΩ
3
4
6
5
+
–
C
LEDN
V
= 15 V
CC
100 pF
310 Ω
SHIELD
3
4
6
5
V
OUT
CMOS
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dV /dt TRANSIENTS.
100 pF
CM
+
SHIELD
*100 pF TOTAL
CAPACITANCE
V
CM
Figure 22. LED Drive Circuit with Resistor Connected to LED
Anode (Not Recommended).
Figure 23. AC Equivalent Circuit for Figure 22 During
Common Mode Transients.
1-59
1
2
8
7
1
2
8
7
20
+5 V
kΩ
20 kΩ
C
20 kΩ
LEDP
C
LED02
C
LED01
310 Ω
V
OUT
C
LEDN
3
4
6
5
3
4
6
5
I
CLEDN*
Q1
100 pF
+ V ** –
R
SHIELD
SHIELD
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dV /dt TRANSIENTS.
CM
** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH
PERFORMANCE.
V
< V
DURING +dV /dt.
R
F (OFF)
CM
Figure 25. Not Recommended Open
Collector LED Drive Circuit.
+
V
CM
Figure 24. AC Equivalent Circuit for Figure 19 During
Common Mode Transients.
1
2
8
7
20
kΩ
C
20 kΩ
LEDP
C
1
8
7
LED02
C
+5 V
LED01
20 kΩ
V
C
Q1
OUT
LEDN
2
3
3
4
6
5
I
CLEDN*
100 pF
6
5
SHIELD
4
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
SHIELD
FLOW FOR +dV /dt TRANSIENTS.
CM
+
V
CM
Figure 27. Recommended LED Drive
Circuit for Ultra High CMR.
Figure 26. AC Equivalent Circuit for Figure 25 During
Common Mode Transients.
HCPL-4506
1
2
8
7
V
CC1
0.1 µF
20 kΩ
IPM
I
LED1
20 kΩ
+5 V
+HV
V
310 Ω
CMOS
OUT1
3
4
6
5
Q1
Q2
M
SHIELD
HCPL-4506
HCPL-4506
1
2
8
7
V
CC2
-HV
0.1 µF
20 kΩ
HCPL-4506
HCPL-4506
HCPL-4506
HCPL-4506
I
LED2
20 kΩ
+5 V
310 Ω
CMOS
V
OUT2
3
4
6
5
SHIELD
Figure 28. Typical Application Circuit.
1-60
I
LED1
Q1 OFF
Q2 ON
Q1 ON
I
V
V
LED1
OUT1
OUT2
Q2 OFF
Q1 OFF
Q2 ON
Q1 ON
V
V
OUT1
OUT2
I
LED2
Q2 OFF
t
PLH
MIN.
t
PLH
MAX.
I
LED2
t
PHL
PDD*
MAX.
t
PLH MAX.
MIN.
t
t
PHL
PHL
MIN.
MAX.
MAX.
DEAD TIME
PDD* MAX. =
(t
t
)
t
t
PLH- PHL MAX. = PLH MAX. - PHL MIN.
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
*PDD = PROPAGATION DELAY DIFFERENCE
= (t
= (t
t
t
) + (t
) - (t
t
)
PLH MAX.
-
-
PLH MIN.
PHL MAX.
-
t
PHL MIN.
)
PLH MAX.
PHL MIN.
PLH MIN.
-
PHL MAX.
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE
PDD ARE TAKEN AT EQUAL TEMPERATURES.
= PDD* MAX. - PDD* MIN.
*PDD = PROPAGATION DELAY DIFFERENCE
Figure 29. Minimum LED Skew for Zero Dead Time.
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.
Figure 30. Waveforms for Dead Time Calculation.
(Figure 19), can achieve 15 kV/µs
CMR while minimizing component
complexity. Note that a CMOS
gate is recommended in Figure 19
to keep the LED off when the gate
is in the high state.
achieved by overdriving the LED
current beyond the input
LED Drive Circuit
Considerations for Ultra
High CMR Performance
threshold so that it is not pulled
below the threshold during a
transient. The recommended
minimum LED current of 10 mA
provides adequate margin over
the maximum ITH of 5.0 mA (see
Figure 5) to achieve 15 kV/µs
CMR. Capacitive coupling is
higher when the internal load
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive coupling
from the input side of the opto-
coupler, through the package, to
the detector IC as shown in
Another cause of CMR failure for
a shielded optocoupler is direct
coupling to the optocoupler
output pins through CLEDO1 and
CLEDO2 in Figure 21. Many factors
influence the effect and magni-
tude of the direct coupling includ-
ing: the use of an internal or
external output pull-up resistor,
the position of the LED current
setting resistor, the connection of
the unused input package pins,
and the value of the capacitor at
the optocoupler output (CL).
Figure 20. The HCPL-4506,
HCPL-0466 and HCNW4506
improve CMR performance by
using a detector IC with an optic-
ally transparent Faraday shield,
which diverts the capacitively
coupled current away from the
sensitive IC circuitry. However,
this shield does not eliminate the
capacitive coupling between the
LED and the optocoupler output
pins and output ground as shown
in Figure 21. This capacitive
resistor is used (due to CLEDO2
)
and an IF = 16 mA is required to
obtain 10 kV/µs CMR.
The placement of the LED current
setting resistor effects the ability of
the drive circuit to keep the LED on
during transients and interacts with
the direct coupling to the
optocoupler output. For example,
the LED resistor in Figure 22 is
connected to the anode. Figure 23
shows the AC equivalent circuit for
Figure 22 during common mode
transients. During a +dVcm/dt in
Figure 23, the current available at
the LED anode (Itotal) is limited by
the series resistor. The LED current
(IF) is reduced from its DC value by
an amount equal to the current that
Techniques to keep the LED in
the proper state and minimize the
effect of the direct coupling are
discussed in the next two
sections.
coupling causes perturbations in
the LED current during common
mode transients and becomes the
major source of CMR failures for
a shielded optocoupler. The main
design objective of a high CMR
LED drive circuit becomes keep-
ing the LED in the proper state
(on or off) during common mode
transients. For example, the
CMR with the LED On
(CMRL)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
flows through CLEDP and CLEDO1
The situation is made worse
.
recommended application circuit
1-61
because the current through CLEDO1
has the effect of trying to pull the
output high (toward a CMR failure)
at the same time the LED current is
being reduced. For this reason, the
recommended LED drive circuit
(Figure 19) places the current set-
ting resistor in series with the LED
cathode. Figure 24 is the AC equiv-
alent circuit for Figure 19 during
common mode transients. In this
case, the LED current is not
reduced during a +dVcm/dt tran-
sient because the current flowing
through the package capacitance is
supplied by the power supply.
During a -dVcm/dt transient, how-
ever, the LED current is reduced by
the amount of current flowing
through CLEDN. But, better CMR
performance is achieved since the
current flowing in CLEDO1 during a
negative transient acts to keep the
output low.
during a 15 kV/µs transient with
CM = 1500 V. Additionalmargin
specifications, preferably over the
desired operating temperature
range.
V
can be obtained by adding a diode
in parallel with the resistor, as
shown by the dashed line connec-
tion in Figure 24, to clamp the
voltage across the LED below
The limiting case of zero dead time
occurs when the input to Q1 turns
off at the same time that the input
to Q2 turns on. This case
determines the minimum delay
between LED1 turn-off and LED2
turn-on, which is related to the
worst case optocoupler propagation
delay waveforms, as shown in
VF(OFF)
.
Since the open collector drive cir-
cuit, shown in Figure 25, cannot
keep the LED off during a +dVcm/
dt transient, it is not desirable for
applications requiring ultra high
CMRH performance. Figure 26 is
the AC equivalent circuit for Figure
25 during common mode
transients. Essentially all the
current flowing through CLEDN
during a +dVcm/dt transient must
be supplied by the LED. CMRH
failures can occur at dV/dt rates
where the current through the LED
and CLEDN exceeds the input
threshold. Figure 27 is an
Figure 29. A minimum dead time of
zero is achieved in Figure 29 when
the signal to turn on LED2 is
delayed by (tPLH max - tPHL min) from
the LED1 turn off. Note that the
propagation delays used to calcu-
late PDD are taken at equal temper-
atures since the optocouplers under
consideration are typically mounted
in close proximity to each other.
(Specifically, tPLH max and tPHL min
in the previous equation are not the
Coupling to the LED and output
pins is also affected by the connec-
tion of pins 1 and 4. If CMR is
limited by perturbations in the LED
on current, as it is for the recom-
mended drive circuit (Figure 19),
pins 1 and 4 should be connected to
the input circuit common. However,
if CMR performance is limited by
direct coupling to the output when
the LED is off, pins 1 and 4 should
be left unconnected.
alternative drive circuit which does
achieve ultra high CMR
performance by shunting the LED
in the off state.
same as the tPLH max and tPHL min,
over the full operating temperature
range, specified in the data sheet.)
This delay is the maximum value for
the propagation delay difference
specification which is specified at
450 ns for the HCPL-4506, HCPL-
0466 and HCNW4506 over an
operating temperature range of
-40°C to 100°C.
IPM Dead Time and
Propagation Delay
Specifications
The HCPL-4506, HCPL-0466 and
HCNW4506 include a Propagation
Delay Difference specification
intended to help designers minimize
“dead time” in their power inverter
designs. Dead time is the time
period during which both the high
and low side power transistors (Q1
and Q2 in Figure 28) are off. Any
overlap in Q1 and Q2 conduction
will result in large currents flowing
through the power devices between
the high and low voltage motor rails.
Delaying the LED signal by the
maximum propagation delay dif-
ference ensures that the minimum
dead time is zero, but it does not
tell a designer what the maximum
dead time will be. The maximum
dead time occurs in the highly
unlikely case where one optocoup-
ler with the fastest tPLH and another
with the slowest tPHL are in the
same inverter leg. The maximum
dead time in this case becomes the
sum of the spread in the tPLH and
CMR with the LED Off
(CMRH)
A high CMR LED drive circuit must
keep the LED off (VF ≤ VF(OFF)
)
during common mode transients.
For example, during a +dVcm/dt
transient in Figure 24, the current
flowing through CLEDN is supplied
by the parallel combination of the
LED and series resistor. As long as
the voltage developed across the
resistor is less than VF(OFF) the LED
will remain off and no common
mode failure will occur. Even if the
LED momentarily turns on, the 100
pF capacitor from pins 6-5 will
keep the output from dipping below
the threshold. The recommended
LED drive circuit (Figure 19) pro-
vides about 10 V of margin between
the lowest optocoupler output
To minimize dead time the designer
must consider the propagation
delay characteristics of the opto-
coupler as well as the characteris-
tics of the IPM IGBT gate drive
circuit. Considering only the delay
characteristics of the optocoupler
(the characteristics of the IPM
IGBT gate drive circuit can be
analyzed in the same way) it is
important to know the minimum
and maximum turn-on (tPHL) and
turn-off (tPLH) propagation delay
t
PHL propagation delays as shown in
Figure 30. The maximum dead time
is also equivalent to the difference
between the maximum and mini-
mum propagation delay difference
specifications. The maximum dead
time (due to the optocouplers) for
the HCPL-4506, HCPL-0466 and
HCNW4506 is 600 ns (= 450ns -
(-150 ns)) over an operating
temperature range of -40°C to
100°C.
voltage and a 3 V IPM threshold
1-62
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