HCPL-5301-200 [AGILENT]
Intelligent Power Module and Gate Drive Interface Hermetically Sealed Optocouplers; 智能功率模块和门驱动接口密封式光电耦合器
| 型号： | HCPL-5301-200 |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | Intelligent Power Module and Gate Drive Interface Hermetically Sealed Optocouplers |
| 文件： | 总17页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intelligent Power Module
and Gate Drive Interface
Hermetically Sealed
Optocouplers
HCPL-5300
HCPL-5301
HCPL-530K
Technical Data
5962-96852
Features
Applications
• Military and Space
• High Reliability Systems
• Harsh Industrial
Environments
• Transportation, Medical, and
Life Critical Systems
• IPM Isolation
• Isolated IGBT/MOSFET Gate
Drive
• AC and Brushless DC Motor
Drives
capable of operation and storage
over the full military temperature
range and can be purchased as
either standard product or with
full MIL-PRF-38534 Class Level
H or K testing or from the DSCC
Drawing 5962-96852. All devices
are manufactured and tested on a
MIL-PRF-38534 certified line and
are included in the DSCC
Qualified Manufacturers List
QML-38534 for Hybrid Micro-
circuits. Minimized propagation
delay difference between devices
make these optocouplersexcellent
solutions for improving inverter
efficiency through reduced
switching dead time. An on chip
20 kΩ output pull-up resistor can
be enabled by shorting output
pins 6 and 7, thus eliminating the
need for an external pull-up
resistor in common IPM applica-
tions. Specifications and
performance plots are given for
typical IPM applications.
• Performance Specified Over
Full Military Temperature
Range: -55°C to +125°C
• Fast Maximum Propagation
Delays
tPHL = 450 ns,
tPLH = 650 ns
• Minimized Pulse Width
Distortion (PWD = 450 ns)
• High Common Mode
Rejection (CMR): 10 kV/µs at
VCM = 1000 V
• CTR > 30% at IF = 10 mA
• 1500 Vdc Withstand Test
Voltage
• Manufactured and Tested on
a MIL-PRF-38534 Certified
Line
• Hermetically Sealed
Packages
• Dual Marked with Device
Part Number and DSCC
Drawing Number
• Industrial Inverters
Description
The HCPL-530X devices consist
of a GaAsP LED optically coupled
to an integrated high gain photo
detector in a hermetically sealed
package. The products are
Schematic Diagram
• QML-38534, Class H and K
• HCPL-4506 Function
Compatibility
1
2
8
7
20 kΩ
Truth Table
3
4
6
5
LED
ON
VO
L
SHIELD
OFF
H
The connection of a 0.1 µF bypass capacitor between pins 5 and 8 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
2
Selection Guide-Package Styles and Lead
Configuration Options
Agilent Part # and Options
Commercial
MIL-PRF-38534, Class H
MIL-PRF-38534, Class K
Standard Lead Finish
Solder Dipped
HCPL-5300
HCPL-5301
HCPL-530K
Gold Plate
Option #200
Option #100
Option #300
Butt Cut/Gold Plate
Gull Wing/Soldered
Class H SMD Part #
Prescript for all below
Either Gold or Solder
Gold Plate
5962-
9685201HPX
9685201HPC
9685201HPA
9685201HYC
9685201HYA
9685201HXA
Solder Dipped
Butt Cut/Gold Plate
Butt Cut/Soldered
Gull Wing/Soldered
Class K SMD Part #
Prescript for all below
Either Gold or Solder
Gold Plate
5962-
9685201KPX
9685201KPC
9685201KPA
9685201KYC
9685201KYA
9685201KXA
Solder Dipped
Butt Cut/Gold Plate
Butt Cut/Soldered
Gull Wing/Soldered
Outline Drawing
9.40 (0.370)
9.91 (0.390)
8.13 (0.320)
MAX.
0.76 (0.030)
1.27 (0.050)
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
0.51 (0.020)
3.81 (0.150)
MIN.
MIN.
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
3
Device Marking
Agilent DESIGNATOR
Agilent P/N
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DSCC SMD*
PIN ONE/
COUNTRY OF MFR.
Agilent CAGE CODE*
ESD IDENT
* QUALIFIED PARTS ONLY
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This
option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for
details).
4.32 (0.170)
MAX.
0.51 (0.020)
1.14 (0.045)
MIN.
0.20 (0.008)
0.33 (0.013)
1.40 (0.055)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
300
Lead finish is solder dipped rather than gold plated. This option is available on commercial
and hi-rel product in 8 pin DIP. DSCC Drawing part numbers contain provisions for lead
finish.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly.
This option is available on commercial and hi-rel product in 8 pin DIP (see drawings below
for details). This option has solder dipped leads.
4.57 (0.180)
MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
5° MAX.
1.40 (0.055)
1.65 (0.065)
9.65 (0.380)
9.91 (0.390)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
4
Absolute Maximum Ratings
Storage Temperature (TS) ............................................................................................................. -65 to 150°C
Operating Temperature (TA) ......................................................................................................... -55 to 125°C
Junction Temperature (TJ) ...................................................................................................................... 175°C
Average Input Current (IF(AVG)) ............................................................................................................... 25 mA
Peak Input Current (50% duty cycle, ≤ 1 ms pulse width) (IF(PEAK)) ........................................................ 50 mA
Peak Transient Input Current (<1 µs pulse width, 300 pps) (IF(TRAN)) ..................................................... 1.0 A
Reverse Input Voltage (Pin 3-2) (VR)............................................................................................................ 5 V
Average Output Current (Pin 6) (IO(AVG)) ................................................................................................ 15 mA
Resistor Voltage (Pin 7) (V7) ......................................................................................................... -0.5 V to VCC
Output Voltage (Pin 6-5) (VO) ........................................................................................................ -0.5 to 30 V
Supply Voltage (Pin 8-5) (VCC) ....................................................................................................... -0.5 to 30 V
Output Power Dissipation (PO)............................................................................................................. 100 mW
Total Power Dissipation (PT)................................................................................................................ 145 mW
Lead Solder Temperature (soldering, 10 seconds) .................................................................................. 260°C
ESD Classification
(MIL-STD-883,
Method 3015).....................(∆),Class 1
Recommended Operating Conditions
Parameter
Power Supply Voltage
Output Voltage
Symbol
VCC
Min.
4.5
0
Max.
30
Units
Volts
Volts
mA
VO
30
Input Current (ON)
Input Voltage (OFF)
IF(ON)
VF(OFF)
10
-5
20
0.8
V
5
Electrical Specifications
Over recommended operating conditions (T = -55°C to +125°C, VCC = +4.5 V to 30 V,
A
IF(ON) = 10 mA to 20 mA, VF(OFF) = -5 V to 0.8 V) unless otherwise specified.
Group A
Sub-
Parameter
Symbol groups[12] Min. Typ.* Max. Units
Test Conditions
Fig. Note
Current Transfer
Ratio
CTR
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
30
90
9.0
0.3
1.5
5
%
IF = 10 mA, VO = 0.6 V
1
Low Level Output
Current
IOL
3.0
mA IF = 10 mA, VO = 0.6 V 1, 2
IO = 2.4 mA
Low Level Output
Voltage
VOL
ITH
0.6
5.0
75
V
Input Threshold
Current
mA VO = 0.8 V,
IO = 0.75 mA
1
3
7
High Level
Output Current
IOH
ICCH
ICCL
VF
µA
VF = 0.8 V
High Level Supply
Current
0.6
0.6
1.5
-1.6
1.5
1.5
1.8
mA VF = 0.8 V, VO = Open
mA IF = 10 mA, VO = Open
7
7
Low Level Supply
Current
Input Forward
Voltage
1.0
5
V
IF = 10 mA
4
Temperature
Coefficient of
Forward Voltage
∆VF/
∆TA
mV/°C IF = 10 mA
Input Reverse
Breakdown Voltage
BVR
1, 2, 3
1
V
IR = 100 µA
Input Capacitance
CIN
II-O
90
pF
f = 1 MHz, VF = 0 V
RH = 45%, t = 5 sec,
Input-Output
Insulation Leakage
Current
1.0
28
µA
2
VI-O = 1500 Vdc,
T = 25°C
A
Resistance
(Input-Output)
RI-O
CI-O
RL
1012
2.4
Ω
VI-O = 500 Vdc
2
2
Capacitance
(Input-Output)
pF
f = 1 MHz
Internal Pull-up
Resistor
1
14
20
kΩ T = 25°C
4, 5,
6
A
Internal Pull-up
Resistor
∆RL/
∆TA
0.014
kΩ/°C
Temperature
Coefficient
*All typical values at 25°C, VCC = 15 V.
6
Switching Specifications (RL= 20 kΩ External)
Over recommended operating conditions:
(TA = -55°C to +125°C, VCC = +4.5 V to 30 V, IF(ON) = 10 mA to 20 mA, VF(OFF) = -5 V to 0.8 V) unless
otherwise specified.
Group A
Parameter
Symbol Subgrps.[12] Min. Typ.* Max. Units
Test Conditions
Fig. Note
Propagation
Delay Time to
Low Output
Level
tPHL
9, 10, 11
30 180 450
ns
CL =
100 pF
CL =
IF(on) = 10 mA, 5, 7,
3, 4,
9-12 5, 6,
7
VF(off) = 0.8 V,
VCC = 15.0 V,
VTHLH = 2.0 V,
VTHHL = 1.5 V
100
ns
10 pF
Propagation
Delay Time to
High Output
Level
tPLH
9, 10, 11
250 350 650
130
ns
CL =
100 pF
CL =
10 pF
Pulse Width
Distortion
PWD
9, 10, 11
9, 10, 11
150 450
ns
ns
CL =
100 pF
11
8
Propagation
Delay
tPLH
-
-170 140 500
tPHL
Difference
Between Any
Two Parts
Output High
Level Common
Mode
Immunity
Transient
|CMH|
9
9
10
10
17
17
kV/µs IF = 0 mA, VCC = 15.0 V,
VO > 3.0 V CL = 100 pF,
VCM = 1000 V
6, 17, 9, 13
18, 21
P-P
T = 25°C
A
Output Low
Level Common
Mode
|CML|
kV/µs IF = 10 mA
10, 13
VO < 1.0 V
Transient
Immunity
*All typical values at 25°C, VCC = 15 V.
7
Switching Specifications (RL= Internal Pull-up)
Over recommended operating conditions:
(TA = -55°C to +125°C, VCC = +4.5 V to 30 V, IF(ON) = 10 mA to 20 mA, VF(OFF) = -5 V to 0.8 V) unless
otherwise specified.
Group A
Parameter
Symbol Subgrps.[12] Min. Typ.* Max. Units Test Conditions
Fig. Note
Propagation
Delay Time to
Low Output
Level
tPHL
9, 10, 11
20 185 500
ns
IF(on) = 10 mA,
VF(off) = 0.8 V,
VCC = 15.0 V,
CL = 100 pF,
VTHLH = 2.0 V
VTHHL = 1.5 V
5, 8,
3, 4,
5, 6,
7
Propagation
Delay Time to
High Output
Level
tPLH
9, 10, 11
220 415 750
ns
Pulse Width
Distortion
PWD
9, 10, 11
9, 10, 11
150 600
ns
ns
11
8
Propagation
Delay
Difference
Between Any
Two Parts
tPLH
-
-225 150 650
tPHL
|CMH|
|CML|
PSR
Output High
Level Common
Mode Transient
Immunity
10
10
kV/µs IF = 0 mA, VCC = 15.0 V,
VO > 3.0 V CL = 100 pF,
VCM = 1000
6, 21
9
10
7
TA = 25°C
Output Low
kV/µs IF =16 mA
Level Common
Mode Transient
Immunity
VO < 1.0 V
Power Supply
Rejection
1.0
VP-P Square Wave, tRISE, tFALL
> 5 ns, no bypass
capacitors.
*All typical values at 25°C, VCC = 15 V.
Notes:
1. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (IO) to the forward LED input current
(IF) times 100.
2. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together and Pins 5, 6, 7 and 8 shorted together.
3. Pulse: f = 20 kHz, Duty Cycle = 10%
4. The internal 20 kΩ resistor can be used by shorting pins 6 and 7 together.
5. Due to the tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can
be improved by using an external 20 kΩ 1% load resistor. For more information on how propagation delay varies with load
resistance, see Figure 8.
6. The RL = 20 kΩ, CL = 100 pF represents a typical IPM (Intelligent Power Module) load.
7. Use of a 0.1 µF bypass capacitor connected between pins 5 and 8 can improve performance by filtering power supply line noise.
8. The difference in tPLH and tPHL between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay
Specifications section.)
9. Common mode transient immunity in a Logic High level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to
assure that the output will remain in a Logic High state (i.e., VO > 3.0 V).
10. Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to
assure that the output will remain in a Logic Low state (i.e., VO < 1.0 V).
11. Pulse Width Distortion (PWD) is defined as the difference between tPLH and tPHL for any given device.
12. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25°C, +125°C,
and -55°C (Subgroups 1 and 9, 2 and 10, 3 and 11 respectively).
13. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed
to limits specified for all lots not specifically tested.
8
LED Drive Circuit
package pins, and the value of
the capacitor at the optocoupler
output (CL).
(toward a CMR failure) at the
same time the LED current is
being reduced. For this reason,
the recommended LED drive
circuit (Figure 13) places the
current setting resistor in series
with the LED cathode. Figure 18
is the AC equivalent circuit for
Figure 13 during common mode
transients. In this case, the LED
current is not reduced during a
+dVCM/dt transient because the
current flowing through the
package capacitance is supplied
by the power supply. During a
-dVCM/dt transient, however, the
LED current is reduced by the
amount of current flowing
Considerations For Ultra
High CMR Performance
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side of
the optocoupler, through the
package, to the detector IC as
shown in Figure 14. The HCPL-
530X improves CMR
performance by using a detector
IC with an optically transparent
Faraday shield, which diverts the
capacitively coupled current away
from the sensitive IC circuitry.
However, this shield does not
eliminate the capacitive coupling
between the LED and the opto-
coupler output pins and output
ground as shown in Figure 15.
This capacitive coupling causes
perturbations in the LED current
during common mode transients
and becomes the major source of
CMR failures for a shielded
Techniques to keep the LED in
the proper state and minimize the
effect of the direct coupling are
discussed in the next two
sections.
CMR With The LED On
(CMRL)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. The recommended
minimum LED current of 10 mA
provides adequate margin over
the maximum ITH of 5.0 mA (see
Figure 1) to achieve 10 kV/µs
CMR. Capacitive coupling is
higher when the internal load
through CLEDN. But better CMR
performance is achieved since the
current flowing in CLEDO1 during
a negative transient acts to keep
the output low.
Coupling to the LED and output
pins is also affected by the
connection of pins 1 and 4. If
CMR is limited by perturbations
in the LED on current, as it is for
the recommended drive circuit
(Figure 13), pins 1 and 4 should
be connected to the input circuit
common. However, if CMR
performance is limited by direct
coupling to the output when the
LED is off, pins 1 and 4 should
be left unconnected.
optocoupler. The main design
objective of a high CMR LED
drive circuit becomes keeping the
LED in the proper state (on or
off) during common mode
transients. For example, the
recommended application circuit
(Figure 13), can achieve 10 kV/µs
CMR while minimizing compo-
nent complexity. Note that a
CMOS gate is recommended in
Figure 13 to keep the LED off
when the gate is in the high state.
resistor is used (due to CLEDO2)
and an IF = 16mA is required to
obtain 10 kV/µs CMR.
The placement of the LED
current setting resistor affects the
ability of the drive circuit to keep
the LED on during transients and
interacts with the direct coupling
to the optocoupler output. For
example, the LED resistor in
Figure 16 is connected to the
anode. Figure 17 shows the AC
equivalent circuit for Figure 16
during common mode transients.
During a +dVCM/dt in Figure 17,
the current available at the LED
anode (ITOTAL) is limited by the
series resistor. The LED current
(IF) is reduced from its DC value
by an amount equal to the current
that flows through CLEDP and
CLEDO1. The situation is made
worse because the current
CMR With The LED Off
(CMRH)
A high CMR LED drive circuit
must keep the LED off
(VF ≤ VF(OFF)) during common
mode transients. For example,
during a +dVCM/dt transient in
Figure 18, the current flowing
through CLEDN is supplied by the
parallel combination of the LED
and series resistor. As long as the
voltage developed across the
resistor is less than VF(OFF) the
LED will remain off and no
Another cause of CMR failure for
a shielded optocoupler is direct
coupling to the optocoupler
output pins through CLEDO1 and
CLEDO2 in Figure 15. Many factors
influence the effect and magni-
tude of the direct coupling
including: the use of an internal
or external output pull-up
resistor, the position of the LED
current setting resistor, the
through CLEDO1 has the effect of
trying to pull the output high
connection of the unused input
9
common mode failure will occur.
Even if the LED momentarily
turns on, the 100 pF capacitor
from pins 6-5 will keep the
output from dipping below the
threshold. The recommended
LED drive circuit (Figure 13)
provides about 10 V of margin
between the lowest optocoupler
output voltage and a 3 V IPM
threshold during a 10 kV/µs
transient with VCM = 1000 V.
Additional margin can be
IPM Dead Time and
Propagation Delay
Specifications
turn-on, which is related to the
worst case optocoupler propaga-
tion delay waveforms, as shown
in Figure 23. A minimum dead
time of zero is achieved in Figure
23 when the signal to turn on
These devices include a
Propagation Delay Difference
specification intended to help
designers minimize “dead time” in
their power inverter designs.
Dead time is the time period
during which both the high and
low side power transistors (Q1
and Q2 in Figure 22) are off. Any
overlap in Q1 and Q2 conduction
will result in large currents
flowing through the power
devices between the high and low
voltage motor rails.
LED2 is delayed by (tPLH max
-
tPHL min) from the LED1 turn off.
This delay is the maximum value
for the propagation delay
difference specification which is
specified at 500 ns for the
HCPL-530X over an operating
temperature range of -55°C to
+125°C.
obtained by adding a diode in
parallel with the resistor, as
shown by the dashed line connec-
tion in Figure 18, to clamp the
voltage across the LED below
Delaying the LED signal by the
maximum propagation delay
difference ensures that the mini-
mum dead time is zero, but it
does not tell a designer what the
maximum dead time will be. The
maximum dead time occurs in the
highly unlikely case where one
optocoupler with the fastest tPLH
and another with the slowest tPHL
are in the same inverter leg. The
maximum dead time in this case
becomes the sum of the spread in
the tPLH and tPHL propagation
delays as shown in Figure 24. The
maximum dead time is also
VF(OFF)
.
To minimize dead time the
designer must consider the
Since the open collector drive
circuit, shown in Figure 19,
cannot keep the LED off during a
+dVCM/dt transient, it is not
desirable for applications
requiring ultra high CMRH
performance. Figure 20 is the AC
equivalent circuit for Figure 16
during common mode transients.
Essentially all the current flowing
through CLEDN during a +dVCM/dt
transient must be supplied by the
LED. CMRH failures can occur at
dv/dt rates where the current
through the LED and CLEDN
exceeds the input threshold.
Figure 21 is an alternative drive
circuit which does achieve ultra
high CMR performance by
propagation delay characteristics
of the optocoupler as well as the
characteristics of the IPM IGBT
gate drive circuit. Considering
only the delay characteristics of
the optocoupler (the character-
istics of the IPM IGBT gate drive
circuit can be analyzed in the
same way) it is important to
know the minimum and maximum
turn-on (tPHL) and turn-off (tPLH
propagation delay specifications,
preferably over the desired
)
equivalent to the difference
between the maximum and
operating temperature range.
minimum propagation delay
difference specifications. The
maximum dead time (due to the
optocouplers) for the HCPL-530X
is 670 ns (= 500 ns - (-170 ns))
over an operating temperature
range of -55°C to +125°C.
The limiting case of zero dead
time occurs when the input to Q1
turns off at the same time that the
input to Q2 turns on. This case
determines the minimum delay
between LED1 turn-off and LED2
shunting the LED in the off state.
10
10
1.0
0.9
25
V
V
= 0.8 V
F
= V = 30 V
CC
O
8
6
4
20
15
10
5
0.8
0.7
0.6
0.5
0
V
= 0.6 V
I
V
= 10 mA
O
F
= 0.6 V
O
2
0
125 °C
25 °C
-55 °C
0
0
5
10
15
20
-60 -40 -20
0
20 40 60 80 100120140
-60 -40 -20
0
20 40 60 80 100120140
I
– FORWARD LED CURRENT – mA
T
– TEMPERATURE – °C
T
A
– TEMPERATURE – °C
F
A
Figure 1. Typical Transfer
Characteristics.
Figure 2. Normalized Output Current
vs. Temperature.
Figure 3. High Level Output Current
vs. Temperature.
1000
T
= 25°C
A
100
10
I
F
+
V
F
–
1.0
0.1
0.01
0.001
1.10 1.20
1.30
1.40
1.50
1.60
V
– FORWARD VOLTAGE – VOLTS
F
Figure 4. Input Current vs. Forward
Voltage.
1
8
7
20 k
Ω
0.1 µF
20 kΩ
I
=10 mA
5 V
F(ON)
+
+
2
3
4
I
–
f
V
= 15 V
t
t
r
CC
f
V
–
O
6
5
V
OUT
90%
10%
90%
10%
C *
L
V
V
THHL
THLH
SHIELD
*TOTAL LOAD CAPACITANCE
t
t
PLH
PHL
Figure 5. Propagation Delay Test Circuit.
11
1
2
8
7
0.1 µF
20 kΩ
20 kΩ
I
F
V
CM
+
V
= 15 V
CC
–
A
B
V
δV
δt
CM
∆t
=
3
4
6
5
V
OUT
100 pF*
OV
∆t
+
–
SHIELD
V
FF
*100 pF TOTAL
CAPACITANCE
V
O
V
V
CC
SWITCH AT A: I = 0 mA
F
V
O
+
OL
SWITCH AT B: I = 10 mA
F
V
= 1000 V
CM
Figure 6. CMR Test Circuit. Typical CMR Waveform.
600
600
800
I
V
= 10 mA
= 15 V
I
V
= 10 mA
= 15 V
F
CC
F
CC
I
V
= 10 mA
= 15 V
CL = 100 pF
RL = 20 kΩ (INTERNAL)
CL = 100 pF
RL = 20 kΩ (EXTERNAL)
F
500
400
500
400
CC
CL = 100 pF
= 25 °C
600
400
200
T
A
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PLH
PHL
300
200
100
300
200
100
20
RL – LOAD RESISTANCE – K Ω
0
10
30
40
50
-60 -40 -20
0
20 40 60 80 100120140
-60 -40 -20
0
20 40 60 80 100120140
T – TEMPERATURE – °C
A
T
– TEMPERATURE – °C
A
Figure 7. Propagation Delay with
External 20 kΩ RL vs. Temperature.
Figure 8. Propagation Delay with
Internal 20 kΩ RL vs. Temperature.
Figure 9. Propagation Delay vs. Load
Resistance.
1400
1400
1200
1000
800
I
= 10 mA
I
= 10 mA
= 15 V
F
F
CL = 100 pF
RL = 20 kΩ
T
V
CC
RL = 20 kΩ
1200
1000
800
= 25°C
T
= 25°C
A
A
t
t
PLH
PLH
t
t
PHL
PHL
600
600
400
400
200
0
200
0
5
10
15
20
25
30
0
100
200
300
400
500
V
– SUPPLY VOLTAGE – V
CL – LOAD CAPACITANCE – pF
CC
Figure 11. Propagation Delay vs.
Supply Voltage.
Figure 10. Propagation Delay vs. Load
Capacitance.
12
500
V
= 15 V
CC
t
t
PLH
PHL
CL = 100 pF
RL = 20 kΩ
T
= 25°C
400
300
200
100
A
0
5
10
15
20
I
– FORWARD LED CURRENT – mA
F
Figure 12. Propagation Delay vs. Input
Current.
1
8
7
1
2
8
7
20 kΩ
0.1 µF
20 kΩ
20 kΩ
C
LEDP
+
2
3
4
+5 V
310 Ω
CMOS
V
= 15 V
–
CC
6
5
V
3
4
6
5
OUT
C
LEDN
100 pF
SHIELD
SHIELD
*100 pF TOTAL
CAPACITANCE
Figure 13. Recommended LED Drive Circuit.
Figure 14. Optocoupler Input to
Output Capacitance Model for
Unshielded Optocouplers.
1
8
7
1
2
8
7
+5 V
20 kΩ
0.1 µF
20 kΩ
20 kΩ
C
LEDP
+
C
2
3
4
LED02
V
= 15 V
–
CC
310 Ω
C
LED01
6
5
V
3
4
6
5
OUT
C
LEDN
CMOS
100 pF
SHIELD
SHIELD
*100 pF TOTAL
CAPACITANCE
Figure 15. Optocoupler Input to
Output Capacitance Model for
Shielded Optocouplers.
Figure 16. LED Drive Circuit with Resistor Connected to LED Anode (Not
Recommended).
13
1
2
8
7
1
2
8
7
20
20
20 kΩ
I
I
TOTAL*
CLEDP
kΩ
kΩ
C
20 kΩ
LEDP
C
C
LED02
LED02
C
I
LEDP
F
300 Ω
C
C
LED01
LED01
I
CLED01
300 Ω
V
OUT
V
C
OUT
LEDN
3
4
6
5
3
4
6
5
C
LEDN
I
CLEDN*
100 pF
100 pF
+ V ** –
R
SHIELD
SHIELD
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dV /dt TRANSIENTS.
FLOW FOR +dV /dt TRANSIENTS.
CM
CM
** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH
+
PERFORMANCE.
V
< V
DURING +dV /dt.
R
F (OFF)
CM
V
CM
+
V
CM
Figure 17. AC Equivalent Circuit for
Figure 16 During Common Mode
Transients.
Figure 18. AC Equivalent Circuit for Figure 13 During
Common Mode Transients.
1
2
8
7
20
kΩ
C
20 kΩ
LEDP
C
LED02
1
8
C
LED01
+5 V
20 kΩ
V
C
Q1
OUT
LEDN
3
4
6
5
2
7
6
5
I
CLEDN*
100 pF
3
SHIELD
Q1
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
4
FLOW FOR +dV /dt TRANSIENTS.
CM
SHIELD
+
V
CM
Figure 19. Not Recommended Open Collector LED Drive
Circuit.
Figure 20. AC Equivalent Circuit for Figure 19 During
Common Mode Transients.
1
2
8
7
+5 V
20 kΩ
3
4
6
5
SHIELD
Figure 21. Recommended LED Drive
Circuit for Ultra High CMR.
14
HCPL-5300
1
2
8
7
V
CC1
0.1 µF
20 kΩ
IPM
I
LED1
20 kΩ
+5 V
+HV
V
310 Ω
CMOS
OUT1
3
4
6
5
Q1
Q2
M
SHIELD
HCPL-5300
HCPL-5300
1
2
8
7
V
CC2
-HV
0.1 µF
20 kΩ
HCPL-5300
HCPL-5300
HCPL-5300
HCPL-5300
I
LED2
20 kΩ
+5 V
310 Ω
CMOS
V
OUT2
3
4
6
5
SHIELD
Figure 22. Typical Application Circuit.
I
LED1
Q1 OFF
Q2 ON
Q1 ON
V
V
OUT1
OUT2
Q2 OFF
I
LED2
t
PLH MAX.
t
PHL
MIN.
PDD* MAX. =
(t
t
)
t
t
PLH- PHL MAX. = PLH MAX. - PHL MIN.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE
PDD ARE TAKEN AT EQUAL TEMPERATURES.
Figure 23. Minimum LED Skew for
Zero Dead Time.
15
I
LED1
MIL-PRF-38534 Class H,
Class K, and DSCC SMD
Test Program
Agilent Technologies’ Hi-Rel
Optocouplers are in compliance
with MIL-PRF-38534 Classes H
and K. Class H and Class K
Q1 OFF
Q2 ON
Q1 ON
V
V
OUT1
OUT2
Q2 OFF
I
LED2
devices are also in compliance
with DSCC drawing 5962-96852.
t
PLH
MIN.
t
PLH
MAX.
t
Testing consists of 100% screen-
ing and quality conformance
inspection to MIL-PRF-38534.
PHL
PDD*
MAX.
MIN.
t
PHL
MAX.
MAX.
DEAD TIME
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
= (t
= (t
t
) + (t
) - (t
t
)
PLH MAX. - PLH MIN.
PHL MAX. - PHL MIN.
t
t
)
PLH MAX. - PHL MIN.
PLH MIN. - PHL MAX.
= PDD* MAX. - PDD* MIN.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.
Figure 24. Waveforms for Dead Time Calculations.
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2000 Agilent Technologies
Obsoletes 5967-5808E
5968-9402E (10/00)
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