HCPL-530K [AVAGO]
Intelligent Power Module and Gate Drive Interface Hermetically Sealed Optocouplers; 智能功率模块和门驱动接口密封式光电耦合器
| 型号： | HCPL-530K |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | Intelligent Power Module and Gate Drive Interface Hermetically Sealed Optocouplers |
| 文件： | 总15页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-5300, HCPL-5301, HCPL-530K, 5962-96852
Intelligent Power Module and Gate Drive
Interface Hermetically Sealed Optocouplers
Data Sheet
Description
Features
The HCPL-530X devices consist of a GaAsP LED optically
coupled to an integrated high gain photo detector in a
hermetically sealed package. The products are capable of
operation and storage over the full military temperature
range and can be purchased as either standard product
or with full MIL-PRF-38534 Class Level H or K testing or
from the DLA Drawing 5962-96852. All devices are man-
ufactured and tested on a MIL-PRF-38534 certified line
and are included in the DLA Qualified Manufacturers
List QML-38534 for Hybrid Microcircuits. Minimized pro-
pagation delay difference between devices make these
optocouplers excellent solutions for improving inverter
Performance specified over full military temperature
Range: -55° C to +125° C
Fast maximum propagation delays
t
t
= 450ns,
= 650ns
PHL
PLH
Minimized pulse width distortion (PWD = 450 ns)
High common mode rejection (CMR): 10kV/s at V
=
CM
1000 V
CTR > 30% at I = 10mA
F
1500 Vdc withstand test voltage
efficiency through reduced switching dead time. An on Manufactured and tested on a MIL-PRF-38534 certified
chip 20 k output pull-up resistor can be enabled by
shorting output pins 6 and 7, thus eliminating the need
for an external pull-up resistor in common IPM applica-
tions. Specifications and performance plots are given for
typical IPM applications.
line
Hermetically sealed packages
Dual marked with device part number and DLA
drawing number
QML-38534, Class H and K
Schematic Diagram
HCPL-4506 function compatibility
Applications
1
2
8
7
20 k
Military and space
High reliability systems
Harsh industrial environments
Transportation, medical, and life critical systems
IPM isolation
3
4
6
5
SHIELD
Isolated IGBT/MOSFET gate drive
AC and brushless DC motor drives
Industrial inverters
Truth Table
LED
ON
OFF
V
O
L
H
The connection of a 0.1 F bypass capacitor between pins 5 and 8 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Selection Guide-Lead Configuration Options
Avago Part # and Options
Commercial
HCPL-5300
MIL-PRF-38534, Class H
MIL-PRF-38534, Class K
Standard Lead Finish
Solder Dipped*
HCPL-5301
HCPL-530K
Gold Plate
Option #200
Option #100
Option #300
Butt Cut/Gold Plate
Gull Wing/Soldered*
Class H SMD Part #
Prescript for all below
Gold Plate
5962-
9685201HPC
9685201HPA
9685201HYC
9685201HYA
9685201HXA
Solder Dipped*
Butt Cut/Gold Plate
Butt Cut/Soldered*
Gull Wing/Soldered*
Class K SMD Part #
Prescript for all below
Gold Plate
5962-
9685201KPC
9685201KPA
9685201KYC
9685201KYA
9685201KXA
Solder Dipped*
Butt Cut/Gold Plate
Butt Cut/Soldered*
Gull Wing/Soldered*
*Solder contains lead.
Outline Drawing
9.40 (0.370)
9.91 (0.390)
8.13 (0.320)
MAX.
0.76 (0.030)
1.27 (0.050)
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
2
Device Marking
Avago DESIGNATOR
Avago P/N
DLA SMD*
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DLA SMD*
COUNTRY OF MFR.
Avago CAGE CODE*
PIN ONE/
ESD IDENT
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on
commercial and hi-rel product in 8 pin DIP (see drawings below for details).
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
300
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in
8 pin DIP. DLA Drawing part numbers contain provisions for lead finish.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available
on commercial and hi-rel product in 8 pin DIP (see drawings below for details). This option has solder dipped leads.
4.57 (0.180)
MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
5° MAX.
1.40 (0.055)
1.07 (0.042)
1.32 (0.052)
1.65 (0.065)
9.65 (0.380)
9.91 (0.390)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Note: Solder contains lead.
3
Absolute Maximum Ratings
Parameter
Symbol
TS
Min.
-65
-55
Max.
Units
°C
Storage Temperature
Operating Temperature
Junction Temperature
Lead Solder Temperature
Average Input Current
+150
+125
+175
260 for 10 sec
25
TA
°C
TJ
°C
°C
IF(AVG)
mA
mA
Peak Input Current
IF(PEAK)
50
(50% duty cycle, ≤ 1 s pulse width)
Peak Transient Input Current
1.0
A
(≤ 1 s pulse width, 300 pps)
Reverse Input Voltage (Pin 3-2)
Average Output Current (Pin 6)
Resistor Voltage (Pin 7)
VR
5
V
IO(AVG)
V7
15
mA
V
-0.5
-0.5
-0.5
VCC
30
Output Voltage (Pin 6-5)
Supply Voltage (Pin 8-5)
Output Power Dissipation
Total Power Dissipation
VO
V
VCC
PO
30
V
100
145
mW
mW
PT
ESD Classification
(MIL-STD-883, Method 3015)
(
), Class 1
Recommended Operating Conditions
Parameter
Symbol
VCC
Min.
4.5
0
Max.
30
Units
Volts
Volts
mA
Power Supply Voltage
Output Voltage
VO
30
Input Current (ON)
Input Voltage (OFF)
IF(ON)
VF(OFF)
10
-5
20
0.8
V
4
Electrical Specifications
Over recommended operating conditions (T = -55° C to +125° C, V = +4.5 V to 30 V, I
= 10 mA to 20 mA,
A
CC
F(ON)
V
F(OFF)
= -5 V to 0.8 V) unless otherwise specified.
Group A
Subgroups
[12]
Parameter
Symbol
Min.
Typ.*
Max.
Units
Test Conditions Fig.
Note
Current Transfer Ratio
CTR
1, 2, 3
30
90
%
IF = 10 mA,
VO = 0.6 V
1
Low Level Output
Current
IOL
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
3.0
9.0
0.3
1.5
5
mA
V
IF = 10 mA,
VO = 0.6 V
1, 2
Low Level Output
Voltage
VOL
ITH
0.6
5.0
75
IO = 2.4 mA
Input Threshold
Current
mA
A
mA
mA
VO = 0.8 V,
IO = 0.75 mA
1
3
7
High Level Output
Current
IOH
ICCH
ICCL
VF = 0.8 V
High Level Supply
Current
0.6
0.6
1.5
1.5
1.8
VF = 0.8 V,
VO = Open
7
7
Low Level Supply
Current
IF = 10 mA,
V
O = Open
Input Forward Voltage
VF
1.0
5
1.5
V
IF = 10 mA
IF = 10 mA
4
Temperature Coefficient
of Forward Voltage
VF/TA
-1.6
mV/°C
Input Reverse
Breakdown Voltage
BVR
CIN
II-O
1, 2, 3
V
IR = 100 A
Input Capacitance
90
pF
A
f = 1 MHz,
VF = 0 V
Input-Output Insulation
Leakage Current
1
1.0
RH ≤ 65%,
t = 5 sec,
2
V
I-O = 1500 Vdc,
TA = 25° C
Resistance
(Input-Output)
RI-O
CI-O
1012
2.4
VI-O = 500 Vdc
2
Capacitance
(Input-Output)
pF
f = 1 MHz
TA = 25° C
2
Internal Pull-up Resistor
RL
1
14
20
28
k
4, 5, 6
Internal Pull-up Resistor
Temperature Coefficient
RL/TA
0.014
k/°C
*All typical values at 25° C, V = 15 V.
CC
5
Switching Specifications (R = 20 k External)
Over recommended operating conditions: (T = -55° C to +125° C, V = +4.5 V to 30 V, I
L
= 10 mA to 20mA,
A
CC
F(ON)
V
F(OFF)
= -5 V to 0.8 V) unless otherwise specified.
Group A
Subgrps.
[12]
Parameter
Symbol
Min. Typ.* Max. Units
Test Conditions
Fig.
Note
Propagation Delay
Time to Low
Output Level
tPHL
9, 10, 11
30
180
100
450
ns
ns
CL = 100 pF IF(on) = 10 mA, 5, 7,
3, 4, 5,
V
F(off) = 0.8 V,
VCC = 15.0 V,
THLH = 2.0 V,
9-12 6, 7
CL = 10 pF
V
Propagation Delay
Time to High
Output Level
tPLH
9, 10, 11
9, 10, 11
250
350
130
650
ns
CL = 100 pF
CL = 10 pF
VTHHL = 1.5 V
Pulse Width
Distortion
PWD
150
450
500
ns
ns
CL = 100 pF
11
8
Propagation Delay
Difference Between
Any Two Parts
tPLH -tPHL 9, 10, 11
-170 140
Output High Level
Common Mode
Immunity Transient
|CMH|
|CML|
9
9
10
10
17
17
kV/s
kV/s
IF = 0 mA,
VCC = 15.0 V,
CL = 100 pF,
6, 17, 9, 13
18, 21
V
O > 3.0 V
V
CM = 1000 VP-P
TA = 25° C
Output Low Level
Common Mode
IF = 10 mA
VO < 1.0 V
10, 13
Transient Immunity
*All typical values at 25° C, V = 15 V.
CC
6
Switching Specifications (R = Internal Pull-up)
L
Over recommended operating conditions: (T = -55°C to +125°C, V = +4.5 V to 30 V, I
= 10 mA to 20mA,
A
CC
F(ON)
V
F(OFF)
= -5 V to 0.8 V) unless otherwise specified.
Group A
Subgrps.
[12]
Parameter
Symbol
Min. Typ.* Max. Units
Test Conditions
Fig.
Note
Propagation Delay
Time to Low
Output Level
tPHL
9, 10, 11
20
185
415
150
500
ns
IF(on) = 10 mA,
VF(off) = 0.8 V,
VCC = 15.0 V,
CL = 100 pF,
VTHLH = 2.0 V
VTHHL = 1.5 V
5, 8,
3, 4, 5,
6, 7
Propagation Delay
Time to High
Output Level
tPLH
9, 10, 11
220
750
ns
Pulse Width Distortion PWD
9, 10, 11
600
650
ns
ns
11
8
Propagation Delay
Difference Between
Any Two Parts
tPLH -tPHL 9, 10, 11
-225 150
Output High Level
Common Mode
Transient Immunity
|CMH|
|CML|
PSR
10
10
1.0
kV/s
kV/s
VP-P
IF = 0 mA,
VO > 3.0 V
VCC = 15.0 V,
CL = 100 pF,
6, 21
9
V
CM = 1000 VP-P
TA = 25° C
Output Low Level
Common Mode
Transient Immunity
IF = 16 mA
10
7
V
O < 1.0 V
Power Supply
Rejection
Square Wave, tRISE, tFALL > 5 ns,
no bypass capacitors.
*All typical values at 25° C, V = 15 V.
CC
Notes:
1. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (I ) to the forward LED input current (I ) times 100.
O
F
2. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together and Pins 5, 6, 7 and 8 shorted together.
3. Pulse: f = 20 kHz, Duty Cycle = 10%
4. The internal 20 k resistor can be used by shorting pins 6 and 7 together.
5. Due to the tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can be improved
by using an external 20 k 1% load resistor. For more information on how propagation delay varies with load resistance, see Figure 8.
6. The R = 20 k, C = 100 pF represents a typical IPM (Intelligent Power Module) load.
L
L
7. Use of a 0.1 F bypass capacitor connected between pins 5 and 8 can improve performance by filtering power supply line noise.
8. The difference in t
section.)
and t
between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay Specifications
PHL
PLH
9. Common mode transient immunity in a Logic High level is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the
CM
CM
output will remain in a Logic High state (i.e., V > 3.0 V).
O
10. Common mode transient immunity in a Logic Low level is the maximum tolerable dV /dt of the common mode pulse, V , to assure that the
CM
CM
output will remain in a Logic Low state (i.e., V < 1.0 V).
11. Pulse Width Distortion (PWD) is defined as the difference between t
O
and t
for any given device.
PHL
PLH
12. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). Hi-Rel and SMD parts receive 100% testing at 25° C, +125° C, and -55° C (Subgroups
1 and 9, 2 and 10, 3 and 11 respectively).
13. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified
for all lots not specifically tested.
7
LED Drive Circuit Considerations For Ultra High CMR
Performance
CMR With The LED On (CMR )
L
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriv-
ing the LED current beyond the input threshold so that
it is not pulled below the threshold during a transient.
The recommended minimum LED current of 10 mA
provides adequate margin over the maximum I of
5.0mA (see Figure 1) to achieve 10kV/s CMR. Capacitive
coupling is higher when the internal load resistor is used
Without a detector shield, the dominant cause of opto-
coupler CMR failure is capacitive coupling from the
input side of the optocoupler, through the package, to
the detector IC as shown in Figure 14. The HCPL-530X
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts
the capacitively coupled current away from the sensitive
IC circuitry. However, this shield does not eliminate the
capacitive coupling between the LED and the optocoupler
output pins and output ground as shown in Figure 15.
This capacitive coupling causes perturbations in the LED
current during common mode transients and becomes
the major source of CMR failures for a shielded opto-
coupler. The main design objective of a high CMR LED
drive circuit becomes keeping the LED in the proper state
(on or off) during common mode transients. For example,
the recommended application circuit (Figure 13), can
achieve 10 kV/s CMR while minimizing component com-
plexity. Note that a CMOS gate is recommended in Figure
13 to keep the LED off when the gate is in the high state.
TH
(due to C
) and an I = 16 mA is required to obtain
LEDO2
F
10 kV/s CMR.
The placement of the LED current setting resistor affects
the ability of the drive circuit to keep the LED on during
transients and interacts with the direct coupling to the
optocoupler output. For example, the LED resistor in
Figure 16 is connected to the anode. Figure 17 shows the
AC equivalent circuit for Figure 16 during common mode
transients. During a +dV
in Figure 17, the current
) is limited by the series
CM/dt
available at the LED anode (I
TOTAL
resistor. The LED current (I ) is reduced from its DC value
F
by an amount equal to the current that flows through
C
and C
. The situation is made worse because
LEDO1
LEDP
the current through C
has the effect of trying to pull
LEDO1
Another cause of CMR failure for a shielded optocoupler
is direct coupling to the optocoupler output pins through
the output high (toward a CMR failure) at the same time
the LED current is being reduced. For this reason, the rec-
ommended LED drive circuit (Figure 13) places the current
setting resistor in series with the LED cathode. Figure 18
is the AC equivalent circuit for Figure 13 during common
mode transients. In this case, the LED current is not
reduced during a +dV
flowing through the package capacitance is supplied by
the power supply. During a -dV transient, however,
C
and C
in Figure 15. Many factors influence the
LEDO1
LEDO2
effect and magnitude of the direct coupling including: the
use of an internal or external output pull-up resistor, the
position of the LED current setting resistor, the connec-
tion of the unused input package pins, and the value of
the capacitor at the optocoupler output (CL).
transient because the current
CM/dt
Techniques to keep the LED in the proper state and
minimize the effect of the direct coupling are discussed in
the next two sections.
CM/dt
the LED current is reduced by the amount of current
flowing through C . But better CMR performance is
LEDN
achieved since the current flowing in C
during a
LEDO1
negative transient acts to keep the output low.
Coupling to the LED and output pins is also affected by the
connection of pins 1 and 4. If CMR is limited by perturba-
tions in the LED on current, as it is for the recommended
drive circuit (Figure 13), pins 1 and 4 should be connected
to the input circuit common. However, if CMR perfor-
mance is limited by direct coupling to the output when the
LED is off, pins 1 and 4 should be left unconnected.
8
CMR With The LED Off (CMR )
IPM Dead Time and Propagation Delay Specifications
H
A high CMR LED drive circuit must keep the LED off
These devices include a Propagation Delay Difference
(V ≤ V
example, during a +dV
) during common mode transients. For specification intended to help designers minimize “dead
F
F(OFF)
transient in Figure 18, the time”in their power inverter designs. Dead time is the time
CM/dt
current flowing through C
combination of the LED and series resistor. As long as the
voltage developed across the resistor is less than V
is supplied by the parallel period during which both the high and low side power
LEDN
transistors (Q1 and Q2 in Figure 22) are off. Any overlap in
Q1 and Q2 conduction will result in large currents flowing
through the power devices between the high and low
F(OFF)
the LED will remain off and no common mode failure will
occur. Even if the LED momentarily turns on, the 100 pF voltage motor rails.
capacitor from pins 6-5 will keep the output from dipping
To minimize dead time the designer must consider the
below the threshold. The recommended LED drive circuit
(Figure 13) provides about 10 V of margin between
the lowest optocoupler output voltage and a 3 V IPM
propagation delay characteristics of the optocoupler
as well as the characteristics of the IPM IGBT gate drive
circuit. Considering only the delay characteristics of the
optocoupler (the characteristics of the IPM IGBT gate drive
circuit can be analyzed in the same way) it is important
threshold during a 10 kV/s transient with V =1000 V.
CM
Additional margin can be obtained by adding a diode
in parallel with the resistor, as shown by the dashed line
connection in Figure 18, to clamp the voltage across the
to know the minimum and maximum turn-on (t ) and
PHL
turn-off (t ) propagation delay specifications, preferably
PLH
LED below V
.
F(OFF)
over the desired operating temperature range.
Since the open collector drive circuit, shown in Figure 19,
cannot keep the LED off during a +dV transient, it is
The limiting case of zero dead time occurs when the input
to Q1 turns off at the same time that the input to Q2 turns
on. This case determines the minimum delay between
LED1 turn-off and LED2 turn-on, which is related to the
worst case optocoupler propagation delay waveforms,
as shown in Figure 23. A minimum dead time of zero is
achieved in Figure 23 when the signal to turn on LED2
CM/dt
not desirable for applications requiring ultra high CMR
H
performance. Figure 20 is the AC equivalent circuit for
Figure16 during common mode transients. Essentially
all the current flowing through C
during a +dV
LEDN
CM/dt
transient must be supplied by the LED. CMR failures can
H
occur at dv/dt rates where the current through the LED
is delayed by (t
- t
) from the LED1 turn off.
PLHmax
PHLmin
and C
exceeds the input threshold. Figure 21 is an
LEDN
This delay is the maximum value for the propagation
delay difference specification which is specified at 500 ns
for the HCPL-530X over an operating temperature range
of -55° C to +125° C.
alternative drive circuit which does achieve ultra high
CMR performance by shunting the LED in the off state.
Delaying the LED signal by the maximum propagation
delay difference ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time occurs in
the highly unlikely case where one optocoupler with the
fastest t
and another with the slowest t
are in the
PLH
PHL
same inverter leg. The maximum dead time in this case
becomes the sum of the spread in the t and t pro-
PLH
PHL
pagation delays as shown in Figure 24. The maximum
dead time is also equivalent to the difference between the
maximum and minimum propagation delay difference
specifications. The maximum dead time (due to the opto-
couplers) for the HCPL-530X is 670 ns (= 500 ns - (-170 ns))
over an operating temperature range of -55° C to +125° C.
9
10
1.0
0.9
8
6
4
0.8
0.7
0.6
0.5
0
I
V
= 10 mA
V
= 0.6 V
F
O
= 0.6 V
O
2
0
125°C
25°C
-55°C
0
5
10
15
20
-60 -40 -20
0 20 40 60 80 100120140
I
– FORWARD LED CURRENT – mA
T
A
– TEMPERATURE – °C
F
Figure 1. Typical transfer characteristics
Figure 2. Normalized output current vs. temperature
1000
25
T
= 25°C
A
V
V
= 0.8 V
F
= V = 30 V
CC
O
100
10
20
15
10
5
I
F
+
V
F
–
1.0
0.1
0.01
0.001
0
1.10 1.20
1.30
1.40
1.50
1.60
-60 -40 -20
0
20 40 60 80 100120140
V
– FORWARD VOLTAGE – VOLTS
T
A
– TEMPERATURE – °C
F
Figure 3. High level output current vs. temperature
Figure 4. Input current vs. forward voltage
1
2
8
7
20 k:
0.1 μF
20 k:
I
=10 mA
5 V
F(ON)
+
+
I
f
–
V
= 15 V
t
t
r
CC
f
V
–
O
3
4
6
5
V
OUT
90%
10%
90%
10%
C *
L
V
V
THHL
THLH
SHIELD
*TOTAL LOAD CAPACITANCE
t
t
PLH
PHL
Figure 5. Propagation delay test circuit
10
1
2
8
7
0.1 μF
20 k:
20 k:
I
F
V
CM
+
V
= 15 V
CC
–
A
B
V
GV
Gt
CM
't
=
3
4
6
5
V
OUT
100 pF*
OV
't
+
–
SHIELD
V
FF
*100 pF TOTAL
CAPACITANCE
V
O
V
V
CC
OL
SWITCH AT A: I = 0 mA
F
V
O
+
SWITCH AT B: I = 10 mA
F
V
= 1000 V
CM
Figure 6. CMR test circuit. Typical CMR waveform
600
600
I
V
= 10 mA
= 15 V
I
V
= 10 mA
= 15 V
F
CC
F
CC
CL = 100 pF
RL = 20 k: (INTERNAL)
CL = 100 pF
RL = 20 k: (EXTERNAL)
500
400
500
400
t
t
t
t
PLH
PHL
PLH
PHL
300
200
100
300
200
100
-60 -40 -20
0
20 40 60 80 100120140
-60 -40 -20
0
20 40 60 80 100120140
T – TEMPERATURE – °C
A
T
– TEMPERATURE – °C
A
Figure 7. Propagation delay with external 20 k RL vs. temperature
Figure 8. Propagation delay with internal 20 k RL vs. temperature
1400
800
I
= 10 mA
= 15 V
F
V
CC
RL = 20 k:
= 25°C
1200
1000
800
I
= 10 mA
= 15 V
F
T
A
V
CC
CL = 100 pF
= 25 °C
600
400
200
t
t
PLH
PHL
T
A
t
t
PLH
PHL
600
400
200
0
20
RL – LOAD RESISTANCE – K:
0
10
30
40
50
0
100
200
300
400
500
CL – LOAD CAPACITANCE – pF
Figure 9. Propagation delay vs. load resistance
Figure 10. Propagation delay vs. load capacitance
11
500
1400
1200
1000
800
I
= 10 mA
V
= 15 V
CC
F
t
t
PLH
PHL
CL = 100 pF
RL = 20 k:
T
CL = 100 pF
RL = 20 k:
T = 25°C
A
= 25°C
A
400
300
200
100
t
t
PLH
PHL
600
400
200
0
5
10
15
20
25
30
0
5
10
15
20
V
– SUPPLY VOLTAGE – V
I
– FORWARD LED CURRENT – mA
CC
F
Figure 11. Propagation delay vs. supply voltage
Figure 12. Propagation delay vs. input current
1
8
7
1
8
7
20 k:
0.1 μF
20 k:
20 k:
C
LEDP
+
–
2
3
4
2
3
4
+5 V
310 :
CMOS
V
= 15 V
CC
6
5
V
6
5
OUT
C
LEDN
100 pF
SHIELD
*100 pF TOTAL
CAPACITANCE
Figure 13. Recommended LED drive circuit
Figure 14. Optocoupler input to output
capacitance model for unshielded optocouplers
1
2
8
7
1
2
8
7
+5 V
20 k:
20 k:
0.1 μF
20 k:
C
LEDP
+
C
LED02
V
= 15 V
–
CC
310 :
C
LED01
3
4
6
5
3
4
6
5
V
OUT
C
LEDN
CMOS
100 pF
SHIELD
SHIELD
*100 pF TOTAL
CAPACITANCE
Figure 15. Optocoupler input to output
Figure 16. LED drive circuit with resistor connected to LED anode (not recommended)
capacitance model for shielded optocouplers
12
1
2
8
7
20
k
1
2
8
7
C
20 k
LEDP
C
C
LED02
20
20 k
I
I
TOTAL*
CLEDP
C
k
C
LED01
C
LED02
300
V
OUT
I
LEDP
F
LEDN
300
C
3
4
6
5
LED01
I
I
CLED01
CLEDN*
V
100 pF
OUT
3
4
6
5
+ V ** –
R
C
LEDN
100 pF
SHIELD
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
SHIELD
FLOW FOR +dV /dt TRANSIENTS.
CM
** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
PERFORMANCE.
V
< V
DURING +dV /dt.
R
F (OFF)
CM
FLOW FOR +dV /dt TRANSIENTS.
CM
+
+
V
V
CM
CM
Figure 17. AC equivalent circuit for Figure 16 during common mode transients
Figure 18. AC equivalent circuit for Figure 13 during common mode transients
1
2
8
7
20
k
C
20 k
LEDP
C
C
LED02
1
2
8
7
C
LED01
+5 V
20 k
V
Q1
OUT
LEDN
3
4
6
5
I
CLEDN*
100 pF
3
4
6
5
SHIELD
Q1
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dV /dt TRANSIENTS.
CM
SHIELD
+
V
CM
Figure 20. AC equivalent circuit for Figure 19 during common mode transients
Figure 19. Not recommended open collector LED drive circuit
1
2
8
7
+5 V
20 k
3
4
6
5
SHIELD
Figure 21. Recommended LED drive circuit for ultra high CMR
13
HCPL-5300
1
2
8
7
V
CC1
0.1 μF
20 k
IPM
I
LED1
20 k
+5 V
+HV
V
310
CMOS
OUT1
3
4
6
5
Q1
Q2
M
SHIELD
HCPL-5300
HCPL-5300
1
2
8
7
V
CC2
-HV
0.1 μF
20 k
HCPL-5300
HCPL-5300
HCPL-5300
HCPL-5300
I
LED2
20 k
+5 V
310
CMOS
V
OUT2
3
4
6
5
SHIELD
Figure 22. Typical application circuit
I
LED1
Q1 OFF
Q2 ON
Q1 ON
V
V
OUT1
OUT2
Q2 OFF
I
LED2
t
PLH MAX.
t
PHL
MIN.
PDD* MAX. =
(t
t
)
t
t
PLH- PHL MAX. = PLH MAX. - PHL MIN.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE
PDD ARE TAKEN AT EQUAL TEMPERATURES.
Figure 23. Minimum LED skew for zero dead time
14
I
LED1
MIL-PRF-38534 Class H, Class K, and
DLA SMD Test Program
Q1 OFF
Q2 ON
Q1 ON
Avago Technologies’ Hi-Rel Optocouplers are in compli-
ance with MIL-PRF-38534 Classes H and K. Class H and
Class K devices are also in compliance with DLA drawing
5962-96852.
V
V
OUT1
OUT2
Q2 OFF
I
LED2
t
Testing consists of 100% screening and quality confor-
mance inspection to MIL-PRF-38534.
PLH
MIN.
t
PLH
MAX.
t
PHL
PDD*
MAX.
MIN.
t
PHL
MAX.
MAX.
DEAD TIME
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
= (t
t
) + (t
t
)
PHL MIN.
PLH MAX.
-
-
PLH MIN.
PHL MAX.
-
t
= (t
t
) - (t
)
PLH MAX.
PHL MIN.
PLH MIN.
-
PHL MAX.
= PDD* MAX. - PDD* MIN.
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.
Figure 24. Waveforms for dead time calculations
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5968-9402EN
AV02-3839EN - October 10, 2012
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