EVAL-ADF7020-1DBZ8_技术文档

High Performance

FSK/ASK Transceiver IC

ADF7020-1

Data Sheet

On-chip VCO and fractional-N PLL

FEATURES

On-chip 7-bit ADC and temperature sensor

Fully automatic frequency control loop (AFC) compensates

for lower tolerance crystals

Digital RSSI

Integrated TRx switch

Low power, low IF transceiver

Frequency bands

135 MHz to 650 MHz, direct output

80 MHz to 325 MHz, divide-by-2 mode

Data rates supported

Leakage current <1 µA in power-down mode

0.15 kbps to 200 kbps, FSK

0.15 kbps to 64 kbps, ASK

2.3 V to 3.6 V power supply

Programmable output power

−20 dBm to +13 dBm in 63 steps

Receiver sensitivity

−119 dBm at 1 kbps, FSK, 315 MHz

−114 dBm at 9.6 kbps, FSK, 315 MHz

−111.8 dBm at 9.6 kbps, ASK, 315 MHz

Low power consumption

APPLICATIONS

Low cost wireless data transfer

Wireless medical applications

Remote control/security systems

Wireless metering

Keyless entry

Home automation

Process and building control

17.6 mA in receive mode

21 mA in transmit mode (10 dBm output)

FUNCTIONAL BLOCK DIAGRAM

RSET

CREG(1:4)

LDO(1:4)

ADCIN

MUXOUT

TEMP

R

POLARIZATION

TEST MUX

LNA

OFFSET

SENSOR

MUX

CORRECTION

LNA

FSK/ASK

DATA

SYNCHRONIZER

R

FIN

DEMODULATOR

7-BIT ADC

RSSI

IF FILTER

R

FINB

GAIN

OFFSET

CORRECTION

CE

AGC

CONTROL

DATA CLK

DATA I/O

Tx/Rx

CONTROL

FSK MOD

CONTROL

GAUSSIAN

FILTER

Σ-∆

MODULATOR

AFC

INT/LOCK

CONTROL

DIVIDERS/

MUXING

DIV P

N/N+1

RFOUT

SLE

SDATA

SREAD

SCLK

SERIAL

PORT

VCO

CP

PFD

CLK

DIV

DIV R

RING OSC

L1 L2 VCOIN CPOUT

OSC1 OSC2

CLKOUT

Figure 1.

Rev. A

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ADF7020-1

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Transmit Protocol and Coding Considerations ..................... 26

Device Programming after Initial Power-Up ......................... 26

Interfacing to Microcontroller/DSP ........................................ 26

Serial Interface ................................................................................ 29

Readback Format........................................................................ 29

Register 0—N Register............................................................... 30

Register 1—Oscillator/Filter Register...................................... 31

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Typical Performance Characteristics ........................................... 13

Frequency Synthesizer ................................................................... 15

Reference Input........................................................................... 15

Choosing Channels for Best System Performance................. 17

Transmitter ...................................................................................... 18

RF Output Stage.......................................................................... 18

Modulation Schemes.................................................................. 18

Receiver Section.............................................................................. 20

RF Front End............................................................................... 20

RSSI/AGC.................................................................................... 21

FSK Demodulators on the ADF7020-1 ................................... 21

FSK Correlator/Demodulator................................................... 21

Linear FSK Demodulator .......................................................... 23

AFC Section ................................................................................ 23

Automatic Sync Word Recognition ......................................... 24

Applications..................................................................................... 25

LNA/PA Matching...................................................................... 25

REVISION HISTORY

Register 2—Transmit Modulation Register (ASK/OOK

Mode)........................................................................................... 32

Register 2—Transmit Modulation Register (FSK Mode) ..... 33

Register 2—Transmit Modulation Register (GFSK/GOOK

Mode)........................................................................................... 34

Register 3—Receiver Clock Register ....................................... 35

Register 4—Demodulator Set-up Register.............................. 36

Register 5—Sync Byte Register................................................. 37

Register 6—Correlator/Demodulator Register ...................... 38

Register 7—Readback Set-up Register .................................... 39

Register 8—Power-Down Test Register .................................. 40

Register 9—AGC Register......................................................... 41

Register 10—AGC 2 Register.................................................... 42

Register 11—AFC Register ....................................................... 42

Register 12—Test Register......................................................... 43

Register 13—Offset Removal and Signal Gain Register ....... 44

Outline Dimensions....................................................................... 45

Ordering Guide .......................................................................... 45

1/2018—Rev. 0 to Rev. A

Changed CP-48-3 to CP-48-5 ...................................... Throughout

Changes to Figure 6 and Table 4................................................... 11

Updated Outline Dimensions....................................................... 45

Changes to Ordering Guide .......................................................... 45

12/2005—Revision 0: Initial Version

Rev. A | Page 2 of 45

Data Sheet

ADF7020-1

GENERAL DESCRIPTION

The ADF7020-1 is a low power, highly integrated FSK/GFSK/

ASK/OOK/GOOK transceiver designed for operation in the

low UHF and VHF bands. The ADF7020-1 uses an external

VCO inductor that allows users to set the operating frequency

anywhere between 135 MHz and 650 MHz. Using the divide-

by-2 circuit allows users to operate the device as low as 80 MHz.

The typical range of the VCO is about 10% of the operating

frequency. A complete transceiver can be built using a small

number of external discrete components, making the ADF7020-

1 very suitable for price-sensitive and area-sensitive

applications.

A low IF architecture is used in the receiver (200 kHz),

minimizing power consumption and the external component

count and avoiding interference problems at low frequencies.

The ADF7020-1 supports a wide variety of programmable

features, including Rx linearity, sensitivity, and IF bandwidth,

allowing the user to trade off receiver sensitivity and selectivity

for current consumption, depending on the application. The

receiver also features a patent-pending automatic frequency

control (AFC) loop, allowing the PLL to compensate for

frequency error in the incoming signal.

An on-chip ADC provides readback of an integrated tempera-

ture sensor, an external analog input, the battery voltage, or the

RSSI signal, which provides savings on an ADC in some

applications. The temperature sensor is accurate to 10°C over

the full operating temperature range of −40°C to +85°C. This

accuracy can be improved by doing a 1-point calibration at

room temperature and storing the result in memory.

The transmit section contains a VCO and low noise

fractional-N PLL with output resolution of <1 ppm. This

frequency agile PLL allows the ADF7020-1 to be used in

frequency-hopping spread spectrum (FHSS) systems. The VCO

operates at twice the fundamental frequency to reduce spurious

emissions and frequency pulling problems.

The transmitter output power is programmable in 63 steps from

−20 dBm to +13 dBm. The transceiver RF frequency, channel

spacing, and modulation are programmable using a simple 3-

wire interface. The device operates with a power supply range of

2.3 V to 3.6 V and can be powered down when not in use.

Rev. A | Page 3 of 45

ADF7020-1

Data Sheet

SPECIFICATIONS

V_DD= 2.3 V to 3.6 V, GND = 0 V, T_A= T_MINto T_MAX, unless otherwise noted. Typical specifications are at V_DD= 3 V, T_A= 25°C.

All measurements are performed using the EVAL-ADF7020-1-DBX and PN9 data sequence, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions

RF CHARACTERISTICS

Frequency Ranges (Direct Output)

135

80

650

325

MHz

See Table 5 for VCO bias settings at different

frequencies

Frequency Ranges

(Divide-by-2 Mode)

VCO Frequency Range

Phase Frequency Detector Frequency RF/256

1.1

1.2

Ratio

MHz

F_MAX/F_MIN, using VCO bias settings in Table 5

PFD must be less than direct output

frequency/31

20.96

TRANSMISSION PARAMETERS

Data Rate

FSK/GFSK

OOK/ASK

0.15

0.3

200

64¹

100

kbps

kbaud

Using Manchester biphase-L encoding

Frequency Shift Keying

GFSK/FSK Frequency Deviation^{2, 3}

1

4.88

100

110

620

kHz

Hz

PFD = 3.625 MHz

PFD = 20 MHz

PFD = 3.625 MHz

Deviation Frequency Resolution

Gaussian Filter BT

0.5

Amplitude Shift Keying

ASK Modulation Depth

OOK-PA Off Feedthrough

Transmit Power⁴

Transmit Power

Transmit Power Variation vs. Temp.

Transmit Power Variation vs. V_DD

30

dB

−50

dBm

dB

−20

+13

+11

V_DD= 3.0 V, T_A= 25°C, FRF > 200 MHz

V_DD= 3.0 V, T_A= 25°C, FRF < 200 MHz

From −40°C to +85°C

1

dB

From 2.3 V to 3.6 V at 315 MHz, T_A= 25°C

Programmable Step Size

−20 dBm to +13 dBm

0.3125

dB

See Figure 13 for how output power varies

with PA setting

Integer Boundary

Reference

−55

−65

dBc

50 kHz loop BW

Harmonics

Second Harmonic

Third Harmonic

All Other Harmonics

VCO Frequency Pulling, OOK Mode

Optimum PA Load Impedance⁵

−27

−21

−35

30

79.4 + j64

109 + j64

40 + j47.5

dBc

Unfiltered conductive

kHz rms DR = 9.6 kbps

FRF = 140 MHz

FRF = 320 MHz

FRF = 590 MHz

Rev. A | Page 4 of 45

Data Sheet

ADF7020-1

Parameter

Min

Typ

Max

Unit

Test Conditions

RECEIVER PARAMETERS

FSK/GFSK Input Sensitivity

At BER = 1E − 3, FRF = 315 MHz,

LNA and PA matched separately⁶

Sensitivity at 1 kbps

Sensitivity at 9.6 kbps

OOK Input Sensitivity

Sensitivity at 1 kbps

Sensitivity at 9.6 kbps

LNA and Mixer, Input IP3⁷

Enhanced Linearity Mode

Low Current Mode

−119.2

−114.2

dBm

FDEV= 5 kHz, high sensitivity mode⁷

FDEV = 10 kHz, high sensitivity mode

At BER = 1E − 3, FRF = 315 MHz

High sensitivity mode

−118.2

−111.8

dBm

High sensitivity mode

6.8

−3.2

−35

dBm

Pin = −20 dBm, 2 CW interferers,

FRF = 315 MHz, F1 = FRF + 3 MHz,

F2 = FRF + 6 MHz, maximum gain

High Sensitivity Mode

Rx Spurious Emissions⁸

−57

−47

<1 GHz at antenna input

>1 GHz at antenna input

AFC

Pull-In Range

Response Time

Accuracy

50

48

1

kHz

Bits

kHz

IF_BW = 200 kHz

Modulation index = 0.875

CHANNEL FILTERING

Adjacent Channel Rejection

(Offset = 1 × IF Filter BW

Setting)

Second Adjacent Channel Rejection

(Offset = 2 × IF Filter BW

Setting)

Third Adjacent Channel Rejection

(Offset = 3 × IF Filter BW

Setting)

27

50

55

dB

IF filter BW settings = 100 kHz, 150 kHz,

200 kHz; desired signal 3 dB above the input

sensitivity level; CW interferer power level

increased until BER = 10⁻³; image channel

excluded

Image Channel Rejection

CO-CHANNEL REJECTION

Wideband Interference Rejection

35

−2

70

dB

Image at FRF − 400 kHz

Swept from 100 MHz to 2 GHz, measured as

channel rejection

BLOCKING

1 MHz

Desired signal 3 dB above the input sensitivity

level, CW interferer power level increased

until BER = 10⁻²

60

dB

5 MHz

10 MHz

68

65

72

12

dB

dBm

Ω

10 MHz (High Linearity Mode)

Saturation (Maximum Input Level)

LNA Input Impedance

FSK mode, BER = 10⁻³

FRF = 130 MHz, RFIN to GND

FRF = 310 MHz

237 − j193

101.4 − j161.6

49.3 − j104.6

Ω

FRF = 610 MHz

RSSI

Range at Input

Linearity

Absolute Accuracy

Response Time

−100 to −36

2

3

dBm

dB

150

µs

See the RSSI/AGC section

Rev. A | Page 5 of 45

ADF7020-1

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions

PHASE-LOCKED LOOP

VCO Gain

40

MHz/V

dBc/Hz

433 MHz, VCO adjust = 0,

VCO_BIAS_SETTING = 2

315 MHz, VCO adjust = 0,

VCO_BIAS_SETTING = 2

135 MHz, VCO adjust = 0,

VCO_BIAS_SETTING = 1

PA = 0 dBm, V_DD= 3.0 V, PFD = 10 MHz,

FRF = 315 MHz, VCO_BIAS_SETTING = 2

35

16.5

−89

−198

Phase Noise (In-Band)

Normalized In-Band Phase Noise

Floor ⁹

Phase Noise (Out-of-Band)

Residual FM

PLL Settling

−110

128

40

dBc/Hz

Hz

µs

1 MHz offset

From 200 Hz to 20 kHz, FRF = 315 MHz

Measured for a 10 MHz frequency step to

within 5 ppm accuracy, PFD = 20 MHz,

LBW = 50 kHz

REFERENCE INPUT

Crystal Reference

External Oscillator

Load Capacitance

Crystal Start-Up Time

3.625

24

MHz

pF

Must ensure PFD maximum is not exceeded

Refer to the crystal’s data sheet

11.0592 MHz crystal, using 33 pF load

capacitors

33

2.1

ms

1.0

ms

Using 16 pF load capacitors

Input Level

CMOS

levels

See the Reference Input section

ADC PARAMETERS

INL

DNL

1

LSB

From 2.3 V to 3.6 V, T_A= 25°C

TIMING INFORMATION

Chip Enabled to Regulator Ready

Chip Enabled to RSSI Ready

Tx-to-Rx Turnaround Time

10

3.0

150 µs +

(5 × T_BIT)

µs

ms

C_REG= 100 nF

See Table 13 for more details

Time to synchronized data out, includes

AGC settling. See AGC Information and

Timing section for more details.

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_INH/I_INL

Input Capacitance, C_IN

Control Clock Input

LOGIC OUTPUTS

0.7 × V _DD

V

µA

pF

MHz

0.2 × V _DD

1

10

50

Output High Voltage, V_OH

Output Low Voltage, V_OL

CLKOUT Rise/Fall

DV_DD− 0.4

V

ns

pF

°C

I_OH= 500 µA

I_OL= 500 µA

0.4

5

10

+85

CLKOUT Load

TEMPERATURE RANGE—T_A

−40

Rev. A | Page 6 of 45

Data Sheet

ADF7020-1

Parameter

Min

Typ

Max

Unit

Test Conditions

POWER SUPPLIES

Voltage Supply

V_DD

2.3

3.6

V

All V_DDpins must be tied together

Transmit Current Consumption

FRF = 315 MHz, V_DD= 3.0 V, PA is matched

to 50 Ω

433 MHz, 0 dBm/5 dBm/10 dBm

Receive Current Consumption

Low Current Mode

13/16/21

mA

VCO_BIAS_SETTING = 2

17.6

20.1

mA

VCO_BIAS_SETTING = 2

High Sensitivity Mode

Power-Down Mode

Low Power Sleep Mode

0.1

1

μA

¹Higher data rates are achievable, depending on local regulations.

²For definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section.

³For definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section.

⁴Measured as maximum unmodulated power. Output power varies with both supply and temperature.

⁵For matching details, see the LNA/PA Matching section.

⁶Sensitivity for combined matching network case is typically 2 dB less than separate matching networks. See Table 11 for sensitivity values at various data rates and

frequencies.

⁷See Table 6 for a description of different receiver modes.

⁸Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.

⁹This figure can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise

performance as seen at the PA output: –198 + 10 log(fPFD) + 20 log N.

Rev. A | Page 7 of 45

ADF7020-1

Data Sheet

TIMING CHARACTERISTICS

V_DD= 3 V ꢀ1%, VGND = 1 V, T_A= 25°C, unless otherwise noted. Guaranteed by design, but not production tested.

Table 2.

Parameter

Limit at T_MINto T_MAX

Unit

ns

Test Conditions/Comments

SDATA-to-SCLK set-up time

SDATA-to-SCLK hold time

SCLK high duration

SCLK low duration

SCLK-to-SLE set-up time

t₁

t₂

t₃

t₄

t₅

t₆

t₈

t₉

t₁₀

<10

<25

<10

<20

<25

<10

SLE pulse width

SCLK-to-SREAD data valid, readback

SREAD hold time after SCLK, readback

SCLK-to-SLE disable time, readback

ns

t₃

t₄

SCLK

t₁

t₂

DB1

DB0 (LSB)

(CONTROL BIT C1)

SDATA

SLE

DB31 (MSB)

DB30

DB2

(CONTROL BIT C2)

t₆

t₅

Figure 2. Serial Interface Timing Diagram

t₁

t₂

SCLK

SDATA

SLE

REG7 DB0

(CONTROL BIT C1)

t₃

t₁₀

X

RV16

RV15

RV2

RV1

SREAD

t₉

t₈

Figure 3. Readback Timing Diagram

Rev. A | Page 8 of 45

Data Sheet

ADF7020-1

±1 × DATA RATE/32

1/DATA RATE

RxCLK

RxDATA

DATA

Figure 4. RxData/RxCLK Timing Diagram

1/DATA RATE

TxCLK

DATA

TxDATA

FETCH

SAMPLE

NOTES

1. TxCLK ONLY AVAILABLE IN GFSK MODE.

Figure 5. TxData/TxCLK Timing Diagram

Rev. A | Page 9 of 45

ADF7020-1

Data Sheet

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 3.

Parameter

V_DDto GND¹

Rating

−0.3 V to +5 V

−0.3 V to AV_DD+ 0.3 V

−0.3 V to DV_DD+ 0.3 V

Analog I/O Voltage to GND

Digital I/O Voltage to GND

Operating Temperature Range

Industrial (B Version)

Storage Temperature Range

Maximum Junction Temperature

MLF θ_JAThermal Impedance

Reflow Soldering

This device is a high performance RF-integrated circuit with an

ESD rating of <2 kV. It is ESD sensitive; proper precautions

should be taken for handling and assembly.

−40°C to +85°C

−65°C to +125°C

150°C

26°C/W

ESD CAUTION

Peak Temperature

Time at Peak Temperature

260°C

40 sec

¹GND = CPGND = RFGND = DGND = AGND = 0 V.

Rev. A | Page 10 of 45

Data Sheet

ADF7020-1

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VCOIN

CREG1

VDD1

1

2

36 CLKOUT

35 DATA CLK

3

DATA I/O

INT/LOCK

34

33

RFOUT

RFGND

RFIN

4

5

32 VDD2

ADF7020-1

6

31 CREG2

TOP VIEW

RFINB

7

ADCIN

GND2

30

29

(Not to Scale)

R

8

LNA

VDD4

RSET

9

28 SCLK

10

27 SREAD

CREG4 11

GND4 12

SDATA

26

25 SLE

NOTES

1. CONNECT EXPOSED PAD TO GND.

Figure 6. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VCOIN

VCO Input Pin. The tuning voltage on this pin determines the output frequency of the voltage controlled

oscillator (VCO). The higher the tuning voltage, the higher the output frequency.

2

3

4

CREG1

VDD1

Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin

and ground for regulator stability and noise rejection.

Voltage Supply for PA Block. Decoupling capacitors of 0.1 μF and 10 pF should be placed as close as possible to

this pin. All V_DDpins should be tied together.

PA Output Pin. The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm.

The output should be impedance matched to the desired load using suitable components. See the Transmitter

section.

RFOUT

5

6

RFGND

RFIN

Ground for Output Stage of Transmitter. All GND pins should be tied together.

LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA input

to ensure maximum power transfer. See the LNA/PA Matching section.

7

8

RFINB

R_LNA

Complementary LNA Input. See the LNA/PA Matching section.

External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.

9

10

11

VDD4

RSET

CREG4

Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.

External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance.

Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND for

regulator stability and noise rejection.

12

GND4

Ground for LNA/MIXER Block.

13 to 18 MIX/FILT

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left

unconnected.

19, 22

GND4

Ground for LNA/MIXER Block.

20, 21,

23

FILT/TEST_A

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left

unconnected.

24

25

26

CE

Chip Enable. Bringing CE low puts the ADF7020-1 into complete power-down. Register values are lost when CE

is low, and the part must be reprogrammed once CE is brought high.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the

four latches. A latch is selected using the control bits.

Serial Data Input. The serial data is loaded MSB first, with the 2 LSBs as the control bits. This pin is a high

impedance CMOS input.

SLE

SDATA

Rev. A | Page 11 of 45

ADF7020-1

Data Sheet

Pin No.

Mnemonic

Description

27

SREAD

Serial Data Output. This pin is used to feed readback data from the ADF7020-1 to the microcontroller. The SCLK

input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin.

28

SCLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the

24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.

29

30

GND2

ADCIN

Ground for Digital Section.

Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 to 1.9 V.

Readback is made using the SREAD pin.

31

CREG2

Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this

pin and ground for regulator stability and noise rejection.

32

33

VDD2

INT/LOCK

Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to this pin.

Bidirectional Pin. In output mode (interrupt mode), the ADF7020-1 asserts the INT/LOCK pin when it has found

a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to lock the

demodulator threshold when a valid preamble has been detected. Once the threshold is locked, NRZ data can

be reliably received. In this mode, a demodulator lock can be asserted with minimum delay.

34

35

DATA I/O

DATA CLK

Transmit Data Input/Received Data Output. This is a digital pin and normal CMOS levels apply.

Transmit/Receive Clock Pin. In receive mode, the pin outputs the synchronized data clock. The positive clock

edge is matched to the center of the received data. In GFSK transmit mode, the pin outputs an accurate clock to

latch the data from the microcontroller into the transmit section at the exact required data rate. See the

Gaussian Frequency Shift Keying (GFSK) section.

36

37

CLKOUT

A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to

drive several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio.

Multiplexer Output Pin. This pin provides the Lock_Detect signal, which is used to determine if the PLL is locked

to the correct frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial

interface regulator.

MUXOUT

38

OSC2

Oscillator Output Pin. The reference crystal should be connected between this pin and OSC1. A TCXO reference

can be used by driving this pin with CMOS levels and disabling the crystal oscillator.

39

40

OSC1

VDD3

Oscillator Input Pin. The reference crystal should be connected between this pin and OSC2.

Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a 0.01 μF

capacitor.

41

42

CREG3

CPOUT

Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be

placed between this pin and ground for regulator stability and noise rejection.

Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated

current changes the control voltage on the input to the VCO.

43

VDD

Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 μF capacitor.

44, 46

L2, L1

External VCO Inductor Pins. A chip inductor should be connected across these pins to set the VCO operating

frequency. See the Voltage Controlled Oscillator (VCO) section for details on choosing the appropriate value.

45, 47

48

GND, GND1

CVCO

Grounds for VCO Block.

VCO Noise Compensation Node. A 22 nF capacitor should be placed between this pin and CREG1 to reduce

VCO noise.

EP

EPAD

Exposed Pad. Connect the exposed pad to GND.

Rev. A | Page 12 of 45

Data Sheet

ADF7020-1

TYPICAL PERFORMANCE CHARACTERISTICS

MKR4 3.482GHz

REF 10dBm

ATTEN 20dB

SWEEP 16.52ms (601pts)

CARRIER POWER –0.28dBm ATTEN 0.00dB MKR1 10.0000kHz

PEAK

LOG

1

REF –70.00dBc/Hz

–87.80dBc/Hz

10.00

dB/

10dB/

1

3

4

REF LEVEL

10.00dBm

START 100MHz

RES BW 3MHz

STOP 10.000GHz

SWEEP 16.52ms (601pts)

VBW 3MHz

1kHz

FREQUENCY OFFSET

10MHz

Figure 7. Phase Noise Response at 315 MHz, V_DD= 3.0 V, ICP = 1.5 mA

Figure 10. Harmonic Response, RF_OUTMatched to 50 Ω, No Filter

∆ Mkr1 1.834GHz

REF 15dBm

1R

ATTEN 30dB

–62.57dB

REF 20dBm

NORM

LOG

ATTEN 30dB

NORM

LOG

10dB/

10

dB/

MARKER

1.834000000GHz

–62.57dB

∆

FSK

LgAv

W1 S2

S3 FC

AA

1

V1 V2

S3FC

AA

GFSK

£(f):

FTun

Swp

f>50k

SWP

START 800MHz

#RES BW 30kHz

STOP 5.000GHz

SWEEP 5.627s (601pts)

CENTER 415.000 0 MHz

#RES BW 300 Hz

SPAN 400 kHz

VBW 300 Hz SWEEP 5.359 s (601pts)

VBW 30kHz

Figure 8. Output Spectrum in FSK and GFSK Modulation

Figure 11. Harmonic Response, Murata Dielectric Filter

0

–5

REF 20dBm

ATTEN 30dB

200kHz FILTER BW

NORM

LOG

10

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

–60

–65

–70

dB/

OOK

ASK

150kHz FILTER BW

100kHz FILTER BW

LgAv

V1 V2

S3FC

AA

GOOK

£(f):

f>50k

SWP

–400 –300 –200 –100

–350 –250 –150 –50

0

100 200 300 400 500 600

150 250 350 450 550

50

CENTER 415.000 0 MHz

#RES BW 360 Hz

SPAN 300 kHz

VBW 360 Hz SWEEP 2.791 s (601pts)

IF FREQ (kHz)

Figure 9. IF Filter Response

Figure 12. Output Spectrum in ASK, OOK, and GOOK Modes, DR = 10 kbps

Rev. A | Page 13 of 45

ADF7020-1

Data Sheet

0

–1

–2

–3

–4

–5

–6

–7

–8

20

15

+2.3V,+85°C

+2.3V,+25°C

9µA

+3.6V,+85°C

11µA

10

+2.3V,–40°C

5

+3.6V,–40°C

+3.0V,–40°C

5µA

+3.6V,+25°C

0

7µA

–5

–10

–15

–20

–25

–127 –126 –125 –124 –123 –122 –121 –120 –119 –118 –117 –116 –115

1

5

9

13 17 21 25 29 33 37 41 45 49 53 57 61

PA SETTING

INPUT POWER (dBm)

Figure 13. PA Output Power vs. Setting

Figure 16. Sensitivity vs. V_DDand Temperature,

RF = 315 MHz, DR = 1 kBPS, Correlator Demod

0

CARRIER POWER 10.75dBm ATTEN 6.00dB MKR1 10.0000kHz

REF –70.00dBc/Hz

10.00

dB/

–86.20dBc/Hz

–1

200.8k

DATA RATE

–2

–3

1.002k

9.760k

DATA RATE

–4

–5

–6

–7

–8

1kHz

FREQUENCY OFFSET

10MHz

RF I/P LEVEL (dBm)

Figure 17. BER vs. Data-Rate (Combined Matching Network) Separate LNA

and PA Matching Paths Typically Improve Performance by 2 dB

Figure 14. Wideband Interference Rejection. Wanted Signal (880 MHz) at 3 dB

above Sensitivity Point Interferer = FM Jammer (9.76 kbps, 10k Deviation)

–60

–65

–70

20

0

ACTUAL INPUT LEVEL

LINEAR AFC OFF

–75

–20

–80

–40

CORRELATION

–85

RSSI READBACK LEVEL

AFC ON

–90

–60

–80

–95

–100

–105

–110

CORRELATION

AFC OFF

LINEAR AFC ON

–100

–120

–100

–80

–60

–40

–20

0

20

FREQUENCY ERROR (kHz)

RF I/P (dB)

Figure 15. Digital RSSI Readback Linearity

Figure 18. Sensitivity vs. Frequency Error with AFC On/Off

Rev. A | Page 14 of 45

Data Sheet

ADF7020-1

FREQUENCY SYNTHESIZER

REFERENCE INPUT

R Counter

The 3-bit R counter divides the reference input frequency by an

integer from 1 to 7. The divided-down signal is presented as the

reference clock to the phase frequency detector (PFD). The

divide ratio is set in Register 1. Maximizing the PFD frequency

reduces the N value. This reduces the noise multiplied at a rate

of 20 log(N) to the output, as well as reducing occurrences of

spurious components. The R Register defaults to R = 1 on

power-up:

The on-board crystal oscillator circuitry (see Figure 19) can use

an inexpensive quartz crystal as the PLL reference. The oscil-

lator circuit is enabled by setting R1_DB12 high. It is enabled by

default on power-up and is disabled by bringing CE low. Errors

in the crystal can be corrected using the automatic frequency

control (see the AFC Section) feature or by adjusting the

fractional-N value (see the N Counter section). A single-ended

reference (TCXO, CXO) can also be used. The CMOS levels

should be applied to OSC2 with R1_DB12 set low.

PFD [Hz] = XTAL/R

MUXOUT and Lock Detect

The MUXOUT pin allows the user to access various digital

points in the ADF7020-1. The state of MUXOUT is controlled

by Bits R0_DB (29:31).

OSC1

OSC2

CP1

CP2

Regulator Ready

Figure 19. Oscillator Circuit on the ADF7020-1

Regulator ready is the default setting on MUXOUT after the

transceiver has been powered up. The power-up time of the

regulator is typically 50 µs. Because the serial interface is

powered from the regulator, the regulator must be at its

nominal voltage before the ADF7020-1 can be programmed.

The status of the regulator can be monitored at MUXOUT.

When the regulator ready signal on MUXOUT is high,

programming of the ADF7020-1 can begin.

Two parallel resonant capacitors are required for oscillation at

the correct frequency; their values are dependent on the crystal

specification. They should be chosen so that the series value of

capacitance added to the PCB track capacitance adds up to the

load capacitance of the crystal, usually 20 pF. Track capacitance

values vary from 2 pF to 5 pF, depending on board layout.

Where possible, choose capacitors that have a very low

temperature coefficient to ensure stable frequency operation

over all conditions.

DV

DD

CLKOUT Divider and Buffer

REGULATOR READY

DIGITAL LOCK DETECT

ANALOG LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

PLL TEST MODES

The CLKOUT circuit takes the reference clock signal from the

oscillator section (see Figure 19) and supplies a divided-down

50:50 mark-space signal to the CLKOUT pin. An even divide

from 2 to 30 is available. This divide number is set in R1_DB

(8:11). On power-up, the CLKOUT defaults to the divide-by-8

block.

MUX

CONTROL

MUXOUT

Σ-∆ TEST MODES

DV

DD

CLKOUT

ENABLE BIT

DGND

Figure 21. MUXOUT Circuit

DIVIDER

1 TO 15

OSC1

÷2

CLKOUT

Digital Lock Detect

Digital lock detect is active high. The lock detect circuit is

located at the PFD. When the phase error on five consecutive

cycles is less than 15 ns, lock detect is set high. Lock detect

remains high until 25 ns phase error is detected at the PFD.

Because no external components are needed for digital lock

detect, it is more widely used than analog lock detect.

Figure 20. CLKOUT Stage

To disable CLKOUT, set the divide number to 0. The output

buffer can drive up to a 20 pF load with a 10% rise time at

4.8 MHz. Faster edges can result in some spurious feedthrough

to the output. A small series resistor (50 Ω) can be used to slow

the clock edges to reduce these spurs at F_CLK

.

Rev. A | Page 15 of 45

ADF7020-1

Data Sheet

Analog Lock Detect

For GFSK, it is recommended that an LBW of 2.0 to 2.5 times

the data rate be used to ensure that sufficient samples are

taken of the input data while filtering system noise. The free

design tool ADIsimPLL can be used to design loop filters for

the ADF7020-1.

This N-channel, open-drain lock detect should be operated

with an external pull-up resistor of 10 kΩ nominal. When a lock

has been detected, this output is high with narrow low-going

pulses.

N Counter

Voltage Regulators

The feedback divider in the ADF7020-1 PLL consists of an 8-bit

integer counter and a 15-bit Σ-Δ fractional-N divider. The

integer counter is the standard pulse-swallow type common in

PLLs. This sets the minimum integer divide value to 31. The

fractional divide value gives very fine resolution at the output,

where the output frequency of the PLL is calculated as

The ADF7020-1 contains four regulators to supply stable

voltages to the part. The nominal regulator voltage is 2.3 V.

Each regulator should have a 100 nF capacitor connected

between CREG and GND. When CE is high, the regulators and

other associated circuitry are powered on, drawing a total

supply current of 2 mA. Bringing the chip-enable pin low

disables the regulators, reduces the supply current to less than

1 µA, and erases all values held in the registers. The serial

interface operates from a regulator supply; therefore, to write to

the part, the user must have CE high and the regulator voltage

must be stabilized. Regulator status (CREG4) can be monitored

using the regulator ready signal from muxout.

XTAL

R

Fractional − N

F

OUT

=

×(Integer − N +

)

2¹⁵

REFERENCE IN

4\R

PFD/

CHARGE

PUMP

VCO

4\N

Loop Filter

The loop filter integrates the current pulses from the charge

pump to form a voltage that tunes the output of the VCO to the

desired frequency. It also attenuates spurious levels generated by

the PLL. A typical loop-filter design is shown in Figure 22.

THIRD-ORDER

Σ-∆ MODULATOR

FRACTIONAL-N

INTEGER-N

CHARGE

PUMP OUT

VCO

Figure 23. Fractional-N PLL

The combination of the integer-N (maximum = 255) and the

fractional-N (maximum = 16,383/16,384) give a maximum N

divider of 255 + 1. Therefore, the minimum usable PFD is

Figure 22. Typical Loop-Filter Configuration

In FSK, the loop should be designed so that the loop bandwidth

(LBW) is approximately 5 times the data rate. Widening the

LBW excessively reduces the time spent jumping between

frequencies, but can cause insufficient spurious attenuation.

PFD_MIN[Hz] = Maximum Required Output Frequency/(255 + 1)

For example, when operating at 620 MHz, PFD_MINequals

2.42 MHz.

Voltage Controlled Oscillator (VCO)

For ASK systems, a wider LBW is recommended. The sudden

large transition between two power levels might result in VCO

pulling and can cause a wider output spectrum than is desired.

By widening the LBW to more than 10 times the data rate, the

amount of VCO pulling is reduced, because the loop settles

quickly back to the correct frequency. The wider LBW might

restrict the output power and data rate of ASK-based systems

more than it would that of FSK-based systems.

The ADF7020-1 features an on-chip VCO with external tank

inductor, which is used to set the frequency range. The center

frequency of the VCO is set by the internal varactor capacitance

and the combined inductance of the external chip inductor,

bond wire, and PCB track. A plot of VCO operating range vs.

total external inductance (chip inductor + PCB track) is shown

in Figure 24. The inductance for a PCB track using FR4

material is approximately 0.57 nH/mm. This should be

subtracted from the total value to determine the correct chip

inductor value.

Narrow-loop bandwidths can result in the loop taking long

periods of time to attain lock. Careful design of the loop filter is

critical to obtaining accurate FSK/GFSK modulation.

An additional frequency divide-by-2 block is included to allow

operation from 80 MHz to 325 MHz. To enable the divide-by-2

block, set R1_DB13 to 1.

Rev. A | Page 16 of 45

Data Sheet

ADF7020-1

The VCO can be recentered, depending on the required

frequency of operation, by programming the VCO adjust bits

R1_DB (20:21).

CHOOSING CHANNELS FOR BEST SYSTEM

PERFORMANCE

The fractional-N PLL allows the selection of any channel within

80 MHz to 650 MHz to a resolution of <300 Hz. This also

facilitates frequency-hopping systems.

The VCO is enabled as part of the PLL by the PLL-enable bit,

R0_DB28.

The VCO needs an external 22 nF between the VCO and the

regulator to reduce internal noise.

Careful selection of the RF transmit channels must be made

to achieve best spurious performance. The architecture of

fractional-N results in some level of the nearest integer channel

moving through the loop to the RF output. These beat-note

spurs are not attenuated by the loop if the desired RF channel

and the nearest integer channel are separated by a frequency of

less than the LBW.

750

700

650

F

(MHz)

MAX

600

550

500

450

400

350

300

250

200

The occurrence of beat-note spurs is rare, because the integer

frequencies are at multiples of the reference, which is typically

>10 MHz.

The amplitude of beat-note spurs can be significantly reduced

by using the frequency doubler to avoid very small or very large

values in the fractional register. By having a channel 1 MHz

away from an integer frequency, a 100 kHz loop filter can

reduce the level to <−45 dBc.

F

(MHz)

MIN

0

5

10

15

20

25

30

TOTAL EXTERNAL INDUCTANCE (nH)

Figure 24. External Inductance vs. Frequency

VCO Bias Current

VCO bias current can be adjusted using Bits R1_DB19 to

R1_DB16. To minimize current consumption, the bias current

setting should be as indicated in Table 5.

Table 5. Recommended VCO Bias Currents

Direct Frequency Output (f)

VCO Bias R1_DB(19:16)

f < 200 MHz

200 MHz < f < 450 MHz

f > 450 MHz

0001

0010

0011

VCO BIAS

R1_DB (16:19)

TO N

DIVIDER

MUX

TO PA

LOOP FILTER

÷2

VCO

÷2

220µF

CVCO PIN

VCO SELECT BIT

Figure 25. Voltage Controlled Oscillator (VCO)

Rev. A | Page 17 of 45

ADF7020-1

Data Sheet

TRANSMITTER

The PA is equipped with overvoltage protection, which makes it

robust in severely mismatched conditions. Depending on the

application, users can design a matching network for the PA to

exhibit optimum efficiency at the desired radiated output power

level for a wide range of different antennas, such as loop or mono-

pole antennas. See the LNA/PA Matching section for details.

RF OUTPUT STAGE

The PA of the ADF7020-1 is based on a single-ended,

controlled current, open-drain amplifier that has been designed

to deliver up to 13 dBm into a 50 Ω load at a maximum

frequency of 650 MHz.

The PA output current and, consequently, the output power are

programmable over a wide range. The PA configurations in

FSK/GFSK and ASK/OOK modulation modes are shown in

Figure 26 and Figure 27, respectively. In FSK/GFSK modulation

mode, the output power is independent of the state of the

DATA_IO pin. In ASK/OOK modulation mode, it is dependent

on the state of the DATA_IO pin and Bit R2_DB29, which

selects the polarity of the TxData input. For each transmission

mode, the output power can be adjusted as follows:

PA Bias Currents

Control Bits R2_DB (30:31) facilitate an adjustment of the PA

bias current to further extend the output power control range, if

necessary. If this feature is not required, the default value of

9 μA is recommended. The output stage is powered down by

resetting Bit R2_DB4. To reduce the level of undesired spurious

emissions, the PA can be muted during the PLL lock phase by

toggling this bit.

MODULATION SCHEMES

Frequency Shift Keying (FSK)



FSK/GFSK: The output power is set using bits

R2_DB (9:14).



ASK: The output power for the inactive state of the TxData

input is set by Bits R2_DB (15:20). The output power for the

active state of the TxData input is set by Bits R2_DB (9:14).

OOK: The output power for the active state of the TxData

input is set by Bits R2_DB (9:14). The PA is muted when

the TxData input is inactive.

Frequency shift keying is implemented by setting the N value

for the center frequency and then toggling this with the TxData

line. The deviation from the center frequency is set using Bits

R2_DB (15:23). The deviation from the center frequency in

hertz is



PFD ModulationNumber

FSK_DEVIATION[Hz]

R2_DB(30:31)

2

2¹⁴

where Modulation Number is a number from 1 to 511

(R2_DB (15:23)).

6

IDAC

R2_DB(9:14)

Select FSK using Bits R2_DB (6:8).

RFOUT

R2_DB4

R2_DB5

+

DIGITAL

LOCK DETECT

RFGND

PFD/

CHARGE

PUMP

PA STAGE

4R

VCO

FROM VCO

Figure 26. PA Configuration in FSK/GFSK Mode

FSK DEVIATION

FREQUENCY

DATA I/O

ASK/OOK MODE

N

R2_DB29

–F

+F

DEV

R2_DB(30:31)

THIRD-ORDER

- MODULATOR

DEV

6

R2_DB(9:14)

6

TxDATA

IDAC

FRACTIONAL-N

INTEGER-N

6

0

R2_DB(15:23)

Figure 28. FSK Implementation

RFOUT

RFGND

R2_DB4

R2_DB5

+

DIGITAL

LOCK DETECT

FROM VCO

Figure 27. PA Configuration in ASK/OOK Mode

Rev. A | Page 18 of 45

Data Sheet

ADF7020-1

Gaussian Frequency Shift Keying (GFSK)

Amplitude Shift Keying (ASK)

Gaussian frequency shift keying reduces the bandwidth

occupied by the transmitted spectrum by digitally prefiltering

the TxData. A TxCLK output line is provided from the

ADF7020-1 for synchronization of TxData from the micro-

controller. The TxCLK line can be connected to the clock input

of a shift register that clocks data to the transmitter at the exact

data rate.

Amplitude shift keying is implemented by switching the output

stage between two discrete power levels. This is accomplished by

toggling the DAC, which controls the output level between two

6-bit values set up in Register 2. A 0 TxData bit sends Bits R2_DB

(15:20) to the DAC. A high TxData bit sends Bits R2_DB (9:14)

to the DAC. A maximum modulation depth of 30 dB is possible.

On-Off Keying (OOK)

Setting Up the ADF7020-1 for GFSK

On-off keying is implemented by switching the output stage to a

certain power level for a high TxData bit and switching the

output stage off for a low TxData bit. For OOK, the transmitted

power for a high input is programmed using Bits R2_DB (9:14).

To set up the frequency deviation, set the PFD and the

modulator control bits according to the following equation:

PFD × 2^m

GFSK _DEVIATION[Hz] =

Gaussian On-Off Keying (GOOK)

2¹²

Gaussian on-off keying represents a prefiltered form of OOK

modulation. The usually sharp symbol transitions are replaced

with smooth Gaussian filtered transitions, the result being a

reduction in frequency pulling of the VCO. Frequency pulling

of the VCO in OOK mode can lead to a wider than desired BW,

especially if it is not possible to increase the loop-filter BW >

300 kHz. The GOOK sampling clock samples data at the data

rate. (See the Setting Up the ADF7020-1 for GFSK section.)

where m is GFSK_MOD_CONTROL set using R2_DB (24:26).

To set up the GFSK data rate, set the PFD and the modulator

control bits according to the following equation:

PFD

DR[bps] =

DIVIDER _ FACTOR × INDEX _ COUNTER

where DIVIDER_FACTOR and INDEX_COUNTER are

programmed in Bits R2_DB (15:21) and R2_DB (27:28),

respectively. For further information, see the Using GFSK on

the ADF7010 section in the EVAL-ADF7010EB1 data sheet.

Rev. A | Page 19 of 45

ADF7020-1

Data Sheet

RECEIVER SECTION

The LNA has two basic operating modes: high gain/low noise

mode and low gain/low power mode. To switch between these

two modes, use the LNA_mode bit, R6_DB15. The mixer is also

configurable between a low current and an enhanced linearity

mode using the mixer_linearity bit, R6_DB18.

RF FRONT END

The ADF7020-1 is based on a fully integrated, low IF receiver

architecture. The low IF architecture facilitates a very low

external component count and does not suffer from power-line-

induced interference problems.

Based on the specific sensitivity and linearity requirements of

the application, it is recommended to adjust control bits

LNA_mode (R6_DB15) and mixer_linearity (R6_DB18) as

outlined in Table 6.

Figure 29 shows the structure of the receiver front end. The

many programming options allow users to trade off sensitivity,

linearity, and current consumption for each other in the most

suitable way for their applications. To achieve a high level of

resilience against spurious reception, the LNA features a

differential input. Switch SW2 shorts the LNA input when

transmit mode is selected (R0_DB27 = 0). This feature facili-

tates the design of a combined LNA/PA matching network,

avoiding the need for an external Rx/Tx switch. See the

LNA/PA Matching section for details on the design of the

matching network.

The gain of the LNA is configured by the LNA_gain field,

R9_DB (20:21), and can be set by either the user or the

automatic gain control (AGC) logic.

IF Filter Settings/Calibration

Out-of-band interference is rejected by means of a fourth-order

Butterworth polyphase IF filter centered around a frequency of

200 kHz. The bandwidth of the IF filter can be programmed

between 100 kHz and 200 kHz by means of Control Bits R1_DB

(22:23); it should be chosen as a compromise between inter-

ference rejection, attenuation of the desired signal, and the AFC

pull-in range.

I (TO FILTER)

RFIN

Tx/Rx SELECT

SW2 LNA

LO

[R0_DB27]

RFINB

Q (TO FILTER)

LNA MODE

[R6_DB15]

To compensate for manufacturing tolerances, the IF filter

should be calibrated once after power-up. The IF filter

calibration logic requires that the IF filter divider in

MIXER LINEARITY

[R6_DB18]

LNA CURRENT

[R6_DB(16:17)]

LNA GAIN

Bits R6_DB (20:28) be set dependent on the crystal frequency.

Once initiated by setting Bit R6_DB19, the calibration is

performed automatically without any user intervention. The

calibration time is 200 μs, during which the ADF7020-1 should

not be accessed. It is important not to initiate the calibration

cycle before the crystal oscillator has fully settled. If the AGC

loop is disabled, the gain of IF filter can be set to three levels

using the filter_gain field, R9_DB (22:23). The filter gain is

adjusted automatically, if the AGC loop is enabled.

[R9_DB(20:21)]

LNA/MIXER ENABLE

[R8_DB6]

Figure 29. ADF7020-1 RF Front End

The LNA is followed by a quadrature down conversion mixer,

which converts the RF signal to the IF frequency of 200 kHz. It

is important to consider that the output frequency of the syn-

thesizer must be programmed to a value 200 kHz below the

center frequency of the received channel.

Table 6. LNA/Mixer Modes

LNA Gain

LNA Mode Value

(R6_DB15) R9_DB (21:20) (R6_DB18)

Mixer

Linearity

Sensitivity

(DR = 9.6 kbps,

f_DEV= 10 kHz)

Rx Current

Consumption

(mA)

Input IP3

(dBm)

Receiver Mode

High Sensitivity Mode (default)

RxMode2

Low Current Mode

Enhanced Linearity Mode

RxMode5

0

1

0

30

10

3

10

30

0

1

−112.5

−105.8

−92.2

−102.5

−99

20.1

19.0

17.6

19.0

20.1

−35

−15.9

−3.2

+6.8

−8.25

−28.8

RxMode6

−105

Rev. A | Page 20 of 45

Data Sheet

ADF7020-1

AGC Settling = AGC_Wait_Time × Number of Gain

Changes

RSSI/AGC

The RSSI is implemented as a successive compression log amp

following the base-band channel filtering. The log amp achieves

3 dB log linearity. It also doubles as a limiter to convert the

signal-to-digital levels for the FSK demodulator. The RSSI itself

is used for amplitude shift keying (ASK) demodulation. In ASK

mode, extra digital filtering is performed on the RSSI value.

Offset correction is achieved using a switched capacitor integra-

tor in feedback around the log amp. This uses the BB offset

clock divide. The RSSI level is converted for user readback and

digitally controlled AGC by an 80-level (7-bit) flash ADC. This

level can be converted to input power in dBm.

Thus, in the worst case, if the AGC loop has to go through all five

gain changes, AGC delay = 10, and SEQ_CLK = 200 kHz, then

AGC settling = 10 × 5 µs × 5 = 250 µs. Minimum AGC_Wait_Time

must be at least 25 µs.

RSSI Formula (Converting to dBm)

Input_Power [dBm] = −120 dBm + (Readback_Code +

Gain_Mode_Correction) × 0.5

where:

Readback_Code is given by Bits RV7 to RV1 in the readback

register (see Readback Format section).

Gain_Mode_Correction is given by the values in Table 7.

LNA gain and filter gain (LG2/LG1, FG2/FG1) are also

obtained from the readback register.

OFFSET

CORRECTION

FSK

DEMOD

1

A

LATCH

CLK

IFWR

Table 7. Gain Mode Correction

RSSI

ASK

DEMOD

LNA Gain

(LG2, LG1)

Filter Gain

(FG2, FG1)

ADC

Gain Mode Correction

R

H (1, 1)

M (1, 0)

L (0, 1)

H (1, 0)

M (0, 1)

L (0, 0)

0

24

45

63

90

105

Figure 30. RSSI Block Diagram

RSSI Thresholds

When the RSSI is above AGC_HIGH_THRESHOLD, the gain is

reduced. When the RSSI is below AGC_LOW_THRESHOLD, the

gain is increased. A delay (AGC_DELAY) is programmed to allow

for settling of the loop. The user programs the two threshold values

(recommended defaults, 30 and 70) and the delay (default, 10).

The default AGC set-up values should be adequate for most

applications. The threshold values must be more than 30 settings

apart for the AGC to operate correctly.

EL (0, 0)

An additional factor should be introduced to account for losses

in the front-end matching network/antenna.

FSK DEMODULATORS ON THE ADF7020-1

The two FSK demodulators on the ADF7020-1 are

•

FSK correlator/demodulator

Linear demodulator

Offset Correction Clock

In Register 3, the user should set the BB offset clock divide bits

R3_DB (4:5) to give an offset clock between 1 MHz and 2 MHz,

where:

Select these using the demodulator select bits, R4_DB (4:5).

FSK CORRELATOR/DEMODULATOR

The quadrature outputs of the IF filter are first limited and then

fed to a pair of digital frequency correlators that perform band-

pass filtering of the binary FSK frequencies at (IF + F_DEV) and

(IF − F_DEV). Data is recovered by comparing the output levels

from each of the two correlators. The performance of this

frequency discriminator approximates that of a matched filter

detector, which is known to provide optimum detection in the

presence of AWGN.

BBOS_CLK (Hz) = XTAL/(BBOS_CLK_DIVIDE)

BBOS_CLK_DIVIDE can be set to 4, 8, or 16.

AGC Information and Timing

AGC is selected by default, and operates by selecting the appro-

priate LNA and filter gain settings for the measured RSSI level.

It is possible to disable AGC by writing to Register 9 if you want

to enter one of the modes listed in Table 6, for example. The

time for the AGC circuit to settle and hence the time it takes to

take an accurate RSSI measurement is typically 150 µs, although

this depends on how many gain settings the AGC circuit has to

cycle through. After each gain change, the AGC loop waits for a

programmed time to allow transients to settle. This wait time

can be adjusted to speed up this settling by adjusting the

appropriate parameters.

FREQUENCY CORRELATOR

SLICER

IF

Rx DATA

I

LIMITERS

Q

Rx CLK

IF – F

DEV

IF + F

DEV

0

DB(8:15)

DB(4:13) DB(14)

Figure 31. FSK Correlator/Demodulator Block Diagram

AGC _ DELAY ×SEQ _ CLK _ DIVIDE

AGC _Wait _Time =

XTAL

Rev. A | Page 21 of 45

ADF7020-1

Data Sheet

Postdemodulator Filter

Table 8. When K Is Even

K

K/2

R6_DB14

R6_DB29

A second-order digital low-pass filter removes excess noise from

the demodulated bit stream at the output of the discriminator.

The bandwidth of this postdemodulator filter is programmable

and must be optimized for the user’s data rate. If the bandwidth

is set too narrow, performance is degraded due to intersymbol

interference (ISI). If the bandwidth is set too wide, excess noise

degrades the receiver’s performance. Typically, the 3 dB bandwidth

of this filter is set at approximately 0.75 times the user’s data

rate, using Bits R4_DB (6:15).

Even

Odd

0

1

Table 9. When K Is Odd

K

(K + 1)/2

R6_DB14

R6_DB29

Odd

Even

Odd

1

0

1

Bit Slicer

Postdemodulator Bandwidth Register Settings

The received data is recovered by the threshold detecting the

output of the postdemodulator low-pass filter. In the correlator/

demodulator, the binary output signal levels of the frequency

discriminator are always centered on zero. Therefore, the slicer

threshold level can be fixed at zero, and the demodulator

performance is independent of the run-length constraints of the

transmit data bit stream. This results in robust data recovery,

which does not suffer from the classic baseline wander prob-

lems that exist in the more traditional FSK demodulators.

The 3 dB bandwidth of the postdemodulator filter is controlled

by Bits R4_ DB (6:15) and is given by

2

¹⁰×2π×F_CUTOFF

Post _ Demod _ BW _ Setting =

DEMOD _ CLK

where F_CUTOFFis the target 3 dB bandwidth in hertz of the post-

demodulator filter. This should typically be set to 0.75 times the

data rate (DR).

Some sample settings for the FSK correlator/demodulator are

Frequency errors are removed by an internal AFC loop that

measures the average IF frequency at the limiter output and

applies a frequency correction value to the fractional-N

synthesizer. This loop should be activated when the frequency

errors are greater than approximately 40% of the transmit

frequency deviation (see the AFC Section).

DEMOD_CLK = 5 MHz

DR = 9.6 kbps

F

_DEV= 20 kHz

Therefore

F

_CUTOFF= 0.75 × 9.6 × 10³Hz

Post_Demod_BW = 2¹¹π 7.2 × 10³Hz/(5 MHz)

Post_Demod_BW = Round(9.26) = 9

Data Synchronizer

An oversampled digital PLL is used to resynchronize the received

bit stream to a local clock. The oversampled clock rate of the

PLL (CDR_CLK) must be set at 32 times the data rate. See the

notes for the Register 3—Receiver Clock Register section for a

definition of how to program the various on-chip clocks. The clock

recovery PLL can accommodate frequency errors of up to 2%.

and

K = Round(200 kHz)/20 kHz) = 10

Discriminator_BW = (5 MHz × 10)/(800 × 10³) = 62.5 =

63 (rounded to nearest integer)

Table 10. Register Settings

FSK Correlator Register Settings

Setting Name

Post_Demod_BW

Discriminator_BW

Dot Product

Register Address

Value

0x09

0x3F

0

To enable the FSK correlator/demodulator, Bits R4_DB (5:4)

should be set to [01]. To achieve best performance, the bandwidth

of the FSK correlator must be optimized for the specific deviation

frequency that is used by the FSK transmitter.

R4_DB (6:15)

R6_DB (4:13)

R6_DB14

Rx Data Invert

R6_DB29

1

The discriminator BW is controlled in Register 6 by R6_DB

(4:13) and is defined as

Discriminator _ BW = (DEMOD _ CLK ×K)/(800×10³)

where:

DEMOD_CLK is as defined in the Register 3—Receiver Clock

Register section, Note 2.

K = round(200e3/FSK deviation)

To optimize the coefficients of the FSK correlator, two

additional bits, R6_DB14 and R6_DB29, must be assigned.

The value of these bits depends on whether K (as defined

above) is odd or even. These bits are assigned according to the

conditions listed in Table 8 and Table 9.

Rev. A | Page 22 of 45

Data Sheet

ADF7020-1

postdemodulator filter.

LINEAR FSK DEMODULATOR

It is also recommended to use Manchester encoding in ASK/OOK

mode to ensure the data run length limit (RLL) is 2 bits. If a longer

RLL, up to a maximum of 4 bits, is required, users should disable

the extra-low gain setting by writing 0x3C00C to the test mode

register.

Figure 32 shows a block diagram of the linear FSK demodulator.

MUX 1

SLICER

ADC RSSI OUTPUT

7

LEVEL

I

Rx DATA

IF

AFC SECTION

LIMITER

Q

The ADF7020-1 supports a real-time AFC loop, which is used

to remove frequency errors that can arise due to mismatches

between the transmit and receive crystals. The AFC loop uses the

frequency discriminator block as described in the Linear FSK

Demodulator section (see Figure 32). The discriminator output

is filtered and averaged to remove the FSK frequency

modulation using a combined averaging filter and envelope

detector. In FSK mode, the output of the envelope detector

provides an estimate of the average IF frequency. Two methods

of AFC, external and internal, are supported on the ADF7020-1

(in FSK mode only).

FREQUENCY

READBACK

AND

FREQUENCY

LINEAR DISCRIMINATOR

AFC LOOP

DB(6:15)

Figure 32. Block Diagram of Frequency Measurement System and

ASK/OOK/Linear FSK Demodulator

This method of frequency demodulation is useful when very

short preamble length is required and the system protocol

cannot support the overhead of the settling time of the internal

feedback AFC loop settling.

A digital frequency discriminator provides an output signal that

is linearly proportional to the frequency of the limiter outputs.

The discriminator output is then filtered and averaged using a

combined averaging filter and envelope detector. The demodu-

lated FSK data is recovered by comparing the filter output with

its average value, as shown in Figure 32. In this mode, the slicer

output shown in Figure 32 is routed to the data synchronizer

PLL for clock synchronization. To enable the linear FSK

demodulator, set Bits R4_DB (4:5) to [00].

External AFC

The user reads back the frequency information through the

ADF7020-1 serial port and applies a frequency correction value

to the fractional-N synthesizer’s N divider.

The frequency information is obtained by reading the 16-bit

signed AFC_readback, as described in the Readback Format

section, and applying the following formula:

FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/2¹⁵

The 3 dB bandwidth of the postdemodulation filter is set in the

same way as the FSK correlator/demodulator, which is set in

R4_DB (6:15) and is defined as

Note that while the AFC_READBACK value is a signed number,

under normal operating conditions it is positive. In the absence

of frequency errors, the FREQ_RB value is equal to the IF

frequency of 200 kHz.

2¹⁰2F_CUTOFF

Post _ Demod _ BW _ Setting 

DEMOD _CLK

Internal AFC

The ADF7020-1 supports a real-time internal automatic fre-

quency control loop. In this mode, an internal control loop

automatically monitors the frequency error and adjusts the

synthesizer N divider using an internal PI control loop.

where:

F_CUTOFFis the target 3 dB bandwidth in hertz of the

postdemodulator filter. DEMOD_CLK is as defined in the

Register 3—Receiver Clock Register section, Note 2.

The internal AFC control loop parameters are controlled in

Register 11. The internal AFC loop is activated by setting

R11_DB20 to 1. A scaling coefficient must also be entered,

based on the crystal frequency in use. This is set up in R11_DB

(4:19) and should be calculated using

ASK/OOK Operation

ASK/OOK demodulation is activated by setting Bits R4_DB (4:5)

to [10].

ASK/OOK demodulation is performed by digitally filtering the

RSSI output, and then comparing the filter output with its average

value in a similar manner to FSK demodulation. The bandwidth

of the digital filter must be optimized to remove any excess

noise without causing ISI in the received ASK/OOK signal.

AFC_Scaling_Coefficient = (500 × 2²⁴)/XTAL

Therefore, using a 10 MHz XTAL yields an AFC scaling

coefficient of 839.

AFC Performance

The 3 dB bandwidth of this filter is typically set at approximately

0.75 times the user data rate and is assigned by R4 _DB (6:15) as

The improved sensitivity performance of the Rx when AFC is

enabled and in the presence of frequency errors is shown in

Figure 18. The maximum AFC pull-in range is 50 kHz, which

corresponds to 58 ppm at 868 MHz. This is the total error

tolerance allowed in the link. For example, in a point-to-point

2¹⁰2F_CUTOFF

Post_Demod_BW_Setting =

DEMOD_CLK

where F_CUTOFFis the target 3 dB bandwidth in hertz of the

Rev. A | Page 23 of 45

ADF7020-1

Data Sheet

system, AFC can compensate for two 29 ppm crystals or one

50 ppm crystal and one 8 ppm TCXO.

This feature can be used to alert the microprocessor that a valid

channel has been detected. It relaxes the computational require-

ments of the microprocessor and reduces the overall power

consumption. The INT/LOCK is automatically deasserted again

after nine data clock cycles.

AFC settling typically takes 48 bits to settle within 1 kHz. This

can be improved by increasing the postdemodulator bandwidth

in Register 4 at the expense of Rx sensitivity.

The automatic sync/ID word detection feature is enabled by

selecting Demodulator Mode 2 or 3 in the demodulator set-up

register. Do this by setting R4_DB (25:23) = [010] or [011].

Bits R5_DB (4:5) are used to set the length of the sync/ID

word, which can be 12, 16, 20, or 24 bits long. The transmitter

must transmit the MSB of the sync byte first and the LSB last to

ensure proper alignment in the receiver sync byte detection

hardware.

When AFC errors have been removed using either the internal

or external AFC, further improvement in the receiver’s sensitivity

can be obtained by reducing the IF filter bandwidth using

Bits R1_DB (22:23).

AUTOMATIC SYNC WORD RECOGNITION

The ADF7020-1 also supports automatic detection of the sync

or ID fields. To activate this mode, the sync (or ID) word must

be preprogrammed in the ADF7020-1. In receive mode, this

preprogrammed word is compared to the received bit stream,

and the external pin INT/LOCK is asserted by the ADF7020-1

when a valid match is identified.

For systems using FEC, an error tolerance parameter can also

be programmed that accepts a valid match when up to three bits

of the word are incorrect. The error tolerance value is assigned

in R5_DB (6:7).

Table 11. Sensitivity Values for Varying RF Frequency and Data Rates

FSK Sensitivity

at BER = 1E-3,

Correlator Demodulator

FSK Sensitivity

at BER = 1E-3,

Linear Demodulator

Deviation in

FSK Mode

ASK Sensitivity

at BER = 1E-3

Frequency

135 MHz

315 MHz

610 MHz

Data Rate (NRZ)

9.6 kbps

1.0 kbps

9.6 kbps

1.0 kbps

10 kHz

5 kHz

10 kHz

5 kHz

10 kHz

5 kHz

−113.2 dBm

−119.5 dBm

−114.2 dBm

−120 dBm

−113.2 dBm

−119.8 dBm

−106.2 dBm

−109.2 dBm

−108.0 dBm

−110.1 dBm

−107.0 dBm

−109.0 dBm

−110.8

−116.8 dBm

−111.8 dBm

−118 dBm

−110.5 dBm

−116.8 dBm

9.6 kbps

1.0 kbps

Rev. A | Page 24 of 45

Data Sheet

ADF7020-1

APPLICATIONS

network with respect to ground, a compromise between the input

reflection coefficient and the maximum differential signal swing

at the LNA input must be established. The use of appropriate

CAD software is strongly recommended for this optimization.

LNA/PA MATCHING

The ADF7020-1 exhibits optimum performance in terms of

sensitivity, transmit power, and current consumption only if its

RF input and output ports are properly matched to the antenna

impedance. For cost-sensitive applications, the ADF7020-1 is

equipped with an internal Rx/Tx switch, which facilitates the

use of a simple combined passive PA/LNA matching network.

Alternatively, an external Rx/Tx switch, such as the Analog

Devices ADG919, can be used, which yields a slightly improved

receiver sensitivity and lower transmitter power consumption.

Depending on the antenna configuration, the user might

need a harmonic filter at the PA output to satisfy the spurious

emission requirement of the applicable government regulations.

The harmonic filter can be implemented in various ways, such

as a discrete LC pi or T-stage filter. The immunity of the

ADF7020-1 to strong out-of-band interference can be improved

by adding a band-pass filter in the Rx path, or alternatively by

selecting one of the high linearity modes outlined in Table 6.

External Rx/Tx Switch

Figure 33 shows a configuration using an external Rx/Tx switch.

This configuration allows an independent optimization of the

matching and filter network in the transmit and receive path

and is therefore more flexible and less difficult to design than

the configuration using the internal Rx/Tx switch. The PA is

biased through Inductor L1, and C1 blocks the dc current. Both

elements, L1 and C1, also form the matching network, which

transforms the source impedance into the optimum PA load

impedance, Z_OPT_PA.

Internal Rx/Tx Switch

Figure 34 shows the ADF7020-1 in a configuration where the

internal Rx/Tx switch is used with a combined LNA/PA

matching network. This is the configuration used in the

ADF7020-1DBX Evaluation boards. For most applications, the

slight performance degradation of 1 dB to 2 dB caused by the

internal Rx/Tx switch is acceptable, allowing the user to take

advantage of the cost saving potential of this solution. The

design of the combined matching network must compensate for

the reactance presented by the networks in the Tx and the Rx

paths, taking the state of the Rx/Tx switch into consideration.

V

BAT

L1

PA_OUT

OPTIONAL

LPF

PA

V

BAT

ANTENNA

Z

_PA

OPT

L1

C1

PA_OUT

Z

_RFIN

IN

PA

C

OPTIONAL

BPF

(SAW)

A

RFIN

ANTENNA

Z _PA

OPT

OPTIONAL

BPF OR LPF

L

LNA

A

Z

_RFIN

IN

RFINB

C

A

RFIN

ADG919

Rx/Tx – SELECT

Z

_RFIN

IN

L

LNA

A

C

B

RFINB

ADF7020-1

Figure 33. ADF7020-1 with External Rx/Tx Switch

Z

_RFIN

IN

C

B

Z_OPT_PA depends on various factors, such as the required

ADF7020-1

output power, the frequency range, the supply voltage range,

and the temperature range. Selecting an appropriate Z_OPT_PA

helps to minimize the Tx current consumption in the

application. The Specifications section lists a number of

Z_OPT_PA values for representative conditions. Under certain

conditions, however, it is recommended to obtain a suitable

Z_OPT_PA value by means of a load-pull measurement.

Figure 34. ADF7020-1 with Internal Rx/Tx Switch

The procedure typically requires several iterations until an

acceptable compromise is reached. The successful implementation

of a combined LNA/PA matching network for the ADF7020-1 is

critically dependent on the availability of an accurate electrical

model for the PC board. In this context, the use of a suitable CAD

package is strongly recommended. To avoid this effort, however, a

small form-factor reference design for the ADF7020-1 is provided,

including matching and harmonic filter components. The design

is on a 2-layer PCB to minimize cost. Gerber files are available

on the www.analog.com website.

Due to the differential LNA input, the LNA matching network

must be designed to provide both a single-ended to differential

conversion and a complex conjugate impedance match. The

network with the lowest component count that can satisfy these

requirements is the configuration shown in Figure 33, which

consists of two capacitors and one inductor. A first-order

implementation of the matching network can be obtained by

understanding the arrangement as two L type matching networks

in a back-to-back configuration. Due to the asymmetry of the

Rev. A | Page 25 of 45

ADF7020-1

Data Sheet

TRANSMIT PROTOCOL AND CODING

CONSIDERATIONS

INTERFACING TO MICROCONTROLLER/DSP

Low level device drivers are available for interfacing to the

ADF7020-1, the ADI ADuC84x microcontroller parts, or the

Blackfin ADSP-BF53x DSPs using the hardware connections

shown in Figure 36 and Figure 37.

SYNC

ID

PREAMBLE

WORD

FIELD

DATA FIELD

CRC

Figure 35. Typical Format of a Transmit Protocol

ADuC84x

ADF7020-1

A dc-free preamble pattern is recommended for FSK/ASK/

OOK demodulation. The recommended preamble pattern is a

dc-free pattern such as a 10101010 … pattern. Preamble

patterns with longer run-length constraints, such as

11001100…, can also be used. However, this results in a longer

synchronization time of the received bit stream in the receiver.

MISO

TxRxDATA

MOSI

SCLOCK

SS

RxCLK

P3.7

CE

P3.2/INT0

P2.4

INT/LOCK

SREAD

SLE

P2.5

GPIO

Manchester coding can be used for the entire transmit protocol.

However, the remaining fields that follow the preamble header

do not have to use dc-free coding. For these fields, the

ADF7020-1 can accommodate coding schemes with a run-

length of up to 6 bits without any performance degradation.

P2.6

P2.7

SDATA

SCLK

Figure 36.ADuC84x to ADF7020-1 Connection Diagram

ADF7020-1

ADSP-BF533

SCK

MOSI

MISO

PF5

SCLK

SDATA

SREAD

SLE

If longer run-length coding must be supported, the ADF7020-1

has several other features that can be activated. These involve a

range of programmable options that allow the envelope detector

output to be frozen after preamble acquisition.

RSCLK1

DT1PRI

DR1PRI

RFS1

PF6

TxRxCLK

TxRxDATA

DEVICE PROGRAMMING AFTER INITIAL

POWER-UP

INT/LOCK

CE

VCC

Table 12 lists the minimum number of writes needed to set up

the ADF7020-1 in either Tx or Rx mode after CE is brought

high. Additional registers can also be written to tailor the part

to a particular application, such as setting up sync byte

detection or enabling AFC. When going from Tx to Rx or vice

versa, the user needs to write only to the N register to alter the

LO by 200 kHz and to toggle the Tx/Rx bit.

GND

Figure 37.ADSP-BF533 to ADF7020-1 Connection Diagram

Table 12. Minimum Register Writes Required for Tx/Rx Setup

Mode

Registers

Tx

Rx

Reg 0

Reg 1

Reg 2

Reg 4

Reg 6

(OOK)

Rx

(G/FSK)

Tx <->

Rx

Reg 0

Reg 1

Reg 2

Figure 38 and Figure 39 show the recommended programming

sequence and associated timing for power-up from

standby mode.

Rev. A | Page 26 of 45

Data Sheet

ADF7020-1

17.6mA TO

20.1mA

14mA

_XTAL

T₀

3.65mA

2.0mA

AFC

T₁₀

REG.

WR3 WR4 WR6

AGC/

RSSI

CDR

TIME

RxDATA

READY WR0 WR1

VCO

T₄

T₅T₆T₇

T₉

T₁₁

T₁

T₂T₃

T₈

T_ON

T

OFF

Figure 38. Rx Programming Sequence and Timing Diagram

Table 13. Power-Up Sequence Description

Parameter

Value

Description/Notes

Signal to Monitor

T0

2 ms

Crystal starts power-up after CE is brought high. This typically depends

on the crystal type and the load capacitance specified.

CLKOUT pin

T1

10 μs

Time for regulator to power up. The serial interface can be written to after

this time.

Time to write to a single register. Maximum SPI_CLK is 25 MHz.

The VCO can power-up in parallel with the crystal. This depends on the

CVCO capacitance value used. A value of 22 nF is recommended as a

trade-off between phase noise performance and power-up time.

MUXOUT pin

CVCO pin

T2, T3, T5, T6, T7

T4

32 × 1/SPI_CLK

1 ms

T8

150 μs

This depends on the number of gain changes the AGC loop needs to cycle Analog RSSI on TEST_A

through and AGC settings programmed. This is described in more detail

in the AGC Information and Timing section.

pin (available by writing

0x3800 000C)

T9

5 × Bit_Period

16 × Bit_Period

Packet Length

This is the time for the clock and data recovery circuit to settle. This typically

requires 5-bit transitions to acquire sync and is usually covered by the

preamble.

This is the time for the automatic frequency control circuit to settle. This

typically requires 16-bit transitions to acquire lock and is usually covered

by an appropriate length preamble.

T10

T11

Number of bits in payload by the bit period.

Rev. A | Page 27 of 45

ADF7020-1

Data Sheet

15mA TO

30mA

14mA

3.65mA

2.0mA

REG.

READY

WR0 WR1

WR2

TIME

TxDATA

T₁₂

XTAL + VCO

T₄

T₂T₃

T₅

T₁

T

OFF

ON

Figure 39. Tx Programming Sequence and Timing Diagram

Rev. A | Page 28 of 45

Data Sheet

ADF7020-1

SERIAL INTERFACE

The serial interface allows the user to program the eleven 32-bit

registers using a 3-wire interface (SCLK, SDATA, and SLE). It

consists of a voltage level shifter, a 32-bit shift register, and

11 latches. Signals should be CMOS compatible. The serial

interface is powered by the regulator and therefore is inactive

when CE is low.

RSSI Readback

The RSSI readback operation yields valid results in Rx mode

with ASK or FSK signals. The format of the readback word is

shown in Figure 40. It is comprised of the RSSI level informa-

tion (Bits RV1 to RV7), the current filter gain (FG1, FG2), and

the current LNA gain (LG1, LG2) setting. The filter and LNA

gain are coded in accordance with the definitions in Register 9.

With the reception of ASK modulated signals, averaging of the

measured RSSI values improves accuracy. The input power can

be calculated from the RSSI readback value as outlined in the

RSSI/AGC.

Data is clocked into the register MSB first on the rising edge of

each clock (SCLK). Data is transferred to one of the 11 latches

on the rising edge of SLE. The destination latch is determined

by the value of the four control bits (C4 to C1). These are the

bottom 4 LSB, DB3 to DB0, as shown in the timing diagram in

Figure 2. Data can also be read back on the SREAD pin.

Battery Voltage ADCIN/Temperature Sensor Readback

READBACK FORMAT

The battery voltage is measured at Pin VDD4. The readback

information is contained in Bits RV1 to RV7. This also applies

for the readback of the voltage at the ADCIN pin and the

temperature sensor. From the readback information, the battery

or ADCIN voltage can be determined using

The readback operation is initiated by writing a valid control

word to the readback register and setting the readback-enable

bit (R7_DB8 = 1). The readback can begin after the control

word has been latched with the SLE signal. SLE must be kept

high while the data is read out. Each active edge at the SCLK

pin clocks the readback word out successively at the SREAD

pin, as shown in Figure 3, starting with the MSB first. The data

appearing at the first clock cycle following the latch operation

must be ignored.

V

_BATTERY= (Battery_Voltage_Readback)/21.1

_ADCIN= (ADCIN_Voltage_Readback)/42.1

Silicon Revision Readback

The silicon revision readback word is valid without setting any

other registers, especially directly after power-up. The silicon

revision word is coded with four quartets in BCD format. The

product code (PC) is coded with three quartets extending

from Bits RV5 to RV16. The revision code (RV) is coded with

one quartet extending from Bits RV1 to RV4. The product code

for the ADF7020-1 should read back as PC = 0x200. The

current revision code should read back as RC = 0x6.

AFC Readback

The AFC readback is valid only during the reception of FSK

signals with either the linear or correlator demodulator active.

The AFC readback value is formatted as a signed 16-bit integer

comprised of Bits RV1 to RV16 and is scaled according to the

following formula:

FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/2¹⁵

Filter Calibration Readback

In the absence of frequency errors, the FREQ_RB value is equal

to the IF frequency of 200 kHz. Note that the down-converted

input signal must not fall outside the bandwidth of the analogue

IF filter for the AFC readback to yield a valid result. At low-

input signal levels, the variation in the readback value can be

improved by averaging.

The filter calibration readback word is contained in Bits RV1 to

RV8 and is for diagnostic purposes only. Using the automatic

filter calibration function, accessible through Register 6, is

recommended. Before filter calibration is initiated Decimal 32

should be read back.

READBACK MODE

READBACK VALUE

DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

RV8

FG1

DB6

RV7

DB5

RV6

DB4

RV5

DB3

RV4

DB2

RV3

DB1

RV2

DB0

RV1

AFC READBACK

RSSI READBACK

RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9

X

LG2

X

LG1

X

FG2

X

BATTERY VOLTAGE/ADCIN/

TEMP. SENSOR READBACK

X

RV7

RV6

RV5

RV4

RV3

RV2

RV1

SILICON REVISION

RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9

RV8

FILTER CAL READBACK

0

Figure 40. Readback Value Table

Rev. A | Page 29 of 45

ADF7020-1

Data Sheet

REGISTER 0—N REGISTER

ADDRESS

BITS

MUXOUT

8-BIT INTEGER-N

15-BIT FRACTIONAL-N

TRANSMIT/

TR1 RECEIVE

FRACTIONAL

DIVIDE RATIO

M15 M14 M13 ...

M3

M2

M1

0

1

TRANSMIT

RECEIVE

0

1

2

.

0

.

1

0

.

1

0

.

1

...

0

.

1

0

1

.

0

1

0

1

0

.

0

1

0

1

PLE1 PLL ENABLE

0

1

PLL OFF

PLL ON

32764

32765

32766

32767

M3

M2

M1

MUXOUT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

REGULATOR READY (DEFAULT)

R DIVIDER OUTPUT

N DIVIDER OUTPUT

DIGITAL LOCK DETECT

ANALOG LOCK DETECT

THREE-STATE

PLL TEST MODES

Σ-∆ TEST MODES

N COUNTER

N8

N7

N6

N5

N4

N3

N2

N1

DIVIDE RATIO

0

.

0

.

0

1

.

1

0

.

1

0

.

1

0

.

1

0

.

1

0

.

31

32

.

1

0

1

253

1

0

1

254

255

Figure 41.

Notes

1. The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and also controls the state of the internal Tx/Rx switch.

XTAL

R

Fractional-N

F_OUT

=

×(Integer-N +

)

2¹⁵

2.

.

Rev. A | Page 30 of 45

Data Sheet

ADF7020-1

REGISTER 1—OSCILLATOR/FILTER REGISTER

CLOCKOUT

DIVIDE

ADDRESS

BITS

VCO BIAS

R COUNTER

FREQUENCY

RF R COUNTER

X1 XTAL OSC

VA2 VA1 OF OPERATION

R3 R2 R1 DIVIDE RATIO

0

1

OFF

ON

0

.

0

1

.

1

0

.

1

2

.

0

1

0

1

0

1

850–920

860–930

870–940

880–950

VCO

V1 DIV-BY-2

.

0

1

DIRECT OUTPUT

DIVIDE-BY-2

OUTPUT

1

7

VCO BIAS

VB3 VB2 VB1 CURRENT

VB4

0

.

0

.

0

1

.

1

0

.

0.375mA

0.625mA

XTAL

D1 DOUBLER

0

1

DISABLE

ENABLED

1

3.875mA

CLK

DIVIDE RATIO

OFF

OUT

FILTER

BANDWIDTH

I

(MA)

CL4

CL3

CL2

CL1

CP

CP1

IR2 IR1

0

.

0

.

0

1

.

0

1

0

.

CP2 RSET 3.6k

0

1

0

1

0

1

100kHz

150kHz

200kHz

NOT USED

2

4

.

0

1

0

1

0

1

0.3

0.9

1.5

2.1

.

30

1

Figure 42.

Notes

1. Set the VCO adjust bits R1_DB (20:21) to 0 for normal operation.

2. See Table 5 for the recommended VCO bias settings.

3. The divide-by-2 block is enabled by setting R1_DB13. As this divide block is outside the PLL loop, users must program an N-value

that corresponds to twice the divide-by-2 output frequency. The deviation frequency is also halved when divide-by-2 is enabled.

Rev. A | Page 31 of 45

ADF7020-1

Data Sheet

REGISTER 2—TRANSMIT MODULATION REGISTER (ASK/OOK MODE)

GFSK MOD

CONTROL

MODULATION

SCHEME

ADDRESS

BITS

PA BIAS

MODULATION PARAMETER

POWER AMPLIFIER

PE1 POWER AMPLIFIER

0

1

OFF

ON

IC2 IC1 MC3 MC2 MC1

X

MUTE PA UNTIL

MP1 LOCK DETECT HIGH

DI1

0

1

TxDATA

0

1

OFF

ON

PA2 PA1 PA BIAS

S3

S2

S1

MODULATION SCHEME

0

1

0

1

0

1

5µA

7µA

9µA

11µA

0

1

0

1

0

1

0

1

FSK

GFSK

ASK

OOK

GOOK

POWER AMPLIFIER OUTPUT LOW LEVEL

POWER AMPLIFIER OUTPUT HIGH LEVEL

D6

D5

.

D2

D1

P6

.

P2

P1

X

0

.

X

0

.

1

.

X

0

1

.

X

0

1

0

.

OOK MODE

PA OFF

–16.0dBm

–16 + 0.45dBm

–16 + 0.90dBm

.

0

.

1

.

X

0

1

.

X

0

1

0

.

PA OFF

–16.0dBm

–16 + 0.45dBm

–16 + 0.90dBm

.

1

.

1

.

1

.

1

.

1

.

1

.

13dBm

Figure 43.

Notes

1. Figure 13 shows how the PA bias affects the power amplifier level. The default level is 9 µA. If you need maximum power, program

this value to 11 µA.

2. In ASK/OOK, Manchester encoding is recommended to keep the data run length limit to 2 bits. See the ASK/OOK Operation

section for more details on dealing with longer run lengths.

3. D7, D8, and D9 are don’t care bits.

Rev. A | Page 32 of 45

Data Sheet

ADF7020-1

REGISTER 2—TRANSMIT MODULATION REGISTER (FSK MODE)

GFSK MOD

CONTROL

MODULATION

SCHEME

ADDRESS

BITS

PA BIAS

MODULATION PARAMETER

POWER AMPLIFIER

PE1 POWER AMPLIFIER

0

1

OFF

ON

IC2 IC1 MC3 MC2 MC1

X

MUTE PA UNTIL

MP1 LOCK DETECT HIGH

DI1

FOR FSK MODE,

D9

....

D3

D2

D1

F DEVIATION

PLL MODE

0

1

TxDATA

0

1

OFF

ON

0

.

....

0

.

0

1

.

0

1

0

1

.

1 × F

2 × F

3 × F

.

STEP

PA2 PA1 PA BIAS

S3

S2

S1

MODULATION SCHEME

0

1

0

1

0

1

5µA

7µA

9µA

11µA

1

511 × F

0

1

0

1

0

1

0

1

FSK

GFSK

ASK

OOK

GOOK

STEP

POWER AMPLIFIER OUTPUT LEVEL

P6

.

P2

P1

0

.

1

.

X

0

1

.

X

0

1

0

.

PA OFF

–16.0dBm

–16 + 0.45dBm

–16 + 0.90dBm

.

1

.

1

.

1

13dBm

Figure 44.

Notes

1.

2. PA bias default = 9 µA.

F

_STEP= PFD/2¹⁴.

Rev. A | Page 33 of 45

ADF7020-1

Data Sheet

REGISTER 2—TRANSMIT MODULATION REGISTER (GFSK/GOOK MODE)

GFSK MOD

CONTROL

MODULATION

SCHEME

ADDRESS

BITS

PA BIAS

MODULATION PARAMETER

POWER AMPLIFIER

PE1 POWER AMPLIFIER

D7

...

D3

D2

D1

DIVIDER_FACTOR

0

1

OFF

ON

0

.

...

0

.

0

1

.

0

1

0

1

.

INVALID

1

2

3

.

MUTE PA UNTIL

MP1 LOCK DETECT HIGH

1

127

DI1

0

1

TxDATA

0

1

OFF

ON

PA2 PA1 PA BIAS

GAUSSIAN – OOK

MODE

S3

S2

S1

MODULATION SCHEME

D9

D8

0

1

0

1

0

1

5µA

7µA

9µA

11µA

0

1

0

1

0

1

0

1

FSK

GFSK

ASK

OOK

GOOK

0

1

0

1

0

1

NORMAL MODE

OUTPUT BUFFER ON

BLEED CURRENT ON

BLEED/BUFFER ON

IC2 IC1 INDEX_COUNTER

POWER AMPLIFIER OUTPUT LEVEL

0

1

0

1

0

1

16

32

64

128

P6

.

P2

P1

0

.

1

.

X

0

1

.

X

0

1

0

.

PA OFF

–16.0dBm

–16 + 0.45dBm

–16 + 0.90dBm

.

1

.

1

.

1

MC3 MC2 MC1 GFSK_MOD_CONTROL

13dBm

0

.

0

.

0

1

.

0

1

.

1

7

Figure 45.

Notes

1. GFSK_DEVIATION = (2^{GFSK_MOD_CONTROL}× PFD)/2¹².

2. Data rate = PFD/(INDEX_COUNTER × DIVIDER_FACTOR).

3. PA bias default = 9 µA.

Rev. A | Page 34 of 45

Data Sheet

ADF7020-1

REGISTER 3—RECEIVER CLOCK REGISTER

ADDRESS

BITS

SEQUENCER CLOCK DIVIDE

CDR CLOCK DIVIDE

SK8 SK7 ...

...

SK3 SK2 SK1 SEQ_CLK_DIVIDE

BK2 BK1 BBOS_CLK_DIVIDE

0

.

0

.

0

.

0

1

.

1

0

.

1

2

.

0

1

0

1

x

4

8

16

...

1

0

1

254

255

OK2 OK1 DEMOD_CLK_DIVIDE

0

1

0

1

0

1

4

1

2

3

FS8

FS7

...

FS3

FS2

FS1 CDR_CLK_DIVIDE

0

.

1

0

.

1

...

0

.

1

0

1

.

1

0

.

0

1

2

.

254

255

Figure 46.

Notes

1. Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where

XTAL

BBOS _ CLK _ DIVIDE

BBOS _ CLK =

.

2. The demodulator clock (DEMOD_CLK) must be <12 MHz for FSK and <6 MHz for ASK, where

XTAL

DEMOD _ CLK =

.

DEMOD _ CLK _ DIVIDE

3. Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where

DEMOD _ CLK

CDR _ CLK _ DIVIDE

CDR _ CLK =

.

Note that this might affect your choice of XTAL, depending on the desired data rate.

4. The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to

40 kHz for ASK:

XTAL

SEQ _ CLK _ DIVIDE

SEQ _ CLK =

.

Rev. A | Page 35 of 45

ADF7020-1

Data Sheet

REGISTER 4—DEMODULATOR SET-UP REGISTER

ADDRESS

BITS

DEMODULATOR LOCK SETTING

POSTDEMODULATOR BW

DEMODULATOR

DS2 DS1 TYPE

0

1

0

1

0

1

LINEAR DEMODULATOR

CORRELATOR/DEMODULATOR

ASK/OOK

INVALID

DEMOD MODE LM2 LM1 DL8 DEMOD LOCK/SYNC WORD MATCH

INT/LOCK PIN

0

1

2

3

4

5

0

1

0

1

0

1

0

1

0

1

X

SERIAL PORT CONTROL—FREE RUNNING

SERIAL PORT CONTROL—LOCK THRESHOLD

SYNC WORD DETECT—FREE RUNNING

SYNC WORD DETECT—LOCK THRESHOLD

INTERRUPT/LOCK PIN LOCKS THRESHOLD

–

OUTPUT

INPUT

–

DL8 DEMOD LOCKED AFTER DL8–DL1 BITS

MODE5 ONLY

DL8 DL7 ...

DL3 DL2 DL1 LOCK_THRESHOLD_TIMEOUT

0

.

1

0

.

1

...

0

.

1

0

1

.

1

0

1

0

.

0

1

0

1

2

.

254

255

Figure 47.

Notes

1. Demodulator Modes 1, 3, 4, and 5 are modes that can be activated to allow the ADF7020-1 to demodulate data-encoding schemes

that have run-length constraints greater than 7.

2. Post_Demod_BW = 2¹¹π F_CUTOFF/DEMOD_CLK, where the cutoff frequency (F_CUTOFF) of the postdemodulator filter should typically

be 0.75 times the data rate.

3. For Mode 5, the timeout delay to lock threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK, where SEQ_CLK is defined in the

Register 3—Receiver Clock Register section.

Rev. A | Page 36 of 45

Data Sheet

ADF7020-1

REGISTER 5—SYNC BYTE REGISTER

CONTROL

BITS

SYNC BYTE SEQUENCE

SYNC BYTE

PL2 PL1 LENGTH

0

1

0

1

0

1

12 BITS

16 BITS

20 BITS

24 BITS

MATCHING

MT2 MT1 TOLERANCE

0

1

0

1

0

1

0 ERRORS

1 ERROR

2 ERRORS

3 ERRORS

Figure 48.

Notes

1. Sync byte detect is enabled by programming Bits R4_DB (25:23) to [010] or [011].

2. This register allows a 24-bit sync byte sequence to be stored internally. If the sync byte detect mode is selected, the INT/LOCK pin

goes high when the sync byte is detected in Rx mode. Once the sync word detect signal goes high, it goes low again after nine data bits.

3. The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte

detection hardware.

4. Choose a sync byte pattern that has good autocorrelation properties, for example, an unequal amount of digital 1s and 0s.

Rev. A | Page 37 of 45

ADF7020-1

Data Sheet

REGISTER 6—CORRELATOR/DEMODULATOR REGISTER

Rx

RESET

ADDRESS

BITS

IF FILTER DIVIDER

DISCRIMINATOR BW

CA1 FILTER CAL

DP1 DOT PRODUCT

DEMOD

RESET

0

1

NO CAL

CALIBRATE

0

1

CROSS PRODUCT

DOT PRODUCT

CDR

RESET

ML1 MIXER LINEARITY

LG1 LNA MODE

0

1

DEFAULT

HIGH

0

1

DEFAULT

REDUCED GAIN

RxDATA

INVERT

RI1

LI2

0

LI1

0

LNA BIAS

RxDATA

0

1

800µA (DEFAULT)

FILTER CLOCK

DIVIDE RATIO

FC9

.

FC6 FC5 FC4 FC3 FC2 FC1

0

.

0

.

0

.

0

.

0

.

0

1

.

1

0

.

1

2

.

1

.

1

.

1

.

1

.

1

.

1

.

1

511

Figure 49.

Notes

1. See the FSK Correlator/Demodulator section for an example of how to determine register settings.

2. Nonadherence to correlator programming guidelines results in poorer sensitivity.

3. The filter clock is used to calibrate the IF filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz. The

formula is XTAL/FILTER_CLOCK_DIVIDE.

4. The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19 is

set high.

5. Discriminator_BW = (DEMOD_CLK × K)/(800 × 10³). See the FSK Correlator/Demodulator section.

Maximum value = 600.

6. When LNA Mode = 1 (reduced gain mode), this prevents the Rx from selecting the highest LNA gain setting. This might be used

when linearity is a concern. See Table 6 for details of the Rx modes.

Rev. A | Page 38 of 45

Data Sheet

ADF7020-1

REGISTER 7—READBACK SET-UP REGISTER

READBACK

SELECT

ADC

MODE

CONTROL

BITS

DB1

DB0

DB7

RB2

DB8

RB3

DB6

RB1

DB5

AD2

DB4

AD1

DB3

DB2

C4(0) C3(1) C2(1) C1(1)

RB3 READBACK

AD2 AD1 ADC MODE

0

1

DISABLED

ENABLED

0

1

0

1

0

1

MEASURE RSSI

BATTERY VOLTAGE

TEMP SENSOR

TO EXTERNAL PIN

RB2 RB1 READBACK MODE

0

1

0

1

0

1

AFC WORD

ADC OUTPUT

FILTER CAL

SILICON REV

Figure 50.

Notes

1. Readback of the measured RSSI value is valid only in Rx mode. To enable readback of the battery voltage, the temperature sensor, or

the voltage at the external pin in Rx mode, users must disable the AGC function in Register 9. To read back these parameters in Tx

mode, users must first power up the ADC using Register 8, because it is off by default in Tx mode to save power. This is the

recommended method of using the battery readback function since most configurations typically require use of the AGC function.

2. Readback of the AFC word is valid in Rx mode only if either the linear demodulator or the correlator/demodulator is active.

3. See the Readback Format section for more information.

Rev. A | Page 39 of 45

ADF7020-1

Data Sheet

REGISTER 8—POWER-DOWN TEST REGISTER

LOG AMP/

RSSI

CONTROL

BITS

DB10 DB9

DB1

DB2

DB0

DB7

PD4

DB15 DB14 DB13 DB12 DB11

DB8

PD5

DB6

PD3

DB5

PD2

DB4

PD1

DB3

SW1

LR2

LR1

PD6

C4(1) C3(0) C2(0) C1(0)

PD7

PD7 PA (Rx MODE)

PLE1

LOOP

(FROM REG 0) PD2 PD1 CONDITION

0

1

PA OFF

PA ON

0

1

0

1

X

0

1

0

1

X

VCO/PLL OFF

PLL ON

VCO ON

PLL/VCO ON

SW1 Tx/Rx SWITCH

0

1

DEFAULT (ON)

OFF

PD3 LNA/MIXER ENABLE

LR2 LR1 RSSI MODE

0

1

LNA/MIXER OFF

LNA/MIXER ON

X

0

1

RSSI OFF

RSSI ON

PD6 DEMOD ENABLE

PD4 FILTER ENABLE

0

1

DEMOD OFF

DEMOD ON

0

1

FILTER OFF

FILTER ON

PD5 ADC ENABLE

0

1

ADC OFF

ADC ON

Figure 51.

Notes

1. For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition.

2. It is not necessary to write to this register under normal operating conditions.

Rev. A | Page 40 of 45

Data Sheet

ADF7020-1

REGISTER 9—AGC REGISTER

DIGITAL

TEST IQ

FILTER

GAIN

LNA

GAIN

ADDRESS

BITS

AGC HIGH THRESHOLD

AGC LOW THRESHOLD

FI1

FILTER CURRENT

GS1 AGC SEARCH

AGC LOW

GL7 GL6 GL5 GL4 GL3 GL2 GL1

THRESHOLD

0

1

LOW

HIGH

0

1

AUTO AGC

HOLD SETTING

0

.

0

.

0

.

0

.

0

1

.

0

1

0

.

1

0

1

0

.

1

2

3

4

.

61

62

63

FG2 FG1 FILTER GAIN

GC1 GAIN CONTROL

0

1

0

1

0

1

8

24

72

INVALID

0

1

AUTO

USER

.

1

0

1

0

1

RSSI LEVEL

CODE

GH7 GH6 GH5 GH4 GH3 GH2 GH1

0

.

1

0

.

0

.

0

1

0

.

1

0

1

.

1

0

1

0

.

1

0

1

0

1

0

.

0

1

0

1

2

3

4

.

78

79

80

LG2 LG1 LNA GAIN

0

1

0

1

0

1

<1

3

10

30

Figure 52.

Notes

1. Default AGC_LOW_THRESHOLD = 30, default AGC_HIGH_THRESHOLD = 70. See the RSSI/AGC for details.

2. AGC high and low settings must be more than 30 settings apart to ensure correct operation.

3. LNA gain of 30 is available only if the LNA mode bit, R6_DB15, is set to 0.

Rev. A | Page 41 of 45

ADF7020-1

Data Sheet

REGISTER 10—AGC 2 REGISTER

I/Q PHASE

ADJUST

ADDRESS

BITS

I/Q GAIN ADJUST

AGC DELAY

LEAK FACTOR

PEAK RESPONSE

SIQ2 SELECT IQ

DEFAULT = 0xA

0

1

PHASE TO I CHANNEL

PHASE TO Q CHANNEL

0

1

GAIN TO I CHANNEL

GAIN TO Q CHANNEL

DEFAULT = 0xA

DEFAULT = 0x2

Figure 53.

Notes

1. This register is not used under normal operating conditions.

REGISTER 11—AFC REGISTER

CONTROL

BITS

AFC SCALING COEFFICIENT

INTERNAL

AE1 AFC

0

1

OFF

ON

Figure 54.

Notes

1. See the Internal AFC section to program AFC scaling coefficient bits.

2. The AFC scaling coefficient bits can be programmed using the following formula:

AFC_Scaling_Coefficient = Round((500 × 2²⁴)/XTAL).

Rev. A | Page 42 of 45

Data Sheet

ADF7020-1

REGISTER 12—TEST REGISTER

ANALOG TEST

MUX

DIGITAL

TEST MODES

Σ-∆

ADDRESS

BITS

IMAGE FILTER ADJUST

TEST MODES

PLL TEST MODES

P

PRESCALER

DEFAULT = 32. INCREASE

CR1 COUNTER RESET

NUMBER TO INCREASE BW

IF USER CAL ON

0

1

4/5 (DEFAULT)

8/9

0

1

DEFAULT

RESET

CS1 CAL SOURCE

0

1

INTERNAL

SERIAL IF BW CAL

Figure 55.

Using the Test DAC on the ADF7020-1 to Implement

Analog FM Demodulation and Measuring of SNR

Programming the test register, Register 12, enables the test

DAC. In correlator mode, this can be done by writing Digital

Test Mode 7 or 0x0001C00C.

The test DAC allows the output of the postdemodulator filter

for both the linear and correlator/demodulators (Figure 31 and

Figure 32) to be viewed externally. It takes the 16-bit filter

output and converts it to a high frequency, single-bit output

using a second-order error feedback Σ-Δ converter. The output

can be viewed on the CLKOUT pin. This signal, when IF

filtered appropriately, can then be used to

To view the test DAC output when using the linear demodulator,

the user must remove a fixed offset term from the signal using

Register 13. This offset is nominally equal to the IF frequency.

The user can determine the value to program by using the

frequency error readback to determine the actual IF and then

programming half this value into the offset removal field. It also

has a signal gain term to allow the usage of the maximum dynamic

range of the DAC.

•

Monitor the signals at the FSK/ASK postdemodulator filter

output. This allows the demodulator output SNR to be

measured. Eye diagrams can also be constructed of the

received bit stream to measure the received signal quality.

Provide analog FM demodulation.

Setting Up the Test DAC

•

Digital test modes = 7: enables the test DAC, with no

offset removal (0x0001 C00C).

•

Digital test modes = 10: enables the test DAC, with

offset removal (needed for linear demod only, 0x02 800C).

While the correlators and filters are clocked by DEMOD_CLK,

CDR_CLK clocks the test DAC. Note that, although the test

DAC functions in a regular user mode, the best performance is

achieved when the CDR_CLK is increased up to or above the

frequency of DEMOD_CLK. The CDR block does not function

when this condition exists.

The output of the active demodulator drives the DAC; that is, if

the FSK correlator/demodulator is selected, the correlator filter

output drives the DAC.

Rev. A | Page 43 of 45

ADF7020-1

Data Sheet

REGISTER 13—OFFSET REMOVAL AND SIGNAL GAIN REGISTER

PULSE

EXTENSION

CONTROL

BITS

TEST DAC GAIN

TEST DAC OFFSET REMOVAL

KI

KP

PE4 PE3 PE2 PE1 PULSE EXTENSION

0

.

0

.

0

1

.

0

1

0

.

NORMAL PULSE WIDTH

2 × PULSE WIDTH

3 × PULSE WIDTH

.

1

16 × PULSE WIDTH

Figure 56.

Notes

1. Because the linear demodulator’s output is proportional to frequency, it usually consists of an offset combined with a relatively low

signal. Up to a maximum of a 300 kHz offset can be removed and gained to use the full dynamic range of the DAC:

DAC_input = (2^{Test_DAC_Gain}) × (Signal − Test_DAC_Offset_Removal/4096).

Rev. A | Page 44 of 45

Data Sheet

ADF7020-1

OUTLINE DIMENSIONS

7.00

BSC SQ

0.30

0.23

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

48

37

36

1

0.50

BSC

EXPOSED

PA

4.25

4.10 SQ

3.95

D

12

13

25

24

0.45

0.40

0.35

0.20 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.

Figure 57. 48-Lead Lead Frame Chip Scale Package [LFCSP]

7 mm × 7 mm Body and 0.75 mm Package Height

(CP-48-5)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CP-48-5

ADF7020-1BCPZ

−40°C to +85°C

48-Lead Lead Frame Chip Scale Package [LFCSP]

400 MHz to 435 MHz Daughter Board

80 MHz to 650 MHz Daughter Board

470 MHz to 510 MHz Daughter Board

310 MHz to 340 MHz Daughter Board

128 MHz to 142 MHz Daughter Board

ADF7020-1BCPZ-RL

ADF7020-1BCPZ-RL7

EVAL-ADF7020-1DBZ4

EVAL-ADF7020-1DBZ5

EVAL-ADF7020-1DBZ6

EVAL-ADF7020-1DBZ7

EVAL-ADF7020-1DBZ8

CP-48-5

¹Z = RoHS-Compliant Part.

registered trademarks are the property of their respective owners.

D05669–0–1/18(A)

Rev. A | Page 45 of 45


型号：	EVAL-ADF7020-1DBZ8
厂家：	ADI
描述：	BOARD EVAL ADF7020-1 128-142MHZ
文件：	总45页 (文件大小：725K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EVAL-ADF7020-1DBZ8 [ADI]

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