EVAL-ADF7021DB [ADI]
High Performance Narrowband ISM Transceiver IC; 高性能窄带ISM收发器IC
| 型号： | EVAL-ADF7021DB |
| 厂家： | 
ADI |
| 描述： | High Performance Narrowband ISM Transceiver IC |
| 文件： | 总44页 (文件大小：462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance Narrowband
ISM Transceiver IC
Preliminary Technical Data
ADF7021
On-chip 7-bit ADC and temperature sensor
Fully automatic frequency control loop (AFC)
Digital RSSI
Integrated Tx/Rx switch
Leakage current <1 μA in power-down mode
FEATURES
Low power, low IF transceiver
Frequency bands
80 MHz to 650 MHz
862 MHz to 940 MHz
Modulation schemes
2FSK, 3FSK, 4FSK
APPLICATIONS
Narrow-band standards
ETSI EN 300-220, FCC Part 90, FCC Part 15, FCC Part 95,
ARIB STD-T67
Low cost, wireless data transfer
Remote control/security systems
Wireless metering
Private mobile radio
Wireless medical telemetry service (WMTS)
Keyless entry
Spectral shaping
Gaussian and raised-cosine filtering
Data rates supported
0.05 kbps to 25 kbps
2.3 V to 3.6 V power supply
Programmable output power
−16 dBm to +13 dBm in 63 steps
Automatic PA ramp control
Receiver sensitivity
Home automation
Process and building control
Pagers
−125 dBm at 1 kbps, 2 FSK
On-chip VCO and fractional-N PLL
FUNCTIONAL BLOCK DIAGRAM
CE
RSET
MUXOUT
CREG(1:4)
TEMP
SENSOR
MUX
7-BIT ADC
R
POLARIZATION
LDO(1:4)
TEST MUX
LNA
2FSK
3FSK
4FSK
LNA
DATA CLK | TxDATA
DATA I/O | RxDATA
RSSI/
CLOCK
AND DATA
RECOVERY
R
FIN
OFFSET
Tx/Rx
CONTROL
IF FILTER
CORRECTION
R
FINB
DEMODULATOR
SWD
GAIN
AGC
CONTROL
SLE
SDATA
SREAD
SCLK
SERIAL
PORT
AFC
CONTROL
PA RAMP
2FSK
GAUSSIAN/
RAISED COSINE
FILTER
DIVIDERS/
MUXING
Σ-Δ
MODULATOR
3FSK
4FSK
DIV P
RFOUT
N/N + 1
MOD CONTROL
3FSK
ENCODING
VCO
MUX
CP
PFD
CLK
DIV
DIV R
RING OSC
L1 L2 VCOIN
CPOUT
OSC1 OSC2
CLKOUT
Figure 1.
Rev. PrI
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADF7021
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
AFC Section ................................................................................ 21
Automatic Sync Word Recognition ......................................... 22
Applications..................................................................................... 23
LNA/PA Matching...................................................................... 23
Transmit Protocol and Coding Considerations ..................... 24
Device Programming after Initial Power-Up ........................... 24
Interfacing to Microcontroller/DSP ........................................ 26
Serial Interface ................................................................................ 27
Readback Format........................................................................ 27
Register 0—N Register............................................................... 28
Register 1—VCO/Oscillator Register...................................... 29
Register 2—Transmit Modulation Register ............................ 30
Register 3—Transmit/Receive Clock Register........................ 31
Register 4—Demodulator Setup Register ............................... 32
Register 5—IF Filter Setup Register......................................... 33
Register 6—IF Fine Cal Setup Register ................................... 34
Register 7—Readback Setup Register...................................... 35
Register 8—Power Down Test Register................................... 36
Register 9—AGC Register......................................................... 37
Register 10—AFC Register ....................................................... 38
Register 11—Sync Word Detect Register................................ 39
Register 12—SWD/Threshold Setup Register........................ 40
Register 13—3FSK Demod Register........................................ 41
Register 14—Test-DAC Register .............................................. 41
Register 15—Test Mode Register ............................................. 42
Outline Dimensions....................................................................... 44
Ordering Guide .......................................................................... 44
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 3
Specifications..................................................................................... 4
Timing Characteristics..................................................................... 7
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Frequency Synthesizer ................................................................... 12
Reference Input........................................................................... 12
MUXOUT.................................................................................... 13
Voltage Controlled Oscillator (VCO)...................................... 14
Choosing Channels for Best System Performance................. 14
Transmitter ...................................................................................... 15
RF Output Stage.......................................................................... 15
Modulation Schemes.................................................................. 15
Spectral Shaping ......................................................................... 17
Modulation and Filtering Options........................................... 17
Receiver Section.............................................................................. 18
RF Front End............................................................................... 18
RSSI/AGC.................................................................................... 19
FSK Demodulators on the ADF7021....................................... 19
FSK Correlator/Demodulator................................................... 19
Linear 2FSK Demodulator ........................................................ 21
3FSK Demodulator..................................................................... 21
4FSK Demodulator..................................................................... 21
Rev. PrI | Page 2 of 44
Preliminary Technical Data
ADF7021
GENERAL DESCRIPTION
The ADF7021 is a low power, highly integrated 2FSK/3FSK/4FSK
transceiver. It is designed to operate in the narrow-band,
license-free ISM bands and licensed bands in the 80 MHz to
650 MHz and 862 MHz to 940 MHz frequency ranges. It has
both Gaussian and raised cosine data filtering options to
improve spectral efficiency for narrow-band applications.
It is suitable for circuit applications targeted at European
ETSI-EN 300-220, the Japanese ARIB STD-T67, the Chinese
Short Range Device regulations, and the North American FCC
Part 15, Part 90, and Part 95 regulatory standards. A complete
transceiver can be built using a small number of external
discrete components, making the ADF7021 very suitable for
price-sensitive and area-sensitive applications.
A low IF architecture is used in the receiver (100 kHz),
minimizing power consumption and the external component
count while avoiding interference problems at low frequencies.
The IF filter has programmable bandwidths of 12.5 kHz,
18.75 kHz, and 25 kHz. The ADF7021 supports a wide variety
of programmable features including Rx linearity, sensitivity, and
IF bandwidth, allowing the user to trade off receiver sensitivity
and selectivity against current consumption, depending on the
application. The receiver also features a patent-pending
automatic frequency control (AFC) loop with programmable
pull-in range, allowing the PLL to track out the frequency error
in the incoming signal.
An on-chip ADC provides readback of an integrated tempera-
ture sensor, an external analog input, the battery voltage, and
the RSSI signal, which provides savings on an ADC in some
applications. The temperature sensor is accurate to 10ꢀC over
the full operating temperature range of −40ꢀC to +85ꢀC. This
accuracy can be improved by doing a 1-point calibration at
room temperature and storing the result in memory.
The transmit section contains a voltage controlled oscillator
(VCO) and a low noise fractional-N PLL with output resolution
of <1 ppm. This frequency-agile PLL allows the ADF7021 to be
used in frequency hopping spread spectrum (FHSS) systems.
The VCO operates at twice the fundamental frequency to
reduce spurious emissions and frequency pulling problems.
The transmitter output power is programmable in 63 steps from
−16 dBm to +13 dBm and has an automatic power ramp control
to prevent spectral splatter and help meet regulatory standards.
The transceiver RF frequency, channel spacing, and modulation
are programmable using a simple 3-wire interface. The device
operates with a power supply range of 2.3 V to 3.6 V and can be
powered down when not in use.
Rev. PrI | Page 3 of 44
ADF7021
Preliminary Technical Data
SPECIFICATIONS
VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25ꢀC.
All measurements are performed with the EVAL-ADF7021DBx using PN9 data sequence, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions
RF CHARACTERISTICS
Frequency Ranges (Direct Output)
Frequency Ranges (Divide-by-2 Mode)
Frequency Ranges (Direct Output)
Frequency Ranges (Divide-by-2 Mode)
Phase Frequency Detector (PFD)
Frequency
135
80
862
431
650
325
940
470
TBD
MHz
MHz
MHz
MHz
MHz
External VCO inductor
External VCO inductor, divide-by-2 enabled
Internal VCO inductor
Internal VCO inductor, divide-by-2 enabled
RF/256
TRANSMISSION PARAMETERS
Data Rate
0.05
25
kbps
Frequency Shift Keying
Frequency Deviation1
56
306
56
Hz
Hz
Hz
Phase frequency detector (PFD) = 3.625 MHz
PFD = 20 MHz
PFD = 3.625 MHz
Deviation Frequency Resolution
Gaussian Filter BT
Raised Cosine Filter Alpha
Transmit Power 2
Transmit Power Variation vs. Temperature
Transmit Power Variation vs. VDD
Transmit Power Flatness
Programmable Step Size
−20 dBm to +13 dBm
Spurious Emissions
0.5
0.5
−20
+13
dBm
dB
dB
VDD = 3.0 V, TA = 25°C
From −40°C to +85°C
From 2.3 V to 3.6 V at 915 MHz, TA = 25°C
From 902 MHz to 928 MHz, 3 V, TA = 25°C
1
1
1
dB
0.3125
dB
Integer Boundary
Reference
−55
−65
dBc
dBc
50 kHz loop bandwidth (BW)
Harmonics
Second Harmonic
Third Harmonic
All Other Harmonics
Optimum PA Load Impedance3
−27
−21
−35
39 + j61
48 + j54
54 + j94
dBc
dBc
dBc
Ω
Ω
Ω
Unfiltered conductive
Unfiltered conductive
Unfiltered conductive
FRF = 915 MHz
FRF = 868 MHz
FRF = 433 MHz
RECEIVER PARAMETERS
2FSK Input Sensitivity
Bit error rate (BER) = 10−3, FRF = 915 MHz, low
noise amplifier (LNA) and power amplifier
(PA) matched separately4
Sensitivity at 1 kbps
LNA and Mixer, Input IP3
Enhanced Linearity Mode
Low Current Mode
High Sensitivity Mode
Rx Spurious Emissions6
−125
dBm
FDEV = 1 kHz, high sensitivity mode5
6.8
−3.2
−35
dBm
dBm
dBm
dBm
dBm
Pin = −20 dBm, 2 CW interferers
FRF = 915 MHz, F1 = FRF + 3 MHz
F2 = FRF + 6 MHz, maximum gain
<1 GHz at antenna input
−57
−47
>1 GHz at antenna input
AFC
Maximum Pull-In Range
Response Time
Accuracy
127.5
48
1
kHz
Bits
kHz
Mod index = 0.875
Rev. PrI | Page 4 of 44
Preliminary Technical Data
ADF7021
Parameter
Min
Typ
Max
Unit
Test Conditions
CHANNEL FILTERING
Adjacent Channel Rejection
(Offset = 1 ꢀ IF Filter BW Setting)
Second Adjacent Channel Rejection
(Offset = 2 ꢀ IF Filter BW Setting)
Third Adjacent Channel Rejection
(Offset = 3 ꢀ IF Filter BW Setting)
27
50
55
dB
dB
dB
IF filter BW setting = 12.5 kHz, 18.75 kHz, 25 kHz
Desired signal 3 dB above the input sensitivity
level, CW interferer power level
Increased until BER = 10−3, image channel
excluded
Image Channel Rejection
Co-Channel Rejection
Wideband Interference Rejection
35
−3
70
dB
dB
dB
Image at FRF − 200 kHz
Swept from 100 MHz to 2 GHz, measured as
channel rejection
BLOCKING
1 MHz
60
dB
Desired signal 3 dB above the input sensitivity
level, CW interferer power level
5 MHz
10 MHz
68
65
72
12
24 − j60
26 − j63
71 − j128
dB
dB
dB
dBm
Ω
Increased until BER = 10−2
10 MHz (High Linearity Mode)
Saturation (Maximum Input Level)
LNA Input Impedance
FSK mode, BER = 10−3
FRF = 915 MHz, RFIN to GND
FRF = 868 MHz
Ω
Ω
FRF = 433 MHz
RECEIVE SIGNAL STRENGTH INDICATOR (RSSI)
Range at Input
Linearity
Absolute Accuracy
Response Time
−110 to −36
2
3
dBm
dB
dB
150
μs
See the RSSI/AGC section
PHASE-LOCKED LOOP (PLL)
VCO Gain
65
MHz/V
902 MHz to 928 MHz band, VCO adjust = 0,
VCO_BIAS_SETTING = 8
130
65
−99
MHz/V
MHz/V
dBc/Hz
860 MHz to 870 MHz band, VCO adjust = 0
433 MHz, VCO adjust = 0
PA = 10 dBm, VDD = 3.0 V, PFD = 24.57 MHz,
Phase Noise (In-Band)
FRF = 433 MHz, VCO_BIAS_SETTING = 15
Phase Noise (Out-of-Band)
Residual FM
PLL Settling
−113
128
40
dBc/Hz
Hz
μs
1 MHz offset
From 200 Hz to 20 kHz, FRF = 868 MHz
Measured for a 10 MHz frequency step to
within 5 ppm accuracy, PFD = 20 MHz,
loop bandwidth (LBW) = 50 kHz
REFERENCE INPUT
Crystal Reference
External Oscillator
Load Capacitance
Crystal Start-Up Time
Input Level
3.625
3.625
TBD
TBD
MHz
MHz
pF
ms
CMOS
levels
33
2.1
PC board layout and crystal specific
11.0592 MHz crystal, using 33 pF load capacitors
See the Reference Input section
ADC PARAMETERS
INL
DNL
1
1
LSB
LSB
From 2.3 V to 3.6 V, TA = 25°C
From 2.3 V to 3.6 V, TA = 25°C
TIMING INFORMATION
Chip Enabled to Regulator Ready
Chip Enabled to RSSI Ready
Tx to Rx Turnaround Time
10
3.0
150 μs +
(5 ꢀ TBIT)
μs
ms
CREG = 100 nF
See Table 14 for more details
Time to synchronized data out, includes AGC
settling; see AGC Information and Timing
section for more details
Rev. PrI | Page 5 of 44
ADF7021
Preliminary Technical Data
Parameter
Min
Typ
Max
Unit
Test Conditions
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
0.7 ꢀ V DD
V
V
0.2 ꢀ
VDD
Input Current, IINH/IINL
Input Capacitance, CIN
Control Clock Input
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
CLKOUT Rise/Fall
1
10
50
μA
pF
MHz
DVDD − 0.4
V
V
ns
pF
°C
IOH = 500 μA
IOL = 500 μA
0.4
5
10
+85
CLKOUT Load
TEMPERATURE RANGE (TA)
POWER SUPPLIES
Voltage Supply
−40
2.3
VDD
3.6
V
All VDD pins must be tied together
VDD = 3.0 V, PA is matched into 50 Ω
FRF = 460 MHz
FRF = 460 MHz
FRF = 868 MHz
Transmit Current Consumption
0 dBm
10 dBm
0 dBm
10 dBm
12.7
21
19.3
28
mA
mA
mA
mA
FRF = 868 MHz
Receive Current Consumption
Low Current Mode
High Sensitivity Mode
Power-Down Mode
Low Power Sleep Mode
20
22
mA
mA
0.1
1
μA
1 For definition of frequency deviation, see the Register 2—Transmit Modulation Register section.
2 Measured as maximum unmodulated power. Output power varies with both supply and temperature.
3 For matching details, see the LNA/PA Matching section.
4 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks.
5 See Table 8 for a description of different receiver modes.
6 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.
Rev. PrI | Page 6 of 44
Preliminary Technical Data
ADF7021
TIMING CHARACTERISTICS
VDD = 3 V 10%, VGND = 0 V, TA = 25ꢀC, unless otherwise noted. Guaranteed by design, but not production tested.
Table 2.
Parameter
Limit at TMIN to TMAX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
SDATA to SCLK setup time
SDATA to SCLK hold time
SCLK high duration
SCLK low duration
SCLK to SLE setup time
t1
t2
t3
t4
t5
t6
t8
t9
t10
<10
<10
<25
<25
<10
<20
<25
<25
<10
SLE pulse width
SCLK to SREAD data valid, readback
SREAD hold time after SCLK, readback
SCLK to SLE disable time, readback
ns
t3
t4
SCLK
t1
t2
DB1
DB0 (LSB)
(CONTROL BIT C1)
SDATA
SLE
DB31 (MSB)
DB30
DB2
(CONTROL BIT C2)
t6
t5
Figure 2. Serial Interface Timing Diagram
t1
t2
SCLK
SDATA
SLE
REG7 DB0
(CONTROL BIT C1)
t3
t10
X
RV16
RV15
RV2
RV1
SREAD
t9
t8
Figure 3. Readback Timing Diagram
Rev. PrI | Page 7 of 44
ADF7021
Preliminary Technical Data
±1 × DATA RATE/32
1/DATA RATE
RxCLK
RxDATA
DATA
Figure 4. RxData/RxCLK Timing Diagram
1/DATA RATE
TxCLK
TxDATA
DATA
FETCH
SAMPLE
Figure 5. TxData/TxCLK Timing Diagram
Rev. PrI | Page 8 of 44
Preliminary Technical Data
ADF7021
ABSOLUTE MAXIMUM RATINGS
TA = 25ꢀC, unless otherwise noted.
Table 3.
Parameter
VDD to GND1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 V to +5 V
−0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
Analog I/O Voltage to GND
Digital I/O Voltage to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
MLF θJA Thermal Impedance
Reflow Soldering
−40°C to +85°C
−65°C to +125°C
150°C
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
26°C/W
Peak Temperature
Time-at-Peak Temperature
260°C
40 sec
ESD CAUTION
1 GND = CPGND = RFGND = DGND = AGND = 0 V.
Rev. PrI | Page 9 of 44
ADF7021
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
36
35
34
33
32
31
30
29
28
27
26
25
CLKOUT
VCOIN
2
DATA CLK | TxDATA
DATA I/O | RxDATA
SWD
CREG1
3
VDD1
4
RFOUT
5
VDD2
RFGND
ADF7021
6
7
RFIN
CREG2
TOP VIEW
ADCIN
RFINB
(Not to Scale)
8
GND2
R
LNA
9
SCLK
VDD4
RSET
10
11
12
SREAD
SDATA
CREG4
GND4
SLE
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Function
1
2
3
4
VCOIN
CREG1
VDD1
The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO).
The higher the tuning voltage, the higher the output frequency.
Regulator Voltage for PA Block. A 100 nF in parallel should be placed between this pin and ground for
regulator stability and noise rejection.
Voltage Supply for PA Block. Decoupling capacitors of 0.1 μF and 100 pF should be placed as close as
possible to this pin. All VDD pins should be tied together.
The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. The output
should be impedance matched to the desired load using suitable components. See the Transmitter
section.
RFOUT
5
6
RFGND
RFIN
Ground for Output Stage of Transmitter. All GND pins should be tied together.
LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer. See the LNA/PA Matching section.
7
8
RFINB
RLNA
Complementary LNA Input. See the LNA/PA Matching section.
External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
9
10
11
VDD4
RSET
CREG4
Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.
External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ with 5% tolerance.
Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND
for regulator stability and noise rejection.
12
GND4
Ground for LNA/MIXER Block.
13 to 18 MIX_I, MIX_I, MIX_Q, Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
MIX_Q, FILT_I, FILT_I,
19, 22
GND4
Ground for LNA/MIXER Block.
20, 21,
23
FILT_Q, FILT_Q,
TEST_A
CE
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
24
25
26
27
Chip Enable. Bringing CE low puts the ADF7021 into complete power-down. Register values are lost when
CE is low, and the part must be reprogrammed once CE is brought high.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches. A latch is selected using the control bits.
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high
impedance CMOS input.
Serial Data Output. This pin is used to feed readback data from the ADF7021 to the microcontroller. The
SCLK input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin.
SLE
SDATA
SREAD
Rev. PrI | Page 10 of 44
Preliminary Technical Data
ADF7021
Pin No. Mnemonic
Function
28
SCLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.
29
30
GND2
ADCIN
Ground for Digital Section.
Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V
to 1.9 V. Readback is made using the SREAD pin.
31
32
33
CREG2
VDD2
SWD
Regulator Voltage for Digital Block. A 100 nF capacitor should be placed between this pin and ground for
regulator stability and noise rejection.
Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to
this pin.
Sync Word Detect. The ADF7021 asserts this pin when it has found a match for the sync word sequence
(See the Register 11—Sync Word Detect Register section). This provides an interrupt for an external
microcontroller indicating valid data is being received.
34
35
DATA I/O | RxDATA
DATA CLK | TxDATA
Transmit Data Input/Received Data Output. This is a digital pin and normal CMOS levels apply.
In UART mode, this pin provides an output for the received data in receive mode. In transmit mode, this
pin is high impedance (see the Register 0—N Register section).
Outputs the data clock in both receive and transmit modes. This is a digital pin and normal CMOS levels
apply. The positive clock edge is matched to the center of the received data. In transmit mode, this pin
outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact
required data rate. In UART mode, this pin is used to input the transmit data in transmit mode. In receive
mode, this pin is high impedance (see the Register 0—N Register section).
36
37
CLKOUT
A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to
drive several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio.
Provides the Lock_Detect Signal. This signal is used to determine if the PLL is locked to the correct
frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial interface
regulator (see the Register 0—N Register section).
MUXOUT
38
OSC2
The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by
driving this pin with CMOS levels and disabling the crystal oscillator.
39
40
OSC1
VDD3
The reference crystal should be connected between this pin and OSC2.
Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a
10 nF capacitor.
41
42
CREG3
CPOUT
Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF capacitor should be placed between this
pin and ground for regulator stability and noise rejection.
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The
integrated current changes the control voltage on the input to the VCO.
43
44, 46
VDD
L2, L1
Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 10 nF capacitor.
External VCO Inductor Pins. If using an external VCO inductor, a chip inductor should be connected across
these pins to set the VCO operating frequency. If using the internal VCO inductor, these pins can be left
floating. See the Voltage Controlled Oscillator (VCO) section for more information.
Grounds for VCO Block.
45, 47
48
GND, GND1
CVCO
A 22 nF capacitor should be placed between this pin and CREG1 to reduce VCO noise.
Rev. PrI | Page 11 of 44
ADF7021
Preliminary Technical Data
FREQUENCY SYNTHESIZER
REFERENCE INPUT
R Counter
The 3-bit R counter divides the reference input frequency by an
integer from 1 to 7. The divided-down signal is presented as the
reference clock to the phase frequency detector (PFD). The
divide ratio is set in Register 1. Maximizing the PFD frequency
reduces the N value. This reduces the noise multiplied at a rate
of 20 log(N) to the output and reduces occurrences of spurious
components. Register 1 defaults to R = 1 on power-up:
The on-board crystal oscillator circuitry (see Figure 7) can use
an inexpensive quartz crystal as the PLL reference. The oscil-
lator circuit is enabled by setting R1_DB12 high. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected by using the automatic frequency
control feature or by adjusting the fractional-N value (see the N
Counter section). A single-ended reference (TCXO, CXO) can
also be used. The CMOS levels should be applied to OSC2 with
R1_DB12 set low.
PFD [Hz] = XTAL/R
Loop Filter
The loop filter integrates the current pulses from the charge
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
the PLL. A typical loop filter design is shown in Figure 9.
OSC1
OSC2
CP1
CP2
Figure 7. Oscillator Circuit on the ADF7021
CHARGE
VCO
PUMP OUT
Two parallel resonant capacitors are required for oscillation at
the correct frequency. Their values are dependent upon the
crystal specification. They should be chosen to make sure that
the series value of capacitance added to the PCB track
capacitance adds up to the load capacitance of the crystal,
usually 18 pF to 20 pF. Track capacitance values vary from 2 pF
to 5 pF, depending on board layout. When possible, choose
capacitors that have a very low temperature coefficient to
ensure stable frequency operation over all conditions.
Figure 9. Typical Loop Filter Configuration
The loop should be designed so that the loop bandwidth (LBW)
is approximately three times the data rate. Widening the LBW
excessively reduces the time spent jumping between
frequencies, but can cause insufficient spurious attenuation.
Narrow-loop bandwidths can result in the loop taking long
periods of time to attain lock. Careful design of the loop filter is
critical to obtain accurate modulation.
Programmable Crystal Bias Current
Bias current in the oscillator circuit can be configured between
20 μA and 35 μA by writing to Bits R1_DB[13:14].
When using the Gaussian or raised cosine data filtering options,
it is recommended to use a LBW of 2.0 to 2.5 times the data rate
to ensure that sufficient samples of the input data are taken
while filtering system noise. The free design tool ADIsimPLL
can be used to design loop filters for the ADF7021.
CLKOUT Divider and Buffer
The CLKOUT circuit takes the reference clock signal from the
oscillator section, shown in Figure 7, and supplies a divided-
down 50:50 mark-space signal to the CLKOUT pin. An even
divide from 2 to 30 is available. This divide number is set in
R1_DB[7:10]. On power-up, the CLKOUT defaults to divide-by-8.
N Counter
The feedback divider in the ADF7021 PLL consists of an 8-bit
integer counter and a 15-bit Σ-Δ fractional-N divider. The
integer counter is the standard pulse-swallow type common in
PLLs. This sets the minimum integer divide value to 23. The
fractional divide value gives very fine resolution at the output,
where the output frequency of the PLL is calculated as
DV
DD
CLKOUT
ENABLE BIT
DIVIDER
1 TO 15
OSC1
÷2
CLKOUT
Fractional − N
⎛
⎞
XTAL
R
⎜
⎟
⎟
FOUT
=
× Integer _ N +
215
⎜
⎝
Figure 8. CLKOUT Stage
⎠
To disable CLKOUT, set the divide number to 0. The output
buffer can drive up to a 20 pF load with a 10% rise time at
4.8 MHz. Faster edges can result in some spurious feedthrough
to the output. A small series resistor (50 Ω) can be used to slow
When VCO divide-by-2 (see the Voltage Controlled Oscillator
(VCO) section) is selected, this formula becomes:
XTAL
R
Fractional − N
⎛
⎝
⎞
⎟
⎠
FOUT
=
×0.5× Integer_N +
⎜
215
the clock edges to reduce these spurs at FCLK
.
Rev. PrI | Page 12 of 44
Preliminary Technical Data
ADF7021
REFERENCE IN
regulator, the regulator must be at its nominal voltage before the
ADF7021 can be programmed. The status of the regulator can
be monitored at MUXOUT. When the regulator ready signal on
MUXOUT is high, programming of the ADF7021 can begin.
PFD/
4\R
CHARGE
PUMP
VCO
4\N
DV
DD
THIRD-ORDER
Σ-Δ MODULATOR
REGULATOR READY (DEFAULT)
FILTER CAL COMPLETE
DIGITAL LOCK DETECT
RSSI READY
FRACTIONAL-N
INTEGER-N
Figure 10. Fractional-N PLL
MUX
CONTROL
MUXOUT
Tx_Rx
LOGIC ZERO
TRISTATE
The combination of the integer-N (maximum = 255) and the
fractional-N (maximum = 32768/32768) give a maximum N
divider of 255 + 1. Therefore, the minimum usable PFD is
LOGIC ONE
Maximum Required Output Frequency
PFDMIN Hz =
[ ]
(
255 +1
)
DGND
Figure 11. MUXOUT Circuit
For example, when operating in the European 868 MHz to
870 MHz band, PFDMIN equals 3.4 MHz.
Filter Cal Complete
Voltage Regulators
MUXOUT can be set to filter cal complete, which is active high.
This indicates when a fine filter calibration has been completed.
It can be used as an interrupt to a microcontroller.
The ADF7021 contains four regulators to supply stable voltages
to the part. The nominal regulator voltage is 2.3 V. Each
regulator should have a 100 nF capacitor connected between
CREG and GND. When CE is high, the regulators and other
associated circuitry are powered on, drawing a total supply
current of 2 mA. Bringing the CE pin low disables the
regulators, reduces the supply current to less than 1 μA, and
erases all values held in the registers. The serial interface
operates from a regulator supply; therefore, to write to the part,
the user must have CE high and the regulator voltage must be
stabilized. Regulator status (CREG4) can be monitored using
the regulator ready signal from muxout.
Digital Lock Detect
Digital lock detect indicates when the PLL has locked. The lock
detect circuit is located at the PFD. When the phase error on
five consecutive cycles is less than 15 ns, lock detect is set high.
Lock detect remains high until a 25 ns phase error is detected at
the PFD.
RSSI Ready
MUXOUT can be set to RSSI ready. This indicates that the
internal analog RSSI has settled and a digital RSSI readback can
be performed.
MUXOUT
TX_RX
The MUXOUT pin allows the user to access various digital
points in the ADF7021. The state of MUXOUT is controlled by
Bits R0_DB[29:31].
TX_RX signifies whether the ADF7021 is in transmit or receive
mode. When in transmit ,mode, this signal is low. When in
receive mode, this signal is high. It can be used to control an
external Tx/Rx switch.
Regulator Ready
Regulator ready is the default setting on MUXOUT after the
transceiver is powered up. The power-up time of the regulator is
typically 50 μs. Because the serial interface is powered from the
Rev. PrI | Page 13 of 44
ADF7021
Preliminary Technical Data
Using the External VCO Inductor
VOLTAGE CONTROLLED OSCILLATOR (VCO)
When using an external inductor, the center frequency of the
VCO is set by the internal varactor capacitance and the
To minimize spurious emissions, the on-chip VCO operates
from 1724 MHz to 1880 MHz. The VCO signal is then divided
by 2 to give the required frequency for the transmitter and the
required LO frequency for the receiver.
combined inductance of the external chip inductor, bond wire,
and PCB track. A plot of the VCO operating frequency vs. total
external inductance (chip inductor + PCB track) is shown in
Figure 13. The inductance for a PCB track using FR4 material is
approximately 0.57 nH/mm. This should be subtracted from the
total value to determine the correct chip inductor value.
The VCO should be recentered, depending on the required
frequency of operation, by programming the VCO adjust bits
R1_DB[23:24]. The VCO is enabled by Bit R1_DB17.
A further frequency divide-by-2 is included after the PLL to
allow operation from 432 MHz to 470 MHz using the internal
VCO inductor and 80 MHz to 325 MHz using the external VCO
inductor. This divide-by-2 is enabled by setting R1_DB18 to 1.
750
700
650
F
(MHz)
MAX
600
550
500
450
400
350
300
250
200
The VCO needs an external 22 nF capacitor between the VCO
and the regulator to reduce internal noise.
VCO BIAS
R1_DB(19:22)
LOOP FILTER
VCO
MUX
÷2
TO PA
F
(MHz)
MIN
÷2
220µF
CVCO PIN
0
5
10
15
20
25
30
TO
N DIVIDER
DIVIDE BY 2
R1_DB18
TOTAL EXTERNAL INDUCTANCE (nH)
Figure 13. VCO Operating Frequency vs. Total External Inductance
Figure 12. Voltage Controlled Oscillator (VCO)
VCO bias current can be adjusted using Bits R1_DB[19:22]. To
minimize current consumption and to ensure reliable
operation, the bias current setting should be as indicated in
Table 6.
The ADF7021 on-chip VCO can use either an internal or
external tank inductor. The possible frequency ranges are given
in Table 5.
Table 5. RF Output Frequency Ranges for Internal/External
VCO Inductor and Divide-by-2 Enabled/Disabled
Table 6. Recommended VCO Bias Currents for External
VCO Inductor
RF Frequency
Output (MHz)
Int/Ext VCO Inductor Divide-by-2
RF Frequency Output (f)
VCO Bias R1_DB[19:22]
R1_DB25
R1_DB18
f < 200 MHz
200 MHz < f < 450 MHz
f > 450 MHz
0001
0010
0011
862 to 940
431 to 470
135 to 650
80 to 325
0
0
1
1
0
1
0
1
CHOOSING CHANNELS FOR BEST SYSTEM
PERFORMANCE
Internal VCO Inductor
To select the internal VCO inductor, set R1_DB25 to Logic 0,
which is the default setting.
The architecture of fractional-N results in some level of the
nearest integer channel moving through the loop to the RF
output. These beat-note spurs are not attenuated by the loop, if
the desired RF channel and the nearest integer channel are
separated by a frequency of less than the LBW. The occurrence
of beat-note spurs is rare because the integer frequencies are at
multiples of the reference, which is typically >10 MHz. Beat-
note spurs can be significantly reduced in amplitude by
avoiding very small or very large values in the fractional register
using the frequency doubler.
VCO bias current can be adjusted using Bits R1_DB[19:22]. To
ensure VCO oscillation, the minimum bias current setting under
all conditions when using the internal VCO inductor is 0xA.
The VCO should be recentered, depending on the required
frequency of operation, by programming the VCO adjust bits
R1_DB[23:24].
Rev. PrI | Page 14 of 44
Preliminary Technical Data
ADF7021
TRANSMITTER
If the PA is enabled/disabled by the PA_ENABLE bit in
RF OUTPUT STAGE
Register 2 (R2_DB7) it ramps up at the programmed rate but
turns hard off. If the PA is enabled/disabled by the TX_RX bit
in Register 0 (R0_DB27), it ramps up and down at the
programmed rate.
The power amplifier (PA) of the ADF7021 is based on a single-
ended, controlled current, open-drain amplifier that has been
designed to deliver up to 13 dBm into a 50 Ω load at a
maximum frequency of 940 MHz.
1
2
3
4
...
8
... 16
The PA output current and, consequently, the output power are
programmable over a wide range. The PA configuration is shown
in Figure 14. The output power is set using Bits R2_DB[13:18].
R2_DB(11:12)
DATA BITS
PA RAMP 0
(NO RAMP)
PA RAMP 1
(256 CODES/BIT)
2
PA RAMP 2
(128 CODES/BIT)
6
IDAC
R2_DB(13:18)
PA RAMP 3
(64 CODES/BIT)
PA RAMP 4
(32 CODES/BIT)
RFOUT
RFGND
R2_DB7
PA RAMP 5
(16 CODES/BIT)
+
R0_DB27
PA RAMP 6
(8 CODES/BIT)
PA RAMP 7
(4 CODES/BIT)
FROM VCO
Figure 15. PA Ramping Settings
Figure 14. PA Configuration in FSK/GFSK Mode
PA Bias Currents
The PA is equipped with overvoltage protection, which makes it
robust in severe mismatch conditions. Depending on the appli-
cation, users can design a matching network for the PA to
exhibit optimum efficiency at the desired radiated output power
level for a wide range of different antennas, such as loop or
mono-pole antennas. See the LNA/PA Matching section for
details.
Control Bits R2_DB[11:12] facilitate an adjustment of the PA
bias current to further extend the output power control range, if
necessary. If this feature is not required, the default value of
7 μA is recommended. If output power of greater than 10 dBm
is required, a PA bias setting of 11 μA is recommended. The
output stage is powered down by resetting Bit R2_DB7.
PA Ramping
MODULATION SCHEMES
When the PA is switched on or off quickly, its changing input
impedance momentarily disturbs the VCO output frequency.
This process is called VCO pulling, and it manifests as spectral
splatter, or spurs in the output spectrum around the desired
carrier frequency. Some radio emissions regulations now place
limits on these PA transient-induced spurs (for example,
ETSI EN 300-220). By gradually ramping the PA on and off, PA
transient spurs can be minimized. The ADF7021 has built-in
PA ramping configurability. As Figure 15 illustrates, there are
eight ramp rate settings, defined as a certain number of PA
setting codes per one data-bit period. The PA steps through
each of its 64 code levels, but at different speeds for each setting.
The ramp rate is set by configuring Bits R2_DB[8:10].
In all modulation schemes, an accurate clock is provided on the
DATA_CLK pin to latch the data from the microcontroller into
the transmit section at the exact required data rate. The exact
frequency of this clock is defined by:
XTAL
DATA_CLK =
DEMOD _ DIVIDER×CDR _ DIVIDER×32
where:
XTAL is the crystal frequency.
DEMOD_DIVIDER is the divider that sets the demod-clock rate
(R3_DB[6:9]).
CDR_DIVIDER is the divider that sets the CDR clock rate
(R3_DB[10:17]).
Rev. PrI | Page 15 of 44
ADF7021
Preliminary Technical Data
Binary Frequency Shift Keying (2FSK)
shaping is P(D) = 1 − D2. A precoder with transfer function
1/P(D) is used to undo the encoding process of the
convolutional code P(D) at the transmitter side.
Two-level frequency shift keying is implemented by setting the
N value for the center frequency and then toggling it with the
TxDATA line. The deviation from the center frequency is set
using Bits R2_DB[19:27]. The deviation from the center
frequency in Hz is:
Tx DATA
0, 1
0, 1
CONVOLUTIONAL
ENCODER
P(D)
PRECODER
1/P(D)
Direct RF output:
0, +1, –1
PFD×TX _ FREQUENCY _ DEVIATION
F
F
F
FSK DEVIATION [Hz] =
C
C
C
216
FSK MOD
CONTROL
+ F
– F
DEV
DEV
TO
AND
DATA FILTERING
N DIVIDER
Divide-by-2 enabled:
FSK DEVIATION [Hz] = 0.5×
Figure 17. 3FSK Encoding
PFD ×TX _ FREQUENCY _ DEVIATION
The signal map of one-zero binary data to the 3-level convolu-
tional output follows. The convolutional encoder restricts the
maximum number of sequential +1’s or −1’s to two and also
delivers an equal number of +1’s and −1’s to the FSK modulator,
thus ensuring equal spectral energy in both 3FSK sidebands.
216
where:
TX_FREQUENCY_DEVIATION is a number from 1 to 511
(R2_DB[19:27]).
3-Level Signal Mapping of the Convolutional Encoder
Tx DATA
1
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
0
1
Precoder O/P
Encoder O/P
1
0
1
1
0
+1
−1 +1
+1
−1
PFD/
CHARGE
PUMP
PA STAGE
4R
VCO
÷N
3FSK is selected by setting bits in R2_DB[4:6]. It can also be
used with raised cosine filtering to further increase the spectral
efficiency of the transmit signal.
FSK DEVIATION
FREQUENCY
–F
Four-Level Frequency Shift Keying (4FSK)
DEV
THIRD-ORDER
Σ-Δ MODULATOR
+F
Four-level frequency shift keying differs from binary FSK in
that four possible frequencies are used to represent each pair of
data bits to be transmitted instead of two possible frequencies
for each bit of data. This halves the symbol rate because a
frequency change is only required after every second bit. It also
doubles the number of symbols because there are four possible
arrangements of a pair of consecutive NRZ data bits. By
minimizing the separation between symbol frequencies, 4FSK
can have high spectral efficiency.
DEV
TxDATA
FRACTIONAL-N
INTEGER-N
Figure 16. 2FSK Implementation
Three-Level Frequency Shift Keying (3FSK)
In three-level FSK modulation (also known as ternary FSK), the
binary data (Logic 0 and Logic 1) is mapped onto three distinct
frequencies:
•
•
the carrier frequency (FC),
the carrier frequency minus a deviation frequency
(FC − FDEV), and
Tx DATA
0
0
0
1
1
0
1
1
F
•
the carrier frequency plus the deviation frequency
(FC + FDEV).
+3F
+F
DEV
DEV
DEV
DEV
A Logic 0 is mapped to the carrier frequency while a Logic 1 is
either mapped onto frequency FC − FDEV or FC + FDEV
SYMBOL
FREQUENCIES
.
–F
The bits to frequency mapping result in a reduced transmission
bandwidth as energy is removed from the sidebands and
transferred to the carrier frequency. This increases the spectral
efficiency in comparison to 2FSK.
–3F
t
To ensure there is no loss in SNR at the receiver due to the
ternary nature of the modulation, a simple convolutional
encoder is used. A block diagram of the transmit hardware used
to realize this system is shown in Figure 17. The convolutional
encoder polynomial used to implement the transmit spectral
Figure 18. 4FSK Encoding
Oversampled 2FSK
In oversampled 2FSK, the data is sampled at 32 times the
programmed rate, allowing odd data rates.
Rev. PrI | Page 16 of 44
Preliminary Technical Data
ADF7021
SPECTRAL SHAPING
MODULATION AND FILTERING OPTIONS
Gaussian or raised cosine filtering can be used to improve
transmit spectral efficiency. The ADF7021 supports Gaussian
filtering (BT = 0.5) on 2FSK modulation. Raised cosine filtering
(alpha = 0.5) can be used with 2FSK, 3FSK, or 4FSK
modulation.
The various modulation and data filtering options are described
in Table 7.
Table 7. Modulation and Filtering Options on the ADF7021
Modulation
Data Filtering
R2_DB[4:6]
2FSK
None
000
Gaussian Frequency Shift Keying (GFSK)
Gaussian
Raised cosine
None
001
101
010
Gaussian frequency shift keying reduces the bandwidth
occupied by the transmitted spectrum by digitally prefiltering
the transmit data. The bandwidth time (BT) product of the
Gaussian filter used is 0.5.
3FSK
Raised cosine
None
110
011
4FSK
Raised cosine
None
111
100
Gaussian filtering can just be used with 2FSK modulation. This
is selected by setting Bits R2_DB[4:6] to 001.
Oversampled 2FSK
Raised Cosine Filtering
Raised cosine filtering provides digital prefiltering of the
transmit data using a rasied cosine filter with a roll-off factor
(alpha) of 0.5. Rasied cosine filtering can be used with 2FSK,
3FSK, and 4FSK.
Raised cosine filtering is enabled by setting Bits R2_DB[4:6] as
outlined in Table 7.
Rev. PrI | Page 17 of 44
ADF7021
Preliminary Technical Data
RECEIVER SECTION
Based on the specific sensitivity and linearity requirements of
the application, it is recommended to adjust control bits LNA
mode (R9_DB25) and mixer linearity (R9_DB28) as outlined in
Table 8.
RF FRONT END
The ADF7021 is based on a fully integrated, low IF receiver
architecture. The low IF architecture facilitates a very low
external component count and does not suffer from power-
line-induced interference problems.
The gain of the LNA is configured by the LNA gain field,
R9_DB[20:21], and can be set by either the user or the
automatic gain control (AGC) logic.
Figure 19 shows the structure of the receiver front end. The
many programming options allow users to trade off sensitivity,
linearity, and current consumption against each other in the
way best suited for their applications. To achieve a high level of
resilience against spurious reception, the low noise amplifier
(LNA) features a differential input. Switch SW2 shorts the LNA
input when transmit mode is selected (R0_DB27 = 0). This
feature facilitates the design of a combined LNA/PA matching
network, avoiding the need for an external Rx/Tx switch. See
the LNA/PA Matching section for details on the design of the
matching network.
IF Filter Settings
Out-of-band interference is rejected by means of a fifth-order
Butterworth polyphase IF filter centered on a frequency of
100 kHz. The bandwidth of the IF filter can be programmed
between 12.5 kHz and 25 kHz by Control Bits R4_DB[30:31], and
should be chosen as a compromise between interference
rejection, attenuation of the desired signal, and the AFC pull-in
range.
Coarse/Fine Filter Calibration
I (TO FILTER)
To compensate for manufacturing tolerances, the IF filter
should be calibrated once after power-up. Coarse and fine
calibration schemes are provided in order to offer a choice
between fast calibration with the coarse scheme and high filter
centering accuracy with fine calibration. Coarse calibration is
enabled by setting Bit R5_DB4 high. Fine calibration is enabled
by setting Bit R6_DB4 high. It is necessary to do a coarse cali-
bration before doing a fine calibration. If the IF_FINE_CAL bit,
R6_DB4, has already been configured high, it is possible to do a
fine calibration by writing only to Register 5. Once initiated by
writing to the part, the calibration is performed automatically
without any user intervention. Calibration time is 200 μs for coarse
calibration and a few milliseconds for fine calibration, during
which the ADF7021 should not be accessed. The IF filter
calibration logic requires that the IF filter divider in Bits
R5_DB[5:13] be set depending on the crystal frequency. It is
important not to initiate the calibration cycle before the crystal
oscillator has fully settled. If the AGC loop is disabled, the gain
of IF filter can be set to three levels using the Filter Gain Field,
R9_DB[22:23]. The filter gain is adjusted automatically if the
AGC loop is enabled.
RFIN
Tx/Rx SELECT
SW2 LNA
LO
[R0_DB27]
RFINB
Q (TO FILTER)
LNA MODE
[R9_DB25]
MIXER LINEARITY
[R9_DB28]
LNA CURRENT
[R9_DB(26:27)]
LNA GAIN
[R9_DB(20:21)]
LNA/MIXER ENABLE
[R8_DB6]
Figure 19. ADF7021 RF Front End
The LNA is followed by a quadrature downconversion mixer,
which converts the RF signal to the IF frequency of 100 kHz.
An important consideration is that the output frequency of the
synthesizer must be programmed to a value 100 kHz below the
center frequency of the received channel.
The LNA has two basic operating modes: high gain/low noise
mode and low gain/low power mode. To switch between these
two modes, use the LNA Mode Bit, R9_DB25. The mixer is also
configurable between a low current and an enhanced linearity
mode using the Mixer Linearity Bit, R9_DB28.
Table 8. LNA/Mixer Modes
LNA
Mixer
Linearity
Sensitivity
(DR = 9.6 kbps,
FDEV = 4.8 kHz)
Rx Current
Consumption
(mA)
LNA Mode Gain Value
(R9_DB25) (R9_DB[20:21]) (R9_DB28)
Input IP3
(dBm)
Receiver Mode
High Sensitivity Mode (default)
Rx Mode2
Low Current Mode
Enhanced Linearity Mode
Rx Mode5
0
1
1
1
1
0
30
10
3
3
10
30
0
0
0
1
1
1
−117
TBD
TBD
TBD
TBD
TBD
22
20
19
19
20
21
TBD
TBD
TBD
TBD
TBD
TBD
Rx Mode6
Rev. PrI | Page 18 of 44
Preliminary Technical Data
ADF7021
where:
RSSI/AGC
AGC Settling = AGC_Wait_Time × Number of Gain Changes
The RSSI is implemented as a successive compression log amp
following the base band channel filtering. The log amp achieves
3 dB log linearity. It also doubles as a limiter to convert the
signal-to-digital levels for the FSK demodulator. Offset
correction is achieved using a switched capacitor integrator in
feedback around the log amp. This uses the BB offset clock
divide. The RSSI level is converted for user readback and
digitally controlled AGC by an 80-level (7-bit) flash ADC. This
level can be converted to input power in dBm.
Thus, in the worst-case scenario, if the AGC loop has to go
through all five gain changes,
AGC_Delay =10 cycles
SEQ_CLK = 200 kHz
AGC Settling = 10 × 5 μs × 5 = 250 μs
Minimum AGC_Wait_Time must be at least 25 μs.
RSSI Formula (Converting to dBm)
Input_Power [dBm] = −120 dBm +
OFFSET
(Readback_Code + Gain_Mode_Correction) × 0.5
CORRECTION
FSK
DEMOD
where:
1
A
A
A
LATCH
CLK
Readback_Code is given by Bit RV7 to Bit RV1 in the readback
register (see the Readback Format section).
IFWR
IFWR
IFWR
IFWR
Gain_Mode_Correction is given by the values in Table 9.
RSSI
ADC
LNA gain (LG2, LG1) and filter gain (FG2, FG1) are obtained
from Register 9.
R
Figure 20. RSSI Block Diagram
Table 9. Gain Mode Correction
RSSI Thresholds
LNA Gain
(LG2, LG1)
Filter Gain
(FG2, FG1)
Gain Mode
Correction
When the RSSI is above AGC_HIGH_THRESHOLD, the gain
is reduced. When the RSSI is below AGC_LOW_THRESHOLD,
the gain is increased. A delay (AGC_DELAY) is programmed to
allow for settling of the loop. All of these parameters are set in
Register 9. The user can program the two threshold values
(defaults 30 and 70) and the delay value (default 10). The
default AGC setup values should be adequate for most
applications. The threshold values must be chosen to be more
than 30 apart for the AGC to operate correctly.
H (1, 0)
H (1, 0)
M (0, 1)
L (0, 0)
L (0, 0)
H (1, 0)
M (0, 1)
M (0, 1)
M (0,1)
L (0, 0)
TBD
TBD
TBD
TBD
TBD
An additional factor should be introduced to account for losses
in the front-end-matching network/antenna.
FSK DEMODULATORS ON THE ADF7021
Offset Correction Clock
There are four demodulators on the ADF7021:
In Register 3, the user should set the BB Offset Clock Divide
Bits R3_DB[4:5] to give an offset clock between 1 MHz and 2
MHz:
•
•
•
•
2FSK correlator/demodulator
2FSK linear demodulator
3FSK demodulator
BBOS_CLK [Hz] = XTAL/(BBOS_CLK_DIVIDE)
where:
4FSK demodulator
BBOS_CLK_DIVIDE can be set to 4, 8, or 16.
AGC Information and Timing
Select these using the Demod Scheme Bits, R4_DB[4:6].
FSK CORRELATOR/DEMODULATOR
AGC is selected by default and operates by selecting the
appropriate LNA and filter gain settings for the measured RSSI
level. It is possible to disable AGC by writing to Register 9 if the
user wants to enter one of the modes listed in Table 8. The time
for the AGC circuit to settle and therefore, the time it takes to
measure the RSSI accurately, is typically 150 μs. However, this
depends on how many gain settings the AGC circuit has to
cycle through. After each gain change, the AGC loop waits for a
programmed time to allow transients to settle. This wait time
can be altered to speed up the settling by adjusting the
appropriate parameters.
The quadrature outputs of the IF filter are first limited and then
fed to a pair of digital frequency correlators that perform band-
pass filtering of the binary FSK frequencies at (IF + FDEV) and
(IF − FDEV). Data is recovered by comparing the output levels
from each of the two correlators. The performance of this
frequency discriminator approximates that of a matched filter
detector, which is known to provide optimum detection in the
presence of AWGN.
AGC_ Delay ×SEQ_CLK _ DIVIDE
AGC_Wait _Time =
XTAL
Rev. PrI | Page 19 of 44
ADF7021
Preliminary Technical Data
FREQUENCY CORRELATOR
IF
SLICER
Discriminator_BW = DEMOD_CLK × K/(400 × 103)
RxDATA
RxCLK
I
where:
LIMITERS
Q
DEMOD_CLK is as defined in the Register 3—
Transmit/Receive Clock Register Comments section.
K = Round (100e3/Fdeviation) and Fdeviation is the 2FSK
frequency deviation in Hz.
IF – F
DEV
IF + F
DEV
0
R3_DB(10:17)
R4_DB(10:19)
R4_DB(20:29)
R4_DB(7)
R4_DB(9)
To optimize the coefficients of the 2FSK correlator, Bits R4_DB7
and R4_DB[8:9] must be assigned. The value of these bits
depends on whether K is odd or even. These bits are assigned
according to Table 10 and Table 11.
Figure 21. FSK Correlator/Demodulator Block Diagram
Postdemodulator Filter
A second-order, digital low-pass filter removes excess noise
from the demodulated bit stream at the output of the
discriminator. The bandwidth of this postdemodulator filter is
programmable and must be optimized for the user’s data rate. If
the bandwidth is set too narrow, performance is degraded due
to intersymbol interference (ISI). If the bandwidth is set too
wide, excess noise degrades the receiver’s performance.
Typically, the 3 dB bandwidth of this filter is set at
approximately 0.75 times the user’s data rate, using Bits
R4_DB[20:29].
Table 10. When K Is Even
K
K/2
R4_DB7
R4_DB[8:9]
Even
Even
Even
Odd
0
0
00
10
Table 11. When K Is Odd
K
(K + 1)/2
R4_DB7
R4_DB[8:9]
Odd
Odd
Even
Odd
1
1
00
10
Bit Slicer
The received data is recovered by threshold detecting the output of
the postdemodulator low-pass filter. In the correlator/demodulator,
the binary output signal levels of the frequency discriminator are
always centered on 0. Therefore, the slicer threshold level can be
fixed at 0 and the demodulator performance is independent of
the run-length constraints of the transmit data bit stream. This
results in robust data recovery, which does not suffer from the
classic baseline wander problems that exist in the more traditional
FSK demodulators.
Postdemodulator Bandwidth Register Settings
The 3 dB bandwidth of the postdemodulator filter is controlled
by Bits R4_DB[20:29] and is given by
2
11 ×π × FCUTOFF
Post _ Demod _ BW _ Setting =
DEMOD _CLK
where:
CUTOFF is the target 3 dB bandwidth in Hz of the postdemodulator
F
filter. This should typically be set to 0.75 times the data rate (DR).
Frequency errors are removed by an internal AFC loop that
measures the average IF frequency at the limiter output and
applies a frequency correction value to the fractional-N
synthesizer. This loop should be activated when the frequency
errors are greater than approximately 40% of the transmit
frequency deviation.
Some sample settings for the FSK correlator/demodulator are
DEMOD_CLK = 11.0592 MHz
DR = 9.6 kbps
F
DEV = 4.8 kHz
therefore,
Data Synchronizer
F
CUTOFF = 0.75 × 9.6 × 103 Hz
An oversampled digital PLL is used to resynchronize the
received bit stream to a local clock. The oversampled clock rate
of the PLL (CDR_CLK) must be set at 32 times the data rate.
See the Register 3—Transmit/Receive Clock Register section for
programming notes. The clock recovery PLL can accommodate
frequency errors of up to 2%.
Post_Demod_BW = 211 × π × 7.2 × 103 Hz/(11.0592 × 106)
Post_Demod_BW = Round(4.188) = 4
and
K = Round(100 kHz)/4.8 kHz) = 21
Discriminator_BW = (11.0592 × 106 × 21)/(400 × 103) =
580.6 = 581 (rounded to nearest integer)
FSK Correlator Register Settings
To enable the FSK correlator/demodulator, Bits R4_DB[4:6]
should be set to 001. To achieve best performance, the
bandwidth of the 2FSK correlator must be optimized for the
specific deviation frequency that is used by the 2FSK
transmitter.
Table 12. Example Register Settings
Setting Name
Post_Demod_BW
Discriminator BW
Dot Product
Register Address
R4_DB[20:29]
R4_DB[10:19]
R4_DB7
Value
0x04
0x245
1
The discriminator BW is controlled in Register 4 by DB[10:19]
and is defined as
Rx Data Invert
R4_DB[8:9]
10
Rev. PrI | Page 20 of 44
Preliminary Technical Data
ADF7021
LINEAR 2FSK DEMODULATOR
3FSK DEMODULATOR
Figure 22 shows a block diagram of the linear 2FSK
demodulator.
The 3FSK demodulator uses a pair of digital frequency
correlators followed by a Viterbi decoder and clock and data
recovery to perform three-level FSK demodulation. To enable
3FSK demodulation, Bits R4_DB[4:6] must be set to 010. The
settings for the 3FSK demodulator are set in Register 13. The
post demod BW, discriminator BW, dot product, and Rx invert
settings of Register 4 also need to be set appropriately as
outlined in the FSK Correlator/Demodulator section.
SLICER
LEVEL
I
RxDATA
IF
LIMITER
Q
FREQUENCY
FREQUENCY
READBACK
AND
4FSK DEMODULATOR
LINEAR DISCRIMINATOR
The 4FSK demodulator uses a pair of digital frequency
correlators and clock and data recovery to perform four-level
FSK demodulation. To enable 4FSK demodulation, Bits
R4_DB[4:6] must be set to 011. The post demod BW,
discriminator BW, dot product, and Rx invert settings of
Register 4 also need to be set appropriately as outlined in the
FSK Correlator/Demodulator section.
AFC LOOP
R4_DB(20:29)
Figure 22. Block Diagram of Frequency Measurement System and
Linear FSK Demodulator
This method of frequency demodulation is useful when the
system protocol cannot support the overhead of the settling
time of the internal feedback AFC loop.
AFC SECTION
A digital frequency discriminator provides an output signal that
is linearly proportional to the frequency of the limiter outputs.
The discriminator output is then filtered and averaged using a
combined averaging filter and envelope detector. The demodu-
lated 2FSK data is recovered by threshold detecting the output
of the averaging filter, as shown in Figure 22. In this mode, the
slicer output shown in Figure 22 is routed to the data synchro-
nizer PLL for clock synchronization. To enable the linear FSK
demodulator, set Bits R4_DB[4:6] to 000.
The ADF7021 supports a real-time AFC loop that is used to
remove frequency errors that can arise due to mismatches between
the transmit and receive crystals. The AFC loop also uses the
frequency discriminator block, as described in the Linear 2FSK
Demodulator section and in Figure 22. The discriminator output
is filtered and averaged to remove the FSK frequency
modulation using a combined averaging filter and envelope
detector. In receive mode, the output of the envelope detector
provides an estimate of the average IF frequency.
The 3 dB bandwidth of the postdemodulation filter is set in the
same way as the 2FSK correlator/demodulator, which is set in
R4_DB[20:29] and is defined as
Two methods of AFC, external and internal, are supported on
the ADF7021.
11 ×π × FCUTOFF
External AFC
2
Post _ Demod _ BW _ Setting =
Here, the user reads back the frequency information through
the ADF7021 serial port and applies a frequency correction
value to the fractional-N synthesizer N divider.
DEMOD _CLK
where:
CUTOFF is the target 3 dB bandwidth in Hz of the
F
The frequency information is obtained by reading the 16-bit
signed AFC_readback, as described in the Readback Format
section, and by applying the following formula:
postdemodulator filter.
DEMOD_CLK is as defined in the Register 3—
Transmit/Receive Clock Register Comments section.
FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/218
Note that while the AFC_READBACK value is a signed
number, under normal operating conditions it is positive. In the
absence of frequency errors, the FREQ_RB value is equal to the
IF frequency of 100 kHz.
Rev. PrI | Page 21 of 44
ADF7021
Preliminary Technical Data
Internal AFC
AUTOMATIC SYNC WORD RECOGNITION
The ADF7021 supports a real-time, internal, automatic
frequency control loop. In this mode, an internal control loop
automatically monitors the frequency error and adjusts the
synthesizer-N divider using an internal PI control loop.
The ADF7021 also supports automatic detection of the sync or
ID fields. To activate this mode, the sync (or ID) word must be
preprogrammed into the ADF7021. In receive mode, this
preprogrammed word is compared to the received bit stream,
and when a valid match is identified, the external SWD pin is
asserted by the ADF7021 on the next Rx clock pulse.
The internal AFC control loop parameters are controlled in
Register 10. The internal AFC loop is activated by setting
R10_DB4 to 1. A scaling coefficient must also be entered, based
on the crystal frequency in use. This is set up in R10_DB[5:16]
and should be calculated using
This feature can be used to alert the microprocessor that a valid
channel has been detected. It relaxes the computational require-
ments of the microprocessor and reduces the overall power
consumption.
AFC_Scaling_Coefficient = (500 × 224)/XTAL
The SWD signal can also be used to frame a received packet
length by staying high for a preprogrammed number of bytes.
The data packet length can be set in Bits R12_DB[8:15].
Maximum AFC Range
The maximum AFC frequency range is 127.5 kHz. This is set
by Bits R10_DB[24:31]. The maximum AFC pull-in range
should be less than or equal to half the channel spacing to
prevent the AFC pulling in a signal in the adjacent channel. If
the maximum AFC pull-in range is larger than the IF filter
bandwidth, the attenuation of the IF filter must be considered.
The SWD pin status can be configured by setting Bits
R12_DB[6:7]. Bits R11_DB[4:5] are used to set the length of the
sync/ID word, which can be 12, 16, 20, or 24 bits long. The
transmitter must transmit the MSB of the sync byte first and the
LSB last to ensure proper alignment in the receiver sync-byte-
detection hardware.
When AFC errors have been removed using either the internal
or external AFC, further improvement in the receiver’s sensi-
tivity can be obtained by reducing the IF filter bandwidth using
Bits R4_DB[30:31].
For systems using FEC, an error tolerance parameter can also
be programmed that accepts a valid match when up to 3 bits of
the word are incorrect. The error tolerance value is assigned in
R11_DB[6:7].
Rev. PrI | Page 22 of 44
Preliminary Technical Data
ADF7021
APPLICATIONS
input reflection coefficient and the maximum differential signal
swing at the LNA input must be established. The use of appropriate
CAD software is strongly recommended for this optimization.
LNA/PA MATCHING
The ADF7021 exhibits optimum performance in terms of
sensitivity, transmit power, and current consumption, only if its
RF input and output ports are properly matched to the antenna
impedance. For cost-sensitive applications, the ADF7021 is
equipped with an internal Rx/Tx switch that facilitates the use
of a simple, combined passive PA/LNA matching network.
Alternatively, an external Rx/Tx switch such as the ADG919 can
be used, which yields a slightly improved receiver sensitivity
and lower transmitter power consumption.
Depending on the antenna configuration, the user might need a
harmonic filter at the PA output to satisfy the spurious emission
requirement of the applicable government regulations. The
harmonic filter can be implemented in various ways, such as a
discrete LC pi or T-stage filter. Dielectric low-pass filter
components, such as the LFL18924MTC1A052 (for operation
in the 915 MHz and 868 MHz band) by Murata Manufacturing
Co. Ltd., represent an attractive alternative to discrete designs.
The immunity of the ADF7021 to strong out-of-band
External Rx/Tx Switch
Figure 23 shows a configuration using an external Rx/Tx switch.
This configuration allows an independent optimization of the
matching and filter network in the transmit and receive path.
Therefore, it is more flexible and less difficult to design than the
configuration using the internal Rx/Tx switch. The PA is biased
through Inductor L1, while C1 blocks dc current. Both
elements, L1 and C1, also form the matching network that
transforms the source impedance into the optimum PA load
impedance, ZOPT_PA.
interference can be improved by adding a band-pass filter in the
Rx path. Apart from discrete designs, SAW or dielectric filter
components such as the SAFCH869MAM0T00B0S,
SAFCH915MAL0N00B0S, DCFB2869MLEJAA-TT1, or
DCFB3915MLDJAA-TT1, all by Murata Manufacturing Co.
Ltd., are well suited for this purpose. Alternatively, the
ADF7021 blocking performance can be improved by selecting
the high linearity mode, as described in Table 8.
Internal Rx/Tx Switch
V
BAT
Figure 24 shows the ADF7021 in a configuration where the
internal Rx/Tx switch is used with a combined LNA/PA
matching network. For most applications, the slight performance
degradation of 1 dB to 2 dB caused by the internal Rx/Tx switch
is acceptable, allowing the user to take advantage of the cost-
saving potential of this solution. The design of the combined
matching network must compensate for the reactance presented
by the networks in the Tx and the Rx paths, taking the state of
the Rx/Tx switch into consideration.
L1
C1
PA_OUT
OPTIONAL
LPF
PA
ANTENNA
Z
_PA
OPT
Z
_RFIN
IN
C
A
OPTIONAL
BPF
(SAW)
RFIN
L
LNA
A
RFINB
ADG919
Rx/Tx – SELECT
V
Z
_RFIN
BAT
IN
C
B
ADF7021
L1
C1
PA_OUT
PA
Figure 23. ADF7021 with External Rx/Tx Switch
ANTENNA
Z
_PA
ZOPT_PA depends on various factors, such as the required
OPTIONAL
BPF OR LPF
OPT
Z
_RFIN
IN
output power, the frequency range, the supply voltage range,
and the temperature range. Selecting an appropriate ZOPT_PA
helps to minimize the Tx current consumption in the
application. Application Note AN-764 contains a number of
C
A
RFIN
L
LNA
A
RFINB
Z
OPT_PA values for representative conditions. Under certain
conditions however, it is recommended to obtain a suitable
OPT_PA value by means of a load-pull measurement.
Z
_RFIN
IN
C
B
Z
ADF7021
Due to the differential LNA input, the LNA matching network
must be designed to provide both a single-ended to differential
conversion, and a complex conjugate impedance match. The
network with the lowest component count that can satisfy these
requirements is the configuration shown in Figure 23,
Figure 24. ADF7021 with Internal Rx/Tx Switch
The procedure typically requires several iterations until an
acceptable compromise has been reached. The successful
implementation of a combined LNA/PA matching network for
the ADF7021 is critically dependent upon the availability of an
accurate electrical model for the PC board. In this context, the
use of a suitable CAD package is strongly recommended. To
avoid this effort, the reference design provided for the ADF7021
RF module can be used. Gerber files are available on request.
consisting of two capacitors and one inductor. A first-order
implementation of the matching network can be obtained by
understanding the arrangement as two L-type matching
networks in a back-to-back configuration. Due to the asymmetry
of the network with respect to ground, a compromise between the
Rev. PrI | Page 23 of 44
ADF7021
Preliminary Technical Data
As with the external Rx/Tx switch, an additional LPF or BPF
could be required to suppress harmonics in the transmit
spectrum or to improve the resilience of the receiver against
out-of-band interferers.
If longer run-length coding must be supported, the ADF7021
has several other features that can be activated. These involve a
range of programmable options that allow the envelope detector
output to be frozen after preamble acquisition.
TRANSMIT PROTOCOL AND CODING
CONSIDERATIONS
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
Table 13 lists the minimum number of writes needed to set up
the ADF7021 in either Tx or Rx mode after CE is brought high.
Additional registers can also be written to tailor the part to a
particular application, such as setting up sync byte detection or
enabling AFC. When going from Tx to Rx or vice versa, the
user needs to write only to Register 1 to alter the LO by 100 kHz
and to toggle the Tx/Rx bit.
SYNC
ID
PREAMBLE
DATA FIELD
CRC
WORD
FIELD
Figure 25. Typical Format of a Transmit Protocol
A dc-free preamble pattern is recommended for FSK demodula-
tion. The recommended preamble pattern is a dc-free pattern
such as a 10101010 … pattern. Preamble patterns with longer
run-length constraints such as 11001100… can also be used.
However, this results in a longer synchronization time of the
received bit stream in the receiver.
Table 13. Minimum Register Writes Required for Tx/Rx Setup
Mode
Registers
Tx
Rx
Reg 0
Reg 0
Reg 1
Reg 1
Reg 2
Reg 3
Reg 3
Reg 4
Reg 5
Manchester coding can be used for the entire transmit protocol.
However, the remaining fields that follow the preamble header
do not have to use dc-free coding. For these fields, the ADF7021
can accommodate coding schemes with a run length of up to
6 bits without any performance degradation.
Tx <-> Rx
Reg 0
Figure 26 and Figure 27 show the recommended programming
sequence and associated timing for power-up from standby mode.
19mA TO
22mA
12mA
XTAL
t0
3.65mA
2.0mA
REG.
AFC
t13
AGC/
WR1
t3
VCO
t4
WR3 WR6 WR5
t5 t6 t7
WR0 WR4
t9 t10
CDR
t12
RxDATA
t14
RSSI
READY
t1
TIME
t2
t8
t11
tOFF
tON
Figure 26. Rx Programming Sequence and Timing Diagram
Rev. PrI | Page 24 of 44
Preliminary Technical Data
ADF7021
11mA TO
30mA
14mA
XTAL
t0
3.65mA
2.0mA
REG.
READY
WR1
VCO
WR3 WR0 WR4
TRANSMIT DATA
TIME
t1
t2
t3
t4
t5 t6 t7
t15
tOFF
tON
Figure 27. Tx Programming Sequence and Timing Diagram
Table 14. Power-Up Sequence Description
Parameter Value Description/Notes
Signal to Monitor
T0
2 ms typ
Crystal starts power-up after CE is brought high. This typically depends on the
specified crystal type and load capacitance.
CLKOUT
T1
T2
10 μs
1ms typ
Time for regulator to power up. The serial interface can be written to after this time. MUXOUT
Variable delay that depends on XTAL settling and VCO settling. Should be set
so that VCO and XTAL finish settling at the same time, thus minimizing current
consumption.
T3, T5,T6, T7,
T9, T10
32 ꢀ 1/SPI_CLK Time to write to a single register. Maximum SPI_CLK is 25 MHz.
T4
1 ms
The VCO can power up in parallel with the crystal. This depends on the CVCO
capacitance value used. A value of 22 nF is recommended as a trade-off
between phase noise performance and power-up time.
CVCO pin
T8
3.2 ms
IF filter coarse and fine calibration times. A coarse calibration typically takes
200 μs, while a fine calibration typically takes 3 ms (see the settings in the
Register 7—Readback Setup Register section).
T11
150 μs
This depends on the number of gain changes the AGC loop needs to cycle
through and AGC settings programmed. This is described in more detail in the
AGC Information and Timing section.
Analog RSSI on TEST_A
pin (available by writing
0x0B00 000F)
T12
T13
5 ꢀ Bit_Period
This is the time for the clock and data recovery circuit to settle. This typically
requires 5-bit transitions to acquire sync and is usually covered by the preamble.
20 ꢀ Bit_Period This is the time for the automatic frequency control circuit to settle. This
typically requires 16-bit transitions to acquire lock and is usually covered by an
appropriate length preamble.
T14, T15
Packet length
Number of bits in payload by the bit period.
Rev. PrI | Page 25 of 44
ADF7021
Preliminary Technical Data
ADuC84x
MISO
ADF7021
INTERFACING TO MICROCONTROLLER/DSP
TxRxDATA
Low level device drivers are available for interfacing to the
ADF7021, such as the ADuC84x microcontroller parts, or the
Blackfin® ADSP-BF53x DSPs. Use the hardware connections
shown in Figure 28 and Figure 29.
MOSI
SCLOCK
SS
RxCLK
P3.7
CE
P3.2/INT0
P2.4
INT/LOCK
SREAD
SLE
UART Mode
P2.5
GPIO
If a data synchronization clock is not required, the DATA_CLK|
TxDATA pin can be configured to input transmit data in
transmit mode. In receive mode, the receive data is available on
the DATA_I/O|RxDATA pin. This allows a UART to be easily
interfaced to the part, with dedicated pins for transmitted and
received data, as shown in Figure 30. To enable this UART
interface mode, set Bit R0_DB28 high.
P2.6
P2.7
SDATA
SCLK
Figure 28. ADuC84x to ADF7021 Connection Diagram
ADSP-BF533
ADF7021
SCLK
SCK
MOSI
MISO
PF5
SDATA
SREAD
SLE
RSCLK1
DT1PRI
DR1PRI
RFS1
PF6
RxCLK/DATA
TxRxDATA
RxCLK/DATA
CE
VCC
VCC
GND
GND
Figure 29. ADSP-BF533 to ADF7021 Connection Diagram
UART
ADF7021
TxDATA
DATA_CLK | TxDATA
RxDATA
DATA I/O | RxDATA
Figure 30. UART to ADF7021 Connection Diagram
Rev. PrI | Page 26 of 44
Preliminary Technical Data
ADF7021
SERIAL INTERFACE
The serial interface allows the user to program the 16, 32-bit
registers using a 3-wire interface (SCLK, SDATA, and SLE). It
consists of a level shifter, 32-bit shift register, and 16 latches.
Signals should be CMOS-compatible. The serial interface is
powered by the regulator, and, therefore, is inactive when CE is low.
RSSI Readback
The RSSI readback operation yields valid results in Rx mode
with ASK or FSK signals. The format of the readback word is
shown in Figure 31. It is comprised of the RSSI level informa-
tion (Bit RV1 to Bit RV7), the current filter gain (FG1, FG2),
and the current LNA gain (LG1, LG2) setting. The filter and
LNA gain are coded in accordance with the definitions in
Register 9. With the reception of ASK modulated signals,
averaging of the measured RSSI values improves accuracy. The
input power can be calculated from the RSSI readback value as
outlined in the RSSI/AGC.
Data is clocked into the register, MSB first, on the rising edge of
each clock (SCLK). Data is transferred to one of 16 latches on
the rising edge of SLE. The destination latch is determined by
the value of the four control bits (C4 to C1). These are the
bottom 4 LSBs, DB3 to DB0, as shown in Figure 2. Data can also
be read back on the SREAD pin.
Battery Voltage ADCIN/Temperature Sensor Readback
READBACK FORMAT
The battery voltage is measured at Pin VDD4. The readback
information is contained in Bit RV1 to Bit RV7. This also
applies for the readback of the voltage at the ADCIN pin and
the temperature sensor. From the readback information, the
battery or ADCIN voltage can be determined using
The readback operation is initiated by writing a valid control
word to the readback register and setting the readback-enable
bit (R7_DB8 = 1). The readback can begin after the control
word has been latched with the SLE signal. SLE must be kept
high while the data is being read out. Each active edge at the
SCLK pin clocks the readback word out successively at the
SREAD pin, as shown in Figure 31, starting with the MSB first.
The data appearing at the first clock cycle following the latch
operation must be ignored.
V
BATTERY = (Battery_Voltage_Readback)/21.1
ADCIN = (ADCIN_Voltage_Readback)/42.1
V
Silicon Revision Readback
The silicon revision readback word is valid without setting any
other registers, especially directly after power-up. The silicon
revision word is coded with four quartets in BCD format. The
product code (PC) is coded with three quartets extending from
Bit RV5 to Bit RV16. The revision code (RV) is coded with one
quartet extending from Bit RV1 to Bit RV4. The product code
for the ADF7021 should read back as PC = 0x210. The current
revision code should read as RC = 0x2.
AFC Readback
The AFC readback is valid only during the reception of FSK
signals with either the linear or correlator demodulator active.
The AFC readback value is formatted as a signed 16-bit integer
comprised of Bit RV1 to Bit RV16, and is scaled according to
the following formula:
FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/218
In the absence of frequency errors, the FREQ_RB value is equal
to the IF frequency of 100 kHz. Note that for the AFC readback
to yield a valid result, the down converted input signal must not
fall outside the bandwidth of the analog IF filter. At low-input
signal levels, the variation in the readback value can be
improved by averaging.
Filter Calibration Readback
The filter calibration readback word is contained in Bit RV1 to
Bit RV8, and is for diagnostic purposes only. Using the automatic
filter calibration function (accessible through Register 5 and
Register 6) is recommended. Before filter calibration is initiated,
decimal 32 should be read back.
READBACK MODE
READBACK VALUE
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7
RV8
FG1
DB6
RV7
RV7
DB5
RV6
RV6
DB4
RV5
RV5
DB3
RV4
RV4
DB2
RV3
RV3
DB1
RV2
RV2
DB0
RV1
RV1
AFC READBACK
RSSI READBACK
RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9
X
X
X
X
X
X
X
X
X
X
LG2
X
LG1
X
FG2
X
BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK
X
RV7
RV7
RV7
RV6
RV6
RV6
RV5
RV5
RV5
RV4
RV4
RV4
RV3
RV3
RV3
RV2
RV2
RV2
RV1
RV1
RV1
SILICON REVISION
RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9
RV8
RV8
FILTER CAL READBACK
0
0
0
0
0
0
0
0
Figure 31. Readback Value Table
Rev. PrI | Page 27 of 44
ADF7021
Preliminary Technical Data
REGISTER 0—N REGISTER
ADDRESS
MUXOUT
8-BIT INTEGER-N
15-BIT FRACTIONAL-N
BITS
TRANSMIT/
RECEIVE
FRACTIONAL
DIVIDE RATIO
TR1
M15 M14 M13 ...
M3
M2
M1
0
1
TRANSMIT
RECEIVE
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
0
0
0
.
.
.
1
1
1
1
...
...
...
...
...
...
...
...
...
...
0
0
0
.
.
.
1
1
1
1
0
0
1
.
.
.
0
0
1
1
0
1
0
.
.
.
0
1
0
1
0
1
2
.
.
.
U1
UART MODE
0
1
DISABLED
ENABLED
32764
32765
32766
32767
M3
M2
M1
MUXOUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
REGULATOR READY (DEFAULT)
END OF
CAL
DIGITAL LOCK DETECT
RSSI READY
Tx_Rx
LOGIC ZERO
THREE STATE
LOGIC ONE
N COUNTER
N8
N7
N6
N5
N4
N3
N2
N1
DIVIDE RATIO
0
0
.
0
0
.
0
1
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
31
32
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
0
1
253
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
254
255
Figure 32.
Register 0—N Register Comments
•
RF Output Frequency
Fractional _ N
⎛
⎝
⎞
⎟
⎠
Direct output: RFOUT = PFD× Integer _ N +
⎜
215
Fractional _ N
⎛
⎝
⎞
⎟
⎠
Divide-by-2 selected: RFOUT = PFD×0.5× Integer _ N +
⎜
215
•
•
In UART mode, the DATA CLK | TxDATA pin is used to input the Tx data. The Rx Data is available on the DATA I/O | RxDATA pin.
MUXOUT
END OF CAL (Active High): Indicates when a fine IF filter calibration has finished.
DIGITAL LOCK DETECT (Active High): Indicates when the PLL has locked.
RSSI READY (Active High): Indicates RSSI signal has settled and RSSI readback can be performed.
Tx_Rx: Gives the status of Bit DB27 in this register. Can be used to control an external Tx/Rx switch.
Rev. PrI | Page 28 of 44
Preliminary Technical Data
ADF7021
REGISTER 1—VCO/OSCILLATOR REGISTER
XTAL
BIAS
CLOCKOUT
DIVIDE
ADDRESS
BITS
R COUNTER
VCO BIAS
RF R COUNTER
DIVIDE RATIO
R3 R2 R1
VCO CENTER
FREQ ADJUST
VCO ÷2
VB1
0
0
.
0
1
.
1
0
.
1
2
.
VA2
VA1
0
1
÷2 OFF
÷2 ON
0
0
1
1
0
1
0
1
NOMINAL
VCO ADJUST UP 1
VCO ADJUST UP 2
VCO ADJUST UP 3
.
.
.
.
.
.
.
.
1
1
1
7
VCO BIAS
CURRENT
0.25mA
VB4
VB3 VB2 VB1
CLK
DIVIDE RATIO
OFF
OUT
0
0
.
0
0
.
0
1
.
1
0
.
CL4
CL3
CL2
CL1
0.5mA
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
2
4
.
1
1
1
1
4mA
LOOP
CONDITION
.
.
.
.
.
VE1
.
.
.
.
.
0
1
VCO OFF
VCO ON
30
VCO
INDUCTOR
1
1
1
1
VCL1
XTAL
DOUBLER
0
1
INTERNAL
EXTERNAL
D1
0
1
DISABLE
ENABLED
I
(mA)
CP
X1 XTAL OSC
CP1
CP2
3.6kΩ
0.3
0
1
OFF
ON
RSET
0
0
1
1
0
1
0
1
0.9
XTAL
1.5
XB2 XB1
BIAS
20µA
25µA
30µA
35µA
2.1
0
0
1
1
0
1
0
1
Figure 33.
Register 1—VCO/Oscillator Register N Comments
•
R_DIVIDE and XTAL DOUBLER
XTAL
If XTAL DOUBLER = 0, PFD =
R _ DIVIDE
XTAL × 2
R _ DIVIDE
If XTAL DOUBLER =1, PFD =
•
•
CLOCKOUT is a divided-down version of the XTAL and is available on Pin 36 (CLKOUT).
XOSC_ENABLE should be set high when using an external crystal. If using an external oscillator (such as TCXO, OCXO) with
CMOS-level outputs into Pin OSC2, the XOSC enable should be set low.
•
•
The VCO_ADJUST bits adjust the center of the VCO operating band. Each bit typically adjusts the VCO band up by 1% of the RF
operating frequency (0.5% if divide-by-2 is enabled).
Setting VCO_INDUCTOR to external allows the use of an external VCO tank inductor, which gives RF operating frequencies of
80 Hz to 650 MHz. If the internal inductor is being used for operation, this bit should be set low.
Rev. PrI | Page 29 of 44
ADF7021
Preliminary Technical Data
REGISTER 2—TRANSMIT MODULATION REGISTER
TxDATA
INVERT
MODULATION
SCHEME
ADDRESS
BITS
Tx FREQUENCY DEVIATION
POWER AMPLIFIER
PA BIAS
PA RAMP
PE1 POWER AMPLIFIER
PA2 PA1 PA BIAS
0
1
OFF
ON
0
0
1
1
0
1
0
1
5µA
7µA
9µA
11µA
DI2 DI1 TxDATA INVERT
S3
S2
S1
PA RAMP RATE
0
0
1
1
0
1
0
1
NORMAL
INVERT CLK
INVERT DATA
INV CLK AND DATA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
NO RAMP
256 CODES/BIT
128 CODES/BIT
64 CODES/BIT
32 CODES/BIT
16 CODES/BIT
8 CODES/BIT
4 CODES/BIT
FOR FSK MODE,
D9
...
D3
D2
D1
0
0
0
0
.
...
...
...
...
...
...
0
0
0
0
.
0
0
1
1
.
0
1
0
1
.
PLL MODE
1 × fSTEP
2 × fSTEP
3 × fSTEP
.
S3
S2
S1
MODULATION SCHEME
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2FSK
GAUSSIAN 2FSK
3FSK
4FSK
OVERSAMPLED 2FSK
RAISED CONSINE FILTER 2FSK
RAISED CONSINE FILTER 3FSK
RAISED CONSINE FILTER 4FSK
1
1
1
1
511 × fSTEP
NARROWBAND
RC
POWER AMPLIFIER OUTPUT HIGH LEVEL
NRC1
P6
.
.
P2
P1
0
1
DEFAULT
EXTRA FILTERING
0
0
0
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
X
0
0
1
.
X
0
1
0
.
PA OFF
–16.0dBm
–16 + 0.45dBm
–16 + 0.90dBm
.
.
.
.
1
.
1
1
1
13dBm
Figure 34.
Register 2—Transmit Modulation Register Comments
•
2FSK/3FSK/4FSK frequency deviation
Direct output:
TX_FREQUENCY_DEVIATION ×PFD
Frequency Deviation[Hz] =
216
Divide-by-2 enabled:
TX_FREQUENCY_DEVIATION ×PFD
Frequency Deviation[Hz] = 0.5×
216
where: TX_FREQUENCY_DEVIATION is set by R2_DB[19:27] and PFD is the PFD frequency.
•
•
•
•
In the case of 4FSK, there are tones at 3 times the frequency deviation and at 1 times the deviation.
Oversampled 2FSK is sampled at 32 times the programmed data rate.
The PA ramps at the programmed rate (R2_DB[8:10]) until it reaches its programmed level (R2_DB[13:18]).
If the PA is enabled/disabled by the PA_Enable Bit (R2_DB7), it ramps up and down. If it is enabled/disabled by the Tx_Rx bit
(R0_DB27), it ramps up and turns hard off.
Rev. PrI | Page 30 of 44
Preliminary Technical Data
ADF7021
REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER
DEMOD
ADDRESS
AGC CLOCK DIVIDE
SEQUENCER CLOCK DIVIDE
CDR CLOCK DIVIDE
CLOCK DIVIDE
BITS
SK8 SK7 ...
...
SK3 SK2 SK1 SEQ_CLK_DIVIDE
BK2 BK1 BBOS_CLK_DIVIDE
0
0
.
0
0
.
0
0
.
0
1
.
1
0
.
1
2
.
0
0
1
1
0
1
0
1
4
8
16
32
...
...
...
...
1
1
1
1
1
1
1
1
0
1
254
255
OK4 OK3 OK2 OK1 DEMOD_CLK_DIVIDE
GD6
GD5
GD4
GD3
GD2
GD1 AGC_CLK_DIVIDE
0
0
0
0
INVALID
0
...
1
0
...
1
0
...
1
1
...
1
1
...
15
0
0
...
1
0
0
...
1
0
0
...
1
0
0
...
1
0
0
...
1
0
1
...
1
INVALID
1
...
127
FS8
FS7
...
FS3
FS2
FS1 CDR_CLK_DIVIDE
0
0
.
1
1
0
0
.
1
1
...
...
...
...
...
0
0
.
1
1
0
1
.
1
1
1
0
.
0
1
1
2
.
254
255
Figure 35.
Register 3—Transmit/Receive Clock Register Comments
•
Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where:
XTAL
BBOS _ CLK _ DIVIDE
BBOS _ CLK =
•
Set the demodulator clock (DEMOD_CLK) such that 2 MHz ≤ DEMOD_CLK ≤ 15 MHz, where:
XTAL
DEMOD _ CLK =
DEMOD _ CLK _ DIVIDE
•
Data/clock recovery frequency (CDR _CLK) needs to be within 2% of (32 × data rate). The user should choose CDR_CLK frequency
to be as high as possible without breaking this 2% constraint or breaking the DEMOD_CLK condition. This 2% constraint can also
affect the choice of XTAL frequency, depending on the desired data rate.
DEMOD _ CLK
CDR _ CLK =
CDR _ CLOCK _ DIVIDE
The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be as close to 100 kHz as possible.
XTAL
SEQ _ CLK =
SEQUENCER _ CLOCK _ DIVIDE
•
The time allowed for each AGC step to settle is determined by the AGC update rate. It should be set close to 20 kHz.
SEQ _ CLK
AGC _ DIVIDE
AGCUpdate Rate[Hz] =
Rev. PrI | Page 31 of 44
ADF7021
Preliminary Technical Data
REGISTER 4—DEMODULATOR SETUP REGISTER
Rx
INVERT
DEMOD
SCHEME
ADDRESS
BITS
IF B/W
POST DEMODULATOR BW
DISCRIMINATOR BW
IF FILTER
B/W
DP1
PRODUCT
IFB2 IFB1
0
1
CROSS PRODUCT
DOT PRODUCT
0
0
1
1
0
1
0
1
12kHz
18kHz
25kHz
INVALID
RI2 RI1
INVERT
0
1
0
1
0
0
1
1
NORMAL
INVERT CLK
INVERT DATA
INVERT CLK/DATA
DEMODULATOR
DS3 DS2 DS1
SCHEME
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2FSK LINEAR DEMODULATOR
2FSK CORRELATOR/DEMODULATOR
3FSK DEMODULATOR
4FSK DEMODULATOR
RESERVED
RESERVED
RESERVED
RESERVED
Figure 36.
Register 4—Demodulator Setup Register Comments
DEMOD _ CLK ×K
•
Discriminator_BW =
400×103
where:
100×103
K =
Frequency Deviation[Hz]
Maximum value = 660.
•
RX_INVERT(R4_DB[8:9]) and DOT_PRODUCT (R4_DB7) need to be set as outlined below in order to optimize the correlator
demodulator. K is calculated using the previous formula and then rounded to the nearest integer.
K
K/2
Dot Product (R4_DB7)
Rx Invert (R4_DB[8:9])
Even
Even
Even
Odd
0
0
00
10
K
(K + 1)/2
Even
Odd
Dot Product (R4_DB7)
Rx Invert (R4_DB[8:9])
Odd
Odd
1
1
00
10
2
11 ×π×FCUTOFF
•
Post_Demod_BW =
DEMOD _ CLK
where the cutoff frequency (FCUTOFF) of the postdemodulator filter should typically be 0.75 times the data rate.
Rev. PrI | Page 32 of 44
Preliminary Technical Data
ADF7021
REGISTER 5—IF FILTER SETUP REGISTER
IR GAIN
ADJUST MAG
IR PHASE
ADJUST MAG
ADDRESS
BITS
IF FILTER ADJUST
IF FILTER DIVIDER
CC1 CAL
0
1
NO CAL
DO CAL
IR PHASE
ADJUST
PM3 PM2 PM1 PM1
FILTER CLOCK
IFD6 IFD5 IFD4 IFD3 IFD2 IFD1
DIVIDE RATIO
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
0
1
2
...
31
IFD9
.
0
0
.
.
.
.
.
.
.
.
.
.
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
1
0
.
1
2
.
1
1
1
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
.
.
.
.
.
.
.
PD1
IR PHASE ADJUST I/Q
1
1
1
1
1
1
511
0
1
ADJUST I CH
ADJUST Q CH
IR GAIN
ADJUST
GM5 GM4 GM3 GM2 GM1
IF FILTER
IFA2 IFA1 ADJUST
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
0
1
2
...
31
IFA6
...
0
0
0
.
...
...
...
...
...
0
0
1
.
0
1
0
.
0
× 300Hz
–1 × 300Hz
–2 × 300Hz
...
1
1
1
1
1
0
1
1
–31 × 300Hz
GQ1 IR GAIN ADJUST I/Q
0
1
ADJUST I CH
ADJUST Q CH
1
1
1
1
1
...
...
...
...
...
0
0
1
.
0
1
0
.
0
1
2
...
× 300Hz
× 300Hz
× 300Hz
GA1 IR GAIN ADJUST UP/DN
1
1
31 × 300Hz
0
1
GAIN
ATTENUATE
Figure 37.
Register 5—IF Filter Setup Register Comments
•
A coarse IF filter calibration is performed when the Coarse Cal Bit (R5_DB4) is set. If the Fine Cal Bit (R6_DB4) in is set, a fine IF
filter calibration is performed after the coarse calibration.
•
Set IF_Filter_DIVIDE such that
XTAL
IF _ FILTER _ DIVIDE
= 50 kHz
•
IF_FILTER_ADJUST allows the IF filter response to be manually adjusted in 300 Hz steps.
Rev. PrI | Page 33 of 44
ADF7021
Preliminary Technical Data
REGISTER 6—IF FINE CAL SETUP REGISTER
ADDRESS
IF CAL DWELL TIME
IF CAL UPPER TONE DIVIDER
IF CAL LOWER TONE DIVIDER
BITS
IF CAL UPPER
TONE DIVIDE
FC1 IF FINE CAL
UT3 UT2 UT1
UT8
...
0
1
DISABLED
ENABLED
0
0
0
.
0
1
1
.
1
0
1
.
0
0
0
.
...
...
...
...
...
1
2
3
.
.
.
.
.
.
1
1
1
1
...
255
IF CAL LOWER
TONE DIVIDE
LT3 LT2 LT1
LT8
...
0
0
0
.
0
1
1
.
1
0
1
.
0
0
0
.
...
...
...
...
...
1
2
3
.
IF CAL
DWELL TIME
CD3 CD2 CD1
CD7
...
0
0
0
.
0
1
1
.
1
0
1
.
0
0
0
.
...
...
...
...
...
1
2
3
.
.
.
.
.
.
1
1
1
1
...
255
.
.
.
.
.
1
1
1
1
...
127
Figure 38.
Register 6—IF Fine Cal Setup Register Comments
•
A fine IF filter calibration is set by enabling the IF_FINE_CAL Bit (DB4). A fine calibration is then carried out only when Register 5
is written to and Bit R5_DB4 is set.
•
The IF upper and lower tones used during fine filter calibration should be set as follows:
XTAL
=160 kHz
IF _ CAL _ LOWER _TONE _ DIVIDE
XTAL
= 220 kHz
IF _ CAL _UPPER _TONE _ DIVIDE
•
The IF tone calibration time is the amount of time that is spent at an IF calibration tone. It is dependent upon the sequencer clock. It
is recommended to have the IF_CAL_DWELL_TIME be at least 300 μs.
IF _ CAL _ DWELL
IF Tone Calibration Time =
SEQ _ CLK
The total time for a fine IF filter calibration is = IF Tone Calibration Time × 10.
Rev. PrI | Page 34 of 44
Preliminary Technical Data
ADF7021
REGISTER 7—READBACK SETUP REGISTER
READBACK
SELECT
ADC
MODE
CONTROL
BITS
DB1
DB0
DB7
RB2
DB8
RB3
DB6
RB1
DB5
AD2
DB4
AD1
DB3
DB2
C4 (0) C3 (1) C2 (1) C1 (1)
RB3 READBACK
AD2 AD1 ADC MODE
0
1
DISABLED
ENABLED
0
0
1
1
0
1
0
1
MEASURE RSSI
BATTERY VOLTAGE
TEMP SENSOR
TO EXTERNAL PIN
RB2 RB1 READBACK MODE
0
0
1
1
0
1
0
1
AFC WORD
ADC OUTPUT
FILTER CAL
SILICON REV
Figure 39.
Register 7—Readback Setup Register Comments
•
Readback of the measured RSSI value is valid only in Rx mode. To enable readback of the battery voltage, the temperature sensor, or
the voltage at the external pin in Rx mode, users need to disable AGC function in Register 9. To read back these parameters in Tx
mode, first power up the ADC using Register 8, as this is off by default in Tx mode to save power. This is the recommended method
of using the battery readback function, as most configurations typically require AGC.
•
AFC readback:
FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/218
•
•
•
VBATTERY = Battery_Voltage_Readback/21.1
VADCIN = ADCIN_Voltage_Readback/42.1
See the Readback Format section for more information.
Rev. PrI | Page 35 of 44
ADF7021
Preliminary Technical Data
REGISTER 8—POWER DOWN TEST REGISTER
CONTROL
BITS
Rx RESET
DB10 DB9
LE1 PD6
DB1
DB0
DB7
PD4
DB15 DB14 DB13 DB12 DB11
DB8
PD5
DB6
PD3
DB5
DB4
PD1
DB3
DB2
PD7
SW1
C4 (1) C3 (0) C2 (0) C1 (0)
CR1
PD1 SYNTH STATUS
CR1 COUNTER RESET
0
1
SYNTH OFF
SYNTH ON
0
1
NORMAL
RESET
CDR
RESET
DEMOD
RESET
PD3 LNA/MIXER ENABLE
PD7 PA (Rx MODE)
0
1
LNA/MIXER OFF
LNA/MIXER ON
0
1
PA OFF
PA ON
PD4 FILTER ENABLE
SW1 Tx/Rx SWITCH
0
1
FILTER OFF
FILTER ON
0
1
DEFAULT (ON)
OFF
PD5 ADC ENABLE
LE1 LOG AMP ENABLE
0
1
ADC OFF
ADC ON
0
1
LOG AMP OFF
LOG AMP ON
PD6 DEMOD ENABLE
0
1
DEMOD OFF
DEMOD ON
Figure 40.
Register 8—Power Down Test Register Comments
•
•
It is not necessary to write to this register under normal operating conditions.
For a combined LNA/PA matching network, Bit R8_DB11 should always be set to 0, which enables the internal Tx_Rx switch. This is
the power-up default condition.
Rev. PrI | Page 36 of 44
Preliminary Technical Data
ADF7021
REGISTER 9—AGC REGISTER
FILTER
GAIN
LNA
GAIN
AGC
MODE
ADDRESS
BITS
AGC HIGH THRESHOLD
AGC LOW THRESHOLD
ML1 MIXER LINEARITY
AGC LOW
THRESHOLD
AGC MODE
GL7 GL6 GL5 GL4 GL3 GL2 GL1
0
1
DEFAULT
HIGH
0
1
2
3
AUTO AGC
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
0
0
0
1
.
0
1
1
0
.
1
0
1
0
.
1
2
3
4
.
.
MANUAL AGC
FREEZE AGC
RESERVED
LI2 LI1 LNA BIAS
0
0
800µA (DEFAULT)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
61
62
63
LG1 LNA MODE
0
1
DEFAULT
REDUCED GAIN
AGC HIGH
GH7 GH6 GH5 GH4 GH3 GH2 GH1
THRESHOLD
FI1 FILTER CURRENT
0
0
0
0
.
.
.
1
1
1
0
0
0
0
.
.
.
0
0
0
0
0
0
0
.
.
.
0
0
1
0
0
0
0
.
.
.
1
1
0
0
0
0
1
.
.
.
1
1
0
0
1
1
0
.
.
.
1
1
0
1
0
1
0
.
.
.
0
1
0
1
2
3
4
.
.
.
78
79
80
0
1
LOW
HIGH
FG2 FG1 FILTER GAIN
0
0
1
1
0
1
0
1
8
24
72
INVALID
LG2 LG1 LNA GAIN
0
0
1
1
0
1
0
1
3
10
30
INVALID
Figure 41.
Register 9—AGC Register Comments
•
•
•
Default AGC_LOW_THRESHOLD = 30, default AGC_HIGH_THRESHOLD = 70. See the RSSI/AGC section for details.
AGC high and low settings must be more than 30 apart to ensure correct operation.
LNA gain of 30 is available only if LNA mode, R9_DB25, is set to zero.
Rev. PrI | Page 37 of 44
ADF7021
Preliminary Technical Data
REGISTER 10—AFC REGISTER
ADDRESS
MAX AFC RANGE
KP
KI
AFC SCALING FACTOR
BITS
AE1 AFC ENABLE
KP3 KP2 KP1 KP
KI4 KI3 KI2 KI1 KI
0
0
.
0
0
.
0
0
.
0
0
.
0
1
.
2^0
2^1
...
0
0
.
0
1
.
2^0
2^1
...
0
1
OFF
AFC ON
1
1
1
1
1
2^7
1
1
2^15
MAX AFC
MA3 MA2 MA1
RANGE
AFC SCALING
FACTOR
...
MA8
...
M3
M2
M1
M12
0
0
0
0
.
.
.
1
1
1
...
...
...
...
...
...
...
...
...
...
0
0
0
1
.
.
.
1
1
1
0
1
1
0
.
.
.
0
1
1
1
0
1
0
.
.
.
1
0
1
1
2
3
4
.
.
.
253
254
255
0
0
0
0
.
.
.
1
1
1
...
...
...
...
...
...
...
...
...
...
0
0
0
1
.
.
.
1
1
1
0
1
1
0
.
.
.
0
1
1
1
0
1
0
.
.
.
1
0
1
1
2
3
4
.
.
.
4093
4094
4095
Figure 42.
Register 10—AFC Register Comments
•
AFC scaling factor:
24
⎛
⎞
2
×500
⎜
⎜
⎟
⎟
AFC _ SCALING _ FACTOR = ROUND
XTAL
⎝
⎠
•
•
The recommended settings for KI and KP are given below. Note that these settings affect the AFC settling time and AFC accuracy.
KI > 6 and KP < 7
Maximum AFC pull-in range:
AFC Pull −in Range = MAX _ AFC _ RANGE×500 Hz
•
Signals that are within the AFC pull-in range but outside the IF filter bandwidth are attenuated by the IF filter. As a result, the signals
may be below the sensitivity point of the receiver, and therefore, not detectable by the AFC. In this case, it is best to scan bandwidths
that are equal to the IF filter bandwidth.
Rev. PrI | Page 38 of 44
Preliminary Technical Data
ADF7021
REGISTER 11—SYNC WORD DETECT REGISTER
CONTROL
SYNC BYTE SEQUENCE
BITS
SYNC BYTE
PL2 PL1 LENGTH
0
0
1
1
0
1
0
1
12 BITS
16 BITS
20 BITS
24 BITS
MATCHING
MT2 MT1 TOLERANCE
0
0
1
1
0
1
0
1
ACCEPT 0 ERRORS
ACCEPT 1 ERROR
ACCEPT 2 ERRORS
ACCEPT 3 ERRORS
Figure 43.
Rev. PrI | Page 39 of 44
ADF7021
Preliminary Technical Data
REGISTER 12—SWD/THRESHOLD SETUP REGISTER
CONTROL
BITS
DATA PACKET LENGTH
DATA PACKET LENGTH
0
1
...
INVALID
1 BYTE
...
255 255 BYTES
INTUPT/LOCK PIN MODE
0
1
2
INTUPT PIN LOW
INTUPT PIN HIGHAFTER NEXT SYNCWORD
INTUPT PIN HIGHAFTER NEXT SYNCWORD
FOR DATA_PACKET_LENGTH NUMBER OF BYTES
INTUPT PIN HIGH
3
LOCK THRESHOLD MODE
0
1
2
THRESHOLD FREE RUNNING
LOCK THRESHOLD AFTER NEXT SYNCWORD
LOCK THRESHOLD AFTER NEXT SYNCWORD
FOR DATA_PACKET_LENGTH NUMBER OF BYTES
LOCK THRESHOLD
3
Figure 44.
Register 12—SWD/Threshold Setup Register Notes
•
Lock threshold locks the threshold of the envelope detector. This has the effect of locking the slicer in linear demod and also locking
the AFC and AGC loops.
Rev. PrI | Page 40 of 44
Preliminary Technical Data
ADF7021
REGISTER 13—3FSK DEMOD REGISTER
3FSK PREAMBLE
TIME VALIDATE
3FSK/4FSK
SLICER THRESHOLD
CONTROL
BITS
3FSK CDR THRESHOLD
Figure 45.
REGISTER 14—TEST-DAC REGISTER
ADDRESS
BITS
TEST DAC GAIN
TEST DAC OFFSET
ED LEAK FACTOR
LEAKAGE =
ED PEAK RESPONSE
TEST DAC GAIN
0
1
2
3
FULL RESPONSE TO PEAK
0.5 RESPONSE TO PEAK
0.25 RESPONSE TO PEAK
0.125 RESPONSE TO PEAK
0
1
...
15
NO GAIN
× 2^1
...
0
1
2
3
4
5
6
7
2^–8
2^–9
2^–10
2^–11
2^–12
2^–13
2^–14
2^–15
× 2^15
PULSE EXTENSION
0
1
2
3
NO PULSE EXTENSION
EXTENDED BY 1
EXTENDED BY 2
EXTENDED BY 3
Figure 46.
Register 14—Test-DAC Register Comments
•
The demod tuning parameters PULSE_EXTENSION, ED_LEAK_FACTOR, and ED_PEAK_RESPONSE can only be enabled by
setting Bits R15_DB[4:7] to 0x9.
Rev. PrI | Page 41 of 44
ADF7021
Preliminary Technical Data
REGISTER 15—TEST MODE REGISTER
ANALOG TEST
MODES
PLL TEST
MODES
PFD/CP TEST
MODES
Σ-Δ TEST
MODES
Tx TEST
MODES
Rx TEST
MODES
ADDRESS
BITS
CLK MUX
CAL OVERRIDE
0
1
2
3
AUTO CAL
OVERRIDE GAIN
OVERRIDE BW
PFD/CP TEST MODES
0
1
2
3
4
5
6
7
DEFAULT, NO BLEED
(+VE) CONSTANT BLEED
(–VE) CONSTANT BLEED
(–VE) PULSED BLEED
(–VE) PULSE BLD, DELAY UP?
CP PUMP UP
OVERRIDE BW AND GAIN
REG1 PD
0
1
NORMAL
PWR DWN
CP TRI-STATE
CP PUMP DN
FORCE LD HIGH
Σ-Δ TEST MODES
0
1
NORMAL
FORCE
0
1
2
3
4
5
6
7
DEFAULT, 3RD ORDER SD, NO DITHER
1ST ORDER SD
2ND ORDER SD
DITHER TO FIRST STAGE
DITHER TO SECOND STAGE
DITHER TO THIRD STAGE
DITHER × 8
ANALOG TEST MODES
0
1
2
3
4
5
6
7
8
9
BAND GAP VOLTGE
40µA CURRENT FROM REG4
FILTER I CHANNEL: STAGE 1
FILTER I CHANNEL: STAGE 2
FILTER I CHANNEL: STAGE 1
FILTER Q CHANNEL: STAGE 1
FILTER Q CHANNEL: STAGE 2
FILTER Q CHANNEL: STAGE 1
ADC REFERENCE VOLTAGE
BIAS CURRENT FROM RSSI 5µA
DITHER × 32
Tx TEST MODES
0
1
2
3
4
5
6
NORMAL OPERATION
Tx CARRIER ONLY
Tx +VE TONE ONLY
Tx –VE TONE ONLY
Tx "1010" PATTERN
Tx PN9 DATA, AT PROGRAMMED RATE
Tx SYNC BYTE REPEATEDLY
10 FILTER COARSE CAL OSCILLATOR O/P
11 ANALOG RSSI I CHANNEL
12 OSET LOOP +VE FBACK V (I CH)
13 SUMMED O/P OF RSSI RECTIFIER+
14 SUMMED O/P OF RSSI RECTIFIER–
15 BIAS CURRENT FROM BB FILTER
Rx TEST MODES
NORMAL
SCLK, SDATA -> I, Q
REVERSE I, Q
DDT SLICER ON RxDATA
T/4 SLICER ON RxDATA
3FSK SLICER ON RxDATA
I, Q TO Rx CLK, RxDATA
SDATA TO CDR
0
1
2
3
4
5
6
7
8
9
PLL TEST MODES
0
1
2
3
4
5
6
7
8
9
NORMAL OPERATION
R DIV
N DIV
RCNTR/2 ON MUXOUT
NCNTR/2 ON MUXOUT
ACNTR TO MUXOUT
PFD PUMP UP TO MUXOUT
PFD PUMP DN TO MUXOUT
SDATA TO MUXOUT (OR SREAD?)
ADDITIONAL FILTERING ON I, Q
ENABLE REG 14 DEMOD PARAMETERS
10 POWER DOWN DDT AND ED IN T/4 MODE
11 ENVELOPE DETECTOR WATCHDOG DISABLED
12 3FSK PREMABLE DETECT ON RxDATA
13 PROHIBIT CALACTIVE
14 FORCE CALACTIVE
15 ENABLE DEMOD DURING CAL
ANALOG LOCK DETECT ON MUXOUT
10 END OF COARSE CAL ON MUXOUT
11 END OF FINE CAL ON MUXOUT
FORCE NEW PRESCALER CONFIG.
FOR ALL N
13 TEST MUX SELECTS DATA
12
14 LOCK DETECT PRECISION
15 NEG PD POLARITY-*NOT SUPPORTED*
CLK MUXES
0
1
2
3
4
5
6
7
NORMAL, NO OUTPUT
DEMOD_CLK
CDR_CLK
SEQ_CLK
BB_OFFSET CLK
SIGMA_DELTA CLK
ADC_CLK
Tx/Rx CLK
Figure 47.
Rev. PrI | Page 42 of 44
Preliminary Technical Data
ADF7021
Using the Test DAC on the ADF7021 to Implement
Analog FM DEMOD and Measuring SNR
While the correlators and filters are clocked by DEMOD_CLK,
CDR_CLK clocks the test DAC. Note that although the test
DAC functions in regular user mode, the best performance is
achieved when the CDR_CLK is increased up to or above the
frequency of DEMOD_CLK. The CDR block does not function
when this condition exists.
The test DAC allows the output of the postdemodulator filter
for both the linear and correlator/demodulators (Figure 21 and
Figure 22) to be viewed externally. It takes the 16-bit filter
output and converts it to a high frequency, single-bit output
using a second-order error feedback Σ-Δ converter. The output
can be viewed on the XCLKOUT pin. This signal, when IF filtered
appropriately, can then be used to
Programming Register 14 enables the test DAC. Both the linear and
correlator/demodulator outputs can be multiplexed into the DAC.
Register 14 allows a fixed offset term to be removed from the
signal (to remove the IF component in the ddt case). It also has
a signal gain term to allow the usage of the maximum dynamic
range of the DAC.
•
Monitor the signals at the FSK postdemodulator filter
output. This allows the demodulator output SNR to be
measured. Eye diagrams can also be constructed of the
received bit stream to measure the received signal quality.
•
Provide analog FM demodulation.
Rev. PrI | Page 43 of 44
ADF7021
Preliminary Technical Data
OUTLINE DIMENSIONS
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
PAD
(BOTTOM VIEW)
4.25
4.10 SQ
3.95
TOP
VIEW
6.75
BSC SQ
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 48. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 × 7 mm Body, Very Thin Quad
(CP-48-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADF7021BCPZ1
−40°C to +85°C
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Control Mother Board
Evaluation Platform
860 MHz to 870 MHz Daughter Board
431 MHz to 470 MHz Daughter Board
CP-48-3
EVAL-ADF70XXMB
EVAL-ADF70XXMB2
EVAL-ADF7021DB2
EVAL-ADF7021DB3
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR05876-0-9/06(PrI)
Rev. PrI | Page 44 of 44
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