AD9629BCPZ-80_技术文档

12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,

1.8 V Analog-to-Digital Converter

AD9629

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

GND

SDIO SCLK CSB

DRVDD

1.8 V analog supply operation

1.8 V to 3.3 V output supply

SNR

RBIAS

VCM

SPI

71.3 dBFS at 9.7 MHz input

OR

PROGRAMMING DATA

69.0 dBFS at 200 MHz input

SFDR

95 dBc at 9.7 MHz input

83 dBc at 200 MHz input

Low power

D11 (MSB)

VIN+

VIN–

ADC

CORE

D0 (LSB)

DCO

VREF

SENSE

45 mW at 20 MSPS

85 mW at 80 MSPS

AD9629

REF

SELECT

Differential input with 700 MHz bandwidth

On-chip voltage reference and sample-and-hold circuit

2 V p-p differential analog input

DNL = 0.16 LSB

MODE

DIVIDE BY

1, 2, 4

CONTROLS

CLK+ CLK–

PDWN DFS MODE

Serial port control options

Figure 1.

Offset binary, gray code, or twos complement data format

Integer 1, 2, or 4 input clock divider

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock out with programmable clock and data alignment

PRODUCT HIGHLIGHTS

1. The AD9629 operates from a single 1.8 V analog power

supply and features a separate digital output driver supply

to accommodate 1.8 V to 3.3 V logic families.

2. The patented sample-and-hold circuit maintains excellent

performance for input frequencies up to 200 MHz and is

designed for low cost, low power, and ease of use.

3. A standard serial port interface (SPI) supports various

product features and functions, such as data output format-

ting, internal clock divider, power-down, DCO and data

output (D11 to D0) timing and offset adjustments, and

voltage reference modes.

4. The AD9629 is packaged in a 32-lead RoHS compliant LFCSP

that is pin compatible with the AD9609 10-bit ADC and

the AD9649 14-bit ADC, enabling a simple migration path

between 10-bit and 14-bit converters sampling from 20 MSPS

to 80 MSPS.

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA

Smart antenna systems

Battery-powered instruments

Hand held scope meters

Portable medical imaging

Ultrasound

Radar/LIDAR

PET/SPECT imaging

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9629

TABLE OF CONTENTS

Features .............................................................................................. 1

Voltage Reference ....................................................................... 19

Clock Input Considerations...................................................... 20

Power Dissipation and Standby Mode .................................... 21

Digital Outputs ........................................................................... 22

Timing ......................................................................................... 22

Built-In Self-Test (BIST) and Output Test .................................. 23

Built-In Self-Test (BIST)............................................................ 23

Output Test Modes..................................................................... 23

Serial Port Interface (SPI).............................................................. 24

Configuration Using the SPI..................................................... 24

Hardware Interface..................................................................... 25

Configuration Without the SPI ................................................ 25

SPI Accessible Features.............................................................. 25

Memory Map .................................................................................. 26

Reading the Memory Map Register Table............................... 26

Open Locations .......................................................................... 26

Default Values............................................................................. 26

Memory Map Register Table..................................................... 27

Memory Map Register Descriptions........................................ 29

Applications Information.............................................................. 30

Design Guidelines ...................................................................... 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 7

Timing Specifications .................................................................. 8

Absolute Maximum Ratings............................................................ 9

Thermal Characteristics .............................................................. 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 11

AD9629-80 .................................................................................. 11

AD9629-65 .................................................................................. 13

AD9629-40 .................................................................................. 14

AD9629-20 .................................................................................. 15

Equivalent Circuits......................................................................... 16

Theory of Operation ...................................................................... 17

Analog Input Considerations.................................................... 17

REVISION HISTORY

10/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD9629

GENERAL DESCRIPTION

deterministic and pseudorandom patterns, along with custom

user-defined test patterns entered via the serial port interface (SPI).

The AD9629 is a monolithic, single channel 1.8 V supply, 12-bit,

20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital conver-

ter (ADC). It features a high performance sample-and-hold

circuit and on-chip voltage reference.

A differential clock input with optional 1, 2, or 4 divide ratios

controls all internal conversion cycles.

The product uses multistage differential pipeline architecture

with output error correction logic to provide 12-bit accuracy at

80 MSPS data rates and to guarantee no missing codes over the

full operating temperature range.

The digital output data is presented in offset binary, gray code,

or twos complement format. A data output clock (DCO) is

provided to ensure proper latch timing with receiving logic. Both

1.8 V and 3.3 V CMOS levels are supported.

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

The AD9629 is available in a 32-lead RoHS compliant LFCSP

and is specified over the industrial temperature range (−40°C

to +85°C).

Rev. 0 | Page 3 of 32

AD9629

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

Table 1.

AD9629-20/AD9629-40

Temp Min Typ Max

AD9629-65

AD9629-80

Parameter

Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION

Full

12

Bits

ACCURACY

No Missing Codes

Offset Error

Full

25°C

Full

25°C

Guaranteed

−0.40 +0.05

−1.5

+0.50

−0.40 +0.05 +0.50 −0.40 +0.05 +0.50 % FSR

−1.5 −1.5 % FSR

0.30 LSB

Gain Error¹

Differential Nonlinearity (DNL)²

0.25

0.30

0.11

2

0.11

0.1ꢀ

LSB

0.35 LSB

LSB

Integral Nonlinearity (INL)²

0.40

0.13

2

0.1ꢀ

2

TEMPERATURE DRIFT

Offset Error

Full

ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode)

Load Regulation Error at 1.0 mA

INPUT-REFERRED NOISE

VREF = 1.0 V

Full

0.984 0.99ꢀ

2

1.008

0.984 0.99ꢀ 1.008 0.984 0.99ꢀ 1.008

V

mV

2

25°C

0.25

LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V

Input Capacitance³

Input Common-Mode Voltage

Input Common-Mode Range

REFERENCE INPUT RESISTANCE

POWER SUPPLIES

Supply Voltage

AVDD

DRVDD

Full

2

ꢀ

0.9

2

ꢀ

0.9

2

ꢀ

0.9

V p-p

pF

V

0.5

1.3

0.5

1.3

0.5

1.3

V

7.5

1.8

7.5

1.8

kΩ

Full

1.7

1.8

1.9

3.ꢀ

1.7

1.9

3.ꢀ

1.7

1.9

3.ꢀ

V

Supply Current

IAVDD²

Full

24.9/31.1 2ꢀ.7/33.2

1.5/2.5

2.7/4.7

41.2

4.2

7.5

4ꢀ.0

4ꢀ.8

5.0

9.0

50.0

mA

IDRVDD²(1.8 V)

IDRVDD²(3.3 V)

POWER CONSUMPTION

DC Input

Sine Wave Input²(DRVDD = 1.8 V)

Sine Wave Input²(DRVDD = 3.3 V)

Standby Power⁴

Full

45.0/5ꢀ.7

47.5/ꢀ0.5 50.7/ꢀ5.0

53.7/71.7

34

0.5

75

85.2

93

114

34

mW

81.7

98.9

34

8ꢀ.0

100

Power-Down Power

0.5

¹Measured with 1.0 V external reference.

²Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.

³Input capacitance refers to the effective capacitance between one differential input pin and AGND.

⁴Standby power is measured with a dc input and the clock active.

Rev. 0 | Page 4 of 32

AD9629

AC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

Table 2.

AD9629-20/AD9629-40

AD9629-65

AD9629-80

Parameter¹

Temp Min

Typ

Max

Min Typ Max Min Typ

Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

f_IN= 9.7 MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

25°C

71.4

71.2

71.3

71.2

71.3

71.2

dBFS

70.5/70.7

70.ꢀ

70.5

f_IN= 70 MHz

70.5/71.0

71.0

ꢀ9.0

70.9

ꢀ9.0

70.3

70.2

f_IN= 200 MHz

SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)

f_IN= 9.7 MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

71.4

71.2

71.3

71.2

71.1

dBFS

70.5/70.ꢀ

f_IN= 70 MHz

70.4/70.9

ꢀ8

70.9

ꢀ8

70.8

ꢀ8

f_IN= 200 MHz

25°C

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 9.7 MHz

f_IN= 30.5 MHz

f_IN= 70 MHz

f_IN= 200 MHz

25°C

11.4/11.ꢀ

11.4/11.5

11.0

11.ꢀ

11.5

11.0

11.5

11.0

Bits

WORST SECOND OR THIRD HARMONIC

f_IN= 9.7 MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

−97

−95

−97

−95

−94

dBc

−83

f_IN= 70 MHz

−9ꢀ/−94

−83

−95

−83

−95

−83

−81

f_IN= 200 MHz

25°C

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_IN= 9.7 MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

97

9ꢀ/95

97

95

93

dBc

83

f_IN= 70 MHz

9ꢀ/94

83

95

83

95

83

81

f_IN= 200 MHz

25°C

WORST OTHER (HARMONIC OR SPUR)

f_IN= 9.7 MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

−100

dBc

−92/−91

−93

f_IN= 70 MHz

−97/−100

−92

−100

−92

−100

−92

−89

f_IN= 200 MHz

25°C

TWO-TONE SFDR

f_IN= 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS)

ANALOG INPUT BANDWIDTH

25°C

90

dBc

700

MHz

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

Rev. 0 | Page 5 of 32

AD9629

DIGITAL SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

Table 3.

AD9629-20/AD9629-40/AD9629-65/AD9629-80

Parameter

Temp

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

Internal Common-Mode Bias

Differential Input Voltage

Input Voltage Range

High Level Input Current

Low Level Input Current

Input Resistance

CMOS/LVDS/LVPECL

0.9

Full

V

0.2

GND − 0.3

−10

8

3.ꢀ

AVDD + 0.2

+10

12

V p-p

V

μA

kΩ

pF

10

4

Input Capacitance

LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN)¹

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.2

0

−50

−10

DRVDD + 0.3

0.8

−75

+10

V

μA

kΩ

pF

30

2

Input Capacitance

LOGIC INPUTS (CSB)²

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.2

0

−10

40

DRVDD + 0.3

0.8

+10

135

V

μA

kΩ

pF

2ꢀ

2

Input Capacitance

DIGITAL OUTPUTS

DRVDD = 3.3 V

High Level Output Voltage, I_OH= 50 μA

High Level Output Voltage, I_OH= 0.5 mA

Low Level Output Voltage, I_OL= 1.ꢀ mA

Low Level Output Voltage, I_OL= 50 μA

DRVDD = 1.8 V

Full

3.29

3.25

V

0.2

0.05

High Level Output Voltage, I_OH= 50 μA

High Level Output Voltage, I_OH= 0.5 mA

Low Level Output Voltage, I_OL= 1.ꢀ mA

Low Level Output Voltage, I_OL= 50 μA

Full

1.79

1.75

V

0.2

0.05

¹Internal 30 kΩ pull-down.

²Internal 30 kΩ pull-up.

Rev. 0 | Page ꢀ of 32

AD9629

SWITCHING SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

Table 4.

AD9629-20/AD9629-40

AD9629-65

AD9629-80

Max Min Typ Max Unit

Parameter

Temp Min

Typ

Max

Min

Typ

CLOCK INPUT PARAMETERS

Input Clock Rate¹

Conversion Rate²

CLK Period, Divide-by-1 Mode (t_CLK

CLK Pulse Width High (t_CH)

Aperture Delay (t_A)

Aperture Uncertainty (Jitter, t_J)

DATA OUTPUT PARAMETERS

Data Propagation Delay (t_PD)

Full

80/1ꢀ0

20/40

2ꢀ0

ꢀ5

320

80

MHz

MSPS

ns

3

12.5

50/25

)

15.38

25.0/12.5

1.0

0.1

7.ꢀ9

1.0

0.1

ꢀ.25

1.0

0.1

Full

ps rms

Full

3

0.1

8

350

ꢀ00/400

2

3

ns

Cycles

μs

DCO Propagation Delay (t_DCO

)

DCO to Data Skew (t_SKEW

)

0.1

8

350

300

2

0.1

8

350

2ꢀ0

2

Pipeline Delay (Latency)

Wake-Up Time³

Standby

ns

OUT-OF-RANGE RECOVERY TIME

Cycles

¹Input clock rate is the clock rate before the internal CLK divider.

²Conversion rate is the clock rate after the CLK divider.

³Wake-up time is dependent on the value of the decoupling capacitors.

N – 1

N + 4

t_A

N + 5

N

N + 3

VIN

N + 1

N + 2

t_CH

t_CLK

CLK+

CLK–

t_DCO

DCO

t_SKEW

N – 8

DATA

N – 7

N – 6

N – 5

N – 4

t_PD

Figure 2. CMOS Output Data Timing

Rev. 0 | Page 7 of 32

AD9629

TIMING SPECIFICATIONS

Table 5.

Parameter

Conditions

Min

Typ

Max

Unit

SPI TIMING REQUIREMENTS

t_DS

t_DH

t_CLK

t_S

t_H

t_HIGH

t_LOW

t_{EN_SDIO}

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

SCLK pulse width high

SCLK pulse width low

Time required for the SDIO pin to switch from an input to an

output relative to the SCLK falling edge

2

40

2

10

ns

t_{DIS_SDIO}

Time required for the SDIO pin to switch from an output to an

input relative to the SCLK rising edge

10

ns

Rev. 0 | Page 8 of 32

AD9629

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

Table 6.

Parameter

Rating

The exposed paddle is the only ground connection for the chip.

The exposed paddle must be soldered to the AGND plane of the

user’s circuit board. Soldering the exposed paddle to the user’s

board also increases the reliability of the solder joints and

maximizes the thermal capability of the package.

AVDD to AGND

DRVDD to AGND

VIN+, VIN− to AGND

CLK+, CLK− to AGND

VREF to AGND

SENSE to AGND

VCM to AGND

RBIAS to AGND

CSB to AGND

SCLK/DFS to AGND

SDIO/PDWN to AGND

MODE/OR to AGND

D0 through D11 to AGND

DCO to AGND

Operating Temperature Range (Ambient)

Maximum Junction Temperature Under Bias

Storage Temperature Range (Ambient)

−0.3 V to +2.0 V

−0.3 V to +3.9 V

−0.3 V to AVDD + 0.2 V

−0.3 V to DRVDD + 0.3 V

−40°C to +85°C

Table 7. Thermal Resistance

Airflow

Package Velocity

1, 2

1, 3

1, 4

1, 2

Type

(m/sec)

θ_JA

θ_JC

θ_JB

20.7

Ψ_JT

0.3

0.5

0.8

Unit

°C/W

32-Lead

LFCSP

5 mm ×

5 mm

0

1.0

2.5

37.1

32.4

29.1

3.1

¹Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.

²Per JEDEC JESD51-2 (still air) or JEDEC JESD51-ꢀ (moving air).

³Per MIL-Std 883, Method 1012.1.

⁴Per JEDEC JESD51-8 (still air).

150°C

−ꢀ5°C to +150°C

Typical θ_JAis specified for a 4-layer PCB with a solid ground

plane. As shown in Table 7, airflow improves heat dissipation,

which reduces θ_JA. In addition, metal in direct contact with the

package leads from metal traces, through holes, ground, and

power planes, reduces the θ_JA.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Rev. 0 | Page 9 of 32

AD9629

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK+

CLK–

AVDD

1

2

3

4

5

6

7

8

24 AVDD

23 MODE/OR

22 DCO

21 D11 (MSB)

20 D10

19 D9

18 D8

17 D7

PIN 1

INDICATOR

CSB

AD9629

TOP VIEW

SCLK/DFS

SDIO/PDWN

NC

(Not to Scale)

NC

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PADDLE MUST BE SOLDERED TO

THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION,

NOISE, AND MECHANICAL STRENGTH BENEFITS.

Figure 3. Pin Configuration

Table 8. Pin Function Description

Pin No.

Mnemonic

Description

0 (EPAD)

GND

Exposed Paddle. The exposed paddle is the only ground connection. It must be soldered to the analog

ground of the customer’s PCB to ensure proper functionality and maximize heat dissipation, noise, and

mechanical strength benefits.

1, 2

3, 24, 29, 32

CLK+, CLK−

AVDD

Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.

1.8 V Supply Pin for ADC Core Domain.

4

5

CSB

SCLK/DFS

SPI Chip Select. Active low enable. 30 kΩ internal pull-up.

SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.

Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.

DFS high = twos complement output; DFS low = offset binary output.

ꢀ

SDIO/PDWN

SPI Data Input/Output (SDIO). Bidirectional SPI data I/O in SPI mode. 30 kΩ internal pull-down.

Non-SPI Mode Power-Down (PDWN). Static control of power-down with 30 kΩ internal pull-down. See

Table 14 for details.

7, 8

NC

Do Not Connect.

9 to 12, 14 to 21 D0 (LSB) to

D11 (MSB)

ADC Digital Outputs.

13

22

23

DRVDD

DCO

MODE/OR

1.8 V to 3.3 V Supply Pin for Output Driver Domain.

Data Clock Digital Output.

Chip Mode Select Input or Out-of-Range (OR) Digital Output in SPI Mode.

Default = out-of-range (OR) digital output (SPI Register 0x2A[0] = 1).

Option = chip mode select input (SPI Register 0x2A[0] = 0).

Chip power down (SPI Register 0x08[7:5] = 100b).

Chip standby (SPI Register 0x08[7:5] = 101b).

Normal operation, output disabled (SPI Register 0x08[7:5] = 110b).

Normal operation, output enabled (SPI Register 0x08[7:5] = 111b).

Out-of-Range (OR) digital output only in non-SPI mode.

25

2ꢀ

27

28

VREF

SENSE

VCM

RBIAS

VIN−, VIN+

1.0 V Voltage Reference Input/Output. See Table 10.

Reference Mode Selection. See Table 10.

Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.

Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.

ADC Analog Inputs.

30, 31

Rev. 0 | Page 10 of 32

AD9629

TYPICAL PERFORMANCE CHARACTERISTICS

AD9629-80

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

0

80MSPS

–15

–30

80MSPS

–15

–30

30.6MHz @ –1dBFS

SNR = 70.1dB (71.1dBFS)

SFDR = 94.4dBc

9.7MHz @ –1dBFS

SNR = 70.2dB (71.2dBFS)

SFDR = 93.6dBc

–45

–60

–75

–90

+

–90

3

+

2

6

2

4

3

5

4

–105

–120

–135

6

–105

–120

–135

0

4

8

12

16

20

24

28

32

36

40

0

4

8

12

16

20

24

28

32

36

40

FREQUENCY (MHz)

Figure 7. AD9629-80 Single-Tone FFT with f_IN= 30.6 MHz

Figure 4. AD9629-80 Single-Tone FFT with f_IN= 9.7 MHz

0

–15

0

80MSPS

–15

–30

69MHz @ –1dBFS

SNR = 69.9dB (70.9dBFS)

SFDR = 94.3dBc

210.3MHz @ –1dBFS

SNR = 67.9dB (68.9dBFS)

SFDR = 83.2dBc

–30

–45

–60

–75

2

3

–90

+

–90

+

6

4

2

6

3

5

4

–105

–120

–135

–105

–120

–135

0

4

8

12

16

20

24

28

32

36

40

0

4

8

12

16

20

24

28

32

36

40

FREQUENCY (MHz)

Figure 5. AD9629-80 Single-Tone FFT with f_IN= 69 MHz

Figure 8. AD9629-80 Single-Tone FFT with f_IN= 210.3 MHz

0

–15

0

80MSPS

28.3 @ –7dBFS

30.6 @ –7dBFS

SFDR = 90dBc

–30

–20

SFDR (dBc)

IMD3 (dBc)

–45

–40

–60

–75

–90

F1 + F2

F2 – F1 2F2 – F1

2F2 – F1

2F1 – F2

2F1 + F2

–80

–105

–120

–135

SFDR (dBFS)

–100

–120

IMD3 (dBFS)

–60

0

4

8

12

16

20

24

28

32

36

40

FREQUENCY (MHz)

–70

–50

–40

–30

–20

–10

INPUT AMPLITUDE (dBFS)

Figure 6. AD9629-80 Two-Tone FFT with f_IN1= 28.3 MHz and f_IN2= 30.6 MHz

Figure 9. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with f_IN1= 30.5 MHz

and f_IN2= 32.5 MHz

Rev. 0 | Page 11 of 32

AD9629

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

100

90

80

70

60

50

40

30

20

10

0

0.3

SFDR

0.2

SNR

0.1

0

–0.1

–0.2

–0.3

0

500

1000 1500 2000 2500 3000

OUTPUT CODE

3500 4000

0

50

100

INPUT FREQUENCY (MHz)

150

200

Figure 13. DNL Error with f_IN= 9.7 MHz

Figure 10. AD9629-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale

100

0.4

0.2

0

90

80

70

60

50

40

30

20

10

0

SFDR

SNRFS

–0.2

0.4

0

500

1000 1500 2000 2500 3000 3500 4000

OUTPUT CODE

10

20

30

40

50

60

70

80

SAMPLE RATE (MHz)

Figure 11. AD9629-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz

Figure 14. INL with f_IN= 9.7 MHz

100

90

SFDRFS

80

SNRFS

70

60

SFDR

50

SNR

40

30

20

10

0

–70

–60

–50

–40

–30

–20

–10

0

INPUT AMPLITUDE (dBc)

Figure 12. AD9629-80 SNR/SFDR vs. Input Amplitude (AIN) with f_IN= 9.7 MHz

Rev. 0 | Page 12 of 32

AD9629

AD9629-65

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

0

120

100

80

60

40

20

0

65MSPS

–15

9.7MHz @ –1dBFS

SNR =70.3 (71.3dBFS)

SFDR = 94.2dBc

SFDRFS

–30

–45

SNRFS

SFDR

–60

–75

–90

+

2

3

5

6

4

SNR

–105

–120

–135

0

3

6

9

12

15

18

21

24

27

30

33

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

INPUT AMPLITUDE (dBc)

Figure 15. AD9629-65 Single-Tone FFT with f_IN= 9.7 MHz

Figure 18. AD9629-65 SNR/SFDR vs. Input Amplitude (AIN) with f_IN= 9.7 MHz

0

100

65MSPS

90

–15

–30

SFDR

69MHz @ –1dBFS

SNR = 69.9dB (70.9dBFS)

SFDR = 92.0dBc

80

SNR

70

–45

60

50

40

30

20

10

0

–60

–75

–90

+

2

5

4

3

6

–105

–120

–135

0

3

6

9

12

15

18

21

24

27

30

0

50

100

150

200

FREQUENCY (MHz)

INPUT FREQUENCY (MHz)

Figure 16. AD9629-65 Single-Tone FFT with f_IN= 69 MHz

Figure 19. AD9629-65 SNR/SFDR vs. Input Frequency (AIN) with

2 V p-p Full Scale

0

65MSPS

–15

–30

30.6MHz @ –1dBFS

SNR = 70.2dB (71.2dBFS)

SFDR = 94.1dBc

–45

–60

–75

–90

+

3

2

5

6

4

–105

–120

–135

0

3

6

9

12

15

18

21

24

27

30

FREQUENCY (MHz)

Figure 17. AD9629-65 Single-Tone FFT with f_IN= 30.6 MHz

Rev. 0 | Page 13 of 32

AD9629

AD9629-40

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

0

120

100

80

60

40

20

0

40MSPS

–15

9.7MHz @ –1dBFS

SNR = 70.3dB (71.3dBFS)

SFDR = 93.8dBc

SFDRFS

SNRFS

–30

–45

–60

–75

SFDR

SNR

–90

+

2

3

5

4

6

–105

–120

–135

0

2

4

6

8

10

12

14

16

18

20

–70

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

INPUT AMPLITUDE (dBc)

Figure 20. AD9629-40 Single-Tone FFT with f_IN= 9.7 MHz

Figure 22. AD9629-40 SNR/SFDR vs. Input Amplitude (AIN) with f_IN= 9.7 MHz

0

40MSPS

–15

–30

30.6MHz @ –1dBFS

SNR = 70.2dB (71.2dBFS)

SFDR = 95.4dBc

–45

–60

–75

–90

+

5

3

6

2

4

–105

–120

–135

0

2

4

6

8

10

12

14

16

18

20

FREQUENCY (MHz)

Figure 21. AD9629-40 Single-Tone FFT with f_IN= 30.6 MHz

Rev. 0 | Page 14 of 32

AD9629

AD9629-20

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

0

120

100

80

60

40

20

0

20MSPS

–15

SFDRFS

9.7MHz @ –1dBFS

SNR = 70.3dB (71.3dBFS)

SFDR = 94.1dBc

–30

–45

SNRFS

SFDR

–60

–75

–90

+

2

5

3

SNR

4

6

–105

–120

–135

0

0.95 1.90 2.85 3.80 4.75 5.70 6.65 7.60 8.55 9.50

FREQUENCY (MHz)

–70

–60

–50

–40

–30

–20

–10

0

INPUT AMPLITUDE (dBc)

Figure 23. AD9629-20 Single-Tone FFT with f_IN= 9.7 MHz

Figure 25. AD9629-20 SNR/SFDR vs. Input Amplitude (AIN) with f_IN= 9.7 MHz

0

20MSPS

–15

30.6MHz @ –1dBFS

SNR = 70.2dB (71.2dBFS)

SFDR = 94.6dBc

–30

–45

–60

–75

–90

+

5

4

2

3

6

–105

–120

–135

0

0.95 1.90 2.85 3.80 4.75 5.70 6.65 7.60 8.55 9.50

FREQUENCY (MHz)

Figure 24. AD9629-20 Single-Tone FFT with f_IN= 30.6 MHz

Rev. 0 | Page 15 of 32

AD9629

EQUIVALENT CIRCUITS

DRVDD

AVDD

VIN±

Figure 26. Equivalent Analog Input Circuit

Figure 30. Equivalent D0 to D11 and OR Digital Output Circuit

DRVDD

AVDD

350Ω

SCLK/DFS, MODE,

375Ω

SDIO/PDWN

VREF

30kΩ

7.5kΩ

Figure 27. Equivalent VREF Circuit

Figure 31. Equivalent SCLK/DFS, MODE, and SDIO/PDWN Input Circuit

AVDD

DRVDD

AVDD

30kΩ

375Ω

350Ω

SENSE

CSB

Figure 28. Equivalent SENSE Circuit

Figure 32. Equivalent CSB Input Circuit

5Ω

CLK+

15kΩ

0.9V

AVDD

15kΩ

5Ω

CLK–

375Ω

RBIAS

AND VCM

Figure 29. Equivalent Clock Input Circuit

Figure 33. Equivalent RBIAS and VCM Circuit

Rev. 0 | Page 1ꢀ of 32

AD9629

THEORY OF OPERATION

high IF frequencies. Either a shunt capacitor or two single-ended

capacitors can be placed on the inputs to provide a matching

passive network. This ultimately creates a low-pass filter at the

input to limit unwanted broadband noise. See the AN-742

Application Note, the AN-827 Application Note, and the Analog

Dialogue article “Transformer-Coupled Front-End for Wideband

A/D Converters” (Volume 39, April 2005) for more information.

In general, the precise values depend on the application.

The AD9629 architecture consists of a multistage, pipelined ADC.

Each stage provides sufficient overlap to correct for flash errors in

the preceding stage. The quantized outputs from each stage are

combined into a final 12-bit result in the digital correction logic.

The pipelined architecture permits the first stage to operate with a

new input sample while the remaining stages operate with pre-

ceding samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor DAC

and an interstage residue amplifier (for example, a multiplying

digital-to-analog converter (MDAC)). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage consists of a flash ADC.

Input Common Mode

The analog inputs of the AD9629 are not internally dc-biased.

Therefore, in ac-coupled applications, the user must provide a

dc bias externally. Setting the device so that VCM = AVDD/2

is recommended for optimum performance, but the device can

function over a wider range with reasonable performance, as

shown in Figure 35 and Figure 36.

An on-board, common-mode voltage reference is included in

the design and is available from the VCM pin. The VCM pin

must be decoupled to ground by a 0.1 μF capacitor, as described

in the Applications Information section.

The output staging block aligns the data, corrects errors, and

passes the data to the CMOS output buffers. The output buffers

are powered from a separate (DRVDD) supply, allowing adjust-

ment of the output voltage swing. During power-down, the output

buffers go into a high impedance state.

100

SFDR (dBc)

ANALOG INPUT CONSIDERATIONS

90

80

The analog input to the AD9629 is a differential switched-

capacitor circuit designed for processing differential input

signals. This circuit can support a wide common-mode range

while maintaining excellent performance. By using an input

common-mode voltage of midsupply, users can minimize

signal-dependent errors and achieve optimum performance.

SNR (dBFS)

70

60

50

H

C_PAR

H

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

VIN+

INPUT COMMON-MODE VOLTAGE (V)

C_SAMPLE

S

Figure 35. SNR/SFDR vs. Input Common-Mode Voltage,

f

_IN= 32.1 MHz, f_S= 80 MSPS

C_SAMPLE

100

90

VIN–

H

C_PAR

SFDR (dBc)

H

Figure 34. Switched-Capacitor Input Circuit

80

The clock signal alternately switches the input circuit between

sample-and-hold mode (see Figure 34). When the input circuit

is switched to sample mode, the signal source must be capable

of charging the sample capacitors and settling within one-half

of a clock cycle. A small resistor in series with each input can

help reduce the peak transient current injected from the output

stage of the driving source. In addition, low Q inductors or ferrite

beads can be placed on each leg of the input to reduce high dif-

ferential capacitance at the analog inputs and, therefore, achieve

the maximum bandwidth of the ADC. Such use of low Q inductors

or ferrite beads is required when driving the converter front end at

SNR (dBFS)

70

60

50

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

INPUT COMMON-MODE VOLTAGE (V)

Figure 36. SNR/SFDR vs. Input Common-Mode Voltage,

f_IN= 10.3 MHz, f_S= 20 MSPS

Rev. 0 | Page 17 of 32

AD9629

Differential Input Configurations

~10 MHz where SNR is a key parameter, differential double balun

coupling is the recommended input configuration (see Figure 40).

Optimum performance is achieved while driving the AD9629 in a

differential input configuration. For baseband applications, the

AD8138, ADA4937-2, and ADA4938-2 differential drivers provide

excellent performance and a flexible interface to the ADC.

An alternative to using a transformer-coupled input at frequencies

in the second Nyquist zone is to use the AD8352 differential driver.

An example is shown in Figure 41. See the AD8352 data sheet

for more information.

The output common-mode voltage of the ADA4938-2 is easily

set with the VCM pin of the AD9629 (see Figure 37), and the

driver can be configured in a Sallen-Key filter topology to

provide band limiting of the input signal.

In any configuration, the value of Shunt Capacitor C is dependent

on the input frequency and source impedance and may need to

be reduced or removed. Table 9 displays the suggested values to set

the RC network. However, these values are dependent on the

input signal and should be used only as a starting guide.

200Ω

33Ω

VIN–

VIN

76.8Ω

AVDD

90Ω

10pF

ADC

ADA4938

Table 9. Example RC Network

0.1µF

120Ω

33Ω

VCM

VIN+

R Series

200Ω

Frequency Range (MHz)

0 to 70

(Ω Each)

C Differential (pF)

Figure 37. Differential Input Configuration Using the ADA4938-2

33

22

70 to 200

125

Open

For baseband applications below ~10 MHz where SNR is a key

parameter, differential transformer-coupling is the recommended

input configuration. An example is shown in Figure 38. To bias

the analog input, the VCM voltage can be connected to the

center tap of the secondary winding of the transformer.

Single-Ended Input Configuration

A single-ended input can provide adequate performance in

cost-sensitive applications. In this configuration, SFDR and

distortion performance degrade due to the large input common-

mode swing. If the source impedances on each input are matched,

there should be little effect on SNR performance. Figure 39

shows a typical single-ended input configuration.

VIN+

R

2V p-p

49.9Ω

C

ADC

R

VCM

VIN–

10µF

AVDD

0.1µF

1kΩ

R

Figure 38. Differential Transformer-Coupled Configuration

VIN+

1V p-p

0.1µF

49.9Ω

1kΩ

The signal characteristics must be considered when selecting

a transformer. Most RF transformers saturate at frequencies

below a few megahertz (MHz). Excessive signal power can

also cause core saturation, which leads to distortion.

AVDD

ADC

C

1kΩ

R

VIN–

10µF

0.1µF

1kΩ

At input frequencies in the second Nyquist zone and above, the

noise performance of most amplifiers is not adequate to achieve

the true SNR performance of the AD9629. For applications above

Figure 39. Single-Ended Input Configuration

0.1µF

R

0.1µF

VIN+

2V p-p

25Ω

P

A

S

P

C

ADC

0.1µF

VCM

VIN–

Figure 40. Differential Double Balun Input Configuration

V

CC

0.1µF

0Ω

0.1µF

16

1

8, 13

11

0.1µF

ANALOG INPUT

R

VIN+

VIN–

2

200Ω

C

ADC

AD8352

10

R

G

C

D

3

4

5

200Ω

VCM

14

0.1µF

ANALOG INPUT

0Ω

0.1µF

Figure 41. Differential Input Configuration Using the AD8352

Rev. 0 | Page 18 of 32

AD9629

External Reference Operation

VOLTAGE REFERENCE

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 44 shows the typical drift characteristics of the

internal reference in 1.0 V mode.

A stable and accurate 1.0 V voltage reference is built into the

AD9629. The VREF can be configured using either the internal

1.0 V reference or an externally applied 1.0 V reference voltage.

The various reference modes are summarized in the sections

that follow. The Reference Decoupling section describes the

best practices PCB layout of the reference.

4

3

Internal Reference Connection

2

VREF ERROR (mV)

1

0

A comparator within the AD9629 detects the potential at the

SENSE pin and configures the reference into two possible modes,

which are summarized in Table 10. If SENSE is grounded, the

reference amplifier switch is connected to the internal resistor

divider (see Figure 42), setting VREF to 1.0 V.

–1

–2

–3

–4

–5

–6

VIN+

VIN–

ADC

CORE

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 44. Typical VREF Drift

VREF

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7.5 kΩ load (see Figure 27). The internal buffer generates the

positive and negative full-scale references for the ADC core.

Therefore, the external reference must be limited to a maximum

of 1.0 V.

1.0µF

0.1µF

SELECT

LOGIC

SENSE

0.5V

ADC

Figure 42. Internal Reference Configuration

If the internal reference of the AD9629 is used to drive multiple

converters to improve gain matching, the loading of the reference

by the other converters must be considered. Figure 43 shows

how the internal reference voltage is affected by loading.

0

–0.5

–1.0

INTERNAL VREF = 0.996V

–1.5

–2.0

–2.5

–3.0

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

LOAD CURRENT (mA)

Figure 43. VREF Accuracy vs. Load Current

Table 10. Reference Configuration Summary

Selected Mode

SENSE Voltage (V) Resulting VREF (V)

Resulting Differential Span (V p-p)

Fixed Internal Reference

Fixed External Reference

AGND to 0.2

AVDD

1.0 internal

1.0 applied to external VREF pin

2.0

Rev. 0 | Page 19 of 32

AD9629

This limit helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9629 while

preserving the fast rise and fall times of the signal that are critical

to a low jitter performance.

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9629 sample clock inputs,

CLK+ and CLK−, with a differential signal. The signal is typi-

cally ac-coupled into the CLK+ and CLK− pins via a transformer

or capacitors. These pins are biased internally (see Figure 45)

and require no external bias.

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown in Figure 48. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers

offer excellent jitter performance.

AVDD

0.9V

CLK+

CLK–

0.1µF

CLOCK

INPUT

CLK+

2pF

AD951x

PECL DRIVER

100Ω

ADC

0.1µF

CLOCK

INPUT

CLK–

240Ω

50kΩ

Figure 45. Equivalent Clock Input Circuit

Clock Input Options

Figure 48. Differential PECL Sample Clock (Up to 4× Rated Sample Rate)

The AD9629 has a very flexible clock input structure. The clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter is

of great concern, as described in the Jitter Considerations section.

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 49. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517

clock drivers offer excellent jitter performance.

Figure 46 and Figure 47 show two preferred methods for clock-

ing the AD9629. The CLK inputs support up to 4× the rated

sample rate when using the internal clock divider feature. A low

jitter clock source is converted from a single-ended signal to a

differential signal using either an RF transformer or an RF balun.

0.1µF

CLOCK

INPUT

CLK+

AD951x

LVDS DRIVER

100Ω

ADC

0.1µF

CLOCK

INPUT

CLK–

®

50kΩ

Mini-Circuits

ADT1-1WT, 1:1 Z

0.1µF

XFMR

Figure 49. Differential LVDS Sample Clock (Up to 4× Rated Sample Rate)

CLOCK

INPUT

CLK+

100Ω

50Ω

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended 1.8 V CMOS signal. In such

applications, drive the CLK+ pin directly from a CMOS gate, and

bypass the CLK− pin to ground with a 0.1 ꢀF capacitor (see

Figure 50).

ADC

0.1µF

CLK–

SCHOTTKY

DIODES:

HSMS2822

0.1µF

Figure 46. Transformer-Coupled Differential Clock (3 MHz to 200 MHz)

V

CC

OPTIONAL

100Ω

0.1µF

1

0.1µF

1kΩ

AD951x

CMOS DRIVER

1nF

50Ω

1nF

0.1µF

CLOCK

INPUT

CLK+

CLOCK

INPUT

CLK+

50Ω

ADC

CLK–

SCHOTTKY

DIODES:

0.1µF

HSMS2822

1

50Ω RESISTOR IS OPTIONAL.

Figure 47. Balun-Coupled Differential Clock (Up to 4× Rated Sample Rate)

Figure 50. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

The RF balun configuration is recommended for clock frequencies

between 80 MHz and 320 MHz, and the RF transformer is recom-

mended for clock frequencies from 3 MHz to 200 MHz. The

back-to-back Schottky diodes across the transformer/balun

secondary limit clock excursions into the AD9629 to ~0.8 V p-p

differential.

Input Clock Divider

The AD9629 contains an input clock divider with the ability

to divide the input clock by integer values of 1, 2, or 4.

Rev. 0 | Page 20 of 32

AD9629

Clock Duty Cycle

The clock input should be treated as an analog signal in cases in

which aperture jitter may affect the dynamic range of the AD9629.

To avoid modulating the clock signal with digital noise, keep

power supplies for clock drivers separate from the ADC output

driver supplies. Low jitter, crystal-controlled oscillators make

the best clock sources. If the clock is generated from another type

of source (by gating, dividing, or another method), it should be

retimed by the original clock at the last step.

Typical high speed ADCs use both clock edges to generate

a variety of internal timing signals and, as a result, may be

sensitive to clock duty cycle. Commonly, a 50% duty cycle clock

with 5% tolerance is required to maintain optimum dynamic

performance as shown in Figure 51.

Jitter on the rising edge of the clock input can also impact dynamic

performance and should be minimized as discussed in the Jitter

Considerations section.

For more information, see the AN-501 Application Note and the

AN-756 Application Note available on www.analog.com.

80

POWER DISSIPATION AND STANDBY MODE

75

70

65

60

55

50

45

40

As shown in Figure 53, the analog core power dissipated by

the AD9629 is proportional to its sample rate. The digital

power dissipation of the CMOS outputs are determined

primarily by the strength of the digital drivers and the load

on each output bit.

The maximum DRVDD current (IDRVDD) can be calculated as

IDRVDD = V_DRVDD× C_LOAD× f_CLK× N

where N is the number of output bits (13, in the case of the

AD9629).

10

20

30

40

50

60

70

80

This maximum current occurs when every output bit switches

on every clock cycle, that is, a full-scale square wave at the Nyquist

frequency of f_CLK/2. In practice, the DRVDD current is estab-

lished by the average number of output bits switching, which

is determined by the sample rate and the characteristics of the

analog input signal.

POSITIVE DUTY CYCLE (%)

Figure 51. SNR vs. Clock Duty Cycle

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR from the low fre-

quency SNR (SNR_LF) at a given input frequency (f_INPUT) due to

jitter (t_JRMS) can be calculated by

Reducing the capacitive load presented to the output drivers

can minimize digital power consumption. The data in Figure 53

was taken using the same operating conditions as those used for

the Typical Performance Characteristics, with a 5 pF load on

each output driver.

SNR_HF= −10 log[(2π × f_INPUT× t_JRMS)²+ 10 ^{(−SNR /10)}

]

LF

In the previous equation, the rms aperture jitter represents the

clock input jitter specification. IF undersampling applications

are particularly sensitive to jitter, as illustrated in Figure 52.

85

80

AD9231-80

75

70

65

0.05ps

0.2ps

70

65

60

55

50

45

40

35

AD9231-65

60

55

50

0.5ps

AD9231-40

1.0ps

1.5ps

AD9231-20

20

2.0ps

2.5ps

10

30

40

50

60

70

80

3.0ps

CLOCK RATE (MSPS)

45

1

10

100

1k

Figure 53. Analog Core Power vs. Clock Rate

FREQUENCY (MHz)

Figure 52. SNR vs. Input Frequency and Jitter

Rev. 0 | Page 21 of 32

AD9629

In SPI mode, the AD9629 can be placed in power-down mode

directly via the SPI port, or by using the programmable external

MODE pin. In non-SPI mode, power-down is achieved by

asserting the PDWN pin high. In this state, the ADC typically

dissipates 500 μW. During power-down, the output drivers are

placed in a high impedance state. Asserting PDWN low (or the

MODE pin in SPI mode) returns the AD9629 to its normal

operating mode. Note that PDWN is referenced to the digital

output driver supply (DRVDD) and should not exceed that

supply voltage.

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI control.

Table 11. SCLK/DFS and SDIO/PDWN Mode Selection

(External Pin Mode)

Voltage at Pin SCLK/DFS

SDIO/PDWN

AGND

Offset binary (default) Normal operation

(default)

DRVDD

Twos complement

Outputs disabled

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering power-

down mode and then must be recharged when returning to normal

operation. As a result, wake-up time is related to the time spent

in power-down mode, and shorter power-down cycles result in

proportionally shorter wake-up times.

Digital Output Enable Function (OEB)

When using the SPI interface, the data outputs and DCO can be

independently three-stated by using the programmable external

MODE pin. The MODE pin (OEB) function is enabled via

Bits[6:5] of Register 0x08.

If the MODE pin is configured to operate in traditional OEB

mode and the OEB pin is low, the output data drivers and

DCOs are enabled. If the OEB pin is high, the output data

drivers and DCOs are placed in a high impedance state. This

OEB function is not intended for rapid access to the data bus.

Note that OEB is referenced to the digital output driver supply

(DRVDD) and should not exceed that supply voltage.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map section

for more details.

DIGITAL OUTPUTS

TIMING

The AD9629 output drivers can be configured to interface with

1.8 V to 3.3 V CMOS logic families. Output data can also be

multiplexed onto a single output bus to reduce the total number

of traces required.

The AD9629 provides latched data with a pipeline delay of

9 clock cycles. Data outputs are available one propagation

delay (t_PD) after the rising edge of the clock signal.

Minimize the length of the output data lines and loads placed

on them to reduce transients within the AD9629. These

transients can degrade converter dynamic performance.

The CMOS output drivers are sized to provide sufficient output

current to drive a wide variety of logic families. However, large

drive currents tend to cause current glitches on the supplies and

may affect converter performance.

The lowest typical conversion rate of the AD9629 is 3 MSPS. At

clock rates below 3 MSPS, dynamic performance can degrade.

Applications requiring the ADC to drive large capacitive loads

or large fanouts may require external buffers or latches.

Data Clock Output (DCO)

The AD9629 provides a data clock output (DCO) signal

intended for capturing the data in an external register. The CMOS

data outputs are valid on the rising edge of DCO, unless the DCO

clock polarity has been changed via the SPI. See Figure 2 for a

graphical timing description.

The output data format can be selected to be either offset binary

or twos complement by setting the SCLK/DFS pin when operating

in the external pin mode (see Table 11).

Table 12. Output Data Format

Input (V)

Condition (V)

< −VREF − 0.5 LSB

= −VREF

Offset Binary Output Mode

0000 0000 0000

1000 0000 0000

1111 1111 1111

Twos Complement Mode

1000 0000 0000

0000 0000 0000

0111 1111 1111

OR

1

0

VIN+ − VIN−

= 0

= +VREF − 1.0 LSB

> +VREF − 0.5 LSB

1111 1111 1111

0111 1111 1111

1

Rev. 0 | Page 22 of 32

AD9629

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

generator, Bit 2 (BIST INIT) of Register 0x0E. At the completion

The AD9629 includes a built-in self-test feature designed to

enable verification of the integrity of each channel as well as to

facilitate board level debugging. A built-in self-test (BIST) feature

that verifies the integrity of the digital datapath of the AD9629

is included. Various output test options are also provided to place

predictable values on the outputs of the AD9629.

of the BIST, Bit 0 of Register 0x24 is automatically cleared. The PN

sequence can be continued from its last value by writing a 0 in

Bit 2 of Register 0x0E. However, if the PN sequence is not reset,

the signature calculation does not equal the predetermined

value at the end of the test. At that point, the user needs to rely

on verifying the output data.

BUILT-IN SELF-TEST (BIST)

OUTPUT TEST MODES

The BIST is a thorough test of the digital portion of the selected

AD9629 signal path. Perform the BIST test after a reset to ensure

the part is in a known state. During BIST, data from an internal

pseudorandom noise (PN) source is driven through the digital

datapath of both channels, starting at the ADC block output.

At the datapath output, CRC logic calculates a signature from

the data. The BIST sequence runs for 512 cycles and then stops.

Once completed, the BIST compares the signature results with a

predetermined value. If the signatures match, the BIST sets Bit 0

of Register 0x24, signifying the test passed. If the BIST test failed,

Bit 0 of Register 0x24 is cleared. The outputs are connected

during this test, so the PN sequence can be observed as it runs.

Writing 0x05 to Register 0x0E runs the BIST. This enables the Bit 0

(BIST enable) of Register 0x0E and resets the PN sequence

The output test options are described in Table 16 at Address

0x0D. When an output test mode is enabled, the analog section

of the ADC is disconnected from the digital back-end blocks

and the test pattern is run through the output formatting block.

Some of the test patterns are subject to output formatting, and

some are not. The PN generators from the PN sequence tests

can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These

tests can be performed with or without an analog signal (if

present, the analog signal is ignored), but they do require an

encode clock. For more information, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI.

Rev. 0 | Page 23 of 32

AD9629

SERIAL PORT INTERFACE (SPI)

The falling edge of CSB, in conjunction with the rising edge of

SCLK, determines the start of the framing. An example of the

serial timing and its definitions can be found in Figure 54 and

Table 5.

The AD9629 serial port interface (SPI) allows the user to configure

the converter for specific functions or operations through a

structured register space provided inside the ADC. The SPI

gives the user added flexibility and customization, depending

on the application. Addresses are accessed via the serial port

and can be written to or read from via the port. Memory is

organized into bytes that can be further divided into fields,

which are documented in the Memory Map section. For

detailed operational information, see the AN-877 Application

Note, Interfacing to High Speed ADCs via SPI.

Other modes involving the CSB are available. The CSB can be

held low indefinitely, which permanently enables the device;

this is called streaming. The CSB can stall high between bytes to

allow for additional external timing. When CSB is tied high, SPI

functions are placed in high impedance mode. This mode turns

on any SPI pin secondary functions.

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase, and its length is determined

by the W0 and W1 bits as shown in Figure 54.

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK, the SDIO,

and the CSB (see Table 13). The SCLK (a serial clock) is used

to synchronize the read and write data presented from and to

the ADC. The SDIO (serial data input/output) is a dual-purpose

pin that allows data to be sent and read from the internal ADC

memory map registers. The CSB (chip select bar) is an active-

low control that enables or disables the read and write cycles.

All data is composed of 8-bit words. The first bit of the first byte in

a multibyte serial data transfer frame indicates whether a read

command or a write command is issued. This allows the serial

data input/output (SDIO) pin to change direction from an input

to an output at the appropriate point in the serial frame.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. If the instruction is a readback

operation, performing a readback causes the serial data input/

output (SDIO) pin to change direction from an input to an output

at the appropriate point in the serial frame.

Table 13. Serial Port Interface Pins

Function

SCLK Serial clock. The serial shift clock input, which is used to

synchronize serial interface reads and writes.

SDIO Serial data input/output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

Data can be sent in MSB-first mode or in LSB-first mode. MSB

first is the default on power-up and can be changed via the SPI

port configuration register. For more information about this

and other features, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

CSB

Chip select bar. An active-low control that gates the read

and write cycles.

t_HIGH

t_DS

t_CLK

t_H

t_S

t_DH

t_LOW

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Figure 54. Serial Port Interface Timing Diagram

Rev. 0 | Page 24 of 32

AD9629

HARDWARE INTERFACE

CONFIGURATION WITHOUT THE SPI

The pins described in Table 13 constitute the physical interface

between the programming device of the user and the serial

port of the AD9629. The SCLK pin and the CSB pin function

as inputs when using the SPI interface. The SDIO pin is

bidirectional, functioning as an input during write phases

and as an output during readback.

In applications that do not interface to the SPI control registers,

the SDIO/PDWN pin, the SCLK/DFS pin serve as standalone

CMOS-compatible control pins. When the device is powered up, it

is assumed that the user intends to use the pins as static control

lines for the power-down and output data format feature control.

In this mode, connect the CSB chip select to DRVDD, which

disables the serial port interface.

The SPI interface is flexible enough to be controlled by

either FPGAs or microcontrollers. One method for SPI

configuration is described in detail in the AN-812 Appli-

cation Note, Microcontroller-Based Serial Port Interface

(SPI) Boot Circuit.

Table 14. Mode Selection

External

SDIO/PDWN DRVDD

AGND (default)

DRVDD

AGND (default)

Voltage

Configuration

Chip power-down mode

Normal operation(default)

Twos complement enabled

Offset binary enabled

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is used for

other devices, it may be necessary to provide buffers between

this bus and the AD9629 to prevent these signals from transi-

tioning at the converter inputs during critical sampling periods.

SCLK/DFS

SPI ACCESSIBLE FEATURES

Table 15 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI. The AD9629 part-specific features are described in

detail in Table 16.

SDIO/PDWN and SCLK/DFS serve a dual function when the

SPI interface is not being used. When the pins are strapped to

DRVDD or ground during device power-on, they are associated

with a specific function. The Digital Outputs section describes

the strappable functions supported on the AD9629.

Table 15. Features Accessible Using the SPI

Feature

Description

Modes

Allows the user to set either power-down mode or

standby mode

Offset Adjust Allows the user to digitally adjust the converter

offset

Test Mode

Allows the user to set test modes to have known

data on output bits

Output Mode Allows the user to set up outputs

Output Phase Allows the user to set the output clock polarity

Output Delay Allows the user to vary the DCO delay

Rev. 0 | Page 25 of 32

AD9629

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

DEFAULT VALUES

Each row in the memory map register table (see Table 16)

contains eight bit locations. The memory map is roughly

divided into four sections: the chip configuration registers

(Address 0x00 to Address 0x02); the device transfer register

(Address 0xFF); the program registers, including setup, control,

and test (Address 0x08 to Address 0x2A); and the AD9629

specific customer SPI control register (Address 0x101).

After the AD9629 is reset, critical registers are loaded with default

values. The default values for the registers are given in the memory

map register table (see Table 16).

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

Table 16 documents the default hexadecimal value for each

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

hexadecimal address shown. The column with the heading Bit 7

(MSB) is the start of the default hexadecimal value given. For

example, Address 0x2A, the OR/MODE select register, has a hexa-

decimal default value of 0x01. This means that in Address 0x2A,

Bits[7:1] = 0, and Bit 0 = 1. This setting is the default OR/MODE

setting. The default value results in the programmable external

MODE/OR pin (Pin 23) functioning as an out-of-range digital

output. For more information on this function and others, see the

AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

This application note details the functions controlled by Register

0x00 to Register 0xFF. The remaining register, Register 0x101, is

documented in the Memory Map section that follows Table 16.

Transfer Register Map

Address 0x08 to Address 0x18 are shadowed. Writes to these

addresses do not affect part operation until a transfer command

is issued by writing 0x01 to Address 0xFF, setting the transfer bit.

This allows these registers to be updated internally and simulta-

neously when the transfer bit is set. The internal update takes

place when the transfer bit is set, and then the bit autoclears.

OPEN LOCATIONS

All address and bit locations that are not included in the SPI map

are not currently supported for this device. Unused bits of a valid

address location should be written with 0s. Writing to these loca-

tions is required only when part of an address location is open

(for example, Address 0x2A). If the entire address location is

open, it is omitted from the SPI map (for example, Address 0x13)

and should not be written.

Rev. 0 | Page 2ꢀ of 32

AD9629

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 16 are not currently supported for this device.

Table 16.

Default

Value

(Hex)

Addr

Bit 7

(MSB)

Bit 0

(LSB)

(Hex) Register Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Comments

Chip Configuration Registers

0x00

SPI port

configuration

0

LSB

first

Soft

reset

1

Soft reset

LSB

first

0

0x18

The nibbles are

mirrored so that LSB

or MSB first mode

registers correctly,

regardless of shift

mode

0x01

0x02

Chip ID

8-bit chip ID, Bits[7:0]

AD9ꢀ29 = 0x70

Read

only

Unique chip ID used

to differentiate

devices; read only

Chip grade

Open

Speed grade ID, Bits[ꢀ:4]

(identify device variants of

chip ID)

Open

Read

only

Unique speed grade

ID used to

differentiate devices;

Read only

20 MSPS = 000

40 MSPS = 001

ꢀ5 MSPS = 010

80 MSPS = 011

Device Index and Transfer Register

0xFF Transfer Open

Open

Open Transfer

0x00

Synchronously

transfers data from

the master shift

register to the slave

Program Registers

0x08

Modes

External External Pin 23

00 = chip run

01 = full power down

10 = standby

11 = chip wide digital

reset

Determines various

generic modes of

chip operation

Pin 23

mode

input

function when high

00 = full power

down

01 = standby

10 = normal

mode: output

disabled

enable

11 = normal

mode: output

enabled

0x0B

0x0D

Clock divide

Test mode

Open

Clock divider, Bits[2:0]

0x00

The divide ratio is

the value plus 1

Clock divide ratio

000 = divide-by-1

001 = divide-by-2

011 = divide-by-4

User test mode

00 = single

01 = alternate

10 = single once

11 = alternate

once

Reset PN Reset

long gen PN

short

Output test mode, Bits[3:0] (local)

0000 = off (default)

0001 = midscale short

0010 = positive FS

When set, the test

data is placed on the

output pins in place

of normal data

gen

0011 = negative FS

0100 = alternating checkerboard

0101 = PN 23 sequence

0110 = PN 9 sequence

0111 = 1/0 word toggle

1000 = user input

1001 = one/zero bit toggle

1010 = 1× sync

1011 = one bit high

1100 = mixed bit frequency

0x0E

0x10

BIST enable

Offset adjust

Open

BIST INIT

Open BIST enable

0x00

When Bit 0 is set, the

built-in self-test

function is initiated

8-bit device offset adjustment [7:0] (local)

Device offset trim

Offset adjust in LSBs from +127 to −128 (twos complement format)

Rev. 0 | Page 27 of 32

AD9629

Default

Value

(Hex)

Addr

Bit 7

(MSB)

Bit 0

(LSB)

(Hex) Register Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Comments

0x14

Output mode

00 = 3.3 V CMOS

10 = 1.8 V CMOS

Open

Output Open

disable

Output

invert

00 = offset binary

01 = twos

complement

0x00

Configures the

outputs and the

format of the data

10 = gray code

11 = offset binary

0x15

Output adjust

3.3 V DCO

1.8 V DCO

3.3 V data

1.8 V data

0x22

Determines CMOS

output drive

strength properties

drive strength

00 = 1 stripe

(default)

01 = 2 stripes

10 = 3 stripes

11 = 4 stripes

drive strength

00 = 1 stripe

01 = 2 stripes

10 = 3 stripes

(default)

drive strength

00 = 1 stripe

(default)

01 = 2 stripes

10 = 3 stripes

11 = 4 stripes

drive strength

00 = 1 stripe

01 = 2 stripes

10 = 3 stripes

(default)

11 = 4 stripes

0x1ꢀ

Output phase

DCO

Open

Input clock phase adjust, Bits[2:0]

(Value is number of input clock

cycles of phase delay)

0x00

On devices that

utilize global clock

divide, determines

which phase of the

divider output is

used to supply the

output clock;

Output

polarity

0 =

normal

1 =

000 = no delay

001 = 1 input clock cycle

010 = 2 input clock cycles

011 = 3 input clock cycles

100 = 4 input clock cycles

101 = 5 input clock cycles

110 = ꢀ input clock cycles

111 = 7 input clock cycles

inverted

internal latching is

unaffected

0x17

Output delay

Enable

DCO

delay

Open

Enable

data

delay

Open

DCO/data delay, Bits[2:0]

000 = 0.5ꢀ ns

001 = 1.12 ns

010 = 1.ꢀ8 ns

011 = 2.24 ns

100 = 2.80 ns

101 = 3.3ꢀ ns

110 = 3.92 ns

111 = 4.48 ns

0x00

Sets the fine output

delay of the output

clock, but does not

change internal

timing

0x19

0x1A

0x1B

0x1C

0x24

USER_PATT1_LSB

B7

Bꢀ

B5

B4

B3

B2

B1

B9

B1

B9

B0

B8

B0

B8

0x00

User-defined

pattern, 1 LSB

USER_PATT1_MSB B15

USER_PATT2_LSB B7

B14

Bꢀ

B13

B5

B12

B4

B11

B3

B10

B2

User-defined

pattern, 1 MSB

User-defined

pattern, 2 LSB

USER_PATT2_MSB B15

BIST signature LSB

B14

B13

B12

B11

B10

User-defined

pattern, 2 MSB

BIST signature, Bits[7:0]

Least significant byte

of BIST signature,

read only

0x2A

OR/MODE select

Open

0 =

0x01

Selects I/O

MODE

1 = OR

(default)

functionality in

conjunction w/

Address 0x08 for

MODE (input) or OR

(output) on external

Pin 23

1.1. AD9ꢀ29 Specific Customer SPI Control

0x101 USR2

1

Enable

GCLK

detect

Run GCLK

Disable

SDIO

pull-

0x88

Enables internal

oscillator for clock

rates of <5 MHz

down

Rev. 0 | Page 28 of 32

AD9629

Bit 2—Run GCLK

MEMORY MAP REGISTER DESCRIPTIONS

This bit enables the GCLK oscillator. For some applications

with encode rates below 10 MSPS, it may be preferable to set

this bit high to supersede the GCLK detector.

For additional information about functions controlled in

Register 0x00 to Register 0xFF, see the AN-877 Application

Note, Interfacing to High Speed ADCs via SPI.

Bit 0—Disable SDIO Pull-Down

USR2 (Register 0x101)

This bit can be set high to disable the internal 30 kꢁ pull-down

on the SDIO pin, which can be used to limit the loading when

many devices are connected to the SPI bus.

Bit 3—Enable GCLK Detect

Normally set high, this bit enables a circuit that detects encode

rates below about 5 MSPS. When a low encode rate is detected,

an internal oscillator, GCLK, is enabled ensuring the proper

operation of several circuits. If set low the detector is disabled.

Rev. 0 | Page 29 of 32

AD9629

APPLICATIONS INFORMATION

To maximize the coverage and adhesion between the ADC and

the PCB, a silkscreen should be overlaid to partition the continuous

plane on the PCB into several uniform sections. This provides

several tie points between the ADC and the PCB during the reflow

process. Using one continuous plane with no partitions guarantees

only one tie point between the ADC and the PCB. For detailed

information about packaging and PCB layout of chip scale

packages, see the AN-772 Application Note, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package

(LFCSP), at www.analog.com.

DESIGN GUIDELINES

Before starting design and layout of the AD9629 as a system,

it is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9629, it is strongly recom-

mended that two separate supplies be used. Use one 1.8 V supply

for analog (AVDD); use a separate 1.8 V to 3.3 V supply for the

digital output supply (DRVDD). If a common 1.8 V AVDD and

DRVDD supply must be used, the AVDD and DRVDD domains

must be isolated with a ferrite bead or filter choke and separate

decoupling capacitors. Several different decoupling capacitors

can be used to cover both high and low frequencies. Locate

these capacitors close to the point of entry at the PCB level

and close to the pins of the part, with minimal trace length.

Encode Clock

For optimum dynamic performance a low jitter encode clock

source with a 50% duty cycle 5% should be used to clock the

AD9629.

VCM

The VCM pin should be decoupled to ground with a 0.1 ꢀF

capacitor, as shown in Figure 38.

A single PCB ground plane should be sufficient when using the

AD9629. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

RBIAS

The AD9629 requires that a 10 kΩ resistor be placed between

the RBIAS pin and ground. This resistor sets the master current

reference of the ADC core and should have at least a 1% tolerance.

Exposed Paddle Thermal Heat Sink Recommendations

The exposed paddle (Pin 0) is the only ground connection for

the AD9629; therefore, it must be connected to analog ground

(AGND) on the customer’s PCB. To achieve the best electrical

and thermal performance, mate an exposed (no solder mask)

continuous copper plane on the PCB to the AD9629 exposed

paddle, Pin 0.

Reference Decoupling

Externally decouple the VREF pin to ground with a low ESR,

1.0 ꢀF capacitor in parallel with a low ESR, 0.1 ꢀF ceramic

capacitor.

SPI Port

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9629 to keep these signals from transitioning at the converter

inputs during critical sampling periods.

The copper plane should have several vias to achieve the

lowest possible resistive thermal path for heat dissipation to

flow through the bottom of the PCB. Fill or plug these vias

with nonconductive epoxy.

Rev. 0 | Page 30 of 32

AD9629

OUTLINE DIMENSIONS

5.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

EXPOSED

PAD

(BOTTOM VIEW)

3.65

3.50 SQ

3.35

TOP

VIEW

4.75

BSC SQ

0.50

0.40

0.30

17

16

8

9

0.25 MIN

0.80 MAX

0.65 TYP

3.50 REF

12° MAX

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 55. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad (CP-32-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

–40°C to +85°C

Package Description

Package Option

CP-32-4

AD9ꢀ29BCPZ-80^{1, 2}

AD9ꢀ29BCPZRL7-80^{1, 2}

AD9ꢀ29BCPZ-ꢀ5^{1, 2}

AD9ꢀ29BCPZRL7-ꢀ5^{1, 2}

AD9ꢀ29BCPZ-40^{1, 2}

AD9ꢀ29BCPZRL7-40^{1, 2}

AD9ꢀ29BCPZ-20^{1, 2}

AD9ꢀ29BCPZRL7-20^{1, 2}

AD9ꢀ29-80EBZ¹

32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

Evaluation Board

AD9ꢀ29-ꢀ5EBZ¹

Evaluation Board

AD9ꢀ29-40EBZ¹

AD9ꢀ29-20EBZ¹

¹Z = RoHS Compliant Part.

²The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND.

Rev. 0 | Page 31 of 32

AD9629

NOTES

registered trademarks are the property of their respective owners.

D08540-0-10/09(0)

Rev. 0 | Page 32 of 32


型号：	AD9629BCPZ-80
厂家：	ADI
描述：	12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter 12位， 20 MSPS / 40 MSPS / 65 MSPS / 80 MSPS ， 1.8 V模拟数字转换器转换器
文件：	总32页 (文件大小：984K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9629BCPZ-80 [ADI]

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