AD9630AQ [ADI]
IC BUFFER AMPLIFIER, CDIP8, CERDIP-8, Buffer Amplifier;
| 型号： | AD9630AQ |
| 厂家： | 
ADI |
| 描述： | IC BUFFER AMPLIFIER, CDIP8, CERDIP-8, Buffer Amplifier 缓冲放大器 |
| 文件： | 总7页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Distortion 750 MHz
Closed-Loop Buffer Amp
a
AD9630*
PIN CONFIGURATION
FEATURES
Excellent Gain Accuracy: 0.99 V/V
Wide Bandwidth: 750 MHz
Slew Rate: 1200 V/s
Low Distortion
–65 dBc @ 20 MHz
–80 dBc @ 4.3 MHz
Settling Time
+V
OUTPUT
NC
1
2
3
4
8
7
6
5
S
**
NC
***
–V
S
INPUT
AD9630
NC = NO CONNECT
5 ns to 0.1%
**OPTIONAL +V
***OPTIONAL –V
S
S
8 ns to 0.02%
Low Noise: 2.4 nV/√Hz
Improved Source for CLC-110
NOTE: FOR BEST SETTLING TIME PERFORMANCE USE
OPTIONAL POWER SUPPLIES. ALL SPECIFICATIONS
ARE BASED ON USING SINGLE ؎V CONNECTIONS,
S
EXCEPT FOR SETTLING TIME TO 0.02% AND SMALL
SIGNAL S21. CONSULT THE FACTORY FOR VERSIONS
WITH OPTIONAL POWER SUPPLY PINS DISCONNECTED
INTERNAL TO THE PACKAGE.
APPLICATIONS
IF/Communications
Impedance Transformations
Drives Flash ADCs
Line Driving
The large signal bandwidth, low distortion over frequency, and
drive capabilities of the AD9630 make the buffer an ideal flash
ADC driver. The AD9630 provides better signal fidelity than
many of the flash ADCs that it has been designed to drive.
GENERAL DESCRIPTION
The AD9630 is a monolithic buffer amplifier that utilizes a
patented, innovative, closed-loop design technique to achieve
exceptional gain accuracy, wide bandwidth, and low distortion.
Slew rate limiting has been overcome as indicated by the
1200 V/µs slew rate; this improvement allows the user greater
flexibility in wideband and pulse applications. The second har-
monic distortion terms for an analog input tone of 4.3 MHz
and 20 MHz are –80 dBc and –66 dBc, respectively. Clearly,
the AD9630 establishes a new standard by combining out-
standing dc and dynamic performance in one part.
Other applications that require increased current drive at unity
voltage gain (such as cable driving) benefit from the AD9630’s
performance.
The AD9630 is available in plastic DIP (N) and SOIC (R).
*Protected under U.S. patent numbers 5,150,074 and 5,537,079.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
AD9630–SPECIFICATIONS
(unless otherwise noted, ؎VS = ؎5 V; RIN = 50 ⍀, RLOAD = 100 ⍀)
ELECTRICAL CHARACTERISTICS
Test
AD9630AN/AR
Typ
Parameter
Conditions
Temp
Level
Min
Max
Units
DC SPECIFICATIONS
Output Offset Voltage
Offset Voltage TC
Input Bias Current
Bias Current TC
+25°C
Full
+25°C
Full
+25 to TMAX
TMIN
+25°C
+25 to TMAX
TMIN
Full
+25 to TMAX
TMIN
+25°C
Full
+25°C
I
IV
I
IV
II
VI
V
–8
±3
±8
±2
±20
450
250
1.0
0.990
0.985
±3.6
+8
mV
µV/°C
µA
nA/°C
kΩ
–40
–25
–100
300
150
+40
+25
+100
Input Resistance
kΩ
pF
Input Capacitance
Gain
VOUT = 2 V p-p
VOUT = 2 V p-p
II
0.983
0.980
+3.2
50
V/V
V/V
V
mA
mA
Ω
VI
VI
II
VI
V
Output Voltage Range
Output Current (50 Ω Load)
–3.2
40
Output Impedance
PSRR
DC Nonlinearity
At DC
∆VS = ±5%
±2 V Full Scale
0.6
55
0.03
VI
V
44
dB
%
FREQUENCY DOMAIN
Bandwidth (–3 dB)
Small Signal
V
V
O ≤ 0.7 V p-p
O ≤ 0.7 V p-p
TMIN to +25
TMAX
TMIN to +25
TMAX
Full
Full
+25°C
+25°C
Full
Full
Full
Full
Full
TMIN to +25
TMAX
+25°C
+25°C
II
II
V
400
330
750
550
120
105
0.4
0
0.7
0.7
–80
–66
–52
–86
–75
–47
–46
2.4
32
MHz
MHz
MHz
MHz
dB
dB
ns
Degrees
dBc
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
µV
Large Signal
VO = 5 V p-p
VO = 5 V p-p
≤200 MHz
≤200 MHz
V
Output Peaking
Output Rolloff
Group Delay
Linear Phase Deviation
2nd Harmonic Distortion
II
II
V
1.2
0.3
DC to 150 MHz
DC to 150 MHz
2 V p-p; 4.3 MHz
2 V p-p; 20 MHz
2 V p-p; 50 MHz
2 V p-p; 4.3 MHz
2 V p-p; 20 MHz
2 V p-p; 50 MHz
2 V p-p; 50 MHz
10 MHz
V
IV
IV
II
IV
IV
II
II
V
–73
–58
–43
–79
–68
–41
–40
3rd Harmonic Distortion
Spectral Input Noise Voltage
Integrated Output Noise
100 kHz – 200 MHz
V
TIME DOMAIN
Slew Rate
Rise/Fall Time
VOUT = 5 V Step
VOUT = 1 V Step
VOUT = 1 V Step
VOUT = 5 V Step
VOUT = 5 V Step
VOUT = 2 V Step
+25°C
+25°C
TMIN to TMAX
+25°C
TMIN to TMAX
Full
IV
IV
IV
IV
IV
IV
700
1200
1.1
1.3
4.2
5.0
2
V/µs
ns
ns
ns
ns
1.7
1.9
5.7
6.5
12
Overshoot Amplitude
Settling Time
To 0.1%
%
VOUT = 2 V Step
VOUT = 2 V Step
VOUT = 2 V Step
VOUT = 2 V Step
4.4 MHz
TMIN to +25
TMAX
TMIN to +25
TMAX
+25°C
+25°C
IV
IV
IV
V
V
V
6
7
8
12
0.015
0.025
10
12
ns
ns
ns
ns
%
Degree
To 0.02%4
Differential Gain
Differential Phase
4.4 MHz
SUPPLY CURRENTS
VCC (+IS)
VEE (–IS)
VCC = +5 V
VEE = –5 V
Full
Full
II
II
19
19
26
26
mA
mA
NOTES
1Short-term settling with 50 Ω source impedance.
Specifications subject to change without notice.
REV. B
–2–
AD9630
ABSOLUTE MAXIMUM RATINGS1
Supply Voltages (±VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V
Continuous Output Current2 . . . . . . . . . . . . . . . . . . . . . 70 mA
Temperature Range over Which Specifications Apply
AD9630AN/AR . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . +300°C
Storage Temperature
EXPLANATION OF TEST LEVELS
Test Level
I
100% Production tested.
II 100% Production tested at +25°C and sample tested at
specified temperatures. AC testing of AN and AR grades
done on sample basis only.
III Sample tested only.
AD9630AN/AR . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
IV Parameter is guaranteed by design and characterization
testing.
Junction Temperature3
AD9630AN/AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
V
Typical value.
NOTES
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2Output is short-circuit protected to ground, but not to supplies. Prolonged short
circuit to ground may affect device reliability.
VI S Versions are 100% production tested at temperature
extremes. Other grades are sample tested at extremes.
100⍀
(5%, 0.25W)
+5V
1
2
3
4
8
7
6
5
0.1F
3Typical thermal impedances (part soldered onto board): Plastic DIP (N): θJA
110°C/W; θJC = 30°C/W; SOIC (R): θJA = 155°C/W; θJC = 40°C/W.
=
NC
NC
AD9630
TOP VIEW
(Not to Scale)
NC
NC
–5.2V
24⍀
(5%, 0.25W)
0.1F
ORDERING GUIDE
NC = NO CONNECT
Temperature
Range
Package
Description
Package
Option
Model
AD9630 Burn-In Circuit
AD9630AN
AD9630AR
–40°C to +85°C 8-Lead Plastic DIP N-8
–40°C to +85°C 8-Lead SOIC SO-8
AD9630AR-REEL –40°C to +85°C 13" Tape and Reel SO-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9630 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
THEORY OF OPERATION
Parasitic or load capacitance (>7 pF) connected directly to the
AD9630 output will result in frequency peaking. A small series
resistor (RS) connected between the buffer output and capaci-
tive load will negate this effect. Figure 1 shows the optimal value
of RS as a function of CL to obtain the flattest frequency re-
sponse. Figure 2 illustrates frequency response for various
capacitive loads utilizing the recommended RS.
The AD9630 is a wide-bandwidth, closed-loop, unity-gain
buffer that makes use of a new voltage-feedback architecture.
This architecture brings together wide bandwidth and high slew
rate along with exceptional dc linearity. Most previous wide-
bandwidth buffers achieved their bandwidth by utilizing an
open-loop topology which sacrificed both dc linearity and fre-
quency distortion when driven into low load impedances. The
design’s high loop correction factor radically improves dc lin-
earity and distortion characteristics without diminishing
bandwidth. This, in combination with high slew rate, results in
exceptionally low distortion over a wide frequency range.
50
R
S
40
30
20
200⍀
"R"
C
L
The AD9630 is an excellent choice to drive high speed and high
resolution analog-to-digital converters. Its output stage is de-
signed to drive high speed flash converters with minimal or no
series resistance. A current booster built into the output driver
helps to maintain low distortion.
NO R NEEDED
S
WHEN C < 7pF;
FOR C > 30pF, "R"
L
CAN BE OMITTED
L
10
0
0
7
20
40
60
80
100
C
– pF
L
Figure 1. Recommended RS vs. CL
REV. B
–3–
AD9630
2
the device output. To avoid this occurrence, the power supply
leads should be tightly twisted (if appropriate). Ferrite beads
mounted between the tantalum and ceramic capacitors will
serve the same purpose.
1
10pF
25pF
0
–1
–2
–3
–4
–5
–6
–7
All unused pins (except the optional power supply pins) should
be connected to ground to reduce pin-to-pin capacitive coupling
and prevent external RF interference. If the source and drive
electronics require “remote” operation (> 1 inch from the
AD9630), the PC board line impedances should be matched
with the buffer input and output resistances. Basic microstrip
techniques should be observed. RIN and RS should be connected
as close to the AD9630 as possible.
50pF
With only minimal pulse overshoot and ringing, the AD9630
can drive terminated cables directly without the use of an output
–8
<0.1MHz
100MHz
200MHz
300MHz
C
L
termination resistor (RS). Termination resistors (RS and RIN
)
can be either standard carbon composition or microwave type.
For matching characteristic impedances, precision microwave
resistors of 1% or better tolerance are preferred.
Figure 2. Frequency Response vs. CL
with Recommended RS
In pulse mode applications, with RS equal to approximately
12 Ω, capacitive loads of up to 50 pF can be driven with mini-
mal settling time degradation.
The AD9630 should be soldered directly to the PC board with
as little vertical clearance as possible. The use of zero insertion
sockets is strongly discouraged because of the high effective pin
inductances. Use of this type socket will result in peaking and
possibly induce oscillation.
The output stage has short circuit protection to ground. The
output driver will shut down if more than approximately
130 mA of instantaneous sink or source current is reached. This
level of current ensures that output clipping will not result when
driving heavy capacitive loads during high slew conditions,
although average load currents above 70 mA may reduce device
reliability.
+V
S
4.7F
0.1F
0.1F
LAYOUT CONSIDERATIONS
Due to the high frequency operation of the AD9630 attention to
board layout is necessary to achieve optimum dynamic perfor-
mance. A two ounce copper ground plane on the top side of the
board is recommended; it should cover as much of the board as
possible with appropriate openings for supply decoupling ca-
pacitors as well as for load and source termination resistors, (see
Figure 3).
1
*
2
R **
S
V
V
OUT
8
IN
AD9630
*
6
R
IN
5
0.1F
0.1F
Optimum settling time and ac performance results will be
achieved with surface mount 0.1 µF supply decoupling ceramic
chip capacitors mounted within 50 mils of the corresponding
device pins with the other side soldered directly to the ground
plane. For best high resolution (<0.02%) settling times, the op-
tional power supply pins should be decoupled as shown above.
If the optional power supply pins are not used, they should be
left open.
4.7F
–V
S
*SEE PINOUTS
**SEE FIGURE 1
Figure 3. AD9630 Application Circuit
If surface mount capacitors cannot be used, radial lead ceramic
capacitors with leads less than 30 mils long are recommended.
Low frequency power supply decoupling is necessary and can be
accomplished with 4.7 µF tantalum capacitors mounted within
0.5 inches of the supply pins. Due to the series inductance of
these capacitors interacting with the 0.1 µF capacitors and
power supply leads, high frequency oscillations might appear on
REV. B
–4–
Typical Performance Curves – AD9630
1M
100k
10k
1k
30
100
80
60
40
20
0
0
–100
–200
–300
–400
–500
–600
–700
–800
–900
–1000
R
R
= 200⍀
= 100⍀
L
25
20
15
|Zo|
L
100
10
10
5
1
0
1M
1M
10M
100M
1G
10M
100M
FREQUENCY – Hz
1G
–3
–2
–1
0
1
2
3
FREQUENCY – Hz
VOLTS
Figure 4. Endpoint DC Linearity
Figure 5. Input Impedance
Figure 6. Output Impedance
10
50
40
50
40
30
20
10
0
50
40
30
20
10
0
8
50⍀
30
6
4
50⍀
20
TEST
CIRCUIT
BIAS CURRENT
10
2
0
0
–2
–10
–20
–30
–40
–50
–4
–6
OFFSET VOLTAGE
–8
–10
–55
25
125
1M
10M
100M
1G
dc
50
100
150
200
250
CASE TEMPERATURE – ؇C
FREQUENCY – Hz
FREQUENCY – MHz
Figure 9. Offset Voltage and Bias
Current vs. Temperature
Figure 7. PSRR vs. Frequency
Figure 8. 2-Tone Intermodulation
Distortion
2
1
3
2
V
= 100mV
IN
0.5
R
= 200⍀
L
0
1
0
V
= 750mV
= 100mV
0.25
–1
–2
–3
–4
–5
–6
–7
–8
GAIN
IN
R
= 50⍀
L
0
R
= 100⍀
–1
–2
–3
–4
–5
–6
–7
L
–45
–90
–135
–180
0
PHASE
TEST CIRCUIT
50⍀
V
IN
–0.25
6pF
50⍀
–0.5
0M
200M
400M 600M
800M
1G
0
40
80
120
160
200
2ns/DIVISION
FREQUENCY – Hz
FREQUENCY – MHz
Figure 10 . Forward Gain and Phase
Figure 11. Frequency Response vs.
RLOAD
Figure 12. Small-Signal Pulse
Response
REV. B
–5–
AD9630
0.1
0.08
0.06
0.04
0.02
0.1
0.08
0.06
0.04
0.02
3.0
TEST CIRCUIT
TEST CIRCUIT
2.5
2.0
1.5
1.0
100⍀
6pF
100⍀
6pF
0.5
0
0
0
TEST CIRCUIT
50⍀
–0.5
–0.02
–0.02
–1.0
–0.04
–0.06
–0.04
–0.06
–1.5
–2.0
–2.5
–3.0
6pF
50⍀
–0.08
–0.1
–0.08
–0.1
V
= 2V STEP
V
= 2V STEP
40 50
OUT
OUT
1
10
100
1k
10k
100k
10
20
30
5ns/DIVISION
TIME – ns
TIME – ns
Figure 13. Short-Term Settling Time
Figure 14. Long-Term Settling Time
Figure 15. Large-Signal Pulse
Response
40
40
R
= 100⍀
R
= 100⍀
L
L
50
60
70
80
50
60
70
80
2nd
3rd
2nd
3rd
90
90
100
100
1
10
FREQUENCY – MHz
100
1
10
FREQUENCY – MHz
100
Figure 16. Harmonic Distortion
OUT = 4 V p-p
Figure 17. Harmonic Distortion
OUT = 2 V p-p
V
V
REV. B
–6–
AD9630
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
8-Lead SOIC
(SO-8)
0.430 (10.92)
0.348 (8.84)
0.1968 (5.00)
0.1890 (4.80)
8
5
8
1
5
4
0.280 (7.11)
0.240 (6.10)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
1
4
0.325 (8.25)
0.300 (7.62)
PIN 1
PIN 1
0.100 (2.54)
BSC
0.0196 (0.50)
؋
45؇ 0.0500 (1.27)
BSC
0.060 (1.52)
0.015 (0.38)
0.0099 (0.25)
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
0.130
(3.30)
MIN
8؇
0؇
0.160 (4.06)
0.115 (2.93)
0.0500 (1.27)
0.0160 (0.41)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
SEATING
PLANE
0.015 (0.381)
0.008 (0.204)
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15)
PLANE
REV. B
–7–
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