AD8347ARUZ [ADI]
0.8 GHz to 2.7 GHz Direct Conversion; 0.8 GHz至2.7 GHz直接转换
| 型号： | AD8347ARUZ |
| 厂家： | 
ADI |
| 描述： | 0.8 GHz to 2.7 GHz Direct Conversion |
| 文件： | 总28页 (文件大小：630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0.8 GHz to 2.7 GHz Direct Conversion
Quadrature Demodulator
AD8347
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Integrated RF and baseband AGC amplifiers
Quadrature phase accuracy 1° typ
I/Q amplitude balance 0.3 dB typ
Third-order intercept (IIP3) +11.5 dBm @ min gain
Noise figure 11 dB @ max gain
AGC range 69.5 dB
Baseband level control circuit
Low LO drive −8 dBm
ADC-compatible I/Q outputs
Single supply 2.7 V to 5.5 V
AD8347
LOIN
VPS1
IOPN
IOPP
VCMO
IAIN
1
2
28 LOIP
PHASE
SPLITTER
27 COM1
26 QOPN
25 QOPP
3
4
PHASE
SPLITTER
5
24
23
22
21
20
19
18
17
16
15
QAIN
COM3
QMXO
VPS3
VDT1
VAGC
VDT2
6
7
COM3
IMXO
COM2
RFIN
RFIP
8
9
10
11
12
13
14
DET
Power-down mode
28-lead TSSOP package
VPS2
IOFS
VREF
VGIN
QOFS
ENBL
GAIN
CONTROL
BIAS
APPLICATIONS
Cellular base stations
Radio links
Figure 1.
Wireless local loop
IF broadband demodulators
RF instrumentation
Satellite modems
GENERAL DESCRIPTION
The AD83471 is a broadband direct quadrature demodulator
with RF and baseband automatic gain control (AGC) amplifiers.
It is suitable for use in many communications receivers, performing
quadrature demodulation directly to baseband frequencies. The
input frequency range is 800 MHz to 2.7 GHz. The outputs can
be connected directly to popular A-to-D converters such as the
AD9201 and AD9283.
Baseband level detectors are included for use in an AGC loop to
maintain the output level. The demodulator dc offsets are
minimized by an internal loop, whose time constant is
controlled by external capacitor values. The offset control can
also be overridden by forcing an external voltage at the offset
nulling pins.
The baseband variable gain amplifier outputs are brought off-
chip for filtering before final amplification. By inserting a
channel selection filter before each output amplifier, high level
out-of-channel interferers are eliminated. Additional internal
circuitry also allows the user to set the dc common-mode level
at the baseband outputs.
The RF input signal goes through two stages of variable gain
amplifiers prior to two Gilbert-cell mixers. The LO quadrature
phase splitter employs polyphase filters to achieve high
quadrature accuracy and amplitude balance over the entire
operating frequency range. Separate I and Q channel variable
gain amplifiers follow the baseband outputs of the mixers. The
RF and baseband amplifiers together provide 69.5 dB of gain
control. A precision control circuit sets the linear-in-dB RF gain
response to the gain control voltage.
1 U.S. patents issued and pending.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD8347
TABLE OF CONTENTS
Features .............................................................................................. 1
LO and Phase Splitters............................................................... 16
Output Level Detector ............................................................... 17
Bias ............................................................................................... 17
Applications..................................................................................... 18
Basic Connections...................................................................... 18
RF Input and Matching ............................................................. 18
LO Drive Interface ..................................................................... 18
Operating the VGA.................................................................... 19
Mixer Output Level and Drive Capability .............................. 19
Operating the VGA in AGC Mode.......................................... 19
Changing the AGC Setpoint..................................................... 20
Baseband Amplifiers.................................................................. 20
Driving Capacitive Loads.......................................................... 21
External Baseband Amplification ............................................ 21
Filter Design Considerations .................................................... 21
DC Offset Compensation.......................................................... 22
Evaluation Board ............................................................................ 23
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 8
RF Amp and Demodulator ......................................................... 8
Baseband Output Amplifiers .................................................... 11
RF Amp/Demod and Baseband Output Amplifiers.............. 12
Equivalent Circuits..................................................................... 14
Theory of Operation ...................................................................... 16
RF Variable Gain Amplifiers (VGA)........................................ 16
Mixers .......................................................................................... 16
Baseband Variable Gain Amplifiers......................................... 16
Output Amplifiers ...................................................................... 16
REVISION HISTORY
10/05—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Change VGIN to VVGIN..........................................................Universal
Changes to Figure 46...................................................................... 19
Changes to Figure 48 ..................................................................... 21
Changes to Figure 49 and Figure 50............................................. 22
Changes to Ordering Guide .......................................................... 27
10/01—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD8347
SPECIFICATIONS
VS = 5 V; TA = 25°C; FLO = 1.9 GHz; VVCMO = 1 V; FRF = 1.905 GHz; PLO = −8 dBm, RLOAD = 10 kΩ, dBm with respect to 50 Ω, unless
otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
OPERATING CONDITIONS
LO/RF Frequency Range
LO Input Level
VGIN Input Level
VSUPPLY (VS)
Temperature Range
RF AMPLIFIER/DEMODULATOR
AGC Gain Range
Conversion Gain (Max)
Conversion Gain (Min)
Gain Linearity
0.8
−10
0.2
2.7
−40
2.7
0
1.2
5.5
+85
GHz
dBm
V
V
°C
From RFIP/RFIN to IMXO and QMXO (IMXO/QMXO load > 1 kΩ)
69.5
39.5
−30
2
dB
dB
dB
dB
VVGIN = 0.2 V (max gain)
VVGIN = 1.2 V (min gain)
VVGIN = 0.3 V to 1 V
Gain Flatness
Input P1 dB
FLO = 0.8 GHz to 2.7 GHz, FBB = 1 MHz
VVGIN = 0.2 V
VVGIN = 1.2 V
+0.7
−30
−2
dB p-p
dBm
dBm
dBm
Third-Order Input Intercept (IIP3)
FRF1 = 1.905 GHz,
+11.5
FRF2 = 1.906 GHz, –10 dBm each tone, (min gain)
Second-Order Input Intercept (IIP2) FRF1 = 1.905 GHz,
FRF2 = 1.906 GHz, −10 dBm each tone, (min gain)
At RFIP
+25.5
dBm
LO Leakage (RF)
−60
−42
+90
1
+0.3
11
dBm
dBm
MHz
degree
dB
LO Leakage (MXO)
At IMXO/QMXO
Demodulation Bandwidth
Quadrature Phase Error
I/Q Amplitude Imbalance
Noise Figure
−3 dB
FRF = 1.9 GHz
FRF = 1.9 GHz
Max Gain
−3
+3
dB
Mixer AGC Output Level
Baseband DC Offset
Mixer Output Swing
See Figure 34
24
2
mV p-p
mV
At IMXO/QMXO, max gain (corrected, REF to VREF)
Level at which IMD3 = 45 dBc
RLOAD = 200 Ω
65
65
3
mV p-p
mV p-p
Ω
RLOAD = 1 kΩ
Mixer Output Impedance
BASEBAND OUTPUT AMPLIFIER
From IAIN to IOPP/IOPN and QAIN to QOPP/QOPN
R
LOAD = 10 kΩ
Gain
30
dB
Bandwidth
−3 dB (see Figure 22)
(VIOPP – VIOPN
(VIOPP + VIOPN)/2 − VVCMO
0 MHz to 50 MHz
65
50
5
+1.8
−49
−67
+2
MHz
+200 mV
Output DC Offset (Differential)
Common-Mode Offset
Group Delay Flatness
Second-Order Intermod. Distortion FIN1 = 5 MHz, FIN2 = 6 MHz, VIN1 = VIN2 = 8 mV p-p
Third-Order Intermod. Distortion
Input Bias Current
)
−200
−40
+40
mV
ns p-p
dBc
dBc
μA
FIN1 = 5 MHz, FIN2 = 6 MHz, VIN1 = VIN2 = 8 mV p-p
Input Impedance
Output Swing Limit (Upper)
Output Swing Limit (Lower)
1||3
MΩ||pF
V
V
VS − 1.3
0.4
Rev. A | Page 3 of 28
AD8347
Parameter
Conditions
Min
0.5
Typ
Max
2.5
Unit
CONTROL INPUT/OUTPUTS
VCMO Input
@ VS = 2.7 V
@ VS = 5 V
VGIN
IOFS, QOFS
RLOAD = 10 kΩ
1
1
<1
10
1.00
V
V
μA
μA
V
Gain Control Input Bias Current
Offset Input Overriding Current
VREF Output
0.95
1.05
RESPONSE FROM RF INPUT TO FINAL
BB AMP
IMXO and QMXO connected directly to IAIN and QAIN,
respectively
Gain @ VVGIN = 0.2 V
Gain @ VVGIN = 1.2 V
Gain Slope
65.5
−3
−96.5
88
69.5
+0.5
−89
94
72.5
+4
−82.5 dB/V
dB
dB
Gain Intercept
Linear extrapolation back to theoretical value at VGIN = 0
(See Figure 30 through Figure 33 for more detail)
Measuring LOIP LOIN, ac-coupled to ground with 100 pF.
Measuring through evaluation board balun with termination
RFIP input pin
101
dB
LO/RF INPUT
LOIP Input Return Loss
−4
−9.5
−10
dB
dB
dB
RFIP Input Return Loss
ENABLE
Power-Up Control
Power-Up Control
Power-Up Time
Low = standby
High = enabled
Time for final BB amps to be within 90% of final amplitude
0
0.5
+VS
V
V
+VS − 1
@ VS = 5 V
@ VS = 2.7 V
20
10
μs
μs
Power-Down Time
Time for supply current to be <4 mA
@ VS = 5 V
30
μs
@ VS = 2.7 V
1.5
ms
POWER SUPPLIES
Voltage
Current (Enabled)
Current (Standby)
Current (Standby)
VPS1, VPS2, VPS3
2.7
48
5.5
80
V
@ 5 V
@ 5 V
@ 3.3 V
64
400
80
mA
μA
μA
Rev. A | Page 4 of 28
AD8347
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
Supply Voltage VPS1, VPS2, VPS3
LO and RF Input Power
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
5.5 V
10 dBm
500 mW
68°C/W
150°C
−40°C to +85°C
−65°C to +150°C
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 28
AD8347
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
LOIN
VPS1
IOPN
IOPP
VCMO
IAIN
28 LOIP
27 COM1
26 QOPN
2
3
4
25
24
23
22
21
20
19
18
17
16
15
QOPP
QAIN
COM3
QMXO
VPS3
VDT1
VAGC
VDT2
5
6
AD8347
TOP VIEW
(Not to Scale)
7
COM3
IMXO
COM2
RFIN
RFIP
8
9
10
11
12
13
14
VPS2
IOFS
VREF
VGIN
QOFS
ENBL
Figure 2. 28-Lead TSSOP Pin Configuration
Table 3. Pin Function Descriptions
Equiv.
Circuit Description
Pin No. Mnemonic
1, 28
LOIN, LOIP
A
LO Input. For optimum performance, these inputs are differentially driven. Typical input drive level is
equal to −8 dBm. To improve the match to a 50 Ω source, connect a 200 Ω shunt resistor between LOIP
and LOIN. A single-ended drive is possible, but slightly increases LO leakage.
2
VPS1
Positive Supply for LO Section. Decouple VPS1 with 0.1 μF and 100 pF capacitors.
3, 4
IOPN, IOPP
B
C
I-Channel Differential Baseband Output. Typical output swing is equal to 760 mV p-p differential in
AGC mode. The common-mode level on these pins is programmed by the voltage on VCMO.
Baseband Amplifier Common-Mode Voltage. The voltage applied to this pin sets the output common-
mode level of the baseband amplifiers. This pin can either be connected to VREF (Pin 14) or to a
reference voltage from another device (typically an ADC).
I-Channel Baseband Amplifier Input. This pin, which has a high input impedance, should be biased to
VREF (approximately 1 V). If IAIN is connected directly to IMXO, biasing is provided by IMXO. If an ac-
coupled filter is placed between IMXO and IAIN, this pin can be biased from VREF through a 1 kΩ
resistor. The gain from IAIN to the differential outputs IOPN/IOPP is 30 dB.
5
6
VCMO
IAIN
D
7, 23
8, 22
COM3
IMXO, QMXO
Ground for Biasing and Baseband Sections.
B
I-Channel and Q-Channel Baseband Mixer/VGA Outputs. Low impedance outputs with bias levels equal to
VREF. IMXO and QMXO are typically connected to IAIN and QAIN, respectively, either directly or through
filters. These outputs have a maximum current limit of about 1.5 mA. This allows for a 600 mV p-p swing into
a 200 Ω load. This corresponds to an input level of −40 dBm @ a maximum gain of 39.5 dB. At lower output
levels, IMXO and QMXO can drive a lower load resistance, subject to the same current limit.
9
COM2
RF Section Ground.
10, 11
RFIN, RFIP
E
RF Input. RFIN must be ac-coupled to ground. The RF input signal should be ac-coupled into RFIP. For
a broadband 50 Ω input impedance, connect a 200 Ω resistor from the signal side of the RFIP coupling
capacitor to ground. Note that RFIN and RFIP are not interchangeable differential inputs. RFIN is the
ground reference for the input system.
12
VPS2
Positive Supply for RF Section. Decouple VPS2 with 0.1 μF and 100 pF capacitors.
13, 16
IOFS, QOFS
F
I-Channel and Q-Channel Offset Nulling Inputs. To null the dc offset on the I-channel and Q-channel
mixer outputs (IMXO, QMXO), connect a 0.1 μF capacitor from these pins to ground. Alternately, a
forced voltage of approximately 1 V on these pins disables the offset compensation circuit.
14
VREF
G
Reference Voltage Output. This output voltage (1 V) is the main bias level for the device and can be
used to externally bias the inputs and outputs of the baseband amplifiers. The VREF pin should be
decoupled with a 0.1 ꢀF capacitor to ground.
15
17
ENBL
VGIN
H
C
Chip Enable Input. Active high.
Gain Control Input. The voltage on this pin controls the gain on the RF and baseband VGAs. The gain
control is applied in parallel to all VGAs. The gain control voltage range is from 0.2 V to 1.2 V and
corresponds to a gain range from +39.5 dB to −30 dB. This is the gain to the output of the baseband
VGAs (that is, QMXO and IMXO). There is an additional 30 dB of gain in the baseband amplifiers. Note
that the gain control function has a negative sense (that is, increasing control voltage decreases gain).
In AGC mode, connect this pin directly to VAGC.
Rev. A | Page 6 of 28
AD8347
Equiv.
Circuit Description
Pin No. Mnemonic
18, 20
VDT2, VDT1
D
Detector Inputs. These pins are the inputs to the on-board detector. VDT2 and VDT1, which have high
input impedances, are normally connected to IMXO and QMXO, respectively.
19
VAGC
I
AGC Output. This pin provides the output voltage from the on-board detector. In AGC mode, connect
this pin directly to VGIN.
21
24
VPS3
QAIN
Positive Supply for Biasing and Baseband Sections. Decouple VPS3 with 0.1 μF and 100 pF capacitors.
D
B
Q-Channel Baseband Amplifier Input. Bias this high input impedance pin to VREF (approximately 1 V).
If QAIN is directly connected to QMXO, biasing is provided by QMXO. If an ac-coupled filter is placed
between QMXO and QAIN, this pin can be biased from VREF through a 1 kΩ resistor. The gain from
QAIN to the QOPN/QOPP differential outputs is 30 dB.
Q-Channel Differential Baseband Output. Typical output swing is equal to 760 mV p-p differential. The
common-mode level on these pins is programmed by the voltage on VCMO.
25, 26
27
QOPP, QOPN
COM1
LO Section Ground.
VPS1
2
VPS2
12
VPS3
21
VREF
14
IMXO IOFS
IAIN
6
IOPP IOPN
8
13
4
3
AD8347
VREF
BIAS
CELL
ENBL 15
VREF
VCMO
5
VCMO
10
RFIN
LOIN
LOIP
1
PHASE
SPLITTER
1
PHASE
SPLITTER
2
11
RFIP
28
7
9
COM3
COM2
COM3
COM1
VCMO
GAIN
CONTROL
INTERFACE
17
23
27
VGIN
DET 1
20
DET 2
VREF
26
19
18
22
16
24
25
VDT1 VAGC VDT2
QMXO QOFS
QAIN
QOPP QOPN
Figure 3. Block Diagram
Rev. A | Page 7 of 28
AD8347
TYPICAL PERFORMANCE CHARACTERISTICS
RF AMP AND DEMODULATOR
3.0
2.5
2.0
1.5
1.0
0.5
0
45
40
35
30
25
20
14
12
10
8
T
= –40°C
A
T
= +85°C
A
T
= +25°C
V
V
= 2.7V, T = +25°C
A
A
6
4
S
S
15
10
V
= 2.7V, T = –40°C
A
S
= 5V, T = +25°C
A
2
0
5
0
–2
–5
T
= –40°C
T
= +25°C
A
A
V
= 5V, T = –40°C
A
–10
–15
–20
S
–4
V
S
= 5V, T = +85°C
A
S
–6
T
A
= +85°C
–8
–25
–30
–35
–0.5
–10
–12
V
= 2.7V, T = +85°C
A
–1.0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
RF FREQUENCY (MHz)
V
(V)
VGIN
Figure 4. Gain and Linearity Error vs. VVGIN
,
Figure 7. Gain vs. FLO, VVGIN = 0.7 V, FBB = 1 MHz
VS = 5 V, FLO = 1900 MHz, FBB = 1 MHz
45
40
35
30
25
20
–27
–28
14
12
10
8
T
= –40°C
A
V
= 5V, T = +25°C
A
S
V
= 2.7V, T = –40°C
A
S
V
= 2.7V, T = +25°C
A
S
–29
–30
T
= +25°C
A
T
= +85°C
= –40°C
A
6
4
15
10
–31
–32
–33
T
A
5
0
2
0
V
= 5V, T = –40°C
A
S
–5
V
= 5V, T = +85°C
A
–2
–4
–6
–8
–10
S
–10
–15
–20
–34
–35
–36
V = 2.7V, T = +85°C
S A
T
= +25°C
A
–25
–30
–35
T
= +85°C
0.4
A
–
37
0.2
0.3
0.5
0.6
0.7
0.8
(V)
0.9
1.0
1.1
1.2
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
RF FREQUENCY (MHz)
V
VGIN
Figure 8. Gain vs. FLO, VVGIN = 1.2 V, FBB = 1 MHz
Figure 5. Gain and Linearity Error vs. VVGIN
,
VS = 2.7 V, FLO = 1900 MHz, FBB = 1 MHz
42
40
V
= 2.7V, T = +25°C
A
S
41
40
39
38
37
36
V
= 2.7V, T = –40°C
A
S
V
= 5V, T = +25°C
A
S
V
= 2.7V, T = +25°C
A
S
39
38
37
V
= 5V, T = –40°C
A
S
V
= 2.7V, T = –40°C
A
S
V
= 5V, T = +25°C
A
S
V
= 2.7V, T = +85°C
A
S
36
35
34
35
34
33
32
31
30
V
= 2.7V, T = +85°C
A
S
V
= 5V, T = –40°C
A
S
V
= 5V, T = +85°C
A
S
V
= 5V, T = +85°C
A
S
33
32
31
30
1
10
BASEBAND FREQUENCY (MHz)
100
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
RF FREQUENCY (MHz)
Figure 6. Gain vs. FLO, VVGIN = 0.2 V, FBB = 1 MHz
Figure 9. Gain vs. FBB, VVGIN = 0.2 V, FLO = 1900 MHz
Rev. A | Page 8 of 28
AD8347
10
9
15
14
13
12
11
V
= 2.7V, T = +85°C
A
S
V
= 5V, T = +85°C
A
S
8
V
= 5V, T = +25°C
A
S
7
V
= 2.7V, T = +85°C
A
S
6
5
V
= 5V, T = +85°C
A
S
4
V
= 2.7V, T = –40°C
A
V
= 2.7V, T = +25°C
A
S
S
3
V
= 5V, T = –40°C
A
10
9
S
2
V
= 2.7V, T = +25°C
A
1
S
V
= 5V, T = +25°C
A
0
S
8
–1
–2
–3
–4
–5
V
= 2.7V, T = –40°C
A
S
7
V
= 5V, T = –40°C
A
S
6
5
1
10
BASEBAND FREQUENCY (MHz)
100
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
RF FREQUENCY (MHz)
Figure 10. Gain vs. FBB, VVGIN = 0.7 V, FLO = 1900 MHz
Figure 13. IIP3 vs. FLO, VVGIN = 1.2 V, FBB = 1 MHz
–25
–26
–27
–28
–29
–30
–31
–32
–33
–34
–35
–10
V
= 2.7V, T = +85°C
A
S
–12
–14
–16
–18
–20
V
= 5V, T = +25°C
A
S
V
= 2.7V, T = –40°C
V = 2.7V, T = +25°C
S A
S
A
V
= 2.7V, T = +25°C
A
S
V
= 5V, T = +25°C
A
S
V
= 5V, T = –40°C
A
S
–22
–24
V
= 2.7V, T = –40°C
A
S
V
= 5V, T = –40°C
A
S
V
= 2.7V, T = +85°C
A
S
V
= 5V, T = +85°C
A
S
–26
–28
–30
V
= 5V, T = +85°C
A
S
1
10
BASEBAND FREQUENCY (MHz)
100
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
RF FREQUENCY (MHz)
Figure 11. Gain vs. FBB, VVGIN = 1.2 V, FLO = 1900 MHz
Figure 14. IIP3 vs. FLO, VVGIN = 0.2 V, FBB = 1 MHz
15
14
0
V
= 5V, T = –40°C
A
S
V
= 2.7V, T = –40°C
A
–5
–10
–15
S
V
= 2.7V, T = +85°C
A
S
V
= 5V, T = +85°C
A
V
= 5V, T = +85°C
A
S
S
V
= 2.7V, T = +85°C
A
S
13
12
11
–20
–25
–30
V
= 5V, T = –40°C
A
S
V
= 5V, T = +25°C
A
S
V
= 2.7V, T = +25°C
A
S
V
= 2.7V, T = –40°C
A
S
V
= 2.7V, T = +25°C
A
S
V
= 5V, T = +25°C
A
S
10
–35
0.2
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95100
BASEBAND FREQUENCY (MHz)
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
V
(V)
VGIN
Figure 12. Input 1 dB Compression Point (OP1 dB) vs. VVGIN
,
Figure 15. IIP3 vs. FBB, VVGIN = 1.2 V, FLO = 1900 MHz
FLO = 1900 MHz, FBB = 1 MHz
Rev. A | Page 9 of 28
AD8347
–10
–12
–14
15
10
70
60
50
40
30
20
10
0
V
= 5V, T = +85°C
A
S
5
–16
–18
–20
–22
V
= 2.7V, T = +85°C
A
S
0
–5
–10
V
= 5V, T = +25°C
A
S
V
= 5V
–24
–26
–28
–30
V
= 5V, T = –40°C
A
S
S
–15
–20
–25
–30
V
= 2.7V
= 5V
V
= 2.7V, T = +25°C
S
S
A
V
T
= 2.7V,
= –40°C
S
A
–32
–34
V
= 2.7V
0.5
S
V
S
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95100
BASEBAND FREQUENCY (MHz)
0.2
0.3
0.4
0.6
0.7
0.8
0.9
1.0
V
(V)
VGIN
Figure 19. Noise Figure and IIP3 vs. VVGIN, Temperature = 25°C,
FLO = 1900 MHz, FBB = 1 MHz
Figure 16. IIP3 vs. FBB, VVGIN = 0.2 V, FLO = 1900 MHz
2.5
2.0
1.5
1.0
50
45
40
35
30
25
20
0.5
LO FREQUENCY = 2700MHz
0
–0.5
–1.0
LO FREQUENCY = 800MHz
–1.5
LO FREQUENCY = 1900MHz
–2.0
–2.5
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
RF FREQUENCY (MHz)
–20 –18 –16 –14 –12 –10
–8
–6
–4
–2
0
LO INPUT LEVEL (dBm)
Figure 20. Quadrature Error vs. LO Power Level, Temperature = 25°C,
Figure 17. IIP2 vs. FLO, VVGIN = 1.2 V, Baseband Tone1 = 5 MHz, −10 dBm,
Baseband Tone2 = 6 MHz, −10 dBm, Temperature = 25°C, VS = 5 V
V
VGIN = 0.2 V, VS = 5 V
14.0
13.5
13.0
12.5
12.0
13.0
12.5
12.0
11.5
11.0
2700MHz
11.5
11.0
10.5
10.0
9.5
1900MHz
800MHz
V
= 5V
S
V
= 2.7V
S
10.5
10.0
9.0
–20 –18 –16 –14 –12 –10
–8
–6
–4
–2
0
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
LO INPUT LEVEL (dBm)
LO FREQUENCY (MHz)
Figure 21. Noise Figure vs. LO Input Level, Temperature = 25°C,
VGIN = 0.2 V, VS = 5 V
Figure 18. Noise Figure vs. LO Frequency (FLO), Temperature = 25°C,
VVGIN = 0.2 V, FBB = 1 MHz
V
Rev. A | Page 10 of 28
AD8347
BASEBAND OUTPUT AMPLIFIERS
34
20
T
= –40°C, V = 5V
S
T
= –40°C, V = 5V
S
A
A
T
= –40°C, V = 2.7V
S
A
15
10
5
32
30
28
T
= +25°C, V = 5V
S
A
T
= +85°C, V = 5V
A
S
T
= +25°C, V = 5V
S
A
T = +25°C, V = 2.7V
A S
T
= +85°C, V = 2.7V
A
S
T
= +85°C, V = 2.7V
S
0
A
T
= –40°C, V = 2.7V
S
A
26
24
22
20
–5
–10
–15
–20
–25
–30
T
= +25°C, V = 2.7V
S
A
T
= +85°C, V = 5V
A
S
18
16
1
10
100
1
10
100
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
Figure 24. OIP3 vs. FBB, VVCMO = 1 V
Figure 22. Gain vs. FBB, VVCMO = 1 V
8
6
5
0
T
= –40°C, V = 5V
S
T
= +85°C, V = 5V
S
A
A
V
= 2.7V, MEAN +
σ
S
V
= 2.7V, MEAN
S
T
= +25°C, V = 5V
S
A
4
V
= 5V, MEAN
–5
S
T
= –40°C, V = 2.7V
S
A
V
= 5V, MEAN + σ
S
2
T
= +25°C, V = 2.7V
S
A
–10
0
T
= +85°C, V = 2.7V
S
A
–15
–20
–2
V
= 2.7V, MEAN – σ
S
–4
–6
V
= 5V, MEAN – σ
S
–25
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1
10
100
V
(V)
BASEBAND FREQUENCY (MHz)
VCMO
Figure 25. Common-Mode Output Offset Voltage vs. VVCMO
,
Figure 23. OP1 vs. FBB, VVCMO = 1 V
Temperature = 25°C (σ = 1 Standard Deviation)
Rev. A | Page 11 of 28
AD8347
RF AMP/DEMOD AND BASEBAND OUTPUT AMPLIFIERS
1.0
75
T
T
T
T
= –40°C, V = 2.7V
S
A
A
A
A
0.8
0.6
0.4
0.2
65
= –40°C, V = 5V
S
= +25°C, V = 2.7V
S
= +25°C, V = 5V
S
55
45
35
25
15
T
V
= +85°C,
= 2.7V
A
S
T
= +85°C
A
T
A
= +25°C
0
–0.2
–0.4
–0.6
T
= +85°C, V = 5V
S
A
T
= –40°C
A
5
–0.8
–1.0
–5
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0
5
10
15
20
25
30
35
40
V
(V)
VGIN
BASEBAND FREQUENCY (MHz)
Figure 29. I/Q Amplitude Imbalance vs. FBB, Temperature = 25°C, VS = 5 V
Figure 26. Voltage Gain vs. VVGIN, FLO = 1900 MHz, FBB = 1 MHz
0
2.5
2.0
1.5
1.0
0.5
–
2
4
–
T
= +25°C, V = 5V
S
A
–
6
8
0
–0.5
–1.0
–1.5
–2.0
–2.5
RF WITH TERMINATION
–
T
= +85°C, V = 5V
S
A
–10
–12
T
= –40°C, V = 5V
S
A
RF WITHOUT TERMINATION
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
RF FREQUENCY (MHz)
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
RF FREQUENCY (MHz)
Figure 27. Quadrature Phase Error vs. FLO, VVGIN = 0.7 V, VS = 5 V
Figure 30. Return Loss of RFIP vs. FRF, VVGIN = 0.7 V, VS = 5 V
2.5
2.0
1.5
1.0
0.5
WITH TERMINATION
2.7GHz
0
–0.5
–1.0
–1.5
T
= +85°C
A
800MHz
T
= +25°C
A
T
= –40°C
A
2.7GHz
800MHz
WITHOUT TERMINATION
–2.0
–2.5
0
5
10
15
20
25
30
35
40
BASEBAND FREQUENCY (MHz)
Figure 28. Quadrature Phase Error vs. FBB, VVGIN = 0.7 V, VS = 5 V
Figure 31. S11 of RFIN vs. FRF, VVGIN = 0.7 V, VS = 5 V
Rev. A | Page 12 of 28
AD8347
0
–2
–4
30
25
20
1.20
1.00
0.80
T
= –40°C
A
T
= +85°C
A
LO PORT WITHOUT TERMINATION
T
= +25°C
A
T
= +85°C
A
–6
–8
T
= +25°C
A
15
10
5
0.60
0.40
0.20
T
= –40°C
A
–10
–12
–14
LO PORT WITH TERMINATION
0
0
10
800 1000 1200 1400 1600 1800 2000 2200 2400 2600
RF FREQUENCY (MHz)
–70
–60
–50
–40
–30
–20
–10
0
RF INPUT POWER (dBm)
Figure 32. Return Loss of LOIP vs. FLO, VVGIN = 0.7 V, VP = 5 V
Figure 34. AGC Voltage and Mixer Output Level vs. RF Input Power,
FLO = 1900 MHz, FBB = 1 MHz, VS = 5 V
85
80
75
WITH TERMINATION
800MHz
V
= 5V
P
70
65
60
55
V
= 5.5V
P
2.7GHz
2.7GHz
V
= 3V
P
800MHz
V
= 2.7V
P
50
45
WITHOUT TERMINATION
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 33. S11 of LOIN vs. FLO, VVGIN = 0.7 V, VS = 5 V
Figure 35. Supply Current vs. Temperature, VVGIN = 0.7 V, VVCMO = 1 V
Rev. A | Page 13 of 28
AD8347
EQUIVALENT CIRCUITS
VPS1
VPS3
LOIN
IAIN
QAIN
PHASE
SPLITTER
CONTINUES
LOIP
COM3
COM1
Figure 36. Circuit A
Figure 39. Circuit D
VPS3
VPS2
IOPP, IOPN,
QOPP, QOPN,
IMXO, QMXO
RFIP
RFIN
COM3
COM2
Figure 37. Circuit B
Figure 40. Circuit E
VPS3
VPS3
IOFS
QOFS
VCMO
CURRENT MIRROR
CURRENT MIRROR
COM3
COM3
Figure 41. Circuit F
Figure 38. Circuit C
Rev. A | Page 14 of 28
AD8347
VPS3
VREF
VPS3
VAGC
COM3
COM3
Figure 42. Circuit G
Figure 44. Circuit I
VPS3
ENBL
COM3
Figure 43. Circuit H
Rev. A | Page 15 of 28
AD8347
THEORY OF OPERATION
VPS1
2
VPS2
12
VPS3
21
VREF
14
IMXO IOFS
IAIN
6
IOPP IOPN
8
13
4
3
AD8347
VREF
BIAS
CELL
15
10
ENBL
RFIN
VCMO
5
VREF
VCMO
1
LOIN
LOIP
PHASE
SPLITTER
1
PHASE
SPLITTER
2
RFIP 11
28
7
9
COM3
COM2
COM3
COM1
VCMO
GAIN
CONTROL
INTERFACE
17
VGIN
23
27
DET 1
20
DET 2
VREF
26
19
18
22
16
24
25
VDT1 VAGC VDT2
QMXO QOFS
QAIN
QOPP QOPN
Figure 45. Block Diagram
The AD8347 is a direct I/Q demodulator usable in digital
wireless communication systems including cellular, PCS, and
digital video receivers. An RF signal in the frequency range of
800 MHz to 2,700 MHz is directly downconverted to the I and
Q components at baseband using a local oscillator (LO) signal
at the same frequency as the RF signal.
differential currents are split and fed to the two Gilbert-cell
mixers through separate cascode stages.
MIXERS
Two double balanced Gilbert-cell mixers, one for each channel,
perform the in-phase (I) and quadrature (Q) down conversion.
Each mixer has four cross-connected transistor pairs that are
terminated in resistive loads and feed the differential baseband
variable gain amplifiers for each channel. The quadrature LO
signals drive the bases of the mixer transistors.
The RF input signal goes through two stages of variable gain
amplifiers before splitting up to reach two Gilbert-cell mixers.
The mixers are driven by a pair of LO signals which are in
quadrature (90 degrees of phase difference). The outputs of the
mixers are applied to baseband I-channel and Q-channel
variable gain amplifiers. The outputs from these baseband
variable gain amplifiers are brought out to pins for external
filtering. The filter outputs are then applied to a pair of on-chip,
fixed gain, baseband amplifiers. These amplifiers gain up the
outputs from the external filters to a level compatible with most
A-to-D converters. A sum of squares detector is available for
use in an automatic gain control (AGC) loop to set the output
level. The RF and baseband amplifiers provide approximately
69.5 dB of gain control range. Additional on-chip circuits allow
the setting of the dc level at the I-channel and Q-channel
baseband outputs, as well as nulling the dc offset at each
channel.
BASEBAND VARIABLE GAIN AMPLIFIERS
The baseband VGAs also use the X-AMP approach with NPN
differential pairs separated by sections of resistive attenuators.
The same interpolator controlling the RF amplifiers controls the
tail currents of the differential pairs. The outputs of these amplifiers
are provided off chip for external filtering. Automatic offset
nulling minimizes the dc offsets at both I- and Q-channels. The
common-mode output voltage is set to the same level as the
reference voltage (1.0 V) generated in the Bias cell, also made
available at the VREF pin (see Figure 45).
OUTPUT AMPLIFIERS
The output amplifiers gain up the signal coming back from each of
the external filters to a level compatible with most high speed A-to-
D converters. These amplifiers are based on an active feedback
design to achieve high gain bandwidth with low distortion.
RF VARIABLE GAIN AMPLIFIERS (VGA)
These amplifiers use the patented X-AMP® approach with NPN
differential pairs separated by sections of resistive attenuators.
The gain control is achieved through a gaussian interpolator
where the control voltage sets the tail currents supplied to the
various differential pairs according to the gain desired. In the
first amplifier, the combined output currents from the
LO AND PHASE SPLITTERS
The incoming LO signal is applied to a polyphase phase splitter
to generate the LO signals for the I-channel and Q-channel
mixers. The polyphase phase splitters are RC networks
connected in a cyclical manner to achieve gain balance and
phase quadrature. The wide operating frequency range of these
phase splitters is achieved by cascading multiple sections of
transconductance cells go through a cascode stage to resistive
loads with inductive peaking. In the second amplifier, the
Rev. A | Page 16 of 28
AD8347
these networks with staggered RC constants. Each branch goes
through a buffer to make up for the loss and high frequency
roll-off. The output from the buffers then goes into another
polyphase phase splitter to enhance the accuracy of phase
quadrature. Each LO signal is buffered again to drive the
mixers.
BIAS
An accurate reference circuit generates the reference currents
used by the different sections. The reference circuit is controlled
by an external power-up (ENBL) logic signal that, when set low,
puts the whole chip into a sleep mode typically requiring less
than 400 μA of supply current. The reference voltage (VREF) of
1.0 V, that serves as the common-mode reference for the
baseband circuits, is made available for external use. The VREF
pin should be decoupled with a 0.1 ꢀF capacitor to ground.
OUTPUT LEVEL DETECTOR
To create an AGC voltage (VAGC), two signals proportional to
the square of each output channel are summed together and
compared to a built-in threshold. The inputs to this rms
detector are referenced to VREF.
Rev. A | Page 17 of 28
AD8347
APPLICATIONS
BASIC CONNECTIONS
RF INPUT AND MATCHING
The basic connections for operating the AD8347 are shown in
Figure 46. The device is powered through three power supply
pins: VPS1, VPS2, and VPS3. These pins supply current to
different parts of the overall circuit. VPS1 and VPS2 power the
local oscillator (LO) and RF sections, respectively, while VPS3
powers the baseband amplifiers. Connect all of these pins to the
same supply voltage; however, separately decouple each pin
using two capacitors. 100 pF and 0.1 μF capacitors are
The RF input signal should be ac-coupled into the RFIP pin and
RFIN should be ac-coupled to ground. To improve broadband
matching to a 50 Ω source, a 200 Ω resistor can be connected
from the signal side of the RFIP coupling capacitor to ground.
LO DRIVE INTERFACE
For optimum performance, the LO inputs, LOIN and LOIP,
should be driven differentially; the M/A-COM balun, ETC1-1-13
is recommended. Unless an ac-coupled transformer is used to
generate the differential LO, the inputs must be ac-coupled, as
shown in Figure 46. To improve broadband matching to a 50 Ω
source, connect a 200 Ω shunt resistor between LOIP and LOIN.
recommended, though values close to these can be used.
Use a supply voltage in the range 2.7 V to 5.5 V. The quiescent
current is 64 mA when operating from a 5 V supply. By pulling
the ENBL pin low, the device goes into its power-down mode.
The power-down current is 400 μA when operating on a 5 V
supply and 80 μA on a 2.7 V supply.
A LO drive level of −8 dBm is recommended. Figure 20 shows
the relationship between LO drive level, LO frequency, and
quadrature error for a typical device.
Like the supply pins, the individual sections of the circuit are
separately grounded. COM1, COM2, and COM3 provide
ground for the LO, RF, and baseband sections, respectively.
Connect all of these pins to the same low impedance ground.
A single-ended drive is also possible as shown in Figure 47, but
this slightly increases LO leakage. Apply the LO signal through
a coupling capacitor to LOIP, and ac-couple LOIN to ground.
Because the inputs are fully differential, the drive orientation
can be reversed. As in the case of the differential drive, a 200 Ω
resistor connected across LOIP and LOIN improves the match
to a 50 Ω source.
+V
S
(2.7V–5.5V)
IOPP
24mV p-p
(AGC MODE)
1V BIAS (VREF)
C9
C10
C6
C5
C7
C8
0.1μF 100pF
0.1μF 100pF 0.1μF 100pF
C16
0.1μF
760mV p-p
DIFFERENTIAL
(AGC MODE)
C13
0.1μF
V
= 1V
CM
VPS3
IOFS IAIN
13
IOPP
VREF
14
IMXO
IOPN
VPS1
15
VPS2
2
12
21
8
6
4
3
AD8347
IOPN
VREF
VREF
BIAS
CELL
ENBL
VCMO
LO INPUT
–8dBm
0.8GHz–2.7GHz
5
C1
100pF
C4
100pF
VCMO
RFIN
RFIP
LOIN
LOIP
10
11
R1
200Ω
3
1
4
1
PHASE
SPLITTER
1
R17
200Ω
PHASE
SPLITTER
2
28
5
C2
100pF
T1
RF INPUT
0.8GHz–2.7GHz
0dBm MAX
C3
100pF
ETC 1-1-13
(M/A-COM)
COM3
7
9
VCMO
COM2
COM3
COM1
(AGC MODE)
VGIN
GAIN
CONTROL
INTERFACE
17
23
27
DET 1
20
DET 2
VREF
QOPN
26
QOPP QOPN
24
25
19
18
22
16
VDT1 VAGC VDT2
QMXO
QOFS
QAIN
C14
0.1μF
760mV p-p
DIFFERENTIAL
(AGC MODE)
C15
0.1μF
24mV p-p
(AGC MODE)
1V BIAS (VREF)
V
= 1V
CM
QOPP
Figure 46. Basic Connections
Rev. A | Page 18 of 28
AD8347
These output stages are not, however, designed to directly drive
50 Ω loads.
100pF
LOIN
LO
200
Ω
AD8347
LOIP
OPERATING THE VGA IN AGC MODE
Although the VGA can be driven by an external source such as
a DAC, the AD8347 has an on-board sum of squares detector to
allow the AD8347 to operate in an automatic leveling mode.
Due to the nature of the detector, an input signal with a higher
peak-to-average ratio causes the AGC loop to settle with a
higher mixer output peak-to-peak voltage. In this data sheet,
peak-to-peak calculations assume a sine wave input when
referencing AGC operation.
100pF
Figure 47. Single-Ended LO Drive
OPERATING THE VGA
A three-stage VGA sets the gain in the RF section. Two of the
three stages come before the mixer while the third amplifies the
mixer output. All three stages are driven in parallel. The gain
range of the first RF VGA and that of the second RF VGA
combined with the mixer are both −13 dB to +10 dB. The gain
range of the baseband VGA is −4 dB to +19.5 dB. Therefore, the
overall gain range from the RF input to the IMXO and QMXO
pins is −30 dB to approximately +39.5 dB.
The connections for operating in this mode are shown in
Figure 46. The two mixer outputs are connected to Detector
Input VDT1 and Detector Input VDT2. The summed detector
output drives an internal integrator which, in turn, delivers a
gain correction voltage to the VAGC pin. A 0.1 μF capacitor
from VAGC to ground sets the dominant pole of the integrator
circuit. VAGC, which should be connected to VGIN, adjusts
gain until an internal threshold is reached. This threshold
corresponds to a level at the IMXO and QMXO pins of approxi-
mately 8.5 mV rms. This level changes slightly as a function of
RF input power (see Figure 34). For a CW (sine wave) input,
this corresponds to approximately 24 mV p-p. If this signal is
applied directly to the subsequent baseband amplifier stage,
the final baseband output is 760 mV p-p differential. See the
Baseband Amplifiers section.
The gain of the VGA is set by the voltage on the VGIN pin,
which is a high impedance input. The gain control function
(which is linear-in-dB) and linearity are shown in Figure 4 and
Figure 5 at 1.9 GHz. Note that the sense of the gain control
voltage is negative because as the gain control voltage ranges
from 0.2 V to 1.2 V, the gain decreases from +39.5 dB to −30 dB.
MIXER OUTPUT LEVEL AND DRIVE CAPABILITY
I- and Q-channel baseband outputs, IMXO and QMXO, are
low impedance outputs (ROUT @ 3 Ω) with bias levels equal to
V
VREF, the voltage on Pin 14. The achievable output levels on
If the VGA gain is set from an external source, VDT1 and
VDT2 (the on-board detector inputs) are not used and are tied
to VREF.
IMXO/QMXO are limited by their current drive capability of
1.5 mA maximum. This allows for a 600 mV p-p swing into a
200 Ω load. At lower output levels, IMXO and QMXO can drive
smaller load resistances, subject to the same current limit.
Rev. A | Page 19 of 28
AD8347
R19
1k
Ω
+V +5V
S
R20
4kΩ
2.5V
IOPP
C9
0.1
C10
F 100pF
C6
0.1
C5
C7
C8
120mV p-p
1V BIAS
μ
μ
F 100pF 0.1
μF 100pF
C16
0.1μF
3.8V p-p
DIFFERENTIAL
C13
0.1
μ
F
V
= 2.5V
CM
VPS3
VREF
14
IMXO
IOFS IAIN
VREF
IOPP
IOPN
VPS1
2
VPS2
12
13
6
21
8
4
3
AD8347
IOPN
VREF
BIAS
CELL
15
ENBL
VCMO
LO INPUT
–8dBm
0.8GHz–2.7GHz
5
C1
100pF
C4
100pF
VCMO
RFIN
10
LOIN
LOIP
R1
200
3
1
4
1
Ω
PHASE
SPLITTER
1
R17
200
PHASE
SPLITTER
2
RFIP
11
Ω
28
5
C2
100pF
T1
RF
INPUT
C3
100pF
ETC 1-1-13
(M/A-COM)
COM3
7
9
VCMO
COM2
COM3
COM1
VGIN
17
GAIN
CONTROL
INTERFACE
23
27
DET 1
20
DET 2
VREF
QOPN
26
QOPP QOPN
19
18
22
16
24
25
VDT1 VAGC VDT2
QMXO
QOFS
C14
QAIN
0.1μF
3.8V p-p
DIFFERENTIAL
120mV p-p
1V BIAS
V
= 2.5V
R21
4kΩ
CM
R22
1kΩ
QOPP
Figure 48. Adjusting AGC Level to Increase Baseband Amplifier Output Swing
IOPP, QOPN, and QOPP) deliver a differential voltage of
approximately 760 mV p-p (380 mV p-p on each side).
CHANGING THE AGC SETPOINT
The AGC circuit can be easily set up to level at voltages higher
than the nominal 24 mV p-p, as shown in Figure 48. The
voltages on Pin IMXO and Pin QMXO are attenuated before
being applied to the detector inputs. In the example shown, an
attenuation factor of 0.2 (−14 dB) between IMXO and QMXO
and the detector inputs causes the VGA to level at approximately
120 mV p-p (note that the resistor divider network must be
referenced to VVREF). This results in a peak-to-peak output
swing at the baseband amplifier outputs of 3.8 V differential,
that is, 1.6 V to 3.4 V on each side. Note that VVCMO has been
increased to 2.5 V to avoid signal clipping at the baseband
outputs. Due to the attenuation between the mixer output and
the detector input, the variation in the settled mixer output level
vs. RF input power will be greater than the variation shown in
Figure 34. The variation will be greater by a factor equal to the
inverse of the attenuation factor.
The single-ended input signal to the baseband amplifiers is
applied at IAIN and QAIN, the high impedance inputs. As
shown in Figure 46, the baseband amplifier operates internally
as a differential amplifier, with the second input driven by VVREF
.
Therefore, bias the input signal to the baseband amplifier at VVREF
.
The output common-mode level of the baseband amplifiers is
set by the voltage on Pin 5, VCMO. Connect this pin to VREF
(Pin 14) or to an external reference voltage from a device such
as an analog-to-digital converter (ADC). VVCMO has a nominal
range from 0.5 V to 2.5 V. However, since the baseband amplifiers
can only swing down to 0.4 V, higher values of VVCMO are gener-
ally required to avoid low end signal clipping. Alternatively, the
positive swing at each output is limited to 1.3 V below the
supply voltage; therefore, the maximum p-p swing is given by
2 × (VPS − 1.3 − 0.4) V differentially.
BASEBAND AMPLIFIERS
For example, for the baseband output amplifier to deliver an
output swing of 2 V p-p (1 V p-p on each side), VVCMO must be
in a range from 0.9 V to 2.5 V.
The final baseband amplifier stage takes the signals from IMXO
and QMXO and amplifies them by 30 dB, or a factor of 31.6.
This results in a maximum system gain of 69.5 dB. When the
VGA is in AGC mode, the baseband I and Q outputs (IOPN,
Rev. A | Page 20 of 28
AD8347
The differential output offset voltages of the baseband amplifiers
are typically 50 mV. This offset voltage results from both input
and output effects.
FILTER DESIGN CONSIDERATIONS
Baseband low-pass or band-pass filtering can be conveniently
performed between the mixer outputs (IMXO and QMXO) and the
input to the baseband amplifiers. Because the output impedance of
the mixer is low (approximately 3 Ω) and the input impedance of
the baseband amplifier is high, it is not practical to design a
filter that is reactively matched to these impedances. An LC
filter can be matched by placing a series resistor at the mixer
output and a shunt resistor (terminated to VVREF) at the input to
the baseband amplifier.
The overall signal-to-noise ratio can be improved by increasing
the VGA gain by driving it with an external voltage or by changing
the setpoint of the AGC circuit. See the Changing the AGC
Setpoint section.
DRIVING CAPACITIVE LOADS
In applications where the baseband amplifiers are driving
unbalanced capacitive loads, place some series resistance between
the amplifier and the capacitive load. For example, for a 10 pF load,
use four 200 Ω series resistors, one in each baseband output.
Because the mixer output drive level is limited to a maximum
current of 1.5 mA, the characteristic impedance of the filter
should be greater than 50 Ω, especially to achieve larger signal
swings.
EXTERNAL BASEBAND AMPLIFICATION
Reduce baseband output offset voltage and noise by bypassing the
internal baseband amplifiers and amplifying the mixer output
signal using a high quality differential amplifier. In the example
shown in Figure 49, two AD8132 differential amplifiers are used
to gain up the mixer output signals by 20 dB. In this example, the
setpoint of the AGC circuit was increased to give an approximate
72 mV p-p input to the external amplifiers. This resulted in final
baseband output signals of 720 mV p-p.
Figure 50 shows the schematic for a 100 Ω, fourth-order elliptic
low-pass filter with a 3 dB cutoff frequency of 20 MHz. Source
and load impedances of approximately 100 Ω ensure that the
filter sees a matched source and load. This also ensures that the
mixer output is driving an overall load of 200 Ω. Note that the
shunt termination resistor is tied to VREF and not to ground.
The frequency response and group delay of this filter are shown
in Figure 51 and Figure 52.
C1
4.7pF
C3
8.2pF
The closed-loop bandwidth of the amplifiers in Figure 49 is equal
to approximately 20 MHz. Higher bandwidths are achievable, but
at the cost of lower closed-loop gain. In Figure 49, the output
common-mode levels at Pin 2 (VOCM pin) of the AD8132s are set
by the AD8347’s VREF (approximately 1 V). The output common-
mode levels can also be externally set, using, for example, the
reference voltage from an ADC.
L
L
3
1.2
RS
95.3
R3
R4
2Ω
1
Ω
2Ω
0.68
μH
μH
C2
C4
RL
150pF
82pF 100Ω
C16
0.1μF
+5V
IMXO
VREF
IAIN VDT1
R19A
10μF
0.1μF
(SEE
TEXT)
4.99kΩ
AD8347
AD8347
R17A
499
72mV p-p
Ω
3
8
IMXO
Figure 50. Typical Baseband Low-Pass Filter
R22
20k
5
720mV p-p
Ω
AD8132
DIFFERENTIAL
VDT1
VREF
2
1
R18A
499
4
R23
V
= 1V
CM
Ω
10k
Ω
6
0
4.99k
R20A
Ω
0.1
μ
F
10
μ
F
F
–10
–20
–30
–40
C16
0.1μF
–5V
+5V
R24
10k
4.99k
R19B
Ω
0.1μF
10
μ
Ω
VDT2
R17B
499
R25
Ω
20kΩ
3
QMXO
8
2
72mV p-p
720mV p-p
DIFFERENTIAL
5
–50
–60
–70
R18B
499
AD8132
Ω
4
V
= 1V
CM
1
6
4.99k
R20B
Ω
0.1
μF
10μF
–80
1
10
100
–5V
FREQUENCY (MHz)
Figure 49. External Baseband Amplification Example
Figure 51. Frequency Response of 20 MHz Baseband Low-Pass Filter
Rev. A | Page 21 of 28
AD8347
50
DC OFFSET COMPENSATION
45
Feedthrough of the LO signal to the RF input port results in
self-mixing of the LO signal. This produces a dc component at
the mixer output that is frequency dependent.
40
35
30
25
20
The AD8347 includes an internal circuit that actively nulls any
dc offsets that appear at the mixer output. The dc bias level of
the mixer output (which should ideally equal VVREF, the bias
level for the baseband sections of the chip) is continually com-
pared to VVREF. Any differences between the mixer output level
and VVREF forces a compensating voltage on to the mixer output.
The time constant of this correction loop is set by the capacitors
that are connected to Pin IOFS and Pin QOFS (each output can
be separately compensated). For normal operation, 0.1 μF
capacitors are recommended. The corner frequency of the
compensation loop is given approximately by
15
10
5
0
1
10
100
FREQUENCY (MHz)
Figure 52. Group Delay of 20 MHz Baseband Low-Pass Filter
If the VGA is operating in AGC mode, the detector inputs
(VDT1 and VDT2) can be tied either to the inputs or outputs of
the filter. Connecting the detector inputs to the inputs of the
filter (IMXO and QMXO) causes the VGA leveling point to be
determined by the composite of the wanted signal and any
unfiltered components, such as blockers or signal harmonics.
Alternatively, connecting VDT1 and VDT2 to the outputs of the
filters ensures that the leveling point of the AGC circuit is based
upon the amplitude of the filtered output only. The latter option
is more desirable as it results in a more constant baseband
output. However, when using this method, set the leveling point
of the AGC so that the out-of-band blockers do not overdrive
the mixer output.
40
f3dB
=
(
COFS in μF
)
COFS
The corner frequency must be set to a frequency that is much
lower than the symbol rate of the demodulated data. This
prevents the compensation loop from falsely interpreting the
data stream as a changing offset voltage.
To disable the offset compensation circuits, tie IOFS and QOFS
to VREF.
Rev. A | Page 22 of 28
AD8347
EVALUATION BOARD
Figure 53 shows the schematic of the AD8347 evaluation board. Note that uninstalled components are indicated with the open
designation. The board is powered by a single supply in the range of 2.7 V to 5.5 V. Table 4 details the various configuration options of
the evaluation board.
TP1
J3
LO
+V
S
4
3
5
1
R35
0Ω
T1
ETC 1-1-13
R37
0Ω
J6
IOPN
J1
C2
100pF
C3
QOPN
100pF
R17
R36
200Ω
0Ω
J5
IOPP
R38
0Ω
C6
C5
C1
0.1μF
AD8347
0.1μF 100pF
J2
QOPP
1
2
LOIP
LOIN 28
J11
VCMO
VPS1
IOPN
IOPP
VCMO
IAIN
COM1 27
QOPN 26
QOPP 25
3
L6
L5
(OPEN)
L4
(OPEN)
(OPEN)
R33
0Ω
4
R34
(OPEN)
5
24
23
22
21
20
19
18
R6
QAIN
COM3
QMXO
VPS3
VDT1
VAGC
VDT2
J8
QMXO
0Ω
L3
(OPEN)
L2
(OPEN)
L1
(OPEN)
TP5
6
LK4
R40
C30
C26
C31
(OPEN) (OPEN) (OPEN)
R8
(OPEN)
LK5
R39
7
COM3
IMXO
COM2
RFIN
RFIP
+V
S
J7
IMXO
C28
C25
C29
C27
(OPEN)
8
C9
0.1μF
C10
100pF
LK6
(OPEN)
(OPEN) (OPEN)
C18
(OPEN)
C4
(OPEN)
C19
(OPEN)
(OPEN)
TP4
9
J9
VAGC
10
11
12
13
14
C11
100pF
C21
(OPEN)
C15
0.1μF
C22
(OPEN)
C20
(OPEN)
C17
LK3
(OPEN)
(OPEN)
R18
200Ω
J4
C12
100pF
VGIN 17
VPS2
IOFS
VREF
LK1
C7
RFIP
J10
TP6
16
QOFS
+V
S
VGIN
V
C8
100pF
POS
15
ENBL
A
0.1μF
TP2
TP3
C14
0.1μF
SW1
LK2
C13
0.1μF
B
C16
0.1μF
Figure 53. Evaluation Board Schematic
Rev. A | Page 23 of 28
AD8347
Figure 54. Silkscreen of Component Side
Figure 55. Layout of Component Side
Figure 56. Layout of Circuit Side
Rev. A | Page 24 of 28
AD8347
Table 4. Evaluation Board Configuration Options
Component
TP1, TP4, TP5
TP2, TP6
TP3
Function
Default Condition
Not applicable
Not applicable
Not applicable
LK1 installed
Power Supply and Ground Vector Pins.
IOFS and QOFS Probe Points.
VREF Probe Point.
LK1, J11
Baseband Amplifier Output Bias. Installing this link connects VREF to VCMO setting
the bias level on the baseband amplifiers to VREF, which is equal to approximately
1 V. Alternatively, the bias level of the baseband amplifiers can be set by applying
an external voltage to SMA Connector J11.
LK2, LK6, LK3, J9,
J10
AGC Mode. Installing LK2 and LK6 connects IMXO and QMXO, the mixer outputs, to
VDT2 and VDT1, the detector inputs. By installing LK3, which connects VGIN to
VAGC, the AGC mode is activated. The AGC voltage can be observed on SMA
Connector J9. With LK3 removed, apply the gain control signal for the internal
variable gain amplifiers to SMA Connector J10.
LK2, LK6, LK3 installed
LK4, LK5, J7, J8
R6, R33,
Baseband Filtering. Installing LK4 and LK5 connects IMXO and QMXO, the mixer
outputs, directly to IAIN and QAIN, the baseband amplifier inputs. With R6 and R33
installed (0 Ω), IAIN and QAIN can be observed on SMA Connector J7 and SMA
Connector J8. By removing LK4 and LK5 and installing R8 and R34, LC filters can be
inserted between the mixer outputs and the baseband amplifier inputs. R8 and R34
can be used to increase the effective output impedance of IMXO and QMXO (these
outputs have low output impedances). R39 and R40 can be used to provide
terminations for the filter at IAIN and QAIN (high impedance inputs.) Terminate R39
and R40 to VREF.
LK4, LK5 installed
R6 = R33 = 0 Ω (Size 0603)
L1 to L5
L1 to L5 = open (Size 0805), C4,
C17 to C22, C25 to C31 = open
(Size 0805), R8 = R34 = open
(Size 0603), R39 = R40 = open
(Size 0603)
C4, C17 to C22,
C25 to C31
R8, R34, R39, R40
R35, R36, R37, R38 Baseband Amplifier Output Series Resistors.
R35 = R36 = R37 = R38 = 0 Ω
(Size 0603)
SW1 Device Enable. When in Position A, the ENBL pin is connected to +VS and the
SW1 = A
AD8347 is in operating mode. In Position B, the ENBL pin is grounded, putting the
device in power-down mode.
Rev. A | Page 25 of 28
AD8347
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 57. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8347ARU
AD8347ARU-REEL7
AD8347ARUZ1
AD8347ARUZ-REEL71
AD8347-EVAL
Temperature Range
Package Description
28-Lead TSSOP
28-Lead TSSOP, 7”Tape and Reel
28-Lead TSSOP
28-Lead TSSOP, 7”Tape and Reel
Evaluation Board
Package Option
RU-28
RU-28
RU-28
RU-28
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
1 Z = Pb-free part.
Rev. A | Page 26 of 28
AD8347
NOTES
Rev. A | Page 27 of 28
AD8347
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02675-0-10/05(A)
Rev. A | Page 28 of 28
相关型号：
AD8347ARUZ-REEL7
800MHz - 2700MHz RF/MICROWAVE QUADRAPHASE DEMODULATOR, MO-153AE, RU-28, TSSOP-28
ROCHESTER
AD8349AREZ-REEL7
RF/Microwave Modulator/Demodulator, 700 MHz - 2700 MHz RF/MICROWAVE QPSK MODULATOR, LEAD FREE, MO-153ABT, TSSOP-16
ADI
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