AD8348ARUZ-REEL7 [ADI]
50 MHz to 1000 MHz Quadrature Demodulator; 50 MHz至1000 MHz的正交解调器
| 型号： | AD8348ARUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 50 MHz to 1000 MHz Quadrature Demodulator |
| 文件： | 总28页 (文件大小：929K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
50 MHz to 1000 MHz
Quadrature Demodulator
AD8348
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VREF
IMXO
IOFS
IAIN
IOPP IOPN
Integrated I/Q demodulator with IF VGA amplifier
Operating IF frequency 50 MHz to 1000 MHz
(3 dB IF BW of 500 MHz driven from RS = 200 Ω)
Demodulation bandwidth 75 MHz
Linear-in-decibel AGC range 44 dB
Third-order intercept
14
8
13
6
4
3
BIAS
CELL
VREF
ENBL 15
5
1
VCMO
LOIP
VCMO
DIVIDE
BY 2
IFIP 11
IFIN 10
PHASE
SPLITTER
28
LOIN
IIP3 +28 dBm @ minimum gain (FIF = 380 MHz)
IIP3 −8 dBm @ maximum gain (FIF = 380 MHz)
Quadrature demodulation accuracy
Phase accuracy 0.5°
Amplitude balance 0.25 dB
Noise figure 11 dB @ maximum gain (FIF = 380 MHz)
LO input −10 dBm
AD8348
GAIN
CONTROL
VGIN 17
VCMO
25
26
23
18
19
24
21
16
MXIP MXIN ENVG
QXMO
QOFS
QAIN
QOPP QOPN
Figure 1.
Single supply 2.7 V to 5.5 V
Power-down mode
Compact, 28-lead TSSOP package
APPLICATIONS
QAM/QPSK demodulator
W-CDMA/CDMA/GSM/NADC
Wireless local loop
LMDS
GENERAL DESCRIPTION
The AD8348 is a broadband quadrature demodulator with an
integrated intermediate frequency (IF), variable gain amplifier
(VGA), and integrated baseband amplifiers. It is suitable for use in
communications receivers, performing quadrature demodulation
from IF directly to baseband frequencies. The baseband amplifiers
are designed to interface directly with dual-channel ADCs, such
as the AD9201, AD9283, and AD9218, for digitizing and post-
processing.
Separate I- and Q-channel baseband amplifiers follow the baseband
outputs of the mixers. The voltage applied to the VCMO pin sets
the dc common-mode voltage level at the baseband outputs.
Typically, VCMO is connected to the internal VREF voltage, but
it can also be connected to an external voltage. This flexibility
allows the user to maximize the input dynamic range to the ADC.
Connecting a bypass capacitor at each offset compensation input
(IOFS and QOFS) nulls dc offsets produced in the mixer. Offset
compensation can be overridden by applying an external voltage
at the offset compensation inputs.
The IF input signal is fed into two Gilbert cell mixers through
an X-AMP® VGA. The IF VGA provides 44 dB of gain control.
A precision gain control circuit sets a linear-in-decibel gain char-
acteristic for the VGA and provides temperature compensation.
The LO quadrature phase splitter employs a divide-by-2 frequency
divider to achieve high quadrature accuracy and amplitude balance
over the entire operating frequency range.
The mixers’ outputs are brought off-chip for optional filtering
before final amplification. Inserting a channel selection filter
before each baseband amplifier increases the baseband amplifiers’
signal handling range by reducing the amplitude of high level,
out-of-channel interferers before the baseband signal is fed into
the I/Q baseband amplifiers. The single-ended mixer output is
amplified and converted to a differential signal for driving ADCs.
Optionally, the IF VGA can be disabled and bypassed. In this
mode, the IF signal is applied directly to the quadrature mixer
inputs via the MXIP and MXIN pins.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD8348
TABLE OF CONTENTS
Features .............................................................................................. 1
Enable........................................................................................... 18
Baseband Offset Cancellation................................................... 18
Applications..................................................................................... 20
Basic Connections...................................................................... 20
Power Supply............................................................................... 20
Device Enable ............................................................................. 20
VGA Enable ................................................................................ 20
Gain Control ............................................................................... 20
LO Inputs..................................................................................... 20
IF Inputs ...................................................................................... 20
MX Inputs ................................................................................... 20
Baseband Outputs ...................................................................... 21
Output DC Bias Level................................................................ 21
Interfacing to Detector for AGC Operation............................... 21
Baseband Filters.......................................................................... 22
LO Generation............................................................................ 23
Evaluation Board........................................................................ 23
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Equivalent Circuits........................................................................... 9
Typical Performance Characteristics ........................................... 11
VGA and Demodulator ............................................................. 11
Demodulator Using MXIP and MXIN.................................... 14
Final Baseband Amplifiers ........................................................ 15
VGA/Demodulator and Baseband Amplifier......................... 16
Theory of Operation ...................................................................... 18
VGA.............................................................................................. 18
Downconversion Mixers ........................................................... 18
Phase Splitter............................................................................... 18
I/Q Baseband Amplifiers........................................................... 18
REVISION HISTORY
4/06—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Specifications................................................................ 3
Changes to IF Inputs Section ........................................................ 20
Changes to Evaluation Board Section.......................................... 23
Changes to Table 6.......................................................................... 27
Changes to Ordering Guide .......................................................... 28
8/03—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD8348
SPECIFICATIONS
VS = 5 V, TA = 25oC, FLO = 380 MHz, FIF = 381 MHz, PLO = −10 dBm, RS (LO) = 50 Ω, RS (IFIP and MXIP/MXIN) = 200 Ω, unless
otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max Unit
OPERATING CONDITIONS
LO Frequency Range
IF Frequency Range
Baseband Bandwidth
LO Input Level
VSUPPLY (VS)
Temperature Range
IF FRONT END WITH VGA
External input = 2 × LO frequency
100
50
2000 MHz
1000 MHz
MHz
75
−10
50 Ω source
−12
2.7
−40
0
5.5
+85
dBm
V
°C
IFIP to IMXO (QMXO),
ENVG = 5 V, IMXO/QMXO load = 1.5 kΩ
Measured differentially across MXIP/MXIN
Input Impedance
Gain Control Range
200||1.1
44
Ω||pF
dB
Maximum Conversion Voltage Gain
Minimum Conversion Voltage Gain
3 dB Bandwidth
Gain Control Linearity
IF Gain Flatness
VGIN = 0.2 V (maximum voltage gain)
VGIN = 1.2 V (minimum voltage gain)
25.5
−18.5
500
0.5
0.1
dB
dB
MHz
dB
dB p-p
dB p-p
VGIN = 0.4 V (+21 dB) to 1.1 V (−14 dB)
FIF = 380 MHz 5% (VGIN = 1.2 V)
FIF = 900 MHz 5% (VGIN = 1.2 V)
1.3
Input 1 dB Compression Point (P1dB)
Second-Order Input Intercept (IIP2)
VGIN = 0.2 V (maximum gain)
VGIN = 1.2 V (maximum gain)
IF1 = 385 MHz, IF2 = 386 MHz
+3 dBm each tone from 200 Ω source,
VGIN = 1.2 V (minimum gain)
−42 dBm each tone from 200 Ω source,
VGIN = 0.2 V (maximum gain)
IF1 = 381 MHz, IF2 = 381.02 MHz
−22
+13
dBm
dBm
65
18
dBm
dBm
Third-Order Input Intercept (IIP3)
Each tone 10 dB below P1dB from
200 Ω source,
VGIN = 1.2 V (minimum gain)
Each tone 10 dB below P1dB from
200 Ω source,
28
−8
dBm
dBm
VGIN = 0.2 V (maximum gain)
LO Leakage
Measured at IFIP, IFIN
−80
−60
75
0.1
−0.0032
+0.01
0.05
0
0.0125
10.75
dBm
dBm
MHz
Degrees
°/°C
°/MHz
dB
dB/°C
dB
Measured at IMXO/QMXO (LO = 50 MHz)
Small signal 3 dB bandwidth
LO = 380 MHz (LOIP/LOIN 760 MHz)
vs. temperature
Demodulation Bandwidth
Quadrature Phase Error1
−0.7
−0.3
+0.7
+0.3
vs. baseband frequency (dc to 30 MHz)
I/Q Amplitude Imbalance1
vs. temperature
vs. baseband frequency (dc to 30 MHz)
Maximum gain, from 200 Ω source,
FIF = 380 MHz
Noise Figure (Double Sideband)
Mixer Output Impedance
dB
40
Ω
Capacitive Load
Resistive Load
Mixer Peak Output Current
Shunt from IMXO, QMXO to VCMO
Shunt from IMXO, QMXO to VCMO
0
200
10
pF
kΩ
mA
1.5
2.5
Rev. A | Page 3 of 28
AD8348
Parameter
Conditions
Min
Typ
Max Unit
IF FRONT END WITHOUT VGA
From MXIP, MXIN to IMXO (QMXO),
ENVG = 0 V, IMXO/QMXO load = 1.5 kΩ
Measured differentially across MXIP/MXIN
Input Impedance
200||1.5
10.5
75
0.1
0.15
−4
Ω||pF
dB
MHz
dB p-p
dB p-p
dBm
dBm
Conversion voltage Gain
3 dB Output Bandwidth
IF Gain Flatness
FIF = 380 MHZ 5%
FIF = 900 MHZ 5%
Input 1 dB Compression Point (P1dB)
Third-Order Input Intercept (IIP3)
IF1 = 381 MHz, IF2 = 381.02 MHz
14
Each tone 10 dB below P1dB from
200 Ω source
LO Leakage
Measured at MXIP/MXIN
Measured at IMXO, QMXO
Small signal 3 dB bandwidth
LO = 380 MHz (LOIP/LOIN 760 MHz,
single-ended)
−70
−60
75
dBm
dBm
MHz
Demodulation Bandwidth
Quadrature Phase Error
−2
0.5
+2
Degrees
I/Q Amplitude Imbalance
Noise Figure (Double Sideband)
I/Q BASEBAND AMPLIFIER
0.25
21
dB
dB
From 200 Ω source, FIF = 380 MHz
From IAIN to IOPP/IOPN and QAIN to QOPP/
QOPN, RLOAD = 2 kΩ, single-ended to ground
Gain
20
dB
Bandwidth
Output DC Offset (Differential)
10 pF differential load
LO leakage offset corrected using 500 pF
capacitor on IOFS, QOFS (VIOPP − VIOPN
(VIOPP + VIOPN)/2 − VCMO
0 MHz to 50 MHz
125
12
MHz
mV
−50
−75
+50
+75
)
Output Common-Mode Offset
Group Delay Flatness
Input-Referred Noise Voltage
Output Swing Limit (Upper)
Output Swing Limit (Lower)
Peak Output Current
35
3
8
mV
ns p-p
nV/√Hz
V
V
mA
Frequency = 1 MHz
VS −1
0.5
1
Input Impedance
Input Bias Current
50||1
2
kΩ||pF
μA
RESPONSE FROM IF AND MX INPUTS TO
BASEBAND AMPLIFIER OUTPUT
IMXO and QMXO connected directly to
IAIN and QAIN, respectively
Gain
From MXIP/MXIN
From IFIP/IFIN, VGIN = 0.2 V
From IFIP/IFIN, VGIN = 1.2 V
30.5
45.5
1.5
dB
dB
dB
CONTROL INPUT/OUTPUTS
VCMO Input Range
VS = 5 V
VS = 2.7 V
0.5
0.5
0.95
0.2
−55
55
1
1
1
4
V
V
V
V
dB/V
dB
1.7
1.05
1.2
−45
67
VREF Output Voltage
Gain Control Voltage Range
Gain Slope
VGIN
−50
61
Gain Intercept
Linear extrapolation back to theoretical
gain at VGIN = 0 V
Gain Control Input Bias Current
LO INPUTS
1
μA
dB
LOIP Input Return Loss
LOIN ac-coupled to ground
(760 MHz applied to LOIP)
−6
Rev. A | Page 4 of 28
AD8348
Parameter
Conditions
Min
Typ
Max Unit
POWER-UP CONTROL
ENBL Threshold Low
ENBL Threshold High
Input Bias Current
Power-Up Time
Low = standby
High = enable
0
VS/2
VS/2
2
1
VS
V
V
μA
μs
VS − 1
Time for final baseband amplifiers to be
within 90% of final amplitude
45
Power-Down Time
Time for supply current to be <10% of
enabled value
700
ns
POWER SUPPLIES
Voltage
Current (Enabled)
Current (Standby)
VPOS1, VPOS2, VPOS3
2.7
38
5.5
58
V
mA
μA
VS = 5 V, VENBL = 5 V
VS = 5 V, VENBL = 0 V
48
75
1 These parameters are guaranteed but not tested in production. Limits are ±6 Σ from the mean.
Rev. A | Page 5 of 28
AD8348
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
Supply Voltage on VPOS1, VPOS2, VPOS3 Pins 5.5 V
LO Input Power
IF Input Power
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
10 dBm (re: 50 Ω)
18 dBm (re: 200 Ω)
450 mW
68°C/W
150°C
−40°C to +85°C
−65°C to +125°C
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 28
AD8348
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LOIP
VPOS1
IOPN
IOPP
LOIN
2
COM1
QOPN
QOPP
ENVG
QAIN
AD8348
3
TOP VIEW
(Not to Scale)
4
5
VCMO
IAIN
6
7
COM3
IMXO
COM2
IFIN
COM3
QMXO
VPOS3
MXIN
8
9
10
11
12
13
14
IFIP
MXIP
VPOS2
IOFS
VGIN
QOFS
ENBL
VREF
Figure 2. 28-Lead TSSOP Pin Configuration
Table 3. Pin Function Descriptions—28-Lead TSSOP
Equivalent
Circuit
Pin No.
Mnemonic
Description
1, 28
LOIP, LOIN
LO Inputs. For optimum performance, these inputs should be ac-coupled and driven
differentially. Differential drive from single-ended sources can be achieved via a balun.
To obtain a broadband 50 Ω input impedance, connect a 60.4 Ω shunt resistor between
LOIP and LOIN. Typical input drive level is equal to −10 dBm.
A
2, 12, 20
3, 4, 25, 26
5
VPOS1, VPOS2,
VPOS3
IOPN, IOPP,
QOPP, QOPN
VCMO
Positive Supply for LO, IF, and Biasing and Baseband Sections, Respectively. These pins
should be decoupled with 0.1 μF and 100 pF capacitors.
I- and Q-Channel Differential Baseband Outputs. Typical output swing is equal to 2 V p-p
differential. The dc common-mode voltage level on these pins is set by the voltage on VCMO.
Baseband DC Common-Mode Voltage. The voltage applied to this pin sets the dc
common-mode levels for all the baseband outputs and inputs (IMXO, QMXO, IOPP, IOPN,
QOPP, QOPN, IAIN, and QAIN). This pin can be connected either to VREF or to a reference
voltage from another device (typically an ADC).
B
C
6, 23
IAIN, QAIN
I- and Q-Channel Baseband Amplifier Inputs. The single-ended signals on these pins are
referenced to VCMO and must have a dc bias equal to the dc voltage on the VCMO pin. If
IMXO (QMXO) is dc-coupled to IAIN (QAIN), biasing will be provided by IMXO (QMXO). If
an ac-coupled filter is placed between IMXO and IAIN, these pins can be biased from the
source driving VCMO through a 1 kΩ resistor. The gain from IAIN/QAIN to the differential
outputs (IOPP/IOPN and QOPP/QOPN) is 20 dB.
D
7, 22
8, 21
COM3
IMXO, QMXO
Ground for Biasing and Baseband Sections.
I- and Q-Channel Mixer Baseband Outputs. These are low impedance (40 Ω) outputs whose
bias levels are set by the voltage applied to the VCMO pin. These pins are typically connected
to IAIN and QAIN, respectively, either directly or through a filter. Each output can drive a
maximum current of 2.5 mA.
H
E
9
COM2
IFIN, IFIP
IF Section Ground.
10, 11
IF Inputs. IFIN should be ac-coupled to ground. The single-ended IF input signal should
be ac-coupled into IFIP. The nominal differential input impedance of these pins is 200 Ω.
For a broadband 50 Ω input impedance, a minimum-loss L pad should be used; RSERIES = 174 Ω,
RSHUNT = 57.6 Ω. This provides a 200 Ω source impedance to the IF input. However, the AD8348
does not necessarily require a 200 Ω source impedance, and a single shunt 66.7 Ω resistor
can be placed between IFIP and IFIN.
13, 16
14
IOFS, QOFS
VREF
I- and Q-Channel Offset Nulling Inputs. DC offsets on the I-channel mixer output (IMXO)
can be nulled by connecting a 0.1 μF capacitor from IOFS to ground. Driving IOFS with a
fixed voltage (typically a DAC calibrated such that the offset at IOPP/IOPN is nulled) can
extend the operating frequency range to include dc. The QOFS pin can likewise be used
to null offsets on the Q-channel mixer output (QMXO).
Reference Voltage Output. This output voltage (1 V) is the main bias level for the device
and can be used to externally bias the inputs and outputs of the baseband amplifiers.
The typical maximum drive current for this output is 2 mA.
F
G
Rev. A | Page 7 of 28
AD8348
Equivalent
Circuit
Pin No.
15
17
Mnemonic
ENBL
VGIN
Description
Chip Enable Input. Active high. Threshold is equal to VS/2.
D
D
Gain Control Input. The voltage on this pin controls the gain on the IF VGA. The gain
control voltage range is from 0.2 V to 1.2 V and corresponds to a conversion gain range
from +25.5 dB to −18.5 dB. This is the gain to the output of the mixers (that is, IMXO and
QMXO). There is an additional 20 dB of fixed gain in the final baseband amplifiers (IAIN to
IOPP/IOPN and QAIN to QOPP/QOPN). Note that the gain control function has a negative
sense (that is, increasing voltage decreases gain).
18, 19
24
MXIP, MXIN
ENVG
Auxiliary Mixer Inputs. If ENVG is low, the IFIP and IFIN inputs are disabled and MXIP and
MXIN are enabled, allowing the VGA to be bypassed. The auxiliary mixer inputs are fully
differential inputs that should be ac-coupled to the signal source.
Active High VGA Enable. When ENVG is high, IFIP and IFIN inputs are enabled and MXIP
and MXIN inputs are disabled. When ENVG is low, MXIP and MXIN inputs are enabled and
IFIP and IFIN inputs are disabled.
I
D
27
COM1
LO Section Ground.
Rev. A | Page 8 of 28
AD8348
EQUIVALENT CIRCUITS
VPOS1
VPOS3
LOIN
LOIP
IAIN, QAIN, VGIN,
ENBL, ENVG
COM1
COM3
Figure 3. Circuit A
Figure 6. Circuit D
VPOS3
VPOS2
IFIP
IFIN
IOPP, IOPN,
QOPP, QOPN
VCMO
COM3
COM3
Figure 7. Circuit E
Figure 4. Circuit B
VPOS3
50µA
MAX
VPOS3
IOFS,
QOFS
VCMO
COM3
COM3
Figure 5. Circuit C
Figure 8. Circuit F
Rev. A | Page 9 of 28
AD8348
VPOS3
VPOS2
VREF
MXIP
MXIN
COM2
COM3
Figure 9. Circuit G
Figure 11. Circuit I
VPOS3
IMXO,
QMXO
COM3
Figure 10. Circuit H
Rev. A | Page 10 of 28
AD8348
TYPICAL PERFORMANCE CHARACTERISTICS
VGA AND DEMODULATOR
30
25
20
15
10
5
4
25
20
4
LINERR T = +85°C, VPOS = 2.7V, FREQ = 900MHz
LINERR T = +25°C, VPOS = 2.7V, FREQ = 900MHz
LINERR T = +85°C, VPOS = 5V, FREQ = 380MHz
3
3
LINERR T = +25°C, VPOS = 5V, FREQ = 380MHz
LINERR T = –40°C, VPOS = 2.7V,
FREQ = 900MHz
LINERR T = –40°C, VPOS = 5V, FREQ = 380MHz
2
15
2
1
10
1
0
5
0
–1
–2
–3
–4
–5
–6
0
–1
–2
–3
–4
–5
0
–5
T = +85°C, VPOS = 2.7V,
FREQ = 900MHz
T = +85°C, VPOS = 5V, FREQ = 380MHz
–5
–10
–15
–20
–10
–15
–20
–25
T = +25°C, VPOS = 5V, FREQ = 380MHz
T = –40°C, VPOS = 5V, FREQ = 380MHz
T = +25°C, VPOS = 2.7V, FREQ = 900MHz
T = –40°C, VPOS = 2.7V, FREQ = 900MHz
–6
1.2
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
VGIN (V)
VGIN (V)
Figure 12. Mixer Gain and Linearity Error vs. VGIN, VPOS = 5 V, FIF = 380 MHz,
FBB = 1 MHz, Temperature = −40°C, +25°C, +85°C
Figure 15. Mixer Gain and Linearity Error vs. VGIN, VPOS = 2.7 V, FIF = 900 MHz,
FBB = 1 MHz, Temperature = −40°C, +25°C, +85°C
28
26
25
20
4
LINERR T = +85°C, VPOS = 5V, FREQ = 900MHz
LINERR T = +25°C, VPOS = 5V, FREQ = 900MHz
3
LINERR T = –40°C, VPOS = 5V,
FREQ = 900MHz
15
2
10
1
24
5
0
5V, 0.2V, +25°C
0
–1
–2
–3
–4
–5
–6
22
–5
T = +85°C, VPOS = 5V,
FREQ = 900MHz
2.7V, 0.2V, +25°C
5V, 0.2V, +85°C
–10
–15
–20
–25
2.7V, 0.2V, +85°C
T = +25°C, VPOS = 5V, FREQ = 900MHz
T = –40°C, VPOS = 5V, FREQ = 900MHz
20
5V, 0.2V, –40°C
2.7V, 0.2V, –40°C
18
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
100 200
300
400
500
600 700
800 900 1000
VGIN (V)
IF FREQUENCY (MHz)
Figure 13. Mixer Gain and Linearity Error vs. VGIN, VPOS = 5 V, FIF = 900 MHz,
FBB = 1 MHz, Temperature = −40°C, +25°C, +85°C
Figure 16. Gain vs. FIF, VGIN = 0.2 V, FBB = 1 MHz,
Temperature = −40°C, +25°C, +85°C
–15
–20
–25
–30
30
25
20
15
10
5
4
LINERR T = +85°C, VPOS = 2.7V, FREQ = 380MHz
LINERR T = +25°C, VPOS = 2.7V, FREQ = 380MHz
5V, 1.2V, +85°C
3
LINERR T = –40°C, VPOS = 2.7V,
FREQ = 380MHz
2
2.7V, 1.2V, +85°C
1
0
5V, 1.2V, –40°C
2.7V, 1.2V, +25°C
–1
–2
–3
–4
–5
–6
0
T = +85°C, VPOS = 2.7V,
FREQ = 380MHz
2.7V, 1.2V, –40°C
5V, 1.2V, +25°C
–5
–10
–15
–20
T = +25°C, VPOS = 2.7V, FREQ = 380MHz
T = –40°C, VPOS = 2.7V, FREQ = 380MHz
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
100 200
300
400
500
600 700
800 900 1000
VGIN (V)
IF FREQUENCY (MHz)
Figure 14. Mixer Gain and Linearity Error vs. VGIN, VPOS = 2.7 V, FIF = 380 MHz,
FBB = 1 MHz, Temperature = −40°C, +25°C, +85°C
Figure 17. Gain vs. FIF, VGIN = 1.2 V, FBB = 1 MHz,
Temperature = −40°C, +25°C, +85°C
Rev. A | Page 11 of 28
AD8348
27
26
25
24
23
22
21
20
19
18
20
15
10
5
–40°C, 5V, 900MHz
5V, 0.2V, +25°C
+25°C, 2.7V, 900MHz
2.7V, 0.2V, +85°C
+25°C, 5V, 900MHz
+85°C, 2.7V, 900MHz
5V, 0.2V, –40°C
2.7V, 0.2V, +25°C
2.7V, 0.2V, –40°C
0
5V, 0.2V, +85°C
–5 +85°C, 5V, 900MHz
–10
–15
–20
–40°C, 2.7V, 900MHz
17
0
10
20
30
40
50
60
70
80
90
100
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
BASEBAND FREQUENCY (MHz)
VGIN (V)
Figure 18. Gain vs. FBB, VGIN = 0.2 V, FIF = 380 MHz, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
Figure 21. Input 1 dB Compression Point (IP1dB) vs. VGIN, FIF = 900 MHz,
F
BB = 1 MHz, VPOS = 2.7 V, 5 V, Temperature = −40°C, +25°C, +85°C
–17
30
29
28
27
26
25
24
5V, 1.2V, +85°C
5V, 1.2V, +25°C
2.7V, 1.2V, +85°C
–20
5V, 1.2V, +85°C
2.7V, 1.2V, +85°C
2.7V, 1.2V, +25°C
5V, 1.2V, +25°C
–23
2.7V, 1.2V, +25°C
5V, 1.2V, –40°C
5V, 1.2V, –40°C
2.7V, 1.2V, –40°C
2.7V, 1.2V, –40°C
400 500 600
IF FREQUENCY (MHz)
–26
0
10
20
30
40
50
60
70
80
90
100
100
200
300
700
800 900 1000
BASEBAND FREQUENCY (MHz)
Figure 19. Gain vs. FBB, VGIN = 1.2 V, FIF = 380 MHz, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
Figure 22. IIP3 vs. FIF, VGIN = 1.2 V, FBB = 1 MHz, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C, Tone Spacing = 20 kHz
15
0
+25°C, 5V, 380MHz
5V, 0.2V, +85°C
10
–40°C, 5V, 380MHz
2.7V, 0.2V, +85°C
5
2.7V, 0.2V, +25°C
–5
+25°C, 2.7V, 380MHz
+85°C, 2.7V, 380MHz
0
–5
5V, 0.2V, –40°C
–10
–15
–20
–25
+85°C, 5V, 380MHz
–10
2.7V, 0.2V, –40°C
5V, 0.2V, +25°C
–40°C, 2.7V, 380MHz
–15
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
100 200
300 400
500
600 700 800
900 1000
VGIN (V)
IF FREQUENCY (MHz)
Figure 20. Input 1 dB Compression Point (IP1dB) vs. VGIN, FIF = 380 MHz,
BB = 1 MHz, VPOS = 2.7 V, 5 V, Temperature = −40°C, +25°C, +85°C
Figure 23. IIP3 vs. FIF, VGIN = 0.2 V, FBB = 1 MHz, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
F
Rev. A | Page 12 of 28
AD8348
32
30
28
26
24
22
45
40
35
30
25
20
15
10
5
35
30
25
2.7V, 1.2V, –40°C
5V, 1.2V, –40°C
NF
2.7V, 1.2V, +25°C
IIP3
20
15
10
5
2.7V, 1.2V, +85°C
5V, 1.2V, +25°C
5V, 1.2V, +85°C
0
–5
–10
0
0.2
0
10
20
30
40
50
60
70
80
90
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
BASEBAND FREQUENCY (MHz)
VGIN (V)
Figure 24. IIP3 vs. FBB, VGIN = 1.2 V, FIF = 380 MHz, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
Figure 27. Noise Figure and IIP3 vs. VGIN, Temperature = 25°C,
F
IF = 380 MHz, FBB = 1 MHz, VPOS = 2.7 V
0
40
35
30
25
20
15
10
5
35
30
25
20
15
10
5
NF
2.7V, 0.2V, +85°C
5V, 0.2V, +85°C
–5
IIP3
5V, 0.2V, +25°C
–10
2.7V, 0.2V, –40°C
5V, 0.2V, –40°C
2.7V, 0.2V, +25°C
–15
0
–5
–10
–20
0
0.2
0
10
20
30
40
50
60
70
80
90
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
BASEBAND FREQUENCY (MHz)
VGIN (V)
Figure 25. IIP3 vs. FBB, VGIN = 0.2 V, FIF = 380 MHz, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
Figure 28. Noise Figure and IIP3 vs. VGIN, Temperature = 25°C,
FIF = 380 MHz, FBB = 1 MHz, VPOS = 5 V
16
15
14
16
15
14
13
12
11
10
9
2.0
1.5
NF @ LO = 900MHz
1.0
NF VGIN = 0.2V
PHASE ERROR 50MHz
PHASE ERROR 380MHz
13
0.5
12
11
10
9
0
PHASE ERROR 900MHz
NF @ LO = 380MHz
–0.5
–1.0
–1.5
–2.0
NF @ LO = 50MHz
8
50
8
–12
150
250
350
450
550
650
750
850
950
–10
–8
–6
–4
–2
0
IF FREQUENCY (MHz)
LO INPUT LEVEL (V)
Figure 26. Noise Figure vs. FIF, T = 25°C, VGIN = 0.2 V, FBB = 1 MHz
Figure 29. Noise Figure and Quadrature Phase Error IMXO/QMXO vs. LO Input
Level, Temperature = 25°C, VGIN = 0.2 V, VPOS = 5 V for FIF = 50 MHz,
380 MHz, and 900 MHz
Rev. A | Page 13 of 28
AD8348
DEMODULATOR USING MXIP AND MXIN
11.0
18
17
16
15
14
13
12
11
10
23.0
22.5
22.0
21.5
21.0
20.5
20.0
19.5
19.0
NF 5V
10.5
10.0
9.5
TEMP = –40°C, V
= 2.7V
POS
TEMP = –40°C, V
= 5V
POS
TEMP = +25°C,
= 5V
IIP3 5V
V
POS
TEMP = +85°C,
= 2.7V
NF 2.7V
9.0
V
POS
TEMP = +25°C,
= 2.7V
V
POS
8.5
IIP3 2.7V
TEMP = +85°C, V
200 300 400
= 5V
POS
8.0
100
500
600
700 800
900 1000
50
150 250 350 450
550
650
750
850
950
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 30. Mixer Gain vs. FIF, VPOS = 2.7 V, 5 V, FBB = 1 MHz,
Temperature = −40°C, +25°C, +85°C
Figure 32. IIP3 and Noise Figure vs. FIF, VPOS = 2.7 V, 5 V, Temperature = 25°C
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
–6.5
–7.0
–7.5
–8.0
TEMP = +85°C, V
= 5V
POS
TEMP = +25°C, V
= 5V
= 5V
POS
TEMP = –40°C, V
POS
TEMP = +85°C, V
= 2.7V
POS
TEMP = –40°C, V
TEMP = +25°C, V
= 2.7V
POS
= 2.7V
POS
100
200 300 400 500
600
700 800 900 1000
IF FREQUENCY (MHz)
Figure 31. Input 1 dB Compression Point vs. FIF, FBB = 1 MHz, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
Rev. A | Page 14 of 28
AD8348
FINAL BASEBAND AMPLIFIERS
21
35
30
25
20
15
10
5
–40°C, 5V
–40°C, 5V
+25°C, 5V
–40°C, 2.7V
+85°C, 5V
20
+85°C, 5V
+25°C, 2.7V
19
18
17
16
15
14
13
+25°C, 5V
+85°C, 2.7V
+85°C, 2.7V
+25°C, 2.7V
0
–40°C, 2.7V
–5
–10
–15
0.1
1
10
100
1000
10
30
50
70
90
110
130 150
170
190
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
Figure 33. Gain vs. FBB, VVCMO = VREF = 1 V, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
Figure 35. OIP3 vs. FBB, VVCMO = VREF = 1 V, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
5
10
+25°C, 5V
–40°C, 5V
+85°C, 5V
9
8
7
6
5
4
3
2
1
0
0
–5
+25°C, 2.7V
–40°C, 2.7V
+85°C, 2.7V
–10
–15
–20
0.1
1
10
100
1000
1
10
100
1000
10000
100000
BASEBAND FREQUENCY (MHz)
FREQUENCY (kHz)
Figure 34. OP1dB Compression vs. FBB, VVCMO = VREF = 1 V, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
Figure 36. Noise Spectral Density
Rev. A | Page 15 of 28
AD8348
VGA/DEMODULATOR AND BASEBAND AMPLIFIER
2.0
2.0
1.5
1.0
0.5
1.5
1.0
5V, 0.2V, +85°C
2.7V, 0.2V, –40°C
0.5
0
0
–0.5
–1.0
–1.5
–2.0
5V, 0.2V, –40°C
2.7V, 0.2V, +85°C
–0.5
–1.0
–1.5
–2.0
2.7V, 0.2V, +25°C
5V, 0.2V, +25°C
100 200 300 400 500 600 700
IF FREQUENCY (MHz)
800
900 1000
100 200 300 400 500
600 700
800
900 1000
IF FREQUENCY (MHz)
Figure 37. Quadrature Phase Error vs. FIF, VGIN = 0.7 V, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C
Figure 40. I/Q Amplitude Imbalance vs. FIF, Temperature = 25°C, VPOS = 5 V
2.0
300
280
260
240
220
200
180
160
140
120
100
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.7V, 0.7V, +25°C
1.5
1.0
0.5
2.7V, 0.7V, –40°C
5V, 0.7V, –40°C
SHUNT CAPACITANCE
SHUNT RESISTANCE
0
–0.5
–1.0
–1.5
–2.0
5V, 0.7V, +85°C
5V, 0.7V, +25°C
2.7V, 0.7V, +85°C
0
5
10
15
20
25
30
35
40
50
150
250
350 450
550 650
750
850 950
BASEBAND FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 38. Quadrature Phase Error vs. FBB, VGIN = 0.7 V, VPOS = 2.7 V, 5 V,
Temperature = −40°C, +25°C, +85°C, FIF = 380 MHz
Figure 41. Input Impedance of IF Input vs. FIF, VGIN = 0.7 V, VPOS = 5 V
90
60
120
0.4
0.2
150
30
180
0
5V, 0.7V, 25°C
IFIP WITH L PAD
0
210
330
IFIP WITHOUT L PAD
–0.2
–0.4
IMPEDANCE CIRCLE
240
300
0
5
10
15
20
25
30
35
40
BASEBAND FREQUENCY (MHz)
270
Figure 39. I/Q Amplitude Imbalance vs. FBB, Temperature = 25°C, VPOS = 5 V
Figure 42. S11 of IF Input vs. FIF, FIF = 50 MHz to 1 GHz, VGIN = 0.7 V,
VPOS = 5 V (with L Pad, with No Pad, Normalized to 50 Ω)
Rev. A | Page 16 of 28
AD8348
0
–5
300
280
260
240
220
200
180
160
140
120
100
2.5
2.0
1.5
1.0
0.5
0
–10
–15
–20
–25
–30
–35
(SHUNT CAPACITANCE)
RETURN LOSS LO INPUT, THROUGH BALUN
WITH 60.4Ω IN SHUNT BETWEEN LOIP/LOIN
(SHUNT RESISTANCE)
IF FREQUENCY (MHz)
FREQUENCY APPLIED TO LOIP/LOIN (MHz)
Figure 43. Input Impedance of Mixer Input vs. FIF, VGIN = 0.7 V, VPOS = 5 V
Figure 46. Return Loss of LO Input vs. External LO Frequency
Through Balun, with Termination Resistor
90
60
120
65
60
55
50
150
30
MX INPUTS WITH 4:1 BALUN
180
0
V
= 5V
S
V
= 2.7V
S
MXIP INPUT PIN
45
40
35
210
330
IMPEDANCE CIRCLE
270
240
300
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 44. S11 of Mixer Input vs. FIF, FIF = 50 MHz to 1 GHz,
VGIN = 0.7 V, VPOS = 5 V (With and Without Balun)
Figure 47. Supply Current vs. Temperature
0
–5
RETURN LOSS LOIP PIN SINGLE-ENDED,
LOIN AC-COUPLED TO GROUND.
–10
–15
–20
–25
–30
–35
EXTERNAL LO FREQUENCY (MHz)
Figure 45. Return Loss of LOIP Input vs. External LO Frequency
Rev. A | Page 17 of 28
AD8348
THEORY OF OPERATION
VREF
14
IMXO
8
IOFS
13
IAIN
6
IOPP IOPN
4
3
PHASE SPLITTER
BIAS
CELL
Quadrature generation is achieved using a divide-by-2 frequency
divider. Unlike a polyphase filter that achieves quadrature over
a limited frequency range, the divide-by-2 approach maintains
quadrature over a broad frequency range and does not attenuate
the LO. The user, however, must provide an external signal XLO
that is twice the frequency of the desired LO frequency. XLO drives
the clock inputs of two flip-flops that divide down the frequency
by a factor of 2. The outputs of the two flip-flops are one-half
period of XLO out of phase. Equivalently, the outputs are one-
quarter period (90°) of the desired LO frequency out of phase.
Because the transitions on XLO define the phase difference at
the outputs, deviation from 50% duty cycle translates directly to
quadrature phase errors.
15
VREF
ENBL
5
1
VCMO
LOIP
VCMO
DIVIDE
BY 2
11
10
IFIP
IFIN
PHASE
SPLITTER
28 LOIN
AD8348
GAIN
CONTROL
17
VGIN
VCMO
18
19
24
21
16
23
25
26
MXIP MXIN ENVG
QXMO
QOFS
QAIN
QOPP QOPN
Figure 48. Functional Block Diagram
VGA
The VGA is implemented using the patented X-AMP architecture.
The single-ended IF signal is attenuated in eight discrete 6 dB
steps by a passive R-2R ladder. Each discrete attenuated version
of the IF signal is applied to the input of a transconductance
stage. The current outputs of all transconductance stages are
summed together and drive a resistive load at the output of the
VGA. Gain control is achieved by smoothly turning on and
off the relevant transconductance stages with a temperature-
compensated interpolation circuit. This scheme allows the gain
to continuously vary over a 44 dB range with linear-in-decibel
gain control. This configuration also keeps the relative dynamic
range constant (for example, IIP3 − NF in dB) over the gain
setting; however, the absolute intermodulation intercepts and
noise figure vary directly with gain. The analog voltage VGIN
sets the gain. VGIN = 0.2 V is the maximum gain setting, and
VGIN = 1.2 V is the minimum voltage gain setting.
If the user generates XLO from a 1× frequency (fREF) and a
frequency-doubling circuit (XLO = 2 × fREF), fundamentally
there is a 180° phase uncertainty between fREF and the AD8348
internal quadrature LO. The phase relationship between I and Q
LO, however, is always 90°.
I/Q BASEBAND AMPLIFIERS
Two (I and Q) fixed gain (20 dB), single-ended-to-differential
amplifiers are provided to amplify the demodulated signal
after off-chip filtering. The amplifiers use voltage feedback to
linearize the gain over the demodulation bandwidth. These
amplifiers can be used to maximize the dynamic range at the
input of an ADC following the AD8348.
The input to the baseband amplifiers, IAIN (QAIN), feeds into
the base of a bipolar transistor with an input impedance of
roughly 50 kΩ. The baseband amplifiers sense the single-ended
difference between IAIN (QAIN) and VCMO. IAIN (QAIN)
can be dc biased by terminating it with a shunt resistor to
VCMO, such as when an external filter is inserted between
IMXO (QMXO) and IAIN (QAIN). Alternatively, any dc
connection to IMXO (QXMO) can provide appropriate bias via
the offset-nulling loop.
DOWNCONVERSION MIXERS
The output of the VGA drives two (I and Q) double-balanced
Gilbert cell downconversion mixers. Alternatively, driving the
ENVG pin low can disable the VGA, and the mixers can be
externally driven directly via the MXIP and MXIN ports. At
the input of the mixer, a degenerated differential pair performs
linear voltage-to-current conversions. The differential output
current feeds into the mixer core where it is downconverted by
the mixing action of the Gilbert cell. The phase splitter provides
quadrature LO signals that drive the LO ports of the in-phase
and quadrature mixers.
ENABLE
A master biasing cell that can be disabled using the ENBL pin
controls the biasing for the chip. If the ENBL pin is held low,
the entire chip powers down to a low power sleep mode,
typically consuming 75 μA at 5 V.
Buffers at the output of each mixer drive the IMXO and QMXO
pins. These linear, low output impedance buffers drive 40 Ω,
temperature-stable, passive resistors in series with each output
pin (IMXO and QMXO). This 40 Ω should be considered when
calculating the reverse termination if an external filter is inserted
between IMXO (QMXO) and IAIN (QAIN). The VCMO pin sets
the dc output level of the buffer. This can be set externally or
connected to the on-chip 1.0 V reference, VREF.
BASEBAND OFFSET CANCELLATION
A low output current integrator senses the output voltage offset
at IOPP and IOPN (QOPP and QOPN) and injects a nulling
current into the signal path. The integration time constant of the
offset-nulling loop is set by Capacitor COFS from IOFS (QOFS) to
Rev. A | Page 18 of 28
AD8348
VCMO. This forms a high-pass response for the baseband
signal path with a lower 3 dB frequency of
The IOFS (QOFS) pin must be connected to either a bypass
capacitor (>0.1 μF) or an external voltage source to prevent the
feedback loop from oscillating.
1
fPASS
=
2π × 2650 Ω × COFS
The feedback loop will be broken at dc if an ac-coupled baseband
filter is placed between the mixer outputs and the baseband
amplifier inputs. If an ac-coupled filter is implemented, the user
must handle the offset compensation via some external means.
Alternatively, the user can externally adjust the dc offset by driving
IOFS (QOFS) with a digital-to-analog converter or other voltage
source. In this case, the baseband circuit operates all the way down
to dc (fPASS = 0 Hz). The integrator output current is only 50 μA
and can be easily overridden with an external voltage source.
The nominal voltage level applied to IOFS (QOFS) to produce
a 0 V differential offset at the baseband outputs is 900 mV.
Rev. A | Page 19 of 28
AD8348
APPLICATIONS
LO
4
3
5
BASIC CONNECTIONS
Figure 49 shows the basic connections schematic for the AD8348.
ETC1-1-13
J21
LO
1
4
5
1000pF
1000pF
T21
ETC1-1-13
60.4Ω
3
1
C21
1000pF
C22
1000pF
R21
60.4Ω
1
28
LOIN
LOIP
AD8348
1
2
3
4
5
6
7
8
9
28
LOIP
LOIN
Figure 50. Differential LO Drive with Balun
+V
S
VPOS1 COM1 27
C52
0.1µF
C51
100pF
J3I
J3Q
26
25
IOPN QOPN
IOPN
QOPN
Alternatively, the LO port can be driven from a single-ended source
without a balun (Figure 51). The LO signal is ac-coupled directly
into the LOIP pin via an ac-coupling capacitor, and the LOIN pin
is ac-coupled to ground. Driving the LO port from a single-
ended source results in an increase in both quadrature phase
error and LO leakage.
J2I
IOPP
J2Q
QOPP
IOPP
QOPP
IF
SW12
MX
+V
S
V
VCMO ENVG 24
REF
IAIN
QAIN 23
COM3 COM3 22
IMXO QMXO 21
COM2 VPOS3 20
C55
100pF
C56
0.1µF
+V
S
C43
R42
C32
1000pF
1000pF 0Ω
10 IFIN
MXIN 19
MXIP 18
LO
T41
ETK4-2T
C41
1µF
R31
57.6Ω
R32
174Ω
11 IFIP
IFIP
MXIP
C31
1000pF
C42
1000pF
1000pF
1000pF
+V
S
12 VPOS2 VGIN 17
VGIN
C54
0.1µF
C53
100pF
60.4Ω
13
IOFS
16
QOFS
C0Q
0.1µF
ENBL
C0l
+V
S
0.1µF
14 VREF
ENBL 15
SW11
28
LOIN
1
LOIP
C11
4.7µF
DENBL
Figure 49. Basic Connections Schematic
Figure 51. Single-Ended LO Drive
POWER SUPPLY
The recommended LO drive level is between −12 dBm and
0 dBm. The LO frequency at the input to the device should be
twice that of the desired LO frequency at the mixer core. The
applied LO frequency range is between 100 MHz and 2 GHz.
The voltage supply for the AD8348, between 2.7 V and 5 V, should
be provided to the +VPOSx pins, and ground should be connected
to the COMx pins. Each supply pin should be decoupled separately
using two capacitors whose recommended values are 100 pF and
0.1 ꢀF (values close to these can also be used).
IF INPUTS
DEVICE ENABLE
The IF inputs have an input impedance of 200 Ω. A broadband
50 Ω match can be presented to the driving source through the use
of a minimum-loss L pad. This minimum-loss pad introduces
an 11.46 dB loss in the input path and must be taken into account
when calculating metrics such as gain and noise figure. Figure 42
shows the S11 of the IF input with and without the L pad.
To enable the device, the ENBL pin should be driven to VS.
Grounding the ENBL pin disables the device.
VGA ENABLE
Driving the voltage on the ENVG pin to VS enables the VGA. In
this mode, the MX inputs are disabled and the IF inputs are
used. Grounding the ENVG pin disables the VGA and the IF
inputs. When the VGA is disabled, the MX inputs should be used.
1000pF
10
IFIN
IFIP
57.6Ω
174Ω
1000pF
11
IFIP
GAIN CONTROL
Figure 52. Minimum-Loss L Pad for 50 Ω IF Input
When the VGA is enabled, the voltage applied to the VGIN pin sets
the gain. The gain control voltage range is between 0.2 V and 1.2 V.
This corresponds to a gain range between +25.5 dB and −18.5 dB.
MX INPUTS
The mixer inputs, MXIP and MXIN, have a nominal impedance
of 200 Ω and should be driven differentially. When driven from
a differential source, the input should be ac-coupled to the
source via capacitors, as shown in Figure 53.
LO INPUTS
For optimum performance, the local oscillator port should be
driven differentially through a balun. The recommended balun
is M/A-COM ETC1-1-13. The LO inputs to the device should
be ac-coupled, unless an ac-coupled transformer is being used.
For a broadband match to a 50 Ω source, a 60.4 Ω resistor
should be placed between the LOIP and LION pins.
Rev. A | Page 20 of 28
AD8348
LO
4
3
5
1
1000pF
1000pF
1:1
MXIN 19
MXIP 18
MXIN
MXIP
1000pF
1000pF
28
60.4Ω
AD8348
1
2
3
4
5
LOIP
LOIN
Figure 53. Driving the MX Inputs from a Differential Source
+V
VPOS1 COM1 27
S
0.1µF
100pF
If the MX inputs are to be driven from a single-ended 50 Ω source,
a 4:1 balun can be used to transform the 200 Ω impedance of
the inputs to 50 Ω while performing the required single-ended-
to-differential conversion. The recommended transformer is the
M/A-COM ETK4-2T.
26
25
IOPN QOPN
TO BASEBAND
I ADC
TO BASEBAND
Q ADC
IOPP
QOPP
V
+V
S
VCMO ENVG 24
REF
6
7
8
9
IAIN
QAIN 23
COM3 COM3 22
IMXO QMXO 21
COM2 VPOS3 20
1.02kΩ
1.24kΩ
1000pF
V
CMO
MXIN 19
+V
1µF
S
ETK4-2T
1000pF
100pF
0.1µF
MXIP 18
MXIP
10 IFIN
MXIN 19
MXIP 18
1000pF
1000pF
1000pF
IF INPUT
= 200Ω
11 IFIP
Z
O
1000pF
Figure 54. Driving the MX Inputs from a Single-Ended 50 Ω Source
12 VPOS2 VGIN 17
+V
S
0.1µF
100pF
100pF
13
IOFS
QOFS
ENBL
16
15
BASEBAND OUTPUTS
100pF
100pF
V
+V
S
14 VREF
REF
The baseband amplifier outputs, IOPP, IOPN, QOPP, and QOPN,
should be presented with loads of at least 2 kΩ (single-ended to
ground). They are not designed to drive 50 Ω loads directly. The
typical swing for these outputs is 2 V p-p differential (1 V p-p
single-ended), but larger swings are possible as long as care is taken
to ensure that the signals remain within the lower limit of 0.5 V
and the upper limit of VS − 1 V of the output swing. To achieve
a larger swing, it is necessary to adjust the common-mode bias of
the baseband output signals. Increasing the swing can have the
benefit of improving the signal-to-noise ratio of the baseband
amplifier output.
1000pF
AD8362
1
2
3
4
5
COMM ACOM 16
1µF
1µF
1µF
1µF
CHPF
VREF 15
DECL VTGT 14
INHI
VPOS 13
VOUT 12
+V
S
100pF
V
0.1µF
INLO
6
7
DECL
VSET 11
SET
PWDN ACOM 10
1µF
8
9
COMM CLPF
When connecting the baseband outputs to other devices, care
should be taken to ensure that the outputs are not capacitively
loaded by approximately 20 pF or more. Such loads could
potentially overload the output or induce oscillations. The effect
of capacitive loading on the baseband amplifier outputs can be
mitigated by inserting series resistors of approximately 200 Ω.
Figure 55. AD8362 Configuration for AGC Operation
Assuming the I and Q channels have the same rms power, the
mixer output (or the output of the baseband filter) of one channel
can be used as the input of the AD8362. The AD8362 should be
operated in a region where its linearity error is small. Also, a
voltage divider should be implemented with an external resistor
in series with the 200 Ω input impedance of the AD8362 input.
This attenuates the AD8348 mixer output so that the AD8362
input is not overdriven. The size of the resistor between the
mixer output and the AD8362 input should be chosen so that
the peak signal level at the input of the AD8362 is about 10 dB
less than the approximately 10 dBm maximum of the AD8362
dynamic range.
OUTPUT DC BIAS LEVEL
The dc bias of the mixer outputs and the baseband amplifier
inputs and outputs is determined by the voltage that is driven
onto the VCMO pin. The range of this voltage is typically
between 500 mV and 4 V when operating with a 5 V supply.
To achieve maximum voltage swing from the baseband amplifiers,
VCMO should be driven at 2.25 V; this allows a swing of up to
7 V p-p differential (3.5 V p-p single-ended).
The other side of the AD8348 baseband output should be
loaded with a resistance equal to the series resistance of the
attenuating resistor in series with the AD8362’s 200 Ω input
impedance. This resistor should be tied to the source driving
VCMO so that there is no dc drawn from the mixer output.
INTERFACING TO DETECTOR FOR AGC OPERATION
The AD8348 can be interfaced with a detector such as the
AD8362 rms-to-dc converter to provide an automatic signal-
leveling function for the baseband outputs.
Rev. A | Page 21 of 28
AD8348
The level of the mixer output (or the output of the baseband
filter) can then be set by varying the setpoint voltage fed to
Pin 11 (VSET) of the AD8362.
Figure 57 shows the schematic for a 100 Ω, fourth-order elliptic
low-pass filter with a 3 dB cutoff frequency of 20 MHz. Source
and load impedances of approximately 100 Ω ensure that the
filter sees a matched source and load. This also ensures that the
mixer output is driving an overall load of 200 Ω. Note that the
shunt termination resistor is tied to the source driving VCMO
and not to ground. This ensures that the input to the baseband
amplifier is biased to the proper reference level. VCMO is not
an output pin and must be biased by a low impedance source.
Care should be taken to ensure that blockers—unwanted signals
in the band of interest that are demodulated along with the desired
signal—do not dominate the rms power of the AD8362 input.
This can cause an undesired reduction in the level of the mixer
output. To overcome this, baseband filtering can be implemented
to filter out undesired signals before the signal is presented to
the AD8362.
The frequency response and group delay of this filter are shown
in Figure 58 and Figure 59.
Figure 56 shows the effectiveness of the AGC loop in
maintaining a baseband amplifier output amplitude with less
than 0.5 dB of amplitude error over an IF input range of 40 dB
while demodulating a QPSK-modulated signal at 380 MHz.
The AD8362 is insensitive to crest factor variations and
therefore provides similar performance regardless of the
modulation of the incoming signal.
0
–10
–20
–30
–40
–50
–60
–70
–80
140
130
120
110
100
90
3
–5.1dBm re 10kΩ
QPSK
2
1
0
ERROR
1
10
100
FREQUENCY (MHz)
–1
–2
–3
–4
Figure 58. Baseband Filter Response
50
45
40
35
30
25
20
15
10
5
80
70
–55
–45
–35
–25
–15
–5
5
IFIP POWER INPUT (dBm, Z = 200Ω)
O
Figure 56. AD8348 Baseband Amplifier Output vs.
IF Input Power with AD8362 AGC Loop
2
1
BASEBAND FILTERS
Baseband low-pass or band-pass filtering can be conveniently
performed between the mixer outputs (IMXO and QMXO) and
the input to the baseband amplifiers. Consideration should be
given to the output impedance of the mixers (40 Ω).
0
1
10
100
FREQUENCY (MHz)
C1
C2
4.7pF
8.2pF
Figure 59. Baseband Filter Group Delay
R1
60Ω
TO AD8362
INPUT IF AGC
LOOP IS USED
L1
0.68µH
L2
1.2µH
C5
C6
R2
150pF
82pF
100Ω
IMXO
VCMO
IAIN
AD8348
Figure 57. Baseband Filter Schematic
Rev. A | Page 22 of 28
AD8348
The device is enabled by moving Switch SW11 (at the bottom left
of the evaluation board) to the ENBL position. The device is
disabled by moving SW11 to the DENBL position. If desired, the
device can be enabled and disabled from an external source that
can be fed into the ENBL SMA connector or the VENB test point,
in which case SW11 should be placed in the DENBL position.
LO GENERATION
Analog Devices has a line of PLLs that can be used for
generating the LO signal. Table 4 lists the PLLs and their
maximum frequency and phase noise performance.
Table 4. ADI PLL Selection Table
@ 1 kHz ΦN
dBc/Hz,
200 kHz PFD
The IF and MX inputs are selected via SW12. The switch should
be moved in the direction of the desired input.
Frequency FIN
(MHz)
ADI Model
ADF4001BRU
ADF4001BCP
ADF4110BRU
ADF4110BCP
ADF4111BRU
ADF4111BCP
ADF4112BRU
ADF4112BCP
ADF4116BRU
ADF4117BRU
ADF4118BRU
165
165
550
550
1200
1200
3000
3000
550
−99
−99
−91
−91
−78
−78
−86
−86
−89
−87
−90
Gain Control
For convenience, a potentiometer, R15, is provided to allow for
changes in gain without the need for an additional dc voltage
source. To use the potentiometer, the SW13 switch must be set
to the POT position. Alternatively, an external voltage applied
to either the test point or SMA connector labeled VGIN can set
the gain. SW13 must be set to the EXT position when an
external gain control voltage is used.
1200
3000
LO Input
The local oscillator signal should be fed to the SMA Connector
J21. This port is terminated in 50 Ω. The acceptable LO power
input range is from −12 dBm to 0 dBm and must be at a
frequency double that of the IF/MX frequency. Remember that
the AD8348 uses a 2:1 frequency divider in the LO path to
generate the internally required quadrature-phase-related LO
signals.
ADI also offers the ADF4360 fully integrated synthesizer and
VCO on a single chip that offers differential outputs for driving
the local oscillator input of the AD8348. This means that the user
can eliminate the use of a balun for single-ended-to-differential
conversions. The ADF4360 comes as a family of chips with six
operating frequency ranges. One can be chosen depending on
the local oscillator frequency required. Table 5 shows the
options available.
IF Input
The IF input should be fed into the SMA connector IFIP. The
VGA must be enabled when this port is used (SW12 in the IF
position). When this IF input is chosen, the signal path includes
a minimum-loss attenuator to transform a 50 Ω input source to
the 200 Ω source impedance level for which the VGA was
designed. This pad provides a very broadband input match at
the expense of an 11.46 dB power attenuation in the input path.
It is very important to take this into account when measuring
the noise and distortion performance of the unmodified board
using the IFIP input; the apparent noise figure will be degraded
by 11.46 dB, and the apparent IIP3 will be 11.46 dB higher than
actual. If full weak-signal performance is desired from the
evaluation board, the attenuator (comprising R31 and R32)
should be removed and replaced with a low-loss RF transformer
providing the desired 4:1 impedance ratio. When a transformer
is used, IFIN should be ac-coupled to ground and not driven
differentially with IFIP.
Table 5. ADF4360 Family Operating Frequencies
ADI Model
ADF4360-1
ADF4360-2
ADF4360-3
ADF4360-4
ADF4360-5
ADF4360-6
ADF4360-7
Output Frequency Range (MHz)
2150 to 2450
1800 to 2150
1550 to 1950
1400 to 1800
1150 to 1400
1000 to 1250
Lower frequencies set by external L
EVALUATION BOARD
Figure 60 shows the schematic for the AD8348 evaluation
board. Note that uninstalled components are indicated with the
OPEN designation. The board is powered by a single supply in
the range of 2.7 V to 5.5 V. Table 6 details the various configu-
ration options of the evaluation board. Table 7 shows the various
jumper configurations for operating the evaluation board with
different signal paths.
MX Input
The evaluation board is by default set for a differential MX drive
through a balun (T41) from a single-ended source fed into the
MXIP SMA connector. When the MX inputs are used, the
internal VGA is bypassed. To change to a differential driving
source, T41 should be removed along with Resistor R42. The
0 Ω R43 and R44 resistors should be installed in place of T41 to
bridge the gap between the input traces. This presents a nominal
Power to operate the board can be fed to a single VS test point
located near the LO input port at the top of the evaluation
board. A GND test point is conveniently provided next to the
VS test point for the return path.
Rev. A | Page 23 of 28
AD8348
differential impedance of 200 Ω (100 Ω per side). The
differential inputs should then be fed into SMA connectors
MXIP and MXIN.
Baseband Outputs
The baseband outputs are made available at the IOPP, IOPN,
QOPP, and QOPN test points and SMA connectors. These
outputs are not designed to be connected directly to 50 Ω loads
and should be presented with loads of approximately 2 kΩ or
greater.
Mixer Outputs
The I and Q mixer outputs are available through the IMXO and
QMXO SMA connectors. These outputs are biased to VCMO
and are not designed to drive loads smaller than 200 Ω. To
prevent damage to test equipment that cannot tolerate dc biases,
pads for series dc-blocking capacitors are provided. These pads
are populated with 0 Ω by default.
The dc bias level of the baseband amplifier outputs are by
default tied to VREF through LK11. If desired, the dc bias level
can be changed by removing LK11 and driving a dc voltage
onto the VCMO test point.
J21
LO
4
5
1
+V
GND
S
C52
0.1µF
C51
100pF
T21
ETC1-1-13
IOPN
GND
QOPN
GND
3
J3I
J3Q
IOPN
QOPN
C21
C22
R5I
R21
R5Q
C9I
C9Q
1000pF
1000pF
28
0Ω
60.4Ω
0Ω
OPEN
OPEN
AD8348
J2I
IOPP
J2Q
QOPP
1
2
3
4
5
LOIP
LOIN
R4I
0Ω
R4Q
0Ω
C8I
OPEN
C8Q
OPEN
IOPP
QOPP
MX
VPOS1 COM1 27
+V
S
IF
26
25
IOPN QOPN
VCMO
SW12
C13
0.1µF
IOPP
QOPP
R3I
R3Q
49.9Ω
49.9Ω
J1I
IMXO
J1Q
QMXO
VCMO ENVG 24
VCMO
C10Q
0Ω
LK4I
LK4Q
C10I
0Ω
LK11
IMXO
QMXO
IAIN
QAIN 23
6
7
8
9
LK3I
LK1I
LK3Q
LK1Q
L3I
L2I
L1I
OPEN
L1Q
OPEN
L2Q
L3Q
OPEN
OPEN
OPEN
OPEN
COM3 COM3 22
IMXO QMXO 21
COM2 VPOS3 20
LK2I
LK2Q
C3I
C2I
C1I
OPEN
C1Q
OPEN
C2Q
C3Q
OPEN
OPEN
OPEN
OPEN
R1I
R1Q
OPEN
R2I
OPEN
R2Q
OPEN
C7I
OPEN
C6I
OPEN
C5I
OPEN
C4I
OPEN
C4Q
OPEN
C5Q
OPEN
C6Q
OPEN
C7Q
OPEN
OPEN
C55
0.1µF
C55
100pF
VCMO
VCMO
10 IFIN
11 IFIP
MXIN 19
MXIP 18
R44
OPEN
+V
S
R42
0Ω
C32
1000pF
C43
1000pF
MXIN
MXIP
C41
1µF
T41
R31
57.6Ω
12 VPOS2 VGIN 17
R32
174Ω
ETK4-2T
IFIP
13
16
15
IOFS
QOFS
ENBL
C31
C42
1000pF
R41
OPEN
1000pF
R43
OPEN
+V
S
14 VREF
C54
0.1µF
C53
100pF
R14
10kΩ
LK5I
LK5Q
+V
S
R15
10kΩ
POT
R12
10kΩ
C11
4.7µF
VREF
POT
EXT
C12
0.1µF
VENB
SW13
SW11
ENBL
VGIN
R11
IOFS
C0I
0.1µF
QOFS
R13
OPEN
C0Q
0.1µF
49.9Ω
ENBL
DENBL
Figure 60. Evaluation Board Schematic
Rev. A | Page 24 of 28
AD8348
Figure 61. Evaluation Board Top Layer
Figure 62. Evaluation Board Top Silkscreen
Rev. A | Page 25 of 28
AD8348
Figure 63. Evaluation Board Bottom Layer
Figure 64. Evaluation Board Bottom Silkscreen
Rev. A | Page 26 of 28
AD8348
Table 6. Evaluation Board Configuration Options
Component
Function
Default Condition
VS, GND
SW11, ENBL
Power supply and ground vector pins.
Not applicable
SW11 = ENBL
Device enable: Place SW11 in the ENBL position to connect the ENBL pin to VS. Place SW11 in
the DENBL position to disable the device by grounding the Pin ENBL through a 50 Ω pull-down
resistor. The device can also be enabled via an external voltage applied to ENBL or VENB.
SW13, R15,
VGIN
Gain control selection: With SW13 in the POT position, the gain of the VGA can be set using the
R15 potentiometer. With SW13 in the EXT position, the VGA gain can be set by an external
voltage to the SMA connector VGIN. For VGA operation, the VGA must first be enabled by
setting SW12 to the IF position.
VGA enable selection: With SW12 in the IF position, the ENVG pin is connected to VS and the
VGA is enabled. The IF input should be used when SW12 is in the IF position. With SW12 in the
MX position, the ENVG pin is grounded and the VGA is disabled. The MX inputs should be used
when SW12 is in the MX position.
SW13 = POT
SW12 = IF
SW12
IFIP, R31, R32 IF inputs: The single-ended IF signal should be connected to this SMA connector. R31 and R32
form an L pad that presents a 50 Ω termination to the driving source. This L pad introduces an
11.46 dB loss in the input signal path and should be taken into consideration when calculating
the gain of the AD8348.
R31 = 57.6 Ω
R32 = 174 Ω
MXIP, MXIN,
T41,
R41, R42,
C42, C43
Mixer inputs: These inputs can be configured for either differential or single-ended operation.
The evaluation board is by default set for differential MX drive through a balun (T41) from a
single-ended source fed into the MXIP SMA connector. To change to a differential driving source,
T41 should be removed along with Resistor R42. The 0 Ω Resistors R43 and R44 should be installed in
place of T41 to bridge the gap between the input traces. This will present a nominal differential
impedance of 200 Ω (100 Ω per side). The differential inputs should then be fed into SMA
connectors MXIP and MXIN.
T41 = M/A-COM ETK4-2T;
R41= OPEN; C42, C43 =
1000 pF; R42 = 0 Ω
LK11, VCMO
Baseband amplifier output bias: Installing LK11 connects VREF to VCMO. This sets the bias level
on the baseband amplifiers to VREF, which is equal to approximately 1 V. Alternatively, with
LK11 removed, the bias level of the baseband amplifiers can be set by applying an external
voltage to the VCMO test point.
LK11 installed
C8, C9, R4, R5 Baseband amplifier outputs and output filter: Additional low-pass filtering can be provided at
(I and Q) the baseband output with these filters.
C10 (I and Q) Mixer output dc-blocking capacitors: The mixer outputs are biased to VCMO. To prevent
damage to test equipment that cannot tolerate dc biases, C10 is provided to block the dc
component, thus protecting the test equipment.
R4, R5 = 0 Ω
C10 = 0 Ω
C1 to C7,
R1, R2,
L1 to L3
(I and Q)
Baseband filter: These components are provided for baseband filtering between the mixer
outputs and the baseband amplifier inputs. The baseband amplifier input impedance is high
and the filter termination impedance is set by R2. See Table 7 for the jumper settings.
All = OPEN
LK5 (I and Q) Offset compensation loop disable: Installing these jumpers will disable the offset compensation LK5x = OPEN
loop for the corresponding channel.
Table 7. Filter-Jumper Configuration Options
Condition
LK1x
LK2x
LK3x
LK4x
xMXO to xAIN Directly
xMXO to xAIN via Filter
xMXO to J1x Directly, xAIN Unused
xMXO to J1x via Filter, xAIN Unused
Drive xAIN from J1x
•
•
•
•
•
•
•
•
•
Rev. A | Page 27 of 28
AD8348
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 65. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8348ARU
AD8348ARU-REEL7
AD8348ARUZ1
AD8348ARUZ-REEL71 −40°C to +85°C
AD8348-EVAL
Temperature Range Package Description
Package Option
RU-28
RU-28
RU-28
RU-28
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP] 7”Tape and Reel
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP] 7”Tape and Reel
Evaluation Board
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03678-0-4/06(A)
Rev. A | Page 28 of 28
相关型号：
AD8349AREZ-REEL7
RF/Microwave Modulator/Demodulator, 700 MHz - 2700 MHz RF/MICROWAVE QPSK MODULATOR, LEAD FREE, MO-153ABT, TSSOP-16
ADI
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