AD8349AREZ-REEL7 [ADI]
RF/Microwave Modulator/Demodulator, 700 MHz - 2700 MHz RF/MICROWAVE QPSK MODULATOR, LEAD FREE, MO-153ABT, TSSOP-16;
| 型号： | AD8349AREZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | RF/Microwave Modulator/Demodulator, 700 MHz - 2700 MHz RF/MICROWAVE QPSK MODULATOR, LEAD FREE, MO-153ABT, TSSOP-16 射频 微波 |
| 文件： | 总28页 (文件大小：584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
700 MHz to 2700 MHz
Quadrature Modulator
AD8349
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Output frequency range: 700 MHz to 2700 MHz
Modulation bandwidth: dc to 160 MHz (large signal BW)
1 dB output compression: 5.6 dBm @ 2140 MHz
Output disable function: output below –50 dBm in < 50 ns
Noise floor: –156 dBm/Hz
Phase quadrature error: 0.3 degrees @ 2140 MHz
Amplitude balance: 0.1 dB
Single supply: 4.75 V to 5.5 V
AD8349
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
QBBP
QBBN
COM3
COM3
VPS2
IBBP
IBBN
COM1
COM1
LOIN
Σ
Pin compatible with AD8345/AD8346s
16-lead, exposed-paddle TSSOP package
PHASE
SPLITTER
LOIP
VOUT
COM3
COM2
APPLICATIONS
VPS1
ENOP
BIAS
Cellular/PCS communication systems infrastructure
WCDMA/CDMA2000/PCS/GSM/EDGE
Wireless LAN/wireless local loop
LMDS/broadband wireless access systems
Figure 1.
PRODUCT DESCRIPTION
The AD8349 is a silicon, monolithic, RF quadrature modulator
that is designed for use from 700 MHz to 2700 MHz. Its
excellent phase accuracy and amplitude balance enable high
performance direct RF modulation for communication systems.
The AD8349 can be used as a direct-to-RF modulator in digital
communication systems such as GSM, CDMA, and WCDMA
base stations, and QPSK or QAM broadband wireless access
transmitters. Its high dynamic range and high modulation
accuracy also make it a perfect IF modulator in local multipoint
distribution systems (LMDS) using complex modulation
formats.
The differential LO input signal is buffered, and then split into
an in-phase (I) signal and a quadrature-phase (Q) signal using a
polyphase phase splitter. These two LO signals are further
buffered and then mixed with the corresponding I channel and
Q channel baseband signals in two Gilbert cell mixers. The
mixers’ outputs are then summed together in the output
amplifier. The output amplifier is designed to drive 50 Ω loads.
The AD8349 is fabricated using Analog Devices’ advanced
complementary silicon bipolar process, and is available in a 16-
lead, exposed-paddle TSSOP package. Its performance is
specified over a –40°C to +85°C temperature range.
The RF output can be switched on and off within 50 ns by
applying a control pulse to the ENOP pin.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8349
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Functional Descriptions.......................... 6
Equivalent Circuits........................................................................... 7
Typical Performance Characteristics ............................................. 8
Circuit Description......................................................................... 14
Overview...................................................................................... 14
LO Interface................................................................................. 14
V-to-I Converter......................................................................... 14
Mixers .......................................................................................... 14
D-to-S Amplifier......................................................................... 14
Bias Circuit.................................................................................. 14
Output Enable............................................................................. 14
Basic Connections .......................................................................... 15
Baseband I and Q Inputs ........................................................... 15
Single-Ended Baseband Drive .................................................. 15
LO Input Drive Level ................................................................. 16
Frequency Range ........................................................................ 16
LO Input Impedance Matching ................................................ 16
Single-Ended LO Drive.............................................................. 17
RF Output.................................................................................... 17
Output Enable............................................................................. 17
Baseband DAC Interface ........................................................... 18
AD9777 Interface ....................................................................... 18
Biasing and Filtering.................................................................. 18
Reducing Undesired Sideband Leakage .................................. 19
Reduction of LO Feedthrough ................................................. 19
Sideband Suppression and LO Feedthrough vs. Temperature
....................................................................................................... 20
Applications..................................................................................... 21
3GPP WCDMA Single-Carrier Application........................... 21
WCDMA MultiCarrier Application ........................................ 21
GSM/EDGE Application ........................................................... 22
Soldering Information ............................................................... 23
LO Generation Using PLLs....................................................... 23
Transmit DAC Options ............................................................. 23
Evaluation Board ............................................................................ 24
Characterization Setups................................................................. 26
SSB Setup..................................................................................... 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
11/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Figure 25 through Figure 30................................11
Changes to Figure 37 through Figure 39................................13
Change to WCDMA MultiCarrier Application section .......21
Change to Figure 60 and Figure 61 .........................................21
11/03—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD8349
SPECIFICATIONS
VS = 5 V; ambient temperature (TA) = 25°C; LO = –6 dBm; I/Q inputs = 1.2 V p-p differential sine waves in quadrature on a 400 mV dc
bias; baseband frequency = 1 MHz; LO source and RF output load impedances are 50 Ω, unless otherwise noted.
Table 1.
Parameter
Conditions
Min Typ
Max Unit
Operating Frequency
LO = 900 MHz
700
2700 MHz
Output Power
1.5
4
6
dBm
Output P1 dB
7.6
dBm
Carrier Feedthrough
Sideband Suppression
Third Harmonic1
Output IP3
–45
–35
–39
21
–30
–31
–36
dBm
dBc
dBc
dBm
POUT – (FLO + (3 × FBB)), POUT = 4 dBm
F1BB = 3 MHz, F2BB = 4 MHz, POUT = -4.2 dBm
Quadrature Error
I/Q Amplitude Balance
Noise Floor
1.9
0.1
–155
–150
–152
degree
dB
dBm/Hz
dBm/Hz
dBc/Hz
20 MHz offset from LO, all BB inputs 400 mV dc bias only
20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc
LO = 884.8 MHz, 6 MHz offset from LO, POUT = 2 dBm
GSM Sideband Noise
LO = 1900 MHz
Output Power
0
3.8
6
dBm
Output P1dB
6.8
dBm
Carrier Feedthrough
Sideband Suppression
Third Harmonic 1
Output IP3
–38
–40
–37
22
dBm
dBc
dBc
dBm
–36
–36
POUT – (FLO + (3 × FBB)), POUT = 3.8 dBm
F1BB = 3 MHz, F2BB = 4 MHz, POUT = –4.5 dBm
Quadrature Error
I/Q Amplitude Balance
Noise Floor
0.7
0.1
–156
–150
–151
degree
dB
dBm/Hz
dBm/Hz
dBc/Hz
20 MHz offset from LO, all BB inputs 400 mV dc bias only
20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc
LO = 1960 MHz, 6 MHz offset from LO, POUT = 2 dBm
GSM Sideband Noise
LO = 2140 MHz
Output Power
–2
2.4
5.1
dBm
Output P1dB
5.6
dBm
Carrier Feedthrough
Sideband Suppression
Third Harmonic 1
Output IP3
–42
–43
–37
19
–30
–36
–36
dBm
dBc
dBc
dBm
POUT – (FLO + (3 × FBB)), POUT = 2.4 dBm
F1BB = 3 MHz, F2BB = 4 MHz, POUT = –6.5 dBm
Quadrature Error
I/Q Amplitude Balance
Noise Floor
0.3
0.1
–156
–151
–156
degree
dB
dBm/Hz
dBm/Hz
dBm/Hz
20 MHz offset from LO, all BB inputs 400 mV dc bias only
20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc
LO = 2140 MHz. 30 MHz offset from LO, PCHAN = –17.3 dBm
Pins LOIP and LOIN
WCDMA Noise Floor
LO INPUTS
LO Drive Level
Characterization performed at typical level
–10
–6
50
–8.6
0
dBm
Ω
dB
Nominal Impedance
Input Return Loss
BASEBAND INPUTS
I and Q Input Bias Level
Input Bias Current
Input Offset Current
Bandwidth (0.1 dB)
Drive via 1:1 balun, LO = 2140 MHz
Pins IBBP, IBBN, QBBP, QBBN
400
11
1.8
10
mV
µA
µA
MHz
MHz
LO = 1500 MHz, baseband input = 600 mV p-p sine wave on 400 mV dc
LO = 1500 MHz, baseband input = 60 mV p-p sine wave on 400 mV dc
24
Rev. A | Page 3 of 28
AD8349
Parameter
Conditions
Min Typ
160
Max Unit
MHz
Bandwidth (3 dB)
LO = 1500 MHz, baseband input = 600 mV p-p sine wave on 400 mV dc
LO = 1500 MHz, baseband input = 60 mV p-p sine wave on 400 mV dc
Pin ENOP
ENOP Low
ENOP Low to High (90% of envelope)
ENOP High to Low (10% of envelope)
340
MHz
OUTPUT ENABLE
Off Isolation
–78
20
50
–50
0.8
dBm
ns
ns
V
Turn-On Settling Time
Turn-Off Settling Time
ENOP High Level (Logic 1)
ENOP Low Level (Logic 0)
POWER SUPPLIES
Voltage
2.0
V
Pins VPS1 and VPS2
4.75
135
130
5.5
V
Supply Current
ENOP = High
ENOP = Low
150
145
mA
mA
1 The amplitude of the third harmonic relative to the single sideband power decreases with decreasing baseband drive level (see Figure 19, Figure 20, and Figure 21).
Rev. A | Page 4 of 28
AD8349
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage VPOS
IBBP, IBBN, QBBP, QBBN
LOIP and LOIN
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Stresses above those listed under Absolute Maximum Ratings
Rating
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
5.5 V
0 V, 2.5 V
10 dBm
800 mW
30°C/W
125°C
−40°C to +85°C
−65°C to +150°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 28
AD8349
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
IBBP
IBBN
COM1
COM1
LOIN
1
2
3
4
5
6
7
8
16 QBBP
15 QBBN
14 COM3
13 COM3
12 VPS2
11 VOUT
10 COM3
AD8349
TOP VIEW
(Not to Scale)
LOIP
VPS1
ENOP
9
COM2
Figure 2.
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
Equivalent
Circuit
1, 2,
15, 16
IBBP, IBBN,
QBBN, QBBP
Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be
dc-biased to approximately 400 mV dc, and must be driven from a low impedance source.
Nominal characterized ac signal swing is 600 mV p-p on each pin (100 mV to 700 mV). This
results in a differential drive of 1.2 V p-p with a 400 mV dc bias. These inputs are not self-biased
and must be externally biased.
Circuit A
3, 4
5, 6
7
COM1
Common Pin for LO Phase Splitter and LO Buffers. COM1, COM2, and COM3 should all be
connected to a ground plane via a low impedance path.
Differential Local Oscillator Inputs. Internally dc-biased to approximately 1.8 V when VS = 5.0 V.
Pins must be ac-coupled. Single-ended drive is possible with degradation in performance.
Positive Supply Voltage (4.75 V to 5.5 V) for the LO Bias-Cell and Buffer. VPS1 and VPS2 should
be connected to the same supply. To ensure adequate external bypassing, connect 0.1 µF and
100 pF capacitors between VPS1 and ground.
Output Enable. This pin can be used to enable or disable the RF output. Connect to high logic
level for normal operation. Connect to low logic level to disable output.
Common Pin for the Output Amplifier. COM1, COM2, and COM3 should all be connected to a
ground plane via a low impedance path.
Common Pin for Input V-to-I Converters and Mixer Cores. COM1, COM2, and COM3 should all
be connected to a ground plane via a low impedance path.
Device Output. Single-ended, 50 Ω internally biased RF output. Pin must be ac-coupled to the
load.
Positive Supply Voltage (4.75 V to 5.5 V) for the Baseband Input V-to-I Converters, Mixer Core,
Band Gap Reference, and Output Amplifer. VPS1 and VPS2 should be connected to the same
supply. To ensure adequate external bypassing, connect 0.1 µF and 100 pF capacitors between
VPS2 and ground.
LOIN, LOIP
VPS1
Circuit B
Circuit C
8
9
ENOP
COM2
COM3
VOUT
VPS2
10, 13,
14
11
Circuit D
12
Rev. A | Page 6 of 28
AD8349
EQUIVALENT CIRCUITS
VPS2
VPS2
ENOP
IBBP
COM3
COM3
Figure 3. Circuit A
Figure 5. Circuit C
VPS1
VPS2
VOUT
COM2
LOIN
LOIP
40Ω
40Ω
COM1
Figure 4. Circuit B
Figure 6. Circuit D
Rev. A | Page 7 of 28
AD8349
TYPICAL PERFORMANCE CHARACTERISTICS
8
10
9
7
6
V
= 5.25V
S
8
V
= 5V
S
7
5
6
T = +85
T = +25
T = –40
°C
°C
°C
4
5
3
4
V
= 4.75V
S
2
3
2
1
1
0
0
–1
–2
–3
–4
–1
–2
–3
–4
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 7. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (FLO
(I and Q Inputs Driven in Quadrature at Baseband Frequency (FBB) = 1 MHz,
I and Q Inputs at 1.2 V p-p Differential, TA = 25°C)
)
Figure 10. SSB Output 1 dB Compression Point (OP1dB) vs. FLO (FBB = 1 MHz,
I and Q Inputs Driven in Quadrature , TA = 25°C)
1
–10
–15
–20
–25
–30
0
60mV p-p
–1
–2
–3
–4
V
= 5.25V
S
–35
–40
–45
–50
–55
–60
600mV p-p
–5
V
= 5V
S
–6
–7
V
= 4.75V
S
–8
–9
–10
1
10
100
1000
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
BASEBAND FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 8. I and Q Input Bandwidth Normalized to Gain @ 1 MHz
(FLO = 1500 MHz, TA = 25°C)
Figure 11. Carrier Feedthrough vs. FLO (FBB = 1 MHz, I and Q Inputs Driven in
Quadrature at 1.2 V p-p Differential, TA = 25°C)
–20
–22
–24
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–26
–28
V
= 5.25V
V
S
–30
–32
= 5V
S
V
= 4.75V
–34
–36
S
V
= 5.25V
S
V
= 5V
S
–38
–40
–42
V
= 4.75V
–44
–46
S
–48
–50
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE ( C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
°
TEMPERATURE (°C)
Figure 12. Carrier Feedthrough vs. Temperature (FLO = 2140 MHz, FBB = 1 MHz,
I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
Figure 9. SSB POUT vs. Temperature (FLO = 2140 MHz, FBB = 1 MHz, I and Q
Inputs Driven in Quadrature at 1.2 V p-p Differential)
Rev. A | Page 8 of 28
AD8349
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
V
= 5.25V
S
V = 4.75V
S
V
= 5V
S
V
= 4.75V
S
V
= 5.25V
S
V
= 5V
S
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 13. Sideband Suppression vs. FLO (FBB = 1 MHz, I and Q Inputs
Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
Figure 16. Third Order Distortion vs. FLO (FBB = 1 MHz, I and Q Inputs
Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
–10
–10
–15
–20
–25
V
= 4.75V
S
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
V
= 5.25V
S
V
= 5V
S
–30
–35
–40
–45
–50
–55
–60
V
= 4.75V
S
V
= 5.25V
S
V
= 5V
S
1
10
BASEBAND FREQUENCY (MHz)
100
1
10
BASEBAND FREQUENCY (MHz)
100
Figure 14. Sideband Suppression vs. FBB (FLO = 2140 MHz, I and Q Inputs
Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
Figure 17. Third Order Distortion vs. FBB (FLO = 2140 MHz, I and Q Inputs
Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
–30
–35
–30
V
= 4.75V
S
V
= 5V
S
–35
–40
–45
–50
–55
–60
V
= 5V
S
V
= 4.75V
S
–40
–45
–50
–55
–60
V
= 5.25V
S
V
= 5.25V
S
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE ( C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE ( C)
°
°
Figure 15. Sideband Suppression vs. Temperature (FLO = 2140 MHz,
BB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential)
Figure 18. Third Order Distortion vs. Temperature (FLO = 2140 MHz,
FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential)
F
Rev. A | Page 9 of 28
AD8349
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
10
8
160
155
150
145
140
135
130
125
120
115
110
3USB, dBc
SSB, dBm
6
4
V
= 5V
S
2
0
V
= 5.25V
S
USB, dBC
–2
–4
–6
–8
–10
–12
–14
V
= 4.75V
S
LO, dBm
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE ( C)
BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)
°
Figure 19. Third Order Distortion (3USB), Carrier Feedthrough, Sideband
Suppression, and SSB POUT vs. Baseband Differential Input Level
Figure 22. Power Supply Current vs. Temperature
(FLO = 900 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature, TA = 25°C)
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
10
8
SSB, dBm
6
4
2
0
500Ω
200Ω
LO, dBm
–2
–4
–6
–8
–10
–12
–14
USB, dBc
3USB, dBc
NO TERMINATION
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)
Figure 20. Third Order Distortion (3USB), Carrier Feedthrough, Sideband
Suppression, and SSB POUT vs. Baseband Differential Input Level
(FLO = 1900 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature, TA = 25°C)
Figure 23. Smith Chart of LOIP Port S11 (LOIN Pin AC-Coupled
to Ground). Curves with Balun and External Termination
Resistors Also Shown (TA = 25°C)
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
10
8
0
3USB, dBc
–5
–10
–15
–20
–25
–30
–35
–40
SSB, dBm
6
4
2
V
= 5V
S
0
LO, dBm
USB, dBc
–2
–4
–6
–8
–10
–12
–14
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
FREQUENCY (MHz)
BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p)
Figure 21. Third Order Distortion (3USB), Carrier Feedthrough, Sideband
Suppression, and SSB POUT vs. Baseband Differential Input Level
Figure 24. Return Loss ⏐S22⏐of VOUT Output (TA = 25°C)
(FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature, TA = 25°C)
Rev. A | Page 10 of 28
AD8349
30
28
26
24
22
20
18
16
14
12
10
8
20
18
16
14
12
10
8
6
6
4
4
2
2
0
0
NOISE FLOOR (dBm/Hz)
NOISE FLOOR (dBm/Hz)
Figure 25. 20 MHz Offset Noise Floor Distribution at FLO = 900 MHz
(BB Inputs at a Bias of 400 mV with no AC signal, TA = 25°C)
Figure 28. 20 MHz Offset Noise Floor Distribution at FLO = 940 MHz
(FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25°C)
30
28
26
24
22
20
18
16
14
12
10
8
28
26
24
22
20
18
16
14
12
10
8
6
6
4
4
2
2
0
0
NOISE FLOOR (dBm/Hz)
NOISE FLOOR (dBm/Hz)
Figure 26. 20 MHz Offset Noise Floor Distribution at FLO = 1900 MHz
(BB Inputs at a Bias of 400 mV with no AC signal, TA = 25°C)
Figure 29. 20 MHz Offset Noise Floor Distribution at FLO = 1960 MHz
(FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25°C)
30
28
26
24
22
20
18
16
14
12
10
8
30
28
26
24
22
20
18
16
14
12
10
8
6
6
4
4
2
2
0
0
NOISE FLOOR (dBm/Hz)
NOISE FLOOR (dBm/Hz)
Figure 27. 20 MHz Offset Noise Floor Distribution at FLO = 2140 MHz
(BB Inputs at a Bias of 400 mV with no AC signal, TA = 25°C)
Figure 30. 20 MHz Offset Noise Floor Distribution at FLO = 2140 MHz
(FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25°C)
Rev. A | Page 11 of 28
AD8349
35
30
25
20
15
10
5
–140
–142
–144
–146
–148
–150
–152
–154
–156
–158
WITH AC INPUT
WITHOUT AC INPUT
–160
–10
0
–0.200 –0.175 –0.150 –0.125 –0.100 –0.075 –0.050 –0.025
0
–8
–6
–4
–2
0
2
MAGNITUDE IMBALANCE (dB)
LO INPUT (dBm)
Figure 34. I and Q Inputs Quadrature Phase Imbalance Distribution
(FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in
Quadrature at 1.2 V p-p Differential, TA = 25°C)
Figure 31. 20 MHz Offset Noise Floor vs. LO Input Power
(FLO = 2140 MHz, TA = 25°C)
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
35
30
25
20
15
10
5
F
= 1900MHz
LO
F
= 2140MHz
LO
F
= 900MHz
–6
LO
0
–10
–8
–4
–2
0
2
0
0.25
0.50
0.75
1.00
1.25
1.50
LO INPUT (dBm)
PHASE (I-Q) IMBALANCE (Degrees)
Figure 32. Carrier Feedthrough vs. LO Input Power (FBB = 1 MHz, I and Q
Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
Figure 35. I and Q Inputs Amplitude Imbalance Distribution
(FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in
Quadrature at 1.2 V p-p Differential, TA = 25°C)
–10
–15
–20
35
30
25
20
15
10
5
F
= 900MHz
LO
–25
–30
–35
–40
–45
–50
–55
–60
F
= 1900MHz
LO
F
= 2140MHz
LO
0
4.5
–10
–8
–6
–4
LO INPUT (dBm)
–2
0
2
5.0
5.5
6.0
6.5
OP1dB (dBm)
Figure 33. Sideband Suppression vs. LO Input Power (FBB = 1 MHz, I and Q
Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25°C)
Figure 36. OP1dB Distribution. (FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs
Driven in Quadrature, TA = 25°C)
Rev. A | Page 12 of 28
AD8349
20
18
16
14
12
10
8
35
30
25
20
15
10
5
T = +85°C
T = –40°C
6
4
2
0
–80
0
–70
–65
–60
CARRIER FEEDTHROUGH (dBm)
AFTER NULLING TO < –65dBm AT +25°C
–55
–50
–45
–70
–60
–50
–40
–30
CARRIER FEEDTHROUGH (dBm)
Figure 37. Carrier Feedthrough Distribution at FLO = 900 MHZ (FBB = 1 MHz,
I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25°C)
Figure 40. Carrier Feedthrough Distribution at Temperature Extremes, After
Carrier Feedthrough Nulled to < - 65 dBm at TA = 25°C. (FLO = 2140 MHz,
I and Q Inputs at a bias of 400 mV)
40
35
30
25
20
15
10
5
30
28
T = +85°C
26
T = –40°C
24
22
20
18
16
14
12
10
8
6
4
2
0
–60
0
–75
–55
–50
–45
–40
–35
–30
–25
–45
–70
–40
–65
–60
–55
–50
–35
SIDEBAND SUPPRESSION (dBc)
AFTER NULLING TO < –50dBc AT +25°C
CARRIER FEEDTHROUGH (dBm)
Figure 38. Carrier Feedthrough Distribution at FLO = 1900 MHz (FBB = 1 MHz,
I and Q Inputs Driven in Quadrature at 1.2 Vp-p, TA = 25°C)
Figure 41. Sideband Suppression Distribution at Temperature Extremes, After
Sideband Suppression Nulled to < -50 dBc at TA = 25°C. (FLO = 2140 MHz,
F
BB = 1 MHz, I and Q Inputs biased at 0.4 V)
24
22
20
18
16
14
12
10
8
6
4
2
0
–70
–65
–60
–55
–50
–45
–40
–35
–30
CARRIER FEEDTHROUGH (dBm)
Figure 39. Carrier Feedthrough Distribution at FLO = 2140 MHz (FBB = 1 MHz,
I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25°C)
Rev. A | Page 13 of 28
AD8349
CIRCUIT DESCRIPTION
OVERVIEW
V-TO-I CONVERTER
The AD8349 can be divided into five sections: the local oscil-
lator (LO) interface, the baseband voltage-to-current (V-to-I)
converter, the mixers, the differential-to-single-ended (D-to-S)
amplifier, and the bias circuit. A detailed block diagram of the
device is shown in Figure 42.
The differential baseband input voltages that are applied to the
baseband input pins are fed to two op amps that perform a
differential voltage-to-current conversion. The differential
output currents of these op amps then feed each of their
respective mixers.
MIXERS
LOIP
The AD8349 has two double-balanced mixers, one for the in-
phase channel (I channel) and one for the quadrature channel
(Q channel). Both mixers are based on the Gilbert cell design of
four cross-connected transistors. The output currents from the
two mixers sum together in a pair of resistor-inductor (R-L)
loads. The signals developed across the R-L loads are sent to the
D-to-S amplifier.
PHASE
SPLITTER
LOIN
IBBP
IBBN
Σ
OUT
QBBP
QBBN
D-TO-S AMPLIFIER
Figure 42. Block Diagram
The output D-to-S amplifier consists of two emitter followers
driving a totem pole output stage. Output impedance is estab-
lished by the emitter resistors in the output transistors. The
output of this stage connects to the output (VOUT) pin.
The LO interface generates two LO signals at 90 degrees of
phase difference to drive two mixers in quadrature. Baseband
signals are converted into currents by the V-to-I converters,
which feed into the two mixers. The outputs of the mixers
combine to feed the differential-to-single-ended amplifier,
which provides a 50 Ω output interface. Reference currents to
each section are generated by the bias circuit. Additionally, the
RF output is controlled by an output enable pin (ENOP), which
is capable of switching the output on and off within 50 ns. A
detailed description of each section follows.
BIAS CIRCUIT
A band gap reference circuit generates the proportional-to-
absolute-temperature (PTAT) reference currents used by
different sections. The band gap reference circuit also generates
a temperature stable current in the V-to-I converters to produce
a temperature independent slew rate.
OUTPUT ENABLE
LO INTERFACE
During normal operation (ENOP = high), the output current
from the V-to-I converters feeds into the mixers, where they
mix with the two phases of LO signals. When ENOP is pulled
low, the V-to-I output currents are steered away from the
mixers, thus turning off the RF output. Power to the final stage
of LO drivers is also removed to minimize LO feedthrough.
Even when the output is disabled, the differential-to-single-
ended stage is still powered up to maintain constant output
impedance.
The LO interface consists of interleaved stages of buffer
amplifiers and polyphase phase splitters. An input buffer
provides a 50 Ω termination to the LO signal source driving
LOIP and LOIN. The buffer also increases the LO signal
amplitude to drive the phase splitter. The phase splitter is
formed by an R-C polyphase network that splits the buffered
LO signal into two parts in precise quadrature phase relation
with each other. Each LO signal then passes through a buffer
amplifier to compensate for the signal loss through the phase
splitter. The two signals pass through another polyphase
network to enhance the quadrature accuracy over the full
operating frequency range. The outputs of the second phase
splitter are fed into the driver amplifiers for the mixers’ LO
inputs.
Rev. A | Page 14 of 28
AD8349
BASIC CONNECTIONS
The basic connections for operating the AD8349 are shown in
Figure 43. A single power supply of between 4.75 V and 5.5 V is
applied to pins VPS1 and VPS2. A pair of ESD protection diodes
connect internally between VPS1 and VPS2, so these must be
tied to the same potential. Both pins should be individually
decoupled using 100 pF and 0.1 μF capacitors to ground. These
capacitors should be located as close as possible to the device.
For normal operation, the output enable pin, ENOP, must be
pulled high. The turn-on threshold for ENOP is 2 V. Pins
COM1, COM2, and COM3 should all be tied to the same
ground plane through low impedance paths.
power of the output signal is at least a crest factor below the
AD8349’s output compression point. Refer to the Applications
section for drive-level considerations in WCDMA and
GSM/EDGE systems.
Reducing the baseband drive level also has the benefit of
increasing the bandwidth of the baseband input. This would
allow the AD8349 to be used in applications requiring a high
modulation bandwidth, e.g., as the IF modulator in high data-
rate microwave radios.
SINGLE-ENDED BASEBAND DRIVE
Where only single-ended I and Q signals are available, a
differential amplifier, such as the AD8132 or AD8138, can be
used to generate the required differential drive signal for the
AD8349.
BASEBAND I AND Q INPUTS
The I and Q inputs should be driven differentially. The typical
differential drive level (as used for characterization measure-
ments) for the I and Q baseband signals is 1.2 V p-p, which is
equivalent to 600 mV p-p on each baseband input. The base-
band inputs have to be externally biased to a level between
400 mV and 500 mV. The optimum level for the best perfor-
mance is 400 mV. The recommended drive level of 1.2 V p-p
does not indicate a maximum drive level. If operation closer to
compression is desired, the 1.2 V p-p differential limit can be
exceeded.
Figure 44 shows an example of a circuit that converts a ground-
referenced, single-ended signal to a differential signal, and adds
the required 400 mV bias voltage.
The baseband inputs can also be driven with a single-ended
signal biased to 400 mV, with the unused inputs biased to
400 mV dc. This mode of operation is not recommended,
however, because any dc level difference between the bias level
of the drive signal and the dc level on the unused input
(including the effect of temperature drift), can result in
increased LO feedthrough. Additionally, the maximum low
distortion output power will be reduced by 6 dB.
For baseband signals with a high peak-to-average ratio (e.g.,
CDDA or WCDMA), the peak signal level will have to be below
the AD8349’s compression level in order to prevent clipping of
the signal peaks. Clipping of signal peaks increases distortion.
In the case of CDMA and WCDMA inputs, clipping results in
an increase of signal leakage into adjacent channels. In general,
the baseband drive should be at a level where the peak signal
QP
IP
IN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
QBBP
QBBN
COM3
COM3
VPS2
IBBP
IBBN
COM1
COM1
LOIN
LOIP
QN
200Ω
+V
5
4
1
2
AD8349
S
100pF
0.1µF
100pF
100pF
T1
ETC1-1-13
VOUT
VOUT
COM3
COM2
100pF
3
LO
VPS1
ENOP
200Ω
+V
S
100pF
0.1µF
Figure 43. Basic Connections
Rev. A | Page 15 of 28
AD8349
+5V
10kΩ
866Ω
+
10µF
0.1µF
100pF
0.1µF
0.1µF
100pF
499Ω
499Ω
49.9Ω
499Ω
24.8Ω
3
8
2
1
I
IN
5
AD8132
0.1µF
VPS1
VPS2
4
6
IBBP
+
IBBN
VOUT
10µF
0.1µF
Σ
499Ω
–5V
+5V
LOIP
LOIN
PHASE
SPLITTER
QBBP
QBBN
+
10µF
0.1µF
AD8349
COM2 COM3
COM1
499Ω
499Ω
49.9Ω
499Ω
24.9Ω
3
8
2
1
Q
IN
5
AD8132
0.1µF
4
6
+
10µF
0.1µF
499Ω
–5V
Figure 44. Single-Ended IQ Drive Circuit
LO INPUT DRIVE LEVEL
LO INPUT IMPEDANCE MATCHING
The local oscillator inputs are designed to be driven differen-
tially. The device is specified with an LO drive level of –6 dBm.
This level was chosen to provide the best noise performance.
Increasing the LO drive level degrades sideband suppression
and increases carrier feedthrough, while improving noise
performance. Reducing the LO drive level creates the opposite
effect: improved sideband suppression and reduced carrier
feedthrough.
Single-ended LO sources are transformed into a differential
signal via a 1:1 balun (ETC1-1-13). A 200 Ω shunt resistor to
GND on each LO input on the device side of the balun reduces
the return loss for the LO input port. Because the LO input pins
are internally dc-biased, ac coupling capacitors must be used on
each LO input pin.
FREQUENCY RANGE
The LO frequency range is from 700 MHz to 2700 MHz. These
limits are defined by the nature of the LO phase splitter
circuitry. The phase splitter generates LO drive signals for the
internal mixers, which are 90 degrees out of phase from each
other. Outside of the specified frequency range (700 MHz to
2700 MHz), this quadrature accuracy degrades, resulting in
poor sideband rejection performance. Figure 45 and Figure 46
show the sideband suppression of a typical device operating
outside the specified LO frequency range. The level of sideband
suppression and degradation is also influenced by manufac-
turing process variations.
Rev. A | Page 16 of 28
AD8349
0
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
4.0
3.5
3.0
2.5
2.0
1.5
1.0
–10
–20
–30
–40
–50
–60
SSB
SINGLE-ENDED LO DRIVE
USB
DIFFERENTIAL LO DRIVE
300
350
400
450
500
550
600
650
700
700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
Figure 48. LO Feedthrough vs. Frequency, Single-Ended vs. Differential LO
Drive (Single-Sideband Modulation)
Figure 45. Sideband Suppression below 700 MHz
–40
–41
0
–1
–2
–3
–4
–5
–6
–7
–8
RF OUTPUT
The RF output is designed to drive a 50 Ω load, but should be
ac-coupled, as shown in Figure 43, because of internal dc
biasing. The RF output impedance is close to 50 Ω and provides
fairly good return loss over the specified operating frequency
range (see Figure 24). As a result, no additional matching
circuitry is required if the output is driving a 50 Ω load. The
output power of the AD8349 under nominal conditions
USB
–42
–43
–44
–45
–46
SSB
(1.2 V p-p differential baseband drive, 400 mV dc baseband
bias, and a 5 V supply) is shown in Figure 7.
–47
–48
OUTPUT ENABLE
2700
2750
2800
2850
2900
2950
3000
The ENOP pin can be used to turn the RF output on and off.
This pin should be held high (greater than 2 V) for normal
operation. Taking ENOP low (less than 800 mV) disables the
output power and provides an off-isolation level of < –50 dBm
at the output.
LO FREQUENCY (MHz)
Figure 46. Sideband Suppression above 2700 MHz
SINGLE-ENDED LO DRIVE
The LO input can be driven single-ended at the expense of
higher LO feedthrough at most frequencies (see Figure 48).
LOIN is ac-coupled to ground, and LOIP is driven through a
coupling capacitor from a single-ended 50 Ω source (see
Figure 47).
Figure 49 and Figure 50 show the enable and disable time
domain responses of the ENOP function at 900 MHz. Typical
enable and disable times are approximately 20 ns and
50 ns, respectively.
8
800
600
400
200
0
A 400 Ω shunt resistor on the signal-source side of the ac
coupling capacitor was used for the measurement.
6
4
2
100pF
5
6
0
LOIN
LOIP
AD8349
100pF
–2
–4
–6
–8
–200
–400
–600
–800
LO
400Ω
Figure 47. Schematic for Single-Ended LO Drive
0
20
40
60
TIME (ns)
80
100
Figure 49. ENOP Enable Time, 900 MHz
Rev. A | Page 17 of 28
AD8349
8
1.50
1.35
1.20
1.05
0.90
0.75
0.60
0.45
0.30
0.15
800
600
400
200
0
6
4
2
0
–2
–4
–6
–200
–400
–600
–800
–8
0
3
1.10
20
40
60
TIME (ns)
80
100
10
100
R3 (Ω)
Figure 50. ENOP Disable Time, 900 MHz
Figure 52. Relationship Between R3 in Figure 51 and Peak
Baseband Input Voltage
BIASING AND FILTERING
BASEBAND DAC INTERFACE
A value of 40 Ω on R1 and R2 in Figure 51 will generate the
required 400 mV dc bias. Note that this is independent of the
value of R3. Figure 52 shows the relationship between the value
of R3 and the peak baseband input voltage with the 40 Ω
resistors in place. From Figure 52, it can be seen that a value of
240 Ω will provide a peak-to-peak swing of approximately
The recommended baseband input swing and bias levels of the
AD8349’s differential baseband inputs allow for direct
connection to most baseband DACs without the need for any
external active components. Typically these DACs have a
differential full-scale output current from 0 mA to 20 mA on
each differential output. These currents can be easily converted
to voltages using ground-referenced shunt resistors. Most
baseband DACs for transmit chains are designed with two
DACs in a single package.
1.2 V p-p differential into the AD8349’s baseband inputs.
The closest available resistor values are 40.2 Ω and 240 Ω, and
these values were used in the characterization of the AD8349
when the DAC was used as a signal source.
AD9777 INTERFACE
The AD977x family of dual DACs is well suited to driving the
baseband inputs of the AD8349. The AD9777 is a dual 16-bit
DAC that can generate either a baseband output or a complex
IF using the device’s complex modulator.
When using a DAC, low-pass image reject filters are typically
used to eliminate images that are produced by the DAC. They
provide the added benefit of eliminating broadband noise that
might feed into the modulator from the DAC.
The basic interface between the AD9777’s IOUT outputs and the
AD8349’s differential baseband inputs is shown in Figure 51.
The Resistors R1 and R2 set the dc bias level, and R3 sets the
amplitude of the baseband input voltage swing.
Figure 53 shows a single sideband spectrum at 2140 MHz. The
baseband sine and cosine signals come from the digital output
of a Rohde & Schwarz AMIQ arbitrary waveform generator.
These signals drive the AD9777 dual DAC, which in turn drives
the AD8349’s baseband inputs. Note that the AD9777’s complex
modulator is not being used.
AD9777
AD8349
73
72
1
2
IBBP
I
OUTA1
OPTIONAL
LOW-PASS
FILTER
Due to offset voltages, internal device mismatch, and imperfect
quadrature over the AD8349’s operating range, the SSB
spectrum has a number of undesirable components such as LO
feedthrough and undesired sideband leakage. When the
AD8349 is driven by a modulated baseband signal, (e.g. 8-PSK,
GMSK, QPSK, or QAM), these nonidealities will manifest
themselves as degraded error vector magnitude (EVM) and
degraded spectral purity.
R1I
R2I
R3I
I
IBBN
OUTB1
16
15
69
68
I
QBBP
QBBN
OUTA2
R1Q
R2Q
OPTIONAL
LOW-PASS
FILTER
R3Q
I
OUTB2
Figure 51. Basic AD9777 to AD8349 Interface
Rev. A | Page 18 of 28
AD8349
10
0
the LO feedthrough is reduced by varying the differential offset
voltages on the I and Q inputs (xBBP – xBBN), not by varying
the nominal bias level of 400 mV. This is easily accomplished by
programming and then storing the appropriate DAC offset code
required to minimize the LO feedthrough. This, however,
requires a dc-coupled path from the DAC to the I and Q inputs.
SSB = 1.7dBm
LO = –44.5dBm
USB = –52dBc
THIRD HARMONIC = –36.8dBc
–10
–20
–30
–40
–50
–60
–70
–80
–90
The procedure for reducing the LO feedthrough is simple. A
differential offset voltage is applied from the I DAC until the LO
feedthrough reaches a trough. With this offset level held, a
differential offset voltage is applied to the Q DAC until a lower
trough is reached (This is an iterative process).
SPAN 10MHz
CENTER 2
.14GHz
Figure 54 shows a plot of LO feedthrough vs. I channel offset (in
mV) after the Q channel offset has been nulled. This suggests
that the compensating offset voltage should have a resolution of
at least 100 µV to reduce the LO feedthrough to be less than –
65 dBm. Figure 55 shows the single sideband spectrum at 2140
MHz after the nulling of the LO. The reduced LO feedthrough
can clearly be seen when compared with the performance
shown in Figure 53.
Figure 53. AD8349 Single Sideband Spectrum at 2140 MHz
REDUCING UNDESIRED SIDEBAND LEAKAGE
Undesired sideband leakage is the result of phase and amplitude
imbalances between the I and Q channel baseband signals.
Therefore, to reduce the undesired sideband leakage, the
amplitude and phase of the baseband signals have to be
matched at the mixer cores. Because of mismatches in the
baseband input paths leading to the mixers, perfectly matched
baseband signals at the pins of the device may not be perfectly
matched when they reach the mixers. Therefore, slight
adjustments have to be made to the phase and amplitudes of the
baseband signals to compensate for these mismatches.
Compensated LO feedthrough degrades somewhat as the LO
frequency is moved away from the frequency at which the
compensation was performed. This variation is very small
across a 30 MHz or 60 MHz cellular band, however. This small
variation is due to the effects of LO-to-RF output leakage
around the package and on the board.
Begin by making one of the inputs, say the I channel, the
reference signal. Then adjust the amplitude and phase of the
Q channel’s signal until the unwanted sideband power reaches a
trough. The AD9777 has built-in gain adjust registers that allow
this to be performed easily. If an iterative adjustment is
performed between the amplitude and the phase, the undesired
sideband leakage can be minimized significantly.
–52
–54
–56
–58
–60
–62
–64
–66
–68
–70
Note that the compensated sideband rejection performance
degrades as the operating baseband frequency is moved away
from the frequency at which the compensation was performed.
As a result, the frequency of the I and Q sine waves should be
approximately half the baseband bandwidth of the modulated
carrier. For example, if the modulator is being used to transmit
a single WCDMA carrier whose baseband spectrum spans from
dc to 3.84/2 MHz, the calibration could be effectively performed
with 1 MHz I and Q sine waves.
3.0
3.5
4.0
4.5
5.0
5.5
IOPP-IOPN (mV)
Figure 54. Plot of LO Feedthrough vs. I Channel Baseband Offset
(Q Channel Offset Nulled)
REDUCTION OF LO FEEDTHROUGH
Because the I and Q signals are being multiplied with the LO,
any internal offset voltages on these inputs will result in leakage
of the LO to the output. Additionally, any imbalance in the LO
to RF in the mixers will also cause the LO signal to leak through
the mixer to the RF output. The LO feedthrough is clearly
visible in the single sideband spectrum. The nominal LO
feedthrough of –42 dBm can be reduced further by applying
offset compensation voltages on the I and Q inputs. Note that
Rev. A | Page 19 of 28
AD8349
10
IMPROVING THIRD HARMONIC DISTORTION
SSB = 1.7dBm
LO = –71.4dBm
0
While sideband suppression can be improved by adjusting the
relative baseband amplitudes and phase, the only means
available to reduce the third harmonic is to reduce the output
power. (See Figure 19, Figure 20, and Figure 21). It is worth
noting, however, that as the output power is reduced, the noise
floor, in dBc, stays fairly constant at the higher end of the power
curve (Figure 56). This indicates that the output power can be
reduced to a level that yields an acceptable third harmonic
without incurring a signal-to-noise ratio penalty. The constant
SNR vs. output power relationship also indicates that baseband
voltage variations can be effectively used to control system
output power and/or regulate signal chain gain.
USB = –52dBc
–10
–20
–30
–40
–50
–60
–70
–80
–90
THIRD HARMONIC = –36.8dBc
SPAN 10MHz
CENTER
2.14GHz
Figure 55. AD8349 Single Sideband Spectrum at 2140 MHz after LO Nulling
6
4
–84
–86
–88
–90
–92
–94
–96
–98
–100
–102
–104
SIDEBAND SUPPRESSION AND LO FEEDTHROUGH
VS. TEMPERATURE
2
940 SSB
1960 SSB
2140 SSB
0
In practical applications, reduction of LO feedthrough and
undesired sideband suppression can be performed as a one time
calibration, with the required correction factors being stored in
nonvolatile RAM. These compensation schemes hold up well
over temperature. Figure 40 and Figure 41 show the variation in
LO feedthrough and sideband suppression over temperature
after compensation is performed at 25°C.
–2
–4
–6
–8
–10
–12
–14
1960 20 MHz NOISE
940 20 MHz NOISE
2140 20 MHz NOISE
SINGLE SIDEBAND PERFORMANCE VS. BASEBAND
DRIVE LEVEL
0.2
0.3
0.4
0.5
0.6
0.8
0.9
1.0
1.1
1.2
0.7
DIFFERENTIAL BASEBAND DRIVE (V p-p)
Figure 56 shows the SSB output power and noise floor in
dBc/100 kHz versus baseband drive level at LO frequencies of
940 MHz, 1960 MHz, and 2140 MHz.
Figure 56. SSB POUT and 20 MHz Noise Floor vs. Baseband Drive Level
(FLO = 940 MHz, 1960 MHz, and 2140 MHz)
Rev. A | Page 20 of 28
AD8349
APPLICATIONS
–147
–148
–149
–150
–151
–152
–153
–154
–155
–156
–62
–63
–64
–65
–66
–67
–68
–69
–70
–71
–72
3GPP WCDMA SINGLE-CARRIER APPLICATION
The interpolation filter used for the measurement of WCDMA
performance is shown in Figure 57. This third order Bessel filter
has a 3 dB bandwidth of 12 MHz. While the 3GPP single
channel bandwidth is only 3.84 MHz, this wide 3 dB bandwidth
of 12 MHz was driven by the need for a flat group delay out to
at least half the bandwidth of the baseband signal. Figure 58
shows a plot of a WCDMA spectrum at 2140 MHz using the
3 GPP Test Model 1 (64 channels active). At an output power of
–17.3 dBm, an adjacent channel power ratio (ACPR) just shy of
–69 dBc was measured.
1960 ADJ CPR
2140 ADJ CPR
1960 NOISE
2140 NOISE
–157
–8
–26
–24
–22
–20
–16
–14
–12
–10
CHANNEL POWER (DBM)
Figure 59 shows the variation in ACPR with output power at
1960 MHz and 2140 MHz. It also shows the noise floor
measured at an offset of 30 MHz from the center of the modu-
lated WCDMA signal. From the graphs, it can be seen that there
is an optimal output power at which to operate that delivers the
best ACPR. If the output power is increased beyond that point,
the ACPR degrades as the result of increased distortion. Below
that optimum, the ACPR degrades due to a reduction in the
signal-to-noise ratio of the signal.
Figure 59. Single-Carrier WCDMA ACPR and Noise Floor (dBm/Hz) at 30 MHz
Carrier Offset vs. Channel Power at 1960 MHz and 2140 MHz
(Test Model 1 with 64 Active Channels)
WCDMA MULTICARRIER APPLICATION
The high dynamic range of the AD8349 also permits use in
multicarrier WCDMA applications. Figure 60 shows a 4-carrier
WCDMA spectrum at 1960 MHz. At a per-carrier power of
–24.2 dBm, an ACPR of –60.4dB is achieved. Figure 61 shows
the variation in ACP and noise floor (dBc/Hz) with output
power.
AD9777
AD8349
680nH
–30
73
72
1
2
CH PWR = –24.2dBm
I
IBBP
OUTA1
ADJ CPR = –60.4dB
–40
40.2Ω
40.2Ω
ALT CPR = –63.1dB
270pF
680nH
680nH
100pF
240Ω
–50
–60
I
IBBN
QBBP
QBBN
OUTB1
–70
69
68
16
15
I
OUTA2
OUTB2
–80
40.2Ω
40.2Ω
270pF
680nH
100pF
240Ω
–90
–100
–110
–120
–130
I
Figure 57. Single-Carrier WCDMA Application Circuit
(DAC-Modulator Interconnect)
SPAN 40MHz
CENTER
4MHz/
1.96GHz
–33
–40
CH PWR = –17.3dBm
ADJ CPR = –68.7dB
ALT CPR = –72.7dB
Figure 60. 4-Carrier WCDMA Spectral Plot at 1960 MHz,
Including Adjacent and Alternate Channel Power Ratio
–50
–60
–70
–80
–90
–100
–110
–120
–130
ADJ
LO
ALT
UP
ALT
LO
ADJ
UP
CH
SPAN 24.6848MHz
CENTER
2.14GHz
Figure 58. Single-Carrier WCDMA Spectral Plot at 2140 MHz,
including Adjacent and Alternate Channel Power Ratio
Rev. A | Page 21 of 28
AD8349
–144
–146
–148
–150
–152
–154
–156
–54
–55
–56
–57
–58
–59
–60
–61
–62
–63
–64
–65
–66
–50
–55
4.0
3.5
3.0
2.5
2.0
1.5
1.0
–60
–65
2140 ADJ CPR
1960 ADJ CPR
400kHz
–70
600kHz
–75
–80
–85
PEAK NOISE FLOOR
–90
EVM
2140 ALT CPR
1960 ALT CPR
–95
–100
–105
–110
1960 NOISE
2140 NOISE
AVERAGE NOISE FLOOR
–29 –28 –27 –26 –25 –24 –23 –22 –21 –20 –19 –18 –17
–14
–12
–10
–8
–6
–4
–2
0
2
4
CHANNEL POWER (dBm)
CHANNEL POWER (dBm)
Figure 63. 8-PSK EVM, Spectral Performance, and Noise Floor
vs. Channel Power (Frequency = 885 MHz)
Figure 61. 4-Carrier WCDMA Adjacent and Alternate Channel Power Ratio
and 50 MHz Noise Floor (dBm/Hz) vs. Per-Channel Power
at 1960 MHz and 2140 MHz
–50
4.0
3.5
3.0
2.5
2.0
1.5
1.0
–55
–60
GSM/EDGE APPLICATION
Figure 62 and Figure 64 show plots of GMSK error vector
magnitude (EVM), spectral performance, and noise floor
(dBc/100 kHz at 6 MHz carrier offset) at 885 MHz and
1960 MHz. Based on spectral performance, a maximum output
power level of around 2 dBm is appropriate. Note, however, that
as the output power decreases below this level, there is only a
very slight increase in the dBc noise floor. This indicates that
baseband drive variation can be used to control or correct the
gain of the signal chain over a range of at least 5 dB, with little
or no SNR penalty.
–65
400kHz
–70
–75
600kHz
–80
PEAK NOISE FLOOR
–85
–90
AVERAGE NOISE FLOOR
–95
–100
–105
–110
EVM
–1
CHANNEL POWER (dBm)
–13
–11
–9
–7
–5
–3
1
3
5
Figure 63 and Figure 65 show plots of 8-PSK EVM, spectral
performance, and noise floor at 885 MHz and 1960 MHz.
Figure 64. GMSK EVM, Spectral Performance, and Noise Floor
vs. Channel Power (Frequency = 1960 MHz)
An LO drive level of approximately –6 dBm is recommended
for GMSK and 8-PSK. A higher LO drive power will improve
the noise floor slightly; however, it also tends to degrade EVM.
–50
4.0
3.5
3.0
2.5
2.0
1.5
1.0
–55
–60
–50
–55
4.0
3.5
3.0
2.5
2.0
1.5
1.0
–65
400kHz
–70
–60
–75
EVM
400kHz
600kHz
–65
–80
–70
–85
600kHz
–75
PEAK NOISE FLOOR
AVERAGE NOISE FLOOR
–90
–80
–95
–85
–100
–105
–110
PEAK NOISE FLOOR
–90
–95
EVM
–2
–14
–12
–10
–8
–6
–4
0
2
–100
–105
–110
CHANNEL POWER (dBm)
AVERAGE NOISE FLOOR
Figure 65. 8-PSK EVM, Spectral Performance, and Noise Floor vs. Channel
Power (Frequency = 1960 MHz)
–10
–8
–6
–4
–2
0
2
4
6
CHANNEL POWER (dBm)
Figure 62.GMSK EVM, Spectral Performance, and Noise Floor
vs. Channel Power (Frequency = 885 MHz)
Rev. A | Page 22 of 28
AD8349
Table 5. ADF4360 Family Operating Frequencies
SOLDERING INFORMATION
ADI Model
ADF4360-1
ADF4360-2
ADF4360-3
ADF4360-4
ADF4360-5
ADF4360-6
ADF4360-7
Output Frequency Range (MHz)
The AD8349 is available in a 16-lead TSSOP package with an
exposed paddle. The exposed paddle must be soldered to the
exposed metal of a ground plane for a lowered thermal
impedance and reduced inductance to ground. This results in a
junction-to-air thermal impedance (θJA) of 30°C/W. If multiple
ground planes are present, the area under the exposed paddle
should be stitched together with vias.
2150/2450
1800/2150
1550/1950
1400/1800
1150/1400
1000/1250
Lower frequencies set by external L
LO GENERATION USING PLLS
Analog Devices has a line of PLLs that can be used for
generating the LO signal. Table 4 lists the PLLs together with
their maximum frequency and phase noise performance.
TRANSMIT DAC OPTIONS
The AD9777 recommended in the previous sections of this data
sheet is by no means the only DAC that can be used to drive the
AD8349. There are other DACs that are appropriate, depending
on the level of performance required. Table 6 lists the dual
Tx-DACs that ADI offers.
Table 4. ADI PLL Selection Table
Frequency FIN
(MHz)
At 1 kHz Phase Noise
dBc/Hz, 200 kHz PFD
ADI Model
ADF4111BRU 1200
ADF4111BCP 1200
ADF4112BRU 3000
ADF4112BCP 3000
ADF4117BRU 1200
ADF4118BRU 3000
–78
–78
–86
–86
–87
–90
Table 6. ADI Dual Tx – DAC Selection Table
Part
Resolution (Bits)
Update Rate (MSPS Min)
AD9709
AD9761
AD9763
AD9765
AD9767
AD9773
AD9775
AD9777
8
125
40
10
10
12
14
12
14
16
125
125
125
160
160
160
Analog Devices also offers the ADF4360 fully integrated
synthesizer and VCO on a single chip that offers differential
outputs for driving the local oscillator input of the AD8349.
This means that the user can eliminate the use of the balun
necessary for the single-ended-to-differential conversion. The
ADF4360 comes as a family of chips with six operating
frequency ranges. One can be chosen depending on the local
oscillator frequency required. The user should be aware that
while the use of the integrated synthesizer might come at the
expense of slightly degraded noise performance from the
AD8349, it can be a much cheaper alternative to a separate PLL
and VCO solution. Figure 61 shows the options available.
Rev. A | Page 23 of 28
AD8349
EVALUATION BOARD
designed without any components on the underside of the
board so that heat may be applied under the AD8349 for easy
removal and replacement of the DUT.
A populated AD8349 evaluation board is available.
The AD8349 has an exposed paddle underneath the package,
which is soldered to the board. The evaluation board is
YuPing Toh
Mike Chowkwanyun
Figure 66. Layout of Evaluation Board, Top Layer
Figure 67. Evaluation Board Silkscreen
Table 7. Evaluation Board Configuration Options
Component
Function
Default Condition
TP1, TP4, TP3
Power Supply and Ground Vector Pins.
Not applicable
SW1, ENOP,
TP2
Output Enable: Place in the A position to connect the ENOP pin to +VS via pull-up resistor R10.
Place in the B position to disable the device by grounding the pin ENOP through a 49.9 Ω pull-
down resistor. The device may be enabled via an external voltage applied to the SMA connector
ENOP or TP2.
SW1 = A
R1, R2, R5, R9,
C8–C11
Baseband Input Filters: These components can be used to implement a low-pass filter for the
baseband signals.
R1, R2, R5, R9 = 0 Ω,
C8 – C11 = OPEN
Rev. A | Page 24 of 28
AD8349
C8
C9
OPEN
OPEN
AD8349
QBBP
R1
R2
QP
QN
IP
IN
IBBP
IBBN
COM1
COM1
LOIN
LOIP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
0Ω
0Ω
R9
R5
QBBN
COM3
COM3
VPS2
0Ω
0Ω
C11
OPEN
C10
OPEN
TP3
VPOS
TP4
GND
TP1
GND
R3
C1
200Ω
R11
100pF
C2
+V
S
0Ω
C5
100pF
C6
R6
0.1µF
OPEN
100pF
VOUT
COM3
COM2
T1
LO
+V
R4
ETC-1-1-13
200Ω
VPS1
ENOP
C7
100pF
VOUT
S
R7
C3
C4
0Ω
0.1µF
100pF
TP2
ENOP
R10
10kΩ
A
B
ENOP
R8
49.9Ω
Figure 68. Evaluation Board Schematic
Rev. A | Page 25 of 28
AD8349
CHARACTERIZATION SETUPS
SSB SETUP
The primary setup used to characterize the AD8349 is shown in
Figure 69. This setup was used to evaluate the product as a
single-sideband modulator. The interface board has circuitry
that converts the single-ended I and Q inputs from the arbitrary
function generator to differential inputs with a dc bias of
400 mV. Additionally, the interface board provides connections
for power supply routing. The HP34970A and its associated
plug-in 34901 were used to monitor power supply currents and
voltages being supplied to the AD8349 characterization board.
Two HP34907 plug-ins were used to provide additional
miscellaneous dc and control signals to the interface board. The
LO input was driven directly by an RF signal generator and the
output was measured directly with a spectrum analyzer. With
the I channel driven by a sine wave and the Q channel by a
cosine wave, the lower sideband is the single sideband (SSB)
output. The typical SSB output spectrum is shown in Figure 53.
IEEE
D1
HP34970A
D2
34907
D2
D3
34901
34907
D3
D1
TEKAFG2020
OUTPUT_1
OUTPUT_2
+15V MAX
COM
VPS1
I_IN
INTERFACE
BOARD
IEEE
IEEE
+25V MAX
–25V MAX
Q_IN
VN
GND
VP
ARB FUNCTION GEN
HP3631
P1 IN IP QP QN
IP
QP
QN
IN
AD8349
AGILENT
E4437B
CHARACTERIZATION
BOARD
HP8561E
LO
IEEE
RFOUT
VOUT
RF I/P
ENOP
P1
SPECTRUM
ANALYZER
IEEE
IEEE
PC CONTROLLER
Figure 69. Characterization Board SSB Test Setup
Rev. A | Page 26 of 28
AD8349
OUTLINE DIMENSIONS
5.10
5.00
4.90
BOTTOM
VIEW
16
9
8
4.50
4.40
4.30
EXPOSED
PAD
(Pins Up)
TOP
VIEW
6.40
BSC
3.00
SQ
1
1.05
1.00
0.80
1.20 MAX
0.20
0.09
8°
0°
0.15
0.00
0.65
BSC
0.30
0.19
0.75
0.60
0.45
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-ABT
Figure 70. 16-Lead Thin Shrink Small Outline with Exposed Pad [TSSOP/EP]
(RE-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range (°C)
Package Description
Package Option
AD8349ARE
–40 to +85
–40 to +85
–40 to +85
–40 to +85
16-Lead TSSOP, Tube
16-Lead TSSOP, 7" Tape and Reel
16-Lead TSSOP, Tube
16-Lead TSSOP, 7" Tape and Reel
Evaluation Board
RE-16
RE-16
RE-16
RE-16
AD8349ARE-REEL7
AD8349AREZ1
AD8349AREZ-REEL71
AD8349-EVAL
1 Z = Pb-free part.
Rev. A | Page 27 of 28
AD8349
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03570-0-11/04(A)
Rev. A | Page 28 of 28
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