AD5291ABRUZ20 [ADI]
IC 20K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14, MO-153AB-1, TSSOP-14, Digital Potentiometer;
| 型号： | AD5291ABRUZ20 |
| 厂家： | 
ADI |
| 描述： | IC 20K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO14, MO-153AB-1, TSSOP-14, Digital Potentiometer 光电二极管 转换器 电阻器 |
| 文件： | 总17页 (文件大小：387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Channel, 256/1024-Position, 1% R-Tol, Digital
Potentiometer with 20-Times Programmable Memory
Preliminary Technical Data
AD5291/AD5292
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Single-channel, 256/1024-position resolution
20 kΩ, 50 kΩ and 100 kΩ nominal resistance
Calibrated 1% Nominal Resistor Tolerance
20-Time Programmable (20-TP) set-and-forget resistance
setting allows multiple time permanent programming
Rheostat mode temperature coefficient: 35 ppm/°C
Voltage divider temperature coefficient: 5 ppm/°C
+21V to +30V single-supply operation
10.5V to 15V dual-supply operation
SPI® compatible serial interface
Wiper setting readback
Power-on refreshed from 20-TP memory
APPLICATIONS
Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage to current conversion
Programmable filters, delays, time constants
Programmable power supply
Figure 1. 14ld TSSOP
Low resolution DAC replacement
Sensor calibration
The AD5291/2 device wiper settings are controllable through
the SPI digital interface. Unlimited adjustments are allowed
before programming the resistance value into the 20-TP (20
Time Programmable) memory. The AD5291/2 do not require
any external voltage supply to facilitate fuse blow and there are
20 opportunities for permanent programming. During 20-TP
activation, a permanent blow fuse command freezes the wiper
position (analogous to placing epoxy on a mechanical trimmer).
GENERAL DESCRIPTION
The AD5291/2 are single-channel, 256/1024-position digital
potentiometers1 with less than 1% end-to-end Resistor
Tolerance error and 20-Time Programmable Memory. The
AD5291/2 perform the same electronic adjustment function as
a mechanical potentiometer with enhanced resolution, solid
state reliability, and superior low temperature coefficient
performance. These devices are capable of operating at high-
voltages; supporting both dual supply 10.5 to 15ꢀ and single
supply operation +21ꢀ to +30ꢀ.
The AD5291/2 are available in a compact 14ld TSSOP package.
The part is guaranteed to operate over the extended industrial
temperature range of −40°C to +105°C.
The AD5291/2 offer guaranteed industry leading low resistor
tolerance errors of ±1% with a nominal temperature coefficient
of 35 ppm/ºC. The low resistor tolerance feature simplifies
open-loop applications as well as precision calibration and
tolerance matching applications.
1 The terms digital potentiometer and RDAC are used interchangeably.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2008 Analog Devices, Inc. All rights reserved.
AD5291/AD5292
Preliminary Technical Data
TABLE OF CONTENTS
REVISION HISTORY
Revision: Preliminary ꢀersion
Rev.PrA | Page 2 of 17
Preliminary Technical Data
AD5291/AD5292
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS – AD5291
ꢀDD = 21ꢀ to 30ꢀ, ꢀSS = 0ꢀ; ꢀDD = 10.5ꢀ to 16.5ꢀ, ꢀSS = -10.5ꢀ to -16.5ꢀ; ꢀLOGIC = 2.7ꢀ to 5.5ꢀ, ꢀA = ꢀDD, ꢀB = ꢀSS , −40°C < TA < +105°C,
unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS— RHEOSTAT MODE
Resolution
N
8
Bits
LSB
LSB
%
ppm/°C
Ω
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
R-DNL
R-INL
∆RAB/RAB
(∆RAB/RAB)/∆T × 106
RWB
−1
−0.5
−1
+1
+0.5
+1
0.5
35
TBD
RW
TBD
DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE
Resolution
N
8
Bits
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature
Coefficient
DNL
INL
−1
−0.5
+1
+0.5
LSB
LSB
ppm/°C
(∆VW/VW)/∆T × 106
Code = half-scale
5
Full-Scale Error
Zero-Scale Error
VWFSE
VWZSE
Code = full scale
Code = zero scale
−2
0
0
TBD
LSB
LSB
RESISTOR TERMINALS
Terminal Voltage Range5
Capacitance6 A, B
VA, B, W
CA, B
VSS
VDD
V
pF
f = 1 MHz, measured to GND,
Code = half-scale
f = 1 MHz, measured to GND,
Code = half-scale
50
Capacitance6 W
CW
ICM
40
pF
Common-Mode Leakage Current6
DIGITAL INPUTS
VA = VB = VW
0.001
50
nA
JEDEC compliant
Input Logic High
VIH
VIH
VIL
IIL
VLOGIC = 4.5V to 5.5 V
VLOGIC = 2.7V to 3.6 V
VLOGIC = 2.7V to 5.5 V
VIN = 0 V or VLOGIC
2.0
1.8
V
V
V
ꢀA
pF
Input Logic Low
Input Current
Input Capacitance6
0.8
1
CIL
5
DIGITAL OUTPUTS(SDO and RDY)
Output High Voltage
VOH
VOL
RPULL_UP = 2.2kΩ to VLOGIC
RPULL_UP = 2.2kΩ to VLOGIC
VLOGIC
0.4
-
V
V
Output Low Voltage
Gnd
+0.4V
1
Three state Leakage Current
Output Capacitance6
-1
ꢀA
pF
COL
5
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
Logic Supply Range
VDD
VDD/VSS
IDD
ISS
VLOGIC
ILOGIC
ILOGIC
ILOGIC_PROG
ILOGIC_FUSE_READ
VSS = 0 V
21
10.5
30
V
V
16.5
TBD
TBD
5.5
TBD
TBD
VDD / VSS = 16.5 V
VDD /VSS = 16.5 V
TBD
TBD
ꢀA
ꢀA
V
ꢀA
ꢀA
mA
mA
2.7
Logic Supply Current
VLOGIC = 5 V; VIH = 5 V or VIL = GND
VLOGIC = 3 V; VIH = 3 V or VIL = GND
VIH = 5 V or VIL = GND
TBD
TBD
TBD
TBD
OTP Store Current6,7
OTP Read Current6,8
VIH = 5 V or VIL = GND
Rev. PrA | Page 3 of 17
AD5291/AD5292
Preliminary Technical Data
Parameter
Symbol
PDISS
PSSR
Conditions
Min
Typ1
Max
Unit
ꢀW
%/%
Power Dissipation9
VIH = 5 V or VIL = GND
∆VDD/∆VSS = 15 V 10%
TBD
TBD
Power Supply Rejection Ratio6
DYNAMIC CHARACTERISTICS6, 10
Bandwidth
0.0006 0.002
TBD
BW
THDW
−3 dB
kHz
dB
Total Harmonic Distortion
VA = 1 V rms, VB = 0 V, f = 1 kHz
RAB = 20 kΩ
RAB = 50 kΩ
-90
-99
-99
RAB = 100 kΩ
VW Settling Time
tS
VA = 10 V, VB = 0 V,
1 LSB error band,
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
1
2.5
5
ꢀs
Resistor Noise Density
eN_WB
RWB = 5 kΩ, TA = 25°C,
TBD
Hz
nV/√
1 Typicals represent average readings at 25°C,VDD = 15 V, VSS = -15 V and VLOGIC = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions.
3
1% resistor tolerance code range; RAB = 20KΩ: 63 to 1,023 for | VDD - VSS | = 26V to 30V and 96 to 1,023 for | VDD - VSS | = 21V to 26V; RAB = 50KΩ: 32 to 1,023 for | VDD
VSS | = 26V to 30V and 43 to 1,023 for | VDD - VSS | = 21V to 26V; RAB = 100KΩ: 20 to 1,023 for | VDD - VSS | = 26V to 30V and 27 to 1,023 for | VDD - VSS | = 21V to 26V;
-
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0V. DNL specification limits of
1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment.
6 Guaranteed by design and not subject to production test.
7 Different from operating current; supply current for fuse program lasts approximately TBDꢀs.
8 Different from operating current; supply current for fuse read lasts approximately TBDꢀs..
9 PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC).
10 All dynamic characteristics use VDD = +15 V, VSS = −15 V and VLOGIC = 5 V.
Rev. PrA | Page 4 of 17
Preliminary Technical Data
AD5291/AD5292
ELECTRICAL CHARACTERISTICS – AD5292
ꢀDD = 21ꢀ to 30ꢀ, ꢀSS = 0ꢀ; ꢀDD = 10.5ꢀ to 16.5ꢀ, ꢀSS = -10.5ꢀ to -16.5ꢀ; ꢀLOGIC = 2.7ꢀ to 5.5ꢀ, ꢀA = ꢀDD, ꢀB = ꢀSS , −40°C < TA < +105°C,
unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS— RHEOSTAT MODE
Resolution
N
10
−1
−1
Bits
LSB
LSB
LSB
LSB
%
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
R-DNL
R-INL
RWB
+1
+1
+1.5
+2
+1
RAB = 50KΩ, 100KΩ
R-INL
RAB = 20KΩ, |VDD − VSS | = 26V to 30V −1.5
RAB = 20KΩ, |VDD − VSS | = 21V to 26V −2
−1
R-INL
∆RAB/RAB
(∆RAB/RAB)/∆T × 106
RW
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
Wiper Resistance
0.5
35
TBD
ppm/°C
Ω
TBD
DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE
Resolution
N
10
Bits
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature
Coefficient
DNL
INL
−1
−1
+1
+1
LSB
LSB
ppm/°C
(∆VW/VW)/∆T × 106
Code = half-scale
5
Full-Scale Error
Zero-Scale Error
VWFSE
VWZSE
Code = full scale
Code = zero scale
−6
0
0
TBD
LSB
LSB
RESISTOR TERMINALS
Terminal Voltage Range5
Capacitance6 A, B
VA, B, W
CA, B
VSS
VDD
V
pF
f = 1 MHz, measured to GND,
Code = half-scale
f = 1 MHz, measured to GND,
Code = half-scale
50
Capacitance6 W
CW
ICM
40
pF
Common-Mode Leakage Current6
DIGITAL INPUTS
VA = VB = VW
0.001
50
nA
JEDEC compliant
Input Logic High
VIH
VIH
VIL
IIL
VLOGIC = 4.5V to 5.5 V
VLOGIC = 2.7V to 3.6 V
VLOGIC = 2.7V to 5.5 V
VIN = 0 V or VLOGIC
2.0
1.8
V
V
V
ꢀA
pF
Input Logic Low
Input Current
Input Capacitance6
0.8
1
CIL
5
DIGITAL OUTPUTS(SDO and RDY)
Output High Voltage
VOH
VOL
RPULL_UP = 2.2kΩ to VLOGIC
RPULL_UP = 2.2kΩ to VLOGIC
VLOGIC
0.4
-
V
V
Output Low Voltage
Gnd
+0.4V
1
Three state Leakage Current
Output Capacitance6
-1
ꢀA
pF
COL
5
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
Logic Supply Range
VDD
VDD/VSS
IDD
ISS
VLOGIC
ILOGIC
ILOGIC
ILOGIC_PROG
ILOGIC_FUSE_READ
VSS = 0 V
21
10.5
30
V
V
16.5
TBD
TBD
5.5
TBD
TBD
VDD / VSS = 16.5 V
VDD /VSS = 16.5 V
TBD
TBD
ꢀA
ꢀA
V
ꢀA
ꢀA
mA
mA
2.7
Logic Supply Current
VLOGIC = 5 V; VIH = 5 V or VIL = GND
VLOGIC = 3 V; VIH = 3 V or VIL = GND
VIH = 5 V or VIL = GND
TBD
TBD
TBD
TBD
OTP Store Current6,7
OTP Read Current6,8
VIH = 5 V or VIL = GND
Rev. PrA | Page 5 of 17
AD5291/AD5292
Preliminary Technical Data
Parameter
Symbol
PDISS
PSSR
Conditions
Min
Typ1
Max
Unit
ꢀW
%/%
Power Dissipation9
VIH = 5 V or VIL = GND
∆VDD/∆VSS = 15 V 10%
TBD
TBD
Power Supply Rejection Ratio6
DYNAMIC CHARACTERISTICS6, 10
Bandwidth
0.0006 0.002
TBD
BW
THDW
−3 dB
kHz
dB
Total Harmonic Distortion
VA = 1 V rms, VB = 0 V, f = 1 kHz
RAB = 20 kΩ
RAB = 50 kΩ
-90
-99
-99
RAB = 100 kΩ
VW Settling Time
tS
VA = 10 V, VB = 0 V,
1 LSB error band,
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
1
2.5
5
ꢀs
Resistor Noise Density
eN_WB
RWB = 5 kΩ, TA = 25°C,
TBD
Hz
nV/√
1 Typicals represent average readings at 25°C,VDD = 15 V, VSS = -15 V and VLOGIC = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.
R-DNL measures the relative step change from ideal between successive tap positions.
3
1% resistor tolerance code range; RAB = 20KΩ: 250 to 1,023 for | VDD - VSS | = 26V to 30V and 383 to 1,023 for | VDD - VSS | = 21V to 26V; RAB = 50KΩ: 128 to 1,023 for |
VDD - VSS | = 26V to 30V and 172 to 1,023 for | VDD - VSS | = 21V to 26V; RAB = 100KΩ: 83 to 1,023 for | VDD - VSS | = 26V to 30V and 105 to 1,023 for | VDD - VSS | = 21V to
26V;
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0V. DNL specification limits of
1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment.
6 Guaranteed by design and not subject to production test.
7 Different from operating current; supply current for fuse program lasts approximately TBDꢀs.
8 Different from operating current; supply current for fuse read lasts approximately TBDꢀs..
9 PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC).
10 All dynamic characteristics use VDD = +15 V, VSS = −15 V and VLOGIC = 5 V.
Rev. PrA | Page 6 of 17
Preliminary Technical Data
AD5291/AD5292
INTERFACE TIMING SPECIFICATIONS
ꢀDD / ꢀSS = ±15 ꢀ, ꢀLOGIC = 2.7ꢀ to 5.5ꢀ, and −40°C < TA < + 105°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Unit
ns min
Test Conditions/Comments
Unit1
2
t1
t2
t3
20
10
10
15
5
SCLK cycle time
SCLK high time
ns min
ns min
ns min
ns min
ns min
ns min
ꢀs min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ꢀs max
SCLK low time
t4
SYNC to SCLK falling edge setup time
Data setup time
t5
t6
5
Data hold time
t7
0
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
t8
TBD
13
t9
SYNC rising edge to next SCLK fall ignore
RDY rise to SYNC falling edge
SYNC rise to RDY fall time
3
3
3
3
3
3
3
3
t10
t11
t12
t12
t13
t13
t14
t15
TBD
TBD
TBD
TBD
TBD
TBD
125
RDY Low Time – RDAC Register write command execute time
RDY Low Time – Memory Program execute time
RDY Low Time – RDAC Register readback execute time
RDY Low Time – Memory readback execute time
SCLK rising edge to SDO valid
SCLK to SDO Data hold time
TBD(40)
TBD
tOTP
Power-on OTP restore time
1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 50 MHz
3 RPULL_UP = 2.2kΩ to VLOGIC
Figure 2. AD5291 Input Register Content
Figure 3. AD5292 Input Register Content
Rev. PrA | Page 7 of 17
AD5291/AD5292
Preliminary Technical Data
TIMING DIAGRAMS
Figure 4. Write Timing Diagram
Figure 5. Read Timing Diagram
Rev. PrA | Page 8 of 17
Preliminary Technical Data
AD5291/AD5292
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
VSS to GND
VLOGIC to GND
VDD to VSS
–0.3 V, +35 V
+0.3 V, −16.5 V
-0.3 V to +7 V
35 V
VA, VB, VW to GND
VSS−0.3 V, VDD+0.3 V
IA, IB, IW
Pulsed1
TBD mA
Continuous
20KΩ End-to-End resistance
50KΩ and 100 KΩ End-to-End resistance
Digital Input and Output Voltage to GND
Operating Temperature Range2
Maximum Junction Temperature (TJ max)
Storage Temperature
Reflow Soldering
3 mA
2 mA
-0.3 V to VLOGIC +0.3 V
−40°C to +105°C
150°C
−65°C to +150°C
Peak Temperature
260°C
Time at peak temperature
Thermal Resistance Junction-to-Ambient3
θJA,TSSOP-14
20 sec to 40 sec
93°C/W
Thermal Resistance Junction-to-Case3 θJC,
TSSOP-14
20°C/W
Package Power Dissipation
(TJ max − TA)/θJA
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Includes programming of OTP memory.
3 Thermal Resistance (JEDEC 4 layer(2S2P) board).
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 9 of 17
AD5291/AD5292
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 6. 14-pin TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic
Description
1
RESET
Hardware reset pin. Refreshes the RDAC register with the contents of the 20-TP memory register. Factory
default loads midscale until the first 20-TP wiper memory location is programmed. RESET is activated at the
logic high transition. Tie RESET to VLOGIC if not used.
2
VSS
Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1µF
ceramic capacitors and 10 µF capacitors.
3
4
5
6
7
8
A
Terminal A of RDAC. VSS ≤ VA ≤ VDD
W
Wiper terminal of RDAC. VSS ≤ VW ≤ VDD
B
Terminal B of RDAC. VSS ≤ VB ≤ VDD
VDD
Positive Power Supply. This pin should be decoupled with 0.1µF ceramic capacitors and 10 µF capacitors.
Connect a 1µF capacitor to MEM_CAP.
MEM_CAP
VLOGIC
Logic Power Supply; 2.7V to 5.5V. This pin should be decoupled with 0.1µF ceramic capacitors and 10 µF
capacitors.
9
10
GND
DIN
Ground Pin, Logic Ground Reference.
Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
11
12
SCLK
SYNC
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 50 MHz.
Falling edge Synchronisation signal.
This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift
register and data is transferred in on the falling edges of the following clocks. The selected DAC register is
updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high before the 16th clock
cycle the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
13
14
SDO
RDY
Serial Data Output. Open Drain Output requires external pull-up resistor. SDO can be used to clock data from
the serial register in daisy chain or readback mode.
Ready pin. Active-high open-drain output. Identifies the completion of a write or read operation to/from the
DAC Register or Memory.
Rev. PrA | Page 10 of 17
Preliminary Technical Data
THEORY OF OPERATION
AD5291/AD5292
RDAC register content regardless of the software commands,
except that the RDAC register can be refreshed from the 20-TP
memory using the software reset command (command #4) or
The AD5291/2 digital potentiometers are designed to operate as
a true variable resistors for analog signals that remain within
the terminal voltage range of ꢀSS < ꢀTERM < ꢀDD. The digital
potentiometer wiper position is determined by the RDAC
register contents. The RDAC register acts as a scratchpad
register, allowing as many value changes as necessary to place
the potentiometer wiper in the correct position. The RDAC
register can be programmed with any position setting using the
standard SPI serial interface by loading the 16-bit data-word.
Once a desirable position is found, this value can be stored in a
20-TP memory register. Thereafter, the wiper position is always
restored to that position for subsequent power-up. The storing
of 20-TP data takes approximately TBD; during this time, the
shift register is locked, preventing any changes from taking
place. The RDY pin pulses low to indicate the completion of
this 20-TP storage.
through hardware by the
pin. To enable programming
RESET
of the variable resistor wiper position (programming the RDAC
register) the write protect bit C1 of the control register must
first be programmed. This is accomplished by loading the serial
data input register with Command #6 (Table 7). To enable
programming of the 20-TP memory block bit C0 of the control
register, set to 0 by default, must first be set to ‘1’.
BASIC OPERATION
The basic mode of setting the variable resistor wiper position
(programming the RDAC register) is accomplished by loading
the serial data input register with Command #1 (Table 8) and
the desired wiper position data. When the desired wiper
position is determined, the user can load the serial data input
register with Command #3 (Table 8) which stores the wiper
position data in the 20-TP memory register. After TBD (µs), the
wiper position is permanently stored in the 20-TP memory. The
The AD5291/2 also features a patented 1% end-to-end resistor
tolerance. This simplifies precision, rheostat mode, and open-
loop applications where knowledge of absolute resistance is
critical.
pin can be used to monitor the completion of this 20-TP
RDY
program. Table 6, provides a programming example listing the
sequence of serial data input (DIN) words with the serial data
output appearing at the SDO pin in hexadecimal format.
RDAC REGISTER AND 20-TP MEMORY
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with all zeros, the wiper is connected to Terminal B of
the variable resistor. The RDAC register is a standard logic
register; there is no restriction on the number of changes
allowed. Once a desirable wiper position is found, this value can
be saved into a 20-TP memory register (Table 6). Thereafter the
wiper position will always be set at that position for any future
ON-OFF-ON power supply sequence. The AD5291/2 have an
array of 20 OTP (One-Time Programmable) memory registers.
When the desired word is programmed to 20-TP memory the
device automatically verifies that the program command was
successful. Bit C3 of the Control register can be polled to verify
that the fuse program command was successful. Programming
data to 20-TP memory consumes approximately 4mA and takes
approximately TBDms, during this time the shift register is
locked preventing any changes from taking place. The RDY pin
can be used to monitor the completion of the 20-TP memory
program and verification. No change in supply voltage is
required to program the 20-TP memory however a 1µF
capacitor on the MEM_CAP pin is required (Figure 11). Prior
to 20-TP activation, the AD5291/2 preset to mid-scale on
power-up.
Table 6. Write and Read to RDAC and 20-TP memory
DIN
SDO
Action
0x1803
0xXXXX
Enable update of wiper position
and 20-TP memory contents
through digital interface
0x0600
0x1803
Write 0x100 to the RDAC register,
Wiper moves to ¼ fullscale
position.
0x0800
0x0C00
0x0600
0x100
Prepare data read from RDAC
Register.
Stores RDAC register content into
20-TP memory. 16-bit word
appears out of SDO, where last 10-
bits contain the contents of the
RDAC Register(0x100).
0x1C00
0x0000
0x0C00
Prepare data read from Control
Register
0xXXXX
NOP instruction 0 sends 16-bit
word out of SDO, where last 10-
bits contain the contents of the
Control Register. If bit C3 = 1,
Fuse program command
successful.
WRITE PROTECTION
On power-up, serial data input register write commands for
both the RDAC register and the 20-TP memory registers are
disabled. The RDAC write protect bit, C1 of the control register
(Table 9), is set to 0 by default. This disables any change of the
Rev. PrA | Page 11 of 17
AD5291/AD5292
Preliminary Technical Data
(TBD) µA and places the RDAC in a zero-power-consumption
state where Terminal Ax is open-circuited and the Wiper Wx is
connected to Terminal Bx.
20-TP READBACK AND SPARE MEMORY STATUS
It is possible to read back the contents of any of the 20-TP
memory registers through SDO by using Command #5 (Table
8). The lower 5 LSB bits, (D0 to D4) of the data byte select
which memory location is to be read back (see Table 10). Data
from the selected memory location will be clocked out of the
SDO pin during the next SPI operation, where the last 10-bits
contain the contents of the specified memory location
RESET
A low to high transition of the hardware
pin loads the
RESET
RDAC Register with the contents of the most recently
programmed 20-TP memory location. The AD5291/2 can also
be reset through software by executing command 4(Table 8).
It is also possible to calculate the address of the most recently
programmed memory location by reading back the contents of
read only memory address locations 0x014 and 0X015 using
Command #5. The data bytes read back from memory address
locations 0x014 and 0X015 are a thermometer encoded version
of the address of the last programmed memory location.
If no 20-Tp memory location is programmed then the RDAC
Register will be loaded with midscale on reset.
SERIAL DATA INTERFACE
The AD5291/2 contain a serial interface (
, SCLK, DIN
SYNC
and SDO), which is compatible with SPI interface standards, as
well as most DSPs. This device allows writing of data via the
serial interface to every register.
For the example outlined in Table 7 the address of the last
programmed location is calculated as:
(# of Bits = ‘1’ in Memory Address 0X14) + (# of Bits = ‘1’ in
Memory Address 0X15) - 1
INPUT SHIFT REGISTER
For the AD5291/2 the input shift register is 16 bits wide (see
Figures 2 and 3). The 16-bit word consists of two unused bits
(should be set to zero), followed by four control bits, and ten
RDAC data bits, the lower 2 DAC data bits are don’t cares for
the AD5291. Data is loaded MSB first (Bit 15). The four control
bits determine the function of the software command (see Table
8). Figure 4 shows a timing diagram of a typical AD5291/2 write
sequence.
= 10 + 8 -1 =17 (0x10)
If no memory location has been programmed then the address
generated is -1.
Table 7. Example 20-TP Memory Readback
DIN
SDO
Action
0x1414
0xXXXX
Prepares data read from memory
location 0x14.
The write sequence begins by bringing the
line low. The
SYNC
pin must be held low until the complete data-word is
SYNC
loaded from the DIN pin. When
returns high, the serial
SYNC
0x1415
0x0000
0x03FF
0x00FF
Prepares data read from memory
location 0x15. Sends 16-bit word
out of SDO, where last 10-bits
contain the contents of memory
location 0x14
data-word is decoded according to the instructions in Table 8.
The command bits (Cx) control the operation of the digital
potentiometer. The data bits (Dx) are the values that are loaded
into the decoded register. The AD5291/2 have an internal
counter that counts a multiple of 16 bits (a frame) for proper
operation. For example, AD5291/2 work with a 32-bit word, but
cannot work properly with a 31-bit or 33-bit word. The
AD5291/2 do not require a continuous SCLK and dynamic
power can be saved by only transmitting clock pulses during a
serial write. All interface pins should be operated at close to the
supply rails to minimize power consumption in the digital input
buffers.
NOP instruction 0 sends 16-bit
word out of SDO, where last 10-
bits contain the contents of
memory location 0x15
0x1410
0x0000
0x0000
Prepares data read from memory
location 0x10
0xXXXX
NOP instruction 0 sends 16-bit
word out of SDO, where last 10-
bits contain the contents of
memory location 0x10(17)
DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes. It can be
used to read the contents of the wiper setting or the internal
memory values using Commands 2 and 5, respectively (see
Table 8) or it can be used for daisy chaining multiple devices.
The remaining instructions are valid for daisy-chaining
multiple devices in simultaneous operations. Daisy-chaining
minimizes the number of port pins required from the
POWER-DOWN MODE
The AD5291/2 can be powered down by executing the software
powerdown command, command 8 (Table 8), and setting the
LSB to 1. This feature reduces the power supply current to
controlling IC (see Figure 7). The SDO pin contains an open-
Rev. PrA | Page 12 of 17
Preliminary Technical Data
AD5291/AD5292
drain N-Ch FET that requires a pull-up resistor, if this function
is used. As shown in Figure 7, users need to tie the SDO pin of
one package to the DIN pin of the next package. Users might
need to increase the clock period, because the pull-up resistor
and the capacitive loading at the SDO–DIN interface might
require additional time delay between subsequent devices.
then pulled high to complete the operation.
When two AD5291/2s are daisy-chained, 32 bits of data are
required. The first 16 bits go to U2, and the second 16 bits go to
U1. The
pin should be kept low until all 32 bits are
SYNC
clocked into their respective serial registers. The
pin is
SYNC
Figure 7. Daisy-Chain Configuration Using SDO
Table 8. Command Operation Truth Table
Command
Data
B8 B7
Operation
B0
B13
C3
0
B9
Command
Number
C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
NOP: Do nothing.
0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of Serial Register Data to
RDAC.
2
3
4
5
6
7
8
0
0
0
0
0
0
1
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Read RDAC wiper setting from SDO
output in the next frame.
Store Wiper Setting: Store RDAC setting
to TTP.
Reset: Refresh RDAC with 20-TP stored
value.
D4 D3 D2 D1 D0 Read contents of 20-TP or Status of 20-TP
from SDO output in the next frame.
X
X
X
X
X
X
D2 D1 D0 Write Contents of Serial Register Data to
Control Register
X
X
X
Read Control Register from SDO output in
the next frame.
X
X
D0 Software Powerdown
D0 = 0; Normal Mode
D0 = 1; Device placed in powerdown
mode
Rev. PrA | Page 13 of 17
AD5291/AD5292
Preliminary Technical Data
Table 9. Control Register and special function codes
Register Name
Data Byte
Operation
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Control
X
X
X
X
X
X
C3 C2 C1 C0
C0 = 20-TP Program Enable
0 = 20-TP program disabled(Default)
1 = Enable device for 20-TP program
C1 = RDAC Register Write Protect.
0 = Wiper position frozen to value in memory(Default)1
1 = Allow update of wiper position through Digital Interface
C2 = Calibration Enable.
0 = RDAC Resistor Tolerance Calibration enabled(Default)
1 = RDAC Resistor Tolerance Calibration enabled
C3 = 20-Tp Memory Program Success Bit.
0 = Fuse program command unsuccessful(Default)
1 = Fuse program command successful
1 Wiper position frozen to value last programmed in 20-TP memory. Wiper will be frozen to mid-scale if 20-TP memory has not been previously programmed
Table 10. Memory Map
Data Byte (Address)
Command
Number
Register Contents
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1st programmed wiper location (0X00)
5
2nd programmed wiper location (0X01)
3rd programmed wiper location (0X02)
4th programmed wiper location (0X03)
5th programmed wiper location (0X04)
10th programmed wiper location (0X09)
15th programmed wiper location (0X0E)
20th programmed wiper location (0X13)
Programmed memory status (Thermometer encoded)1 (0X14)
Programmed memory status (Thermometer encoded)1 (0X15)
1 Allows user to calculate remaining spare memory locations
Rev. PrA | Page 14 of 17
Preliminary Technical Data
AD5291/AD5292
maximum of 1% absolute resistance error over both the full
supply and temperature ranges. As a result, the general
equations for determining the digitally programmed output
resistance between the W terminal and B terminal are
AD5291:
RDAC ARCHITECTURE
In order to achieve optimum cost performance, Analog Devices
has patented the RDAC segmentation architecture for all the
digital potentiometers. In particular, the AD5291/2 employ a
3-stage segmentation approach as shown in Figure 8. The
AD5291/2 wiper switch is designed with the transmission gate
D
RWB (D) =
× RAB
(1)
CMOS topology and with the gate voltage derived from ꢀDD
.
256
AD5292:
D
RWB (D) =
× RAB
(2)
1,024
where:
D is the decimal equivalent of the binary code loaded in
the 8/10-bit RDAC register.
R
AB is the end-to-end resistance.
Similar to the mechanical potentiometer, the resistance of
the RDAC between the W terminal and the A terminal also
produces a digitally controlled complementary resistance, RWA
.
RWA is also calibrated to give a maximum of 1% absolute
resistance error. RWA starts at the maximum resistance value
and decreases as the data loaded into the latch increases. The
general equations for this operation are
AD5291:
256 − D
RWA (D) =
× RAB
(1)
256
AD5292:
1,024 − D
RWA (D) =
× RAB
(2)
Figure 8. AD5291/2 Simplified RDAC Circuit.
1,024
where:
D is the decimal equivalent of the binary code loaded in
the 8/10-bit RDAC register.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation - 1% Resistor Tolerance
R
AB is the end-to-end resistance.
The AD5291/2 operate in rheostat mode when only two termi-
nals are used as a variable resistor. The unused terminal can
be floating or tied to the W terminal as shown in Figure 9.
In the zero-scale condition, a finite total wiper resistance of
TBD Ω is present. Regardless of which setting the part is oper-
ating in, care should be taken to limit the current between
the A terminal to B terminal, W terminal to A terminal, and
W terminal to B terminal, to the maximum continuous current of
3 mA(20KΩ) or 2 mA(50KΩ and 100 KΩ) or pulse current of
TBD mA. Otherwise, degradation, or possible destruction of the
internal switch contact, can occur.
Figure 9. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
RAB, is available in 20 kΩ, 50 kΩ, and 100 kΩ and has 256/1,024
tap points accessed by the wiper terminal. The 8/10-bit data in
the RDAC latch is decoded to select one of the 256/1,024
possible wiper settings. The AD5291/2 contain an internal
1% resistor tolerance calibration feature which can be disabled
or enabled, enabled by default, by programming bit C2 of the
control register (see Table 9). The digitally programmed output
resistance between the W terminal and the A terminal, RWA and
the W terminal and B terminal, RWB, is calibrated to give a
Rev. PrA | Page 15 of 17
AD5291/AD5292
Preliminary Technical Data
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider
at wiper to B and wiper to A proportional to the input voltage
at A to B as shown in Figure 10. Unlike the polarity of ꢀDD to
GND, which must be positive, voltage across A to B, W to A,
and W to B can be at either polarity.
Figure 11. Hardware setup for MEM_CAP pin
TERMINAL VOLTAGE OPERATING RANGE
The AD5291/2’s positive ꢀDD and negative ꢀSS power supplies
define the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on Terminals
A, B, and W that exceed ꢀDD or ꢀSS are clamped by the internal
forward-biased diodes (see Figure 12).
Figure 10. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for simplicity, con-
necting the A terminal to 30 ꢀ and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 ꢀ to 1 LSB less than 30 ꢀ. Each LSB of voltage
is equal to the voltage applied across Terminal A and Terminal B,
divided by the 256/1,024 positions of the potentiometer divider.
The general equations defining the output voltage at ꢀW with
respect to ground for any valid input voltage applied to Terminal
A and Terminal B are
V
DD
A
W
B
AD5291:
D
256− D
256
VW (D) =
×VA +
×VB
(5)
V
SS
256
Figure 12. Maximum Terminal Voltages Set by VDD and V SS
AD5292:
The ground pin of the AD5291/2 device is primarily used as a
digital ground reference. To minimize the digital ground
bounce, the AD5291/2 ground terminal should be joined
remotely to the common ground. The digital input control
signals to the AD5291/2 must be referenced to the device
ground pin (GND), and satisfy the logic level defined in the
Specifications section.
D
1,024 − D
VW (D) =
×VA +
×VB
(6)
1,024
1,024
In voltage divider mode, to optimize wiper position update rate,
it is recommended to disable the internal 1% resistor tolerance
calibration feature by programming bit C2 of the control
register (Table 9).
Power-Up Sequence
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
To ensure the AD5291/2 power up correctly a 1uF cap must be
connected to the MEM_CAP pin. Because there are diodes to
limit the voltage compliance at Terminals A, B, and W (Figure
12), it is important to power ꢀDD/ꢀSS first before applying any
voltage to Terminals A, B, and W. Otherwise, the diode is
forward-biased such that ꢀDD/ꢀSS are powered unintentionally.
The ideal power-up sequence is GND, ꢀDD/ꢀSS, ꢀLOGIC, digital
inputs, and ꢀA, ꢀB, and ꢀW. The order of powering ꢀA, ꢀB, ꢀW,
and digital inputs is not important as long as they are powered
MEM_CAP CAPACITOR
A 1µF capacitor to GND must be connected to the MEM_CAP
pin (Figure 11) on power-up and throughout the operation of
the AD5291/2.
after ꢀDD/ꢀSS and ꢀLOGIC
.
Regardless of the power-up sequence and the ramp rates of the
power supplies, once ꢀLOGIC is powered, the power-on preset
activates, which restores the 20-TP memory value to the RDAC
registers.
Rev. PrA | Page 16 of 17
Preliminary Technical Data
AD5291/AD5292
OUTLINE DIMENSIONS
Figure 13. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)
Dimensions shown in millimeters
ORDERING GUIDE
RAB
(kΩ)
Resolution
Memory
Temperature
Range
Package
Package
Option
Model
Description
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
AD5291ABRUZ20
AD5291ABRUZ50
AD5291ABRUZ100
AD5292ABRUZ20
AD5292ABRUZ50
AD5292ABRUZ100
20
50
100
20
50
100
256
256
256
1,024
1,024
1,024
20-TP
20-TP
20-TP
20-TP
20-TP
20-TP
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
©
2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07674-0-7/08(PrA)
Rev. PrA | Page 17 of 17
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