AD5291BRUZ-100-RL7_技术文档

256-/1024-Position, Digital Potentiometers with

Maximum 1ꢀ ꢁ-ꢂoleranꢃe ꢄrror anꢅ 20-ꢂP Memorꢆ

AD5291/AD5292

FEATURES

FUNCTIONAL BLOCK DIAGRAM

V

RESET

DD

Single-channel, 256-/1024-position resolution

20 kΩ, 50 kΩ, and 100 kΩ nominal resistance

Maximum 1ꢀ nominal resistor tolerance error (resistor

performance mode)

20-times programmable wiper memory

Rheostat mode temperature coefficient: 35 ppm/°C

Voltage divider temperature coefficient: 5 ppm/°C

+9 V to +33 V single-supply operation

9 V to 16.5 V dual-supply operation

SPI-compatible serial interface

POWER-ON

RESET

AD5291/

AD5292

V

LOGIC

RDAC

REGISTER

SCLK

SYNC

A

DATA

SERIAL

INTERFACE

W

OTP

MEMORY

BLOCK

DIN

B

Wiper setting readback

SDO

Power-on refreshed from 20-TP memory

RDY

APPLICATIONS

V

EXT_CAP

GND

SS

Mechanical potentiometer replacement

Instrumentation: gain and offset adjustment

Programmable voltage-to-current conversion

Programmable filters, delays, and time constants

Programmable power supply

Figure 1.

Low resolution DAC replacement

Sensor calibration

GENERAL DESCRIPTION

The AD5291 and AD5292 are single-channel, 256-/1024-

position digital potentiometers¹that combine industry leading

variable resistor performance with nonvolatile memory (NVM)

in a compact package. These devices are capable of operating

across a wide voltage range, supporting both dual supply

operation at 10.5 V to 16.5 V and single supply operation at

+21 V to +33 V, while ensuring less than 1% end-to-end resistor

tolerance error and offering 20-time programmable (20-TP)

memory.

The AD5291 and AD5292 device wiper settings are controllable

through the SPI digital interface. Unlimited adjustments are

allowed before programming the resistance value into the

20-TP memory. The AD5291 and AD5292 do not require any

external voltage supply to facilitate fuse blow, and there are 20

opportunities for permanent programming. During 20-TP

activation, a permanent blow fuse command freezes the wiper

position (analogous to placing epoxy on a mechanical trimmer).

The AD5291 and AD5292 are available in a compact 14-lead

TSSOP package. The part is guaranteed to operate over the

extended industrial temperature range of −40°C to +105°C.

The guaranteed industry leading low resistor tolerance error

feature simplifies open-loop applications as well as precision

calibration and tolerance matching applications.

¹The terms digital potentiometer and RDAC are used interchangeably.

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD5291/AD5292

ꢂABLꢄ OF CONꢂꢄNꢂS

Features .............................................................................................. 1

20-TP Memory ........................................................................... 23

Write Protection ......................................................................... 23

Basic Operation .......................................................................... 24

20-TP Readback and Spare Memory Status ........................... 24

Shutdown Mode ......................................................................... 24

Resistor Performance Mode...................................................... 25

Reset............................................................................................. 25

SDO Pin and Daisy-Chain Operation..................................... 25

RDAC Architecture.................................................................... 25

Programming the Variable Resistor......................................... 26

Programming the Potentiometer Divider............................... 26

EXT_CAP Capacitor.................................................................. 27

Terminal Voltage Operating Range ......................................... 27

Applications Information.............................................................. 28

High Voltage DAC...................................................................... 28

Programmable Voltage Source with Boosted Output ........... 28

High Accuracy DAC .................................................................. 28

Variable Gain Instrumentation Amplifier .............................. 28

Audio Volume Control .............................................................. 29

Outline Dimensions....................................................................... 30

Ordering Guide .......................................................................... 30

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—AD5291 .......................................... 3

Resistor Performance Mode Code Range ................................. 4

Electrical Characteristics—AD5292 .......................................... 6

Resistor Performance Mode Code Range ................................. 7

Interface Timing Specifications.................................................. 8

Absolute Maximum Ratings.......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Typical Performance Characteristics ........................................... 12

Test Circuits..................................................................................... 21

Theory of Operation ...................................................................... 22

Serial Data Interface................................................................... 22

Shift Register ............................................................................... 22

RDAC Register............................................................................ 22

REVISION HISTORY

Changes to Table 1.............................................................................3

Changes to Table 2.............................................................................4

Added Table 3 ....................................................................................5

Changes to Table 4.............................................................................6

Changes to Table 5.............................................................................7

Added Table 6 ....................................................................................8

Change to Table 7 ..............................................................................8

Changes to Absolute Maximum Rating Section ........................ 10

Changes Table 9 .............................................................................. 11

Changes to Typical Performance Characteristics Section ........ 12

Changes to Ordering Guide.......................................................... 30

9/10—Rev. C to Rev. D

Changes to SDO Pin and Daisy-Chain Operation Section....... 25

3/10—Rev. B to Rev. C

Changes to Revision History........................................................... 2

Changes to Figure 3 and Figure 4 Captions .................................. 9

3/10—Rev. A to Rev. B

Changes to Data Sheet Title ............................................................ 1

Changes to General Description Section ...................................... 1

Changes to Theory of Operation Section.................................... 22

4/09—Revision 0: Initial Version

12/09—Rev. 0 to Rev. A

Added 50 kΩ and 100 kΩ specifications .........................Universal

Changes to Features Section............................................................ 1

Rev. D | Page 2 of 32

AD5291/AD5292

SPꢄCIFICAꢂIONS

ELECTRICAL CHARACTERISTICS—AD5291

V_DD= 21 V to 33 V, V_SS= 0 V; V_DD= 10.5 V to 16.5 V, V_SS= −10.5 V to −16.5 V; V_LOGIC= 2.7 V to 5.5 V, V_A= V_DD, V_B= V_SS,

−40°C < T_A< +105°C, unless otherwise noted.

Table 1.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution

N

8

Bits

LSB

%

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

Nominal Resistor Tolerance (R-Perf Mode)³

Nominal Resistor Tolerance (Normal Mode)

Resistance Temperature Coefficient⁴

Wiper Resistance

R-DNL

R_WB, V_A= NC

−1

+1

R-INL

∆R_AB/R_AB

(∆R_AB/R_AB)/∆T × 1±⁶

R_W

±±.5

±ꢀ

See Table 2, Table 3

%

35

ppm/°C

Ω

Code = full-scale; See Figure 38

Code= zero scale

6±

1±±

DC CHARACTERISTICS—POTENTIOMETER

DIVIDER MODE

Resolution

N

8

Bits

Differential Nonlinearity⁵

Integral Nonlinearity⁵

Voltage Divider Temperature Coefficient⁴

Full-Scale Error

DNL

−±.5

+±.5

LSB

INL

LSB

(∆V_W/V_W)/∆T × 1±⁶

1.5

ppm/°C

LSB

Code = half-scale; See Figure 41

Code = full scale

V_WFSE

V_WZSE

−2

±

+±.25

2

Zero-Scale Error

Code = zero scale

LSB

RESISTOR TERMINALS

Terminal Voltage Range⁶

Capacitance A, Capacitance B⁴

V_A, V_B, V_W

C_A, C_B

V_SS

V_DD

V

f = 1 MHz, measured to GND,

code = half-scale

85

65

±1

pF

Capacitance W⁴

C_W

I_CM

f = 1 MHz, measured to GND,

code = half-scale

pF

Common-Mode Leakage Current⁴

DIGITAL INPUTS

V_A= V_B= V_W

nA

JEDEC compliant

Input Logic High⁴

Input Logic Low⁴

V_IH

V_IL

I_IL

V_LOGIC= 2.ꢀ V to 5.5 V

V_IN= ± V or V_LOGIC

2.±

V

±.8

±1

V

Input Current

Input Capacitance⁴

μA

pF

C_IL

5

DIGITAL OUTPUTS (SDO and RDY)

Output High Voltage⁴

Output Low Voltage⁴

Three-State Leakage Current

Output Capacitance⁴

POWER SUPPLIES

V_OH

V_OL

R_{PULL_UP}= 2.2 kΩ to V_LOGIC

V_LOGIC− ±.4

−1

V

GND + ±.4 V

+1

V

μA

pF

C_OL

Single-Supply Power Range

Dual-Supply Power Range

Positive Supply Current

Negative Supply Current

Logic Supply Range

V_DD

V_SS= ± V

9

33

V

V_DD/V_SS

I_DD

±9

±16.5

2

V

V_DD/V_SS= ±16.5 V

±.1

μA

V

I_SS

−2

−±.1

V_LOGIC

I_LOGIC

2.ꢀ

5.5

1±

Logic Supply Current

OTP Store Current^{4, ꢀ}

OTP Read Current^{4, 8}

V_LOGIC= 5 V; V_IH= 5 V or V_IL= GND

V_IH= 5 V or V_IL= GND

∆V_DD/∆V_SS= ±15 V ± 1±%

R_AB= 2± kΩ

1

μA

mA

μW

%/%

I_{LOGIC_PROG}

I_{LOGIC_FUSE_READ}

P_DISS

25

8

Power Dissipation⁹

11±

Power Supply Rejection Ratio

PSRR

±.1±3

±.±39

±.±21

R_AB= 5± kΩ

R_AB= 1±± kΩ

Rev. D | Page 3 of 32

AD5291/AD5292

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DYNAMIC CHARACTERISTICS^{5, 1±}

Bandwidth

BW

−3 dB, code = half-scale

R_AB= 2± kΩ

kHz

52±

21±

1±5

R_AB= 5± kΩ

R_AB= 1±± kΩ

Total Harmonic Distortion

V_WSettling Time

THD_W

V_A= 1 V rms, V_B= ± V, f = 1 kHz

R_AB= 2± kΩ

dB

−93

R_AB= 5± kΩ

−1±1

−1±6

R_AB= 1±± kΩ

t_S

V_A= 3± V, V_B= ± V, ±±.5 LSB error

band, initial code = zero scale,

board capacitance = 1ꢀ± pF

Code = full-scale, normal mode

Code = full-scale, R-Perf mode

Code = half-scale, normal mode

R_AB= 2± kΩ

ꢀ5±

2.5

ns

μs

2.5

ꢀ

R_AB= 5± kΩ

R_AB= 1±± kΩ

14

Code = half-scale, R-Perf mode

R_AB= 2± kΩ

μs

5

R_AB= 5± kΩ

9

R_AB= 1±± kΩ

16

Resistor Noise Density

e_{N_WB}

Code = half-scale, T_A= 25°C, ± kHz

to 2±± kHz

nV/√Hz

R_AB= 2± kΩ

R_AB= 5± kΩ

R_AB= 1±± kΩ

1±

18

2ꢀ

¹Typical values represent average readings at 25°C, V_DD= 15 V, V_SS= −15 V, and V_LOGIC= 5 V.

²Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the R_WBat code ±x±2 to code ±xFF or between R_WAat code ±xFD to

code ±x±±. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with

a wiper current of 1 mA for V_A< 12 V and 1.2 mA for V_A≥ 12 V.

³Resistor performance mode (see the Resistor Performance Mode section). The terms resistor performance mode and R-Perf mode are used interchangeably.

⁴Guaranteed by design and characterization, not subject to production test.

⁵INL and DNL are measured at V_WBwith the RDAC configured as a potentiometer divider similar to a voltage output DAC. V_A= V_DDand V_B= ± V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

⁶Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-

referenced bipolar signal adjustment.

^ꢀDifferent from operating current; supply current for fuse program lasts approximately 55± μs.

⁸Different from operating current; supply current for fuse read lasts approximately 55± μs.

⁹P_DISSis calculated from (I_DD× V_DD) + (I_SS× V_SS) + (I_LOGIC× V_LOGIC).

^1±All dynamic characteristics use V_DD= 15 V, V_SS= −15 V, and V_LOGIC= 5 V.

RESISTOR PERFORMANCE MODE CODE RANGE

Table 2.

R_AB= 20 kΩ

|V_DD− V_SS| = 26 V to 30 V |V_DD− V_SS| = 22 V to 26 V

Resistor

Tolerance per

Code

|V_DD− V_SS| = 30 V to 33 V

|V_DD− V_SS| = 21 V to 22 V

R_WB

R_WA

R_WB

R_WA

R_WB

R_WA

R_WB

R_WA

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

From ±x5A

to ±xFF

From ±x23

to ±xFF

From ±x1E

to ±xFF

From ±x±±

to ±xA5

From ±x±±

to ±xDC

From ±x±±

to ±xE1

From ±xꢀD

to ±xFF

From ±x2D

to ±xFF

From ±x19

to ±xFF

From ±x±±

to ±x82

From ±x±±

to ±xD2

From ±x±±

to ±xE6

From ±xꢀD

to ±xFF

From ±x23

to ±xFF

From ±x1ꢀ

to ±xFF

From ±x±±

to ±x82

From ±x±±

to ±xDC

From ±x±±

to ±xE8

N/A

From ±x23

to ±xFF

From ±x1ꢀ

to ±xFF

From ±x±±

to ±xDC

From ±x±±

to ±xE8

Rev. D | Page 4 of 32

AD5291/AD5292

Table 3.

R_AB= 50 kΩ

|V_DD− V_SS| = 26 V to 33 V |V_DD− V_SS| = 21 V to 26 V

R_AB= 100 kΩ

|V_DD− V_SS| = 26 V to 33 V |V_DD− V_SS| = 21 V to 26 V

Resistor Tolerance

per Code

R_WB

R_WA

R_WB

R_WA

R_WB

R_WA

R_WB

R_WA

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

From ±x2A

to ±xFF

From ±x11

to ±xFF

From ±x±A

to ±xFF

From ±x±±

to ±xD5

From ±x±±

to ±xEE

From ±x±±

to ±xF5

From ±x3ꢀ

to ±xFF

From ±x16

to ±xFF

From ±x±D

to ±xFF

From ±x±±

to ±xC8

From ±x±±

to ±xE9

From ±x±±

to ±xF2

From ±x1E

to ±xFF

From ±x±A

to ±xFF

From ±x±ꢀ

to ±xFF

From ±x±±

to ±xE1

From ±x±±

to ±xF5

From ±x±±

to ±xF8

From ±x14

to ±xFF

From ±x±A

to ±xFF

From ±x±ꢀ

to ±xFF

From ±x±±

to ±xEB

From ±x±±

to ±xF5

From ±x±±

to ±xF8

Rev. D | Page 5 of 32

AD5291/AD5292

ELECTRICAL CHARACTERISTICS—AD5292

V_DD= 21 V to 33 V, V_SS= 0 V; V_DD= 10.5 V to 16.5 V, V_SS= −10.5 V to −16.5 V; V_LOGIC= 2.7 V to 5.5 V, V_A= V_DD, V_B= V_SS,

−40°C < T_A< +105°C, unless otherwise noted.

Table 4.

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution

Resistor Differential Nonlinearity²

Resistor Integral Nonlinearity²

N

1±

−1

−2

−3

−1

Bits

LSB

%

R-DNL

R-INL

∆R_AB/R_AB

R_WB, V_A= NC

+1

+2

+3

+1

R

_AB=5± kΩ, 1±± kΩ

R_AB=2± kΩ , |V_DD− V_SS| = 26 V to 33 V

R_AB=2± kΩ , |V_DD− V_SS| = 21 V to 26 V

See Table 5 and Table 6

Nominal Resistor Tolerance (R-Perf Mode)³

±±.5

±ꢀ

Nominal Resistor Tolerance (Normal

Mode)⁴

%

Resistance Temperature Coefficient

Wiper Resistance

(∆R_AB/R_AB)/∆T × 1±⁶

R_W

35

6±

ppm/°C

Ω

Code = full scale; See Figure 38

Code= zero scale

1±±

DC CHARACTERISTICS—POTENTIOMETER

DIVIDER MODE

Resolution

N

1±

Bits

Differential Nonlinearity⁵

Integral Nonlinearity⁵

Voltage Divider Temperature Coefficient⁴

Full-Scale Error

DNL

−1

+1

LSB

INL

−1.5

+1.5

LSB

(∆V_W/V_W)/∆T × 1±⁶

5

ppm/°C

LSB

Code = half scale; See Figure 41

Code = full scale

V_WFSE

V_WZSE

−8

±

+1

8

Zero-Scale Error

Code = zero scale

LSB

RESISTOR TERMINALS

Terminal Voltage Range⁴

Capacitance A, Capacitance B⁶

V_A, V_B, V_W

C_A, C_B

V_SS

V_DD

V

f = 1 MHz, measured to GND,

code = half scale

85

65

±1

pF

Capacitance W⁵

C_W

I_CM

f = 1 MHz, measured to GND,

code = half scale

pF

Common-Mode Leakage Current⁴

DIGITAL INPUTS

V_A= V_B= V_W

nA

JEDEC compliant

Input Logic High⁴

Input Logic Low⁴

V_IH

V_IL

I_IL

V_LOGIC= 2.ꢀ V to 5.5 V

V_IN= ± V or V_LOGIC

2.±

V

±.8

±1

V

Input Current

Input Capacitance⁴

μA

pF

C_IL

5

DIGITAL OUTPUTS (SDO and RDY)

Output High Voltage⁴

Output Low Voltage⁴

Three-State Leakage Current

Output Capacitance⁴

POWER SUPPLIES

V_OH

V_OL

R_{PULL_UP}= 2.2 kΩ to V_LOGIC

V_LOGIC− ±.4

−1

V

GND + ±.4

+1

V

μA

pF

C_OL

Single-Supply Power Range

Dual-Supply Power Range

Positive Supply Current

Negative Supply Current

Logic Supply Range

V_DD

V_SS= ± V

9

33

V

V_DD/V_SS

I_DD

±9

±16.5

2

V

V_DD/V_SS= ±16.5 V

±.1

μA

V

I_SS

−2

−±.1

V_LOGIC

I_LOGIC

2.ꢀ

5.5

1±

Logic Supply Current

OTP Store Current^{6, ꢀ}

OTP Read Current^{6, 8}

Power Dissipation⁹

Power Supply Rejection Ratio⁶

V_LOGIC= 5 V; V_IH= 5 V or V_IL= GND

V_IH= 5 V or V_IL= GND

∆V_DD/∆V_SS= ±15 V ± 1±%

R_AB= 2± kΩ

1

μA

mA

μW

%/%

I_{LOGIC_PROG}

I_{LOGIC_FUSE_READ}

P_DISS

25

8

11±

PSSR

±.1±3

±.±39

±.±21

R_AB= 5± kΩ

R_AB= 1±± kΩ

Rev. D | Page 6 of 32

AD5291/AD5292

Parameter

Symbol

Conditions

Min

Typ¹

Max

Unit

DYNAMIC CHARACTERISTICS^{5, 1±}

Bandwidth

BW

−3 dB

kHz

R_AB= 2± kΩ

R_AB= 5± kΩ

R_AB= 1±± kΩ

52±

21±

1±5

Total Harmonic Distortion

V_WSettling Time

THD_W

V_A= 1 V rms, V_B= ± V, f = 1 kHz

R_AB= 2± kΩ

dB

−93

R_AB= 5± kΩ

−1±1

−1±6

R_AB= 1±± kΩ

t_S

V_A= 3± V, V_B= ± V, ±±.5 LSB error

band, initial code = zero scale, board

capacitance = 1ꢀ± pF

Code = full-scale, normal mode

Code = full-scale, R-Perf mode

Code = half-scale, normal mode

R_AB= 2± kΩ

ꢀ5±

2.5

ns

μs

2.5

ꢀ

R_AB= 5± kΩ

R_AB= 1±± kΩ

14

Code = half-scale, R-Perf mode

R_AB= 2± kΩ

μs

5

R_AB= 5± kΩ

9

R_AB= 1±± kΩ

16

Resistor Noise Density

e_{N_WB}

Code = half-scale, T_A= 25°C, ± kHz to

2±± kHz

nV/√Hz

R_AB= 2± kΩ

R_AB= 5± kΩ

R_AB= 1±± kΩ

1±

18

2ꢀ

¹Typical values represent average readings at 25°C, V_DD= 15 V, V_SS= −15 V, and V_LOGIC= 5 V.

²Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the R_WBat code ±x±±B to code ±x3FF or between R_WAat code ±x3F3 to

code ±x±±±. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with

a wiper current of 1 mA for V_A< 12 V and 1.2 mA for V_A≥ 12 V.

³Resistor performance mode (see the Resistor Performance Mode section). The terms resistor performance mode and R-Perf mode are used interchangeably.

⁴Guaranteed by design and characterization, not subject to production test.

⁵INL and DNL are measured at V_Wwith the RDAC configured as a potentiometer divider similar to a voltage output DAC. V_A= V_DDand V_B= ± V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

⁶Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-

referenced bipolar signal adjustment.

^ꢀDifferent from operating current; supply current for fuse program lasts approximately 55± μs.

⁸Different from operating current; supply current for fuse read lasts approximately 55± μs.

⁹P_DISSis calculated from (I_DD× V_DD) + (I_SS× V_SS) + (I_LOGIC× V_LOGIC).

^1±All dynamic characteristics use V_DD= 15 V, V_SS= −15 V, and V_LOGIC= 5 V.

RESISTOR PERFORMANCE MODE CODE RANGE

Table 5.

R_AB= 20 kΩ

|V_DD− V_SS| = 26 V to 30 V |V_DD− V_SS| = 22 V to 26 V

R_WBR_WAR_WBR_WA

From ±x1F4 From ±x±±± From ±x1F4 From ±x±±± N/A

Resistor

Tolerance per

Code

|V_DD− V_SS| = 30 V to 33 V

|V_DD− V_SS| = 21 V to 22 V

R_WB

R_WA

R_WB

R_WA

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

From ±x15E From ±x±±±

N/A

to ±x3FF

to ±x2A1

to ±x3FF

From ±xB4

to ±x3FF

From ±x64

to ±x3FF

to ±x2±B

From ±x±±± From ±xFA

to ±x34B to ±x3FF

From ±x±±± From ±xꢀ8

to ±x39B to ±x3FF

to ±x3FF

to ±x2±B

From ±x±±± From ±xFA

to ±x3±5

From ±x±±± From ±xꢀ8

to ±x38ꢀ to ±x3FF

From ±x8C

to ±x3FF

From ±x±±±

to ±x3ꢀ3

From ±x±±±

to ±x3±5

From ±x±±±

to ±x38ꢀ

to ±x3FF

From ±x5A

to ±x3FF

From ±x±±±

to ±x3A5

Rev. D | Page ꢀ of 32

AD5291/AD5292

Table 6.

R_AB= 50 kΩ

|V_DD− V_SS| = 26 V to 33 V |V_DD− V_SS| = 21 V to 26 V

R_WBR_WAR_WBR_WA

From ±x±8C From ±x±±± From ±x±B4 From ±x±±±

to ±x3FF to ±x35F to ±x3FF to ±x31E

From ±X±3C From ±x±±± From ±x±5± From ±x±±±

to ±x3FF to ±x3C3 to ±x3FF to ±x3AF

From ±X±28 From ±x±±± From ±x±32 From ±x±±±

to ±x3FF to ±x3Dꢀ to ±x3FF to ±x3CD

R_AB= 100 kΩ

|V_DD− V_SS| = 26 V to 33 V |V_DD− V_SS| = 21 V to 26 V

R_WBR_WAR_WBR_WA

From ±x±4B From ±x±±± From ±x±64 From ±x±±±

to ±x3FF to ±x3B4 to ±x3FF to ±x39B

From ±x±28 From ±x±±± From ±x±28 From ±x±±±

to ±x3FF to ±x3Dꢀ to ±x3FF to ±x3Dꢀ

From ±x±19 From ±x±±± From ±x±19 From ±x±±±

to ±x3FF to ±x3E6 to ±x3FF to ±x3E6

Resistor

Tolerance per

Code

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

INTERFACE TIMING SPECIFICATIONS

V_DD/V_SS

= 15 V, V_LOGIC= 2.7 V to 5.5 V, −40°C < T_A< +105°C. All specifications T_MINto T_MAX, unless otherwise noted.

Table 7.

Parameter

Limit¹

2±

1±

5

1

4±±³

14

1

Unit

Description

2

t₁

ns min

ns max

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge setup time

Data setup time

t₂

t₃

t₄

t₅

t₆

t_ꢀ

t₈

t₉

Data hold time

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

SYNC rising edge to next SCLK fall ignore

RDY rising edge to SYNC falling edge

SYNC rising edge to RDY fall time

4

t_1±

4

t₁₁

4±

4

t₁₂

2.4

41±

8

μs max

ns max

ms max

ms min

ns max

ms max

ns max

ns min

ms max

RDY low time, RDAC register write command execute time (R-Perf mode)

RDY low time, RDAC register write command execute time (normal mode)

RDY low time, memory program execute time

Software/hardware reset

4

t₁₂

4

t₁₂

4

t₁₂

1.5

45±

1.3

45±

2±

4

t₁₃

RDY low time, RDAC register readback execute time

RDY low time, memory readback execute time

SCLK rising edge to SDO valid

4

t₁₃

4

t₁₄

t_RESET

Minimum RESET pulse width (asynchronous)

Power-on OTP restore time

5

t_POWER-UP

2

¹All input signals are specified with t_R= t_F= 1 ns/V (1±% to 9±% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

²Maximum SCLK frequency is 5± MHz.

³Refer to t₁₂and t₁₃for RDAC register and memory commands operations.

⁴R_{PULL_UP}= 2.2 kΩ to V_LOGIC, with a capacitance load of 168 pF.

⁵Maximum time after V_LOGICis equal to 2.5 V.

DB9 (MSB)

DB0 (LSB)

C3

C1

C0

D9

D7

D6

D5

D4

D3

D0

0

C2

D8

D2

D1

DATA BITS

CONTROL BITS

Figure 2. Shift Register Content

Rev. D | Page 8 of 32

AD5291/AD5292

Timing Diagrams

t₄

t₇

t₂

t₁

SCLK

t₉

t₃

t₈

SYNC

t₅

t₆

D7

DIN

D6

D2

X

C3

C2

D1

D0

SDO

t₁₁

t₁₀

t₁₂

RDY

t_RESET

RESET

Figure 3. Write Timing Diagram, CPOL = 0, CPHA = 1

SCLK

SYNC

t₉

DIN

X

C3

D0

X

D0

C3

D1

D0

t₁₄

C3

SDO

RDY

X

D1

D0

t₁₁

t₁₃

Figure 4. Read Timing Diagram, CPOL = 0, CPHA = 1

Rev. D | Page 9 of 32

AD5291/AD5292

ABSOLUꢂꢄ MAXIMUM ꢁAꢂINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 8.

Parameter

Rating

V_DDto GND

V_SSto GND

V_LOGICto GND

V_DDto V_SS

−±.3 V to +35 V

+±.3 V to − 25 V

−±.3 V to + ꢀ V

35 V

V_SS− ±.3 V, V_DD+ ±.3 V

−±.3 V to V_LOGIC+ ±.3 V

−±.3 V to +ꢀ V

V_A, V_B, V_Wto GND

THERMAL RESISTANCE

Digital Input and Output Voltage to GND

EXT_CAP Voltage to GND

I_A, I_B, I_W

θ_JAis defined by JEDEC specification JESD-51 and the value is

dependent on the test board and test environment.

Continuous

Table 9. Thermal Resistance

Package Type

R_AB= 2± kΩ

R_AB= 5± kΩ, 1±± kΩ

Pulsed¹

Frequency > 1± kHz

Frequency ≤ 1± kHz

Operating Temperature Range⁴

Maximum Junction Temperature (T_Jmax)

Storage Temperature Range

Reflow Soldering

±3 mA

±2mA

θ_JA

93¹

θ_JC

Unit

14-Lead TSSOP

2±

°C/W

MCC²/d³

MCC²/√d³

−4±°C to +1±5°C

15±°C

−65°C to +15±°C

¹JEDEC 2S2P test board, still air (± m/sec to 1 m/sec air flow).

ESD CAUTION

Peak Temperature

Time at Peak Temperature

Package Power Dissipation

26±°C

2± sec to 4± sec

(T_Jmax − T_A)/θ_JA

¹Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum

applied voltage across any two of the A, B, and W terminals at a given

resistance.

²Maximum continuous current

³Pulse duty factor.

⁴Includes programming of OTP memory.

Rev. D | Page 1± of 32

AD5291/AD5292

PIN CONFIGUꢁAꢂION AND FUNCꢂION DꢄSCꢁIPꢂIONS

RESET

1

2

3

4

5

6

7

14 RDY

V

13

SDO

SS

AD5291/

AD5292

A

W

B

12

SYNC

11 SCLK

10 DIN

TOP VIEW

Not to Scale

V

9

8

GND

DD

EXT_CAP

V

LOGIC

Figure 5. Pin Configuration

Table 10. Pin Function Descriptions

Pin No. Mnemonic Description

1

RESET

Hardware Reset Pin. Refreshes the RDAC register with the contents of the 2±-TP memory register. Factory

default loads midscale until the first 2±-TP wiper memory location is programmed. RESET is activated at the

logic high transition. Tie RESET to V_LOGICif not used.

2

V_SS

Negative Supply. Connect to ± V for single-supply applications. This pin should be decoupled with ±.1 μF

ceramic capacitors and 1± μF capacitors.

3

4

5

6

ꢀ

8

A

W

B

V_DD

EXT_CAP

V_LOGIC

Terminal A of RDAC. V_SS≤ V_A≤ V_DD.

Wiper Terminal of RDAC. V_SS≤ V_W≤ V_DD.

Terminal B of RDAC. V_SS≤ V_B≤ V_DD.

Positive Power Supply. This pin should be decoupled with ±.1 μF ceramic capacitors and 1± μF capacitors.

External Capacitor. Connect a 1 μF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥ꢀ V.

Logic Power Supply; 2.ꢀ V to 5.5 V. This pin should be decoupled with ±.1 μF ceramic capacitors and 1± μF

capacitors.

9

1±

GND

DIN

Ground Pin, Logic Ground Reference.

Serial Data Input. The AD5291 and AD5292 have a 16-bit shift register. Data is clocked into the register on the

falling edge of the serial clock input.

11

12

SCLK

SYNC

Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be

transferred at rates up to 5± MHz.

Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The

selected register is updated on the rising edge of SYNC following the 16^thclock cycle. If SYNC is taken high

before the 16^thclock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by

the DAC.

13

14

SDO

RDY

Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data

from the shift register in daisy-chain mode or in readback mode.

Ready Pin. This active-high open-drain output identifies the completion of a write or read operation to or from

the RDAC register or memory.

Rev. D | Page 11 of 32

AD5291/AD5292

ꢂYPICAL PꢄꢁFOꢁMANCꢄ CHAꢁACꢂꢄꢁISꢂICS

1.0

0.8

–40°C

20kꢀ

50kꢀ

100kꢀ

TEMPERATURE = 25°C

+25°C

0.8

+105°C

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

R

= 20kΩ

AB

0

128

256

384

512

640

768

896

1023

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5292)

Figure 9. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)

0.6

TEMPERATURE = 25°C

R

= 20kΩ

AB

0.5

0.4

0.3

0.2

0.1

0

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

20kꢀ

–0.2

50kꢀ

100kꢀ

+105°C

768

+25°C

512

CODE (Decimal)

–40°C

–0.3

0

128

256

384

512

640

768

896

1023

0

128

256 384

640

896

1023

CODE (Decimal)

Figure 10. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)

Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5292)

1.0

20kꢀ

50kꢀ

100kꢀ

TEMPERATURE = 25°C

R

= 20kΩ

AB

0.8

0.6

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.2

–0.4

–0.6

+105°C

768

+25°C

512

CODE (Decimal)

–40°C

0

128

256 384

640

896

1023

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 8. R-INL in Normal Mode vs. Code vs. Temperature (AD5292)

Figure 11. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)

Rev. D | Page 12 of 32

AD5291/AD5292

0.15

0.10

0.05

0

0.15

0.10

0.05

0

20kꢀ

50kꢀ

100kꢀ

TEMPERATURE = 25°C

R

= 20kꢀ

AB

–0.05

–0.10

–0.15

–0.20

–0.05

–0.10

–0.15

–0.20

+105°C

768

+25°C

512

CODE (Decimal)

–40°C

0

128

256 384

640

896

1023

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 12. R-DNL in Normal Mode vs. Code vs. Temperature (AD5292)

Figure 15. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)

1.5

0.8

TEMPERATURE = 25°C

R

= 20kꢀ

AB

1.0

0.5

0.6

0.2

0

–0.5

–1.0

–1.5

–0.2

–0.6

20kꢀ

50kꢀ

100kꢀ

+105°C

768

+25°C

512

CODE (Decimal)

–40°C

–0.8

0

128

256 384

640

896

1023

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 13. INL in R-Perf Mode vs. Code vs. Temperature (AD5292)

Figure 16. INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)

0.6

R

= 20kꢀ

AB

TEMPERATURE = 25°C

0.5

0.4

0.3

0.2

0.1

0

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

20kꢀ

–0.2

50kꢀ

100kꢀ

+105°C

768

+25°C

512

CODE (Decimal)

–40°C

–0.3

0

128

256 384

640

896

1023

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 14. DNL in R-Perf Mode vs. Code vs. Temperature (AD5292)

Figure 17. DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)

Rev. D | Page 13 of 32

AD5291/AD5292

0.8

0.6

–40°C

+25°C

+105°C

20kꢀ

50kꢀ

100kꢀ

TEMPERATURE = 25°C

R

= 20kꢀ

AB

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–0.2

–0.4

–0.6

–0.8

0

128

256

384

512

640

768

896

1023

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 21. INL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)

Figure 18. INL in Normal Mode vs. Code vs. Temperature (AD5292)

0.08

0.10

20kꢀ

50kꢀ

100kꢀ

–40°C

+25°C

+105°C

0.04

0

0.05

0

–0.04

–0.08

–0.12

–0.05

–0.10

–0.15

–0.20

TEMPERATURE = 25°C

–0.16

R

= 20kꢀ

AB

0

128

256

384

512

640

768

896

1023

0

128

256

384

512

640

768

896

1023

CODE (Decimal)

Figure 22. DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)

Figure 19. DNL in Normal Mode vs. Code vs. Temperature (AD5292)

0.30

+105°C

TEMPERATURE = 25°C

+25°C

20kꢀ

–40°C

50kꢀ

0.25

0.20

0.15

0.10

0.05

0

0.25

100kꢀ

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.05

–0.10

–0.15

–0.20

R

= 20kꢀ

AB

0

32

64

96

128

160

192

224

255

0

32

64

96

128

160

192

224

255

CODE (Decimal)

Figure 23. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)

Figure 20. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5291)

Rev. D | Page 14 of 32

AD5291/AD5292

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

TEMPERATURE = 25°C

R

= 20kꢀ

AB

–0.02

–0.04

–0.06

–0.02

–0.04

–0.06

20kꢀ

50kꢀ

100kꢀ

+105°C

192

+25°C

128

CODE (Decimal)

–40°C

64

0

32

64

96

128

160

192

224

255

0

32

96

160

224

255

CODE (Decimal)

Figure 27. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)

Figure 24. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5291)

0.25

20kꢀ

+105°C

+25°C

TEMPERATURE = 25°C

–40°C

50kꢀ

100kꢀ

0.20

0.15

0.10

0.05

0

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.05

–0.10

R

= 20kꢀ

AB

0

32

64

96

128

160

192

224

255

0

32

64

96

128

160

192

224

255

CODE (Decimal)

Figure 25. R-INL in Normal Mode vs. Code vs. Temperature (AD5291)

Figure 28. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)

0.03

+105°C

+25°C

20kꢀ

50kꢀ

100kꢀ

–40°C

TEMPERATURE = 25°C

0.02

0.01

0.02

0.01

0

–0.01

–0.02

–0.03

–0.04

–0.05

–0.01

–0.02

–0.03

–0.04

–0.05

R

= 20kꢀ

AB

0

32

64

96

128

160

192

224

255

0

32

64

96

128

160

192

224

255

CODE (Decimal)

Figure 29. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)

Figure 26. R-DNL in Normal Mode vs. Code vs. Temperature (AD5291)

Rev. D | Page 15 of 32

AD5291/AD5292

0.25

0.20

0.15

0.10

0.05

0

0.25

TEMPERATURE = 25°C

+105°C

+25°C

–40°C

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

–0.05

–0.10

–0.15

–0.20

20kꢀ

50kꢀ

100kꢀ

R

= 20kꢀ

AB

–0.25

0

32

64

96

128

160

192

224

255

0

32

64

96

128

160

192

224

255

CODE (Decimal)

Figure 30. INL in R-Perf Mode vs. Code vs. Temperature (AD5291)

Figure 33. INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)

0.14

TEMPERATURE = 25°C

+105°C

+25°C

–40°C

0.12

0.10

0.08

0.06

0.04

0.02

0

0.12

0.10

0.08

0.06

0.04

0.02

0

–0.02

–0.04

–0.06

20kꢀ

–0.04

50kꢀ

R

= 20kꢀ

100kꢀ

AB

–0.06

0

32

64

96

128

160

192

224

255

0

32

64

96

128

160

192

224

255

CODE (Decimal)

Figure 31. DNL in R-Perf Mode vs. Code vs. Temperature (AD5291)

Figure 34. DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)

0.20

20kꢀ

50kꢀ

100kꢀ

+105°C

TEMPERATURE = 25°C

+25°C

–40°C

0.15

0.10

0.05

0

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.05

–0.10

–0.15

–0.20

0

32

64

96

128

160

192

224

255

0

32

64

96

128

160

192

224

256

CODE (Decimal)

Figure 32. INL in Normal Mode vs. Code vs. Temperature (AD5291)

Figure 35. INL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)

Rev. D | Page 16 of 32

AD5291/AD5292

0.03

0.02

0.03

0.02

+105°C

+25°C

–40°C

TEMPERATURE = 25°C

0.01

0

–0.01

–0.02

–0.03

–0.04

–0.05

–0.01

–0.02

–0.03

–0.04

–0.05

20kꢀ

50kꢀ

100kꢀ

R

AB

= 20kꢀ

0

32

64

96

128

160

192

224

255

0

32

64

96

128

160

192

224

255

CODE (Decimal)

Figure 36. DNL in Normal Mode vs. Code vs. Temperature (AD5291)

Figure 39. DNL in Normal Mode vs. Code vs. Temperature (AD5291)

450

0.20

V

/V = ±15V

DD SS

V

= ±15V

DD

= +5V

LOGIC

400

350

300

250

200

150

100

50

0.18

0.16

0.14

0.12

0.1

I

LOGIC

0.08

0.06

0.04

0.02

0

I

DD

0

I

SS

–50

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

DIGITAL INPUT VOLTAGE (V)

Figure 37. Supply Current (I_DD, I_SS, I_LOGIC) vs. Temperature

Figure 40. Supply Current I_LOGICvs. Digital Input Voltage

700

600

500

400

300

200

100

0

700

V

= 30V,

V

= 30V

DD

= 0V

DD

= 0V

SS

600

500

400

300

200

100

0

20kꢀ

50kꢀ

100kꢀ

50kꢀ

100kꢀ

0

256

64

512

128

768

192

1023 AD5292

255 AD5291

0

256

64

512

128

768

192

1023 AD5292

255 AD5291

CODE (Decimal)

Figure 41. Potentiometer Mode Tempco ΔR_WB/ΔT vs. Code

Figure 38. Rheostat Mode Tempco ΔR_WB/ΔT vs. Code

Rev. D | Page 1ꢀ of 32

AD5291/AD5292

0

–5

0

AD5292 (AD5291)

0x200 (0x80)

0x100 (0x40)

0x200 (0x80)

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

0x100 (0x40)

–15

–20

0x080 (0x20)

0x040 (0x10)

0x020 ( 0x08)

0x080 (0x20)

0x040 (0x10)

–25

–30

–35

–40

–45

–50

–55

0x010 (0x04)

0x008 (0x02)

0x020 ( 0x08)

0x010 (0x04)

0x008 (0x02)

0x004 (0x01)

0x002

0x001

0x004 (0x01)

–60

0x002

0x001

–65

–67.5

10

100

1k

10k

100k

1M

1

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 45. 100 kΩ Gain vs. Frequency vs. Code

Figure 42. 20 kΩ Gain vs. Frequency vs. Code

0

–10

–20

–30

–40

–50

–60

–70

0

100kꢀ

20kꢀ

50kꢀ

AD5292 (AD5291)

0x200 (0x80)

–10

–20

–30

–40

–50

–60

0x100 (0x40)

0x080 (0x20)

0x040 (0x10)

0x020 ( 0x08)

0x010 (0x04)

0x008 (0x02)

0x004 (0x01)

0x002

0x001

100

1k

10k

100k

1M

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 46. Power Supply Rejection Ratio vs. Frequency

Figure 43. 50 kΩ Gain vs. Frequency vs. Code

0

–20

0

–15

V

/V = ±15V,

DD SS

V

/V = ±15V

DD SS

CODE = HALF SCALE

f_IN= 1kHz

NOISE BW = 22kHz

20kꢀ

CODE = HALF SCALE

= 1V rms

V

IN

Noise BW = 22kHz

20kꢀ

50kꢀ

100kꢀ

–40

50kꢀ

100kꢀ

–30

–45

–60

–80

–75

–100

–120

–140

–90

–105

–120

0.001

0.01

0.1

AMPLITUDE (V rms)

1

10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 44. THD + Noise vs. Frequency

Figure 47. THD + Noise vs. Amplitude

Rev. D | Page 18 of 32

AD5291/AD5292

1,000,000

900,000

800,000

700,000

600,000

500,000

400,000

300,000

200,000

100,000

0

8

7

6

5

4

3

2

1

0

20k – 0pF

50k – 150pF

50k – 250pF

100k – 0pF

100k – 75pF

100k – 150pF

100k – 250pF

V

/V = 30V/0V

DD SS

20k – 75pF

20k – 150pF

20k – 250pF

50k – 0pF

= V

A

B

DD

SS

50k – 75pF

20kꢀ

50kꢀ

100kꢀ

0

8

16

32

16

CODE (Decimal)

64

128

256

64

512 AD5292

128 AD5291

0

256

64

512

128

768

192

1023 AD5292

255 AD5291

8

32

CODE (Decimal)

Figure 48. Bandwidth vs Code vs Net Capacitance

Figure 51. Theoretical Maximum Current vs. Code

35

1.2

1.0

V

/V = ±15V

DD SS

30

25

20

15

10

5

= +5V

LOGIC

= V

A

B

DD

SS

0.8

20kꢀ

0.6

50kꢀ

100kꢀ

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

0

–5

–0.4

–0.2

0

0.2

0.4

TIME (ms)

0.6

0.8

1.0

1.2

–2

0

2

4

6

8

10

12

14

16

TIME (µs)

Figure 49. I_DDWaveform While Blowing/Reading Fuse

Figure 52. Maximum Transition Glitch

35

40

32

24

16

8

V

, CODE: FULL SCALE,

NORMAL MODE

ꢀ

WB

V

/V = ±15V

DD SS

= V

A

DD

30

25

20

15

10

5

= V

B

SS

V

/V = 30V/0V

DD SS

CODE = HALF CODE

= 5V

LOGIC

= V

A

B

DD

SS

V

, CODE: FULL SCALE,ꢀ

WB

R-PERF MODE

0

–8

SYNC

–16

20kꢀ

50kꢀ

100kꢀ

20kꢀ

50kꢀ

100kꢀ

V

, CODE: HALF-SCALE,

NORMAL MODE

WB

–24

–32

0

V

, CODE: HALF-SCALE,

WB

R-PERF MODE

–5

–40

–0.5

0

5

10

15

20

25

30

35

40

45

TIME (µs)

Figure 50. 20kΩ Large-Signal Settling Time from Code Zero Scale

Figure 53. Digital Feedthrough

Rev. D | Page 19 of 32

AD5291/AD5292

6

75.0

62.5

50.0

37.5

25.0

12.5

0

300

250

200

150

100

50

V

/V = ±15V

DD SS

V

/V = ±15V

DD SS

= +5V

LOGIC

20kꢀ

50kꢀ

100kꢀ

5

4

3

2

1

0

–1

0

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

TIME (ms)

Figure 54. V_{EXT_CAP}Waveform While Reading Fuse Or Calibration

Figure 56. Code Range > 1% R-Tolerance Error vs. Temperature

8

20.0

80

70

60

50

40

30

20

10

0

V

/V = ±15V

DD SS

V

= V

20kꢀ

50kꢀ

100kꢀ

A

B

DD

= +5V

LOGIC

SS

17.5

15.0

12.5

10.0

7.5

TEMPERATURE = 25°C

6

3

2

5.0

0

2.5

–2

0

21

26

30

33

VOLTAGE V /V

DD SS

TIME (ms)

Figure 57. Code Range > 1% R-Tolerance Error vs. Voltage

Figure 55. V_{EXT_CAP}Waveform While Writing Fuse

Rev. D | Page 2± of 32

AD5291/AD5292

ꢂꢄSꢂ CIꢁCUIꢂS

Figure 58 to Figure 63 define the test conditions used in the Specifications section.

NC

DUT

A

I

V

W

A

V+ = V ± 10%

DD

W

∆V

MS

DD

V

A

B

DD

PSRR (dB) = 20 log

B

W

V+

~

V

MS

∆V

%

MS

DD

PSS (%/%) =

V

MS

NC = NO CONNECT

Figure 61. Power Supply Sensitivity (PSS, PSRR)

Figure 58. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

+15V

A

W

DUT

A

V+ = V

DD

V

IN

N

DUT

1LSB = V+/2

OP42

–15V

V

OUT

B

W

OFFSET

GND

V+

B

2.5V

V

MS

Figure 62. Gain vs. Frequency

Figure 59. Potentiometer Divider Nonlinearity Error

(INL, DNL)

+15V

NC

–15V

GND

0.1V

A

V

DUT

R

=

I

DD

WB

CM

I

DUT

B

WB

+15V

–15V

W

R

CODE = 0x00

WB

2

R

W

V

GND

SS

B

+

–

GND

0.1V

I

WB

NC

+15V

GND

V

TO V

DD

SS

NC = NO CONNECT

A = NC

–15V

Figure 63. Common-Mode Leakage Current

Figure 60. Wiper Resistance

Rev. D | Page 21 of 32

AD5291/AD5292

ꢂHꢄOꢁY OF OPꢄꢁAꢂION

The AD5291 and AD5292 digital potentiometers are designed to

operate as true variable resistors for analog signals that remain

within the terminal voltage range of V_SS< V_TERM< V_DD. The

patented 1% resistor tolerance feature helps to minimize the total

RDAC resistance error, which reduces the overall system error

by offering better absolute matching and improved open-loop

performance. The digital potentiometer wiper position is

determined by the RDAC register contents. The RDAC register

acts as a scratchpad register, allowing as many value changes as

necessary to place the potentiometer wiper in the correct

position. The RDAC register can be programmed with any

position setting using the standard SPI interface by loading the

16-bit data-word. Once a desirable position is found, this value

can be stored in a 20-TP memory register. Thereafter, the wiper

position is always restored to that position for subsequent power-

up. The storing of 20-TP data takes approximately 6 ms; during

this time, the shift register is locked, preventing any changes from

taking place. The RDY pin identifies the completion of this 20-

TP storage.

For the AD5291, the lower two RDAC data bits are don’t cares if

the RDAC register is read from or written to. Data is loaded MSB

first (Bit DB15). The four control bits determine the function of

the software command (see Table 11). Figure 3 shows a timing

diagram of a typical AD5291 and AD5292 write sequence.

SYNC

The write sequence begins by bringing the

line low. The

SYNC

pin must be held low until the complete data-word is

SYNC

loaded from the DIN pin. When

returns high, the serial

data-word is decoded according to the commands in Table 11.

The command bits (Cx) control the operation of the digital

potentiometer. The data bits (Dx) are the values that are loaded

into the decoded register. The AD5291 and AD5292 have an

internal counter that counts a multiple of 16 bits (a frame) for

proper operation. For example, AD5291 and AD5292 work with

a 32-bit word but does not work properly with a 31-bit or 33-bit

word. The AD5291 and AD5292 do not require a continuous

SYNC

SCLK, when

is high, and all serial interface pins should

be operated at close to the V_LOGICsupply rails to minimize

power consumption in the digital input buffers.

SERIAL DATA INTERFACE

RDAC REGISTER

The AD5291 and AD5292 contain a serial interface (

SCLK, DIN and SDO) that is compatible with SPI interface

standards, as well as most DSPs. The part allows writing of data

via the serial interface to every register.

,

SYNC

The RDAC register directly controls the position of the digital

potentiometer wiper. For example, when the RDAC register is

loaded with all zeros, the wiper is connected to Terminal B of

the variable resistor. The RDAC register is a standard logic register;

there is no restriction on the number of changes allowed.

SHIFT REGISTER

The AD5291 and AD5292 shift register is 16 bits wide (see

Figure 2). The 16-bit input word consists of two unused bits

(set to 0), followed by four control bits, and 10 RDAC data bits.

Table 11. Command Operation Truth Table

Command Bits [DB13:DB10]

Data Bits [DB9:DB0]¹

Command

C3

±

C2

±

C1

±

C0

±

D9

X

D8

X

D7

X

D6

X

D5

X

D4

X

D3

X

D2

X

D1

X

D0

X

Operation

±

1

2

NOP command: do nothing.

Write contents of serial data to RDAC.

±

1

D9

X

D8

X

Dꢀ

X

D6

X

D5

X

D4

X

D3

X

D2

X

D1²

D±²

±

1

±

X

Read RDAC wiper setting from the SDO

output in the next frame.

3

4

5

±

1

±

1

±

1

X

Store wiper setting: store RDAC setting

to 2±-TP memory.

X

Reset: refresh RDAC with 2±-TP stored

value.

D4

D3

D2

D1

D±

Read contents of 2±-TP memory, or

status of 2±-TP memory, from the SDO

output in the next frame.

6

ꢀ

8

±

1

±

1

±

1

±

X

D3

X

D2

X

D1

X

D±

X

Write contents of serial data to control

register.

Read control register from the SDO

output in the next frame.

X

D±

Software shutdown.

D± = ± (normal mode).

D± = 1 (device placed in shutdown mode).

¹X = don’t care.

²In the AD5291, this bit is a don’t care.

Rev. D | Page 22 of 32

AD5291/AD5292

20-TP MEMORY

WRITE PROTECTION

Once a desirable wiper position is found, the contents of the

RDAC register can be saved into a 20-TP memory register

(see Table 12). Thereafter, the wiper position is always set at that

position for any future on-off-on power supply sequence. The

AD5291 and AD5292 have an array of 20 one-time programmable

(OTP) memory registers. When the desired word is programmed

to 20-TP memory, the device automatically verifies that the

program command was successful. The verification process

includes margin testing. Bit C3 of the control register can be

polled to verify that the fuse program command was successful.

Programming data to 20-TP memory consumes approximately

25 mA for 550 μs and takes approximately 8 ms to complete.

During this time, the shift register is locked, preventing any

changes from taking place. The RDY pin can be used to monitor

the completion of the 20-TP memory program and verification.

No change in supply voltage is required to program the 20-TP

memory. However, a 1 μF capacitor on the EXT_CAP pin is

required (see Figure 68). Prior to 20-TP activation, the AD5291

and AD5292 preset to midscale on power-up.

On power-up, the shift register write commands for both the

RDAC register and the 20-TP memory register are disabled.

The RDAC write protect bit, C1 of the control register (see

Table 13 and Table 14), is set to 0 by default. This disables any

change of the RDAC register content regardless of the software

commands, except that the RDAC register can be refreshed

from the 20-TP memory using the software reset command

RESET

(Command 4) or through hardware by the

pin. To enable

programming of the variable resistor wiper position (program-

ming the RDAC register), the write protect bit, C1 of the control

register, must first be programmed. This is accomplished by

loading the shift register with Command 6 (see Table 11). To

enable programming of the 20-TP memory block bit, C0 of the

control register (set to 0 by default) must first be set to 1.

Table 12. Write and Read to RDAC and 20-TP Memory

DIN

SDO

Action

±x18±3

±x±5±±

±x±8±±

±x±C±±

±xXXXX

±x18±3

±x±5±±

±x±1±±

Enable update of wiper position and 2±-TP memory contents through digital interface.

Write ±x1±± to the RDAC register; wiper moves to ¼ full-scale position.

Prepare data read from the RDAC register.

Stores RDAC register content into 2±-TP memory. The 16-bit word appears out of SDO, where the last 1± bits

contain the contents of the RDAC register (±x1±±).

±x1C±±

±x±±±±

±x±C±±

±x±±±X

Prepare data read from the control register.

NOP Instruction ± sends 16-bit word out of SDO, where the last four bits contain the contents of the control

register. If Bit C3 = 1, the fuse program command is successful.

Table 13. Control Register Bit Map¹

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

X

C3

C2

C1

C±

¹X = don’t care.

Table 14. Control Register Function

Bit Name

Description

C±

2±-TP program enable

± = 2±-TP program disabled (default)

1 = enable device for 2±-TP program

RDAC register write protect

± = wiper position frozen to value in memory (default)¹

1 = allow update of wiper position through digital Interface

Calibration enable

C1

C2

C3

± = resistor performance mode enabled (default)

1 = normal mode enabled

2±-TP memory program success

± = fuse program command unsuccessful (default)

1 = fuse program command successful

¹Wiper position frozen to value last programmed in 2±-TP memory. Wiper is frozen to midscale if 2±-TP memory has not been previously programmed.

Rev. D | Page 23 of 32

AD5291/AD5292

read-only Memory Address 0x14 and Memory Address 0x15

using Command 5. The data bytes read back from Memory

Address 0x014 and Memory Address 0x015 are thermometer

encoded versions of the address of the last programmed

memory location.

BASIC OPERATION

The basic mode of setting the variable resistor wiper position

(programming the RDAC register) is accomplished by loading

the shift register with Command 1 (see Table 11) and the desired

wiper position data. When the desired wiper position is deter-

mined, the user can load the shift register with Command 3

(see Table 11), which stores the wiper position data in the 20-TP

memory register. After 6 ms, the wiper position is permanently

stored in the 20-TP memory. The RDY pin can be used to moni-

tor the completion of this 20-TP program. Table 12 provides a

programming example, listing the sequence of serial data input

(DIN) words with the serial data output appearing at the SDO

pin in hexadecimal format.

For the example outlined in Table 15, the address of the last

programmed location is calculated as

(Number of Bits = 1 in Memory Address 0x14) + (Number

of Bits = 1 in Memory Address 0x15) − 1 = 10 + 8 − 1 = 17

(0x10)

If no memory location has been programmed, then the address

generated is −1.

SHUTDOWN MODE

20-TP READBACK AND SPARE MEMORY STATUS

The AD5291 and AD5292 can be placed in shutdown mode by

executing the software shutdown command, Command 8 (see

Table 11), and setting the LSB, D0, to 1. This feature places the

RDAC in a special state in which Terminal A is open-circuited,

and Wiper W is connected to Terminal B. The contents of the

RDAC register are unchanged by entering shutdown mode.

However, all commands listed in Table 11 are supported while

in shutdown mode. Execute Command 8 (see Table 11), and set

the LSB, D0, to 0 to exit shutdown mode.

It is possible to read back the contents of any of the 20-TP

memory registers through SDO by using Command 5 (see

Table 11). The lower five LSB bits (D0 to D4) of the data byte

select which memory location is to be read back (see Table 16).

Data from the selected memory location are clocked out of the

SDO pin during the next SPI operation, where the last 10 bits

contain the contents of the specified memory location.

It is also possible to calculate the address of the most recently

programmed memory location by reading back the contents of

Table 15. Example 20-TP Memory Readback

DIN

SDO

Action

±x1414 ±xXXXX Prepares data read from Memory Address ±x14.

±x1415 ±x±3FF

Prepares data read from Memory Address ±x15. Sends 16-bit word out of SDO, where the last 1± bits contain the

contents of Memory Address ±x14.

±x±±±± ±x±±FF

±x141± ±x±±±±

NOP Command ± sends 16-bit word out of SDO, where last 1±-bits contain the contents of Memory Address ±x15.

Prepares data read from memory location ±x1±.

±x±±±± ±xXXXX NOP Instruction ± sends 16-bit word out of SDO, where the last 1± bits contain the contents of Memory Address ±x1± (1ꢀ).

Table 16. Memory Map of Command 5

Data Bits [DB9:DB0]¹

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Register Contents

X

…

X

…

X

…

X

…

X

…

X

±

…

±

1

±

…

1

±

1

…

±

1

±

1

±

1

±

…

±

1

±

1

±

1

±

…

1

±

1

±

1

1^stprogrammed wiper location (±x±±)

2^ndprogrammed wiper location (±x±1)

3^rdprogrammed wiper location (±x±2)

4^thprogrammed wiper location (±x±3)

5^thprogrammed wiper location (±x±4)

…

1±^thprogrammed wiper location (±x±9)

15^thprogrammed wiper location (±x±E)

2±^thprogrammed wiper location (±x13)

Programmed memory status (thermometer encoded)²(±x14)

Programmed memory status (thermometer encoded)²(±x15)

¹X = don’t care.

²Allows the user to calculate the remaining spare memory locations.

Rev. D | Page 24 of 32

AD5291/AD5292

SYNC

Keep the

pin low until all 32 bits are clocked into their

RESISTOR PERFORMANCE MODE

SYNC

respective serial registers. The

complete the operation.

pin is then pulled high to

This mode activates a new, patented 1% end-to-end resistor

tolerance that ensures a 1% resistor tolerance on each code,

that is, code = half scale, R_WB= 10 kΩ 100 Ω. See Table 2

(AD5291) or Table 5 (AD5292) to check which codes achieve

1% resistor tolerance. The resistor performance mode is

activated by programming Bit C2 of the control register (see

Table 13 and Table 14). The typical settling time is shown in

Figure 50.

V

LOGIC

R

AD5291/

AD5292

AD5291/

AD5292

P

2.2kꢀ

MOSI

DIN

SDO

DIN

U1 SDO

U2

MICRO-

CONTROLLER

SCLK

SS

SYNC

SCLK

SYNC

SCLK

RESET

Figure 64. Daisy-Chain Configuration Using SDO

RESET

A low-to-high transition of the hardware

pin loads the

RDAC register with the contents of the most recently programmed

20-TP memory location. The AD5291 and AD5292 can also be

reset through software by executing Command 4 (see Table 11).

If no 20-TP memory location is programmed, then the RDAC

register loads with midscale upon reset. The control register is

restored with default bits; see Table 14.

RDAC ARCHITECTURE

To achieve optimum performance, Analog Devices has patented

the RDAC segmentation architecture for all the digital

potentiometers. In particular, the AD5291 and AD5292 employ

a three-stage segmentation approach, as shown in Figure 65.

The AD5291 and AD5292 wiper switches are designed with the

transmission gate CMOS topology and with the gate voltages

derived from V_DDand V_SS.

SDO PIN AND DAISY-CHAIN OPERATION

The serial data output pin (SDO) serves two purposes: it can be

used to read the contents of the wiper setting, 50-TP values and

control register using Command 2, Command 5 and Command 7,

respectively (see Table 11) or the SDO pin can be used in daisy-

chain mode. Data is clocked out of SDO on the rising edge of

SCLK. The SDO pin contains an open-drain N-channel FET

that requires a pull-up resistor if this pin is used. To place the

pin in high impedance and minimize the power dissipation

when the pin is used, the 0x8001 data word followed by

Command 0 should be sent to the part. Table 17 provides a

sample listing for the sequence of the serial data input (DIN).

Daisy chaining minimizes the number of port pins required

from the controlling IC. As shown in Figure 64, users need to

tie the SDO pin of one package to the DIN pin of the next

package. Users may need to increase the clock period, because

the pull-up resistor and the capacitive loading at the SDO-to-

DIN interface may require additional time delay between

subsequent devices.

A

R

L

R

M

S

W

R

M

R

W

8-/10-BIT

ADDRESS

DECODER

R

M

R

L

R

M

R

L

B

When two AD5291 and AD5292 devices are daisy-chained, 32

bits of data are required. The first 16 bits go to U2, and the

SYNC

second 16 bits go to U1. Hold the

pin low until all 32 bits

SYNC

are clocked into their respective shift registers. The

then pulled high to complete the operation.

pin is

Figure 65. Simplified RDAC Circuit

Table 17. Minimize Power Dissipation at SDO Pin

DIN

SDO¹

Action

±xXXXX

±x8±±1

±x±±±±

±xXXXX

High impedance

Last user command sent to the digipot

Prepares the SDO pin to be placed in high impedance mode

The SDO pin is placed in high impedance

¹X is don’t care.

Rev. D | Page 25 of 32

AD5291/AD5292

where:

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation—1% Resistor Tolerance

D is the decimal equivalent of the binary code loaded in the

8-/10-bit RDAC register.

The AD5291 and AD5292 operate in rheostat mode when only

two terminals are used as a variable resistor. The unused

terminal can be left floating or tied to the W terminal, as shown in

Figure 66.

R

_ABis the end-to-end resistance.

In the zero-scale condition, a finite total wiper resistance of 120 Ω

is present. Regardless of which setting the part is operating in,

take care to limit the current between Terminal A and Terminal B,

between Terminal W and Terminal A, and between Terminal W

and Terminal B, to the maximum continuous current of 3 mA or

to the pulse current specified in Table 8. Otherwise, degradation

or possible destruction of the internal resistors may occur.

A

W

B

Figure 66. Rheostat Mode Configuration

The nominal resistance between Terminal A and Terminal B,

R_AB, is available in 20 kΩ, 50 kΩ, and 100 kΩ, and 256 or 1024

tap points accessed by the wiper terminal. The 8-/10-bit data in

the RDAC latch is decoded to select one of the 256/1024

possible wiper settings. The AD5291 and AD5292 contain an

internal 1% resistor performance mode that can be disabled or

enabled (this is enabled by default), by programming Bit C2 of

the control register (see Table 13 and Table 14). The digitally

programmed output resistance between the W terminal and the

A terminal, R_WA, and between the W terminal and B terminal,

R_WB, is internally calibrated to give a maximum of 1% absolute

resistance error across a wide code range. As a result, the

general equations for determining the digitally programmed

output resistance between the W terminal and B terminal are

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at

the wiper to B and at the wiper to A that is proportional to the

input voltage at A to B, as shown in Figure 67. Unlike the polarity

of V_DDto GND, which must be positive, voltage across A to B,

W to A, and W to B can be at either polarity.

V

IN

A

W

V

OUT

B

Figure 67. Potentiometer Mode Configuration

If ignoring the effect of the wiper resistance for simplicity, con-

necting the A terminal to 30 V and the B terminal to ground

produces an output voltage at the Wiper W to Terminal B

ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage is

equal to the voltage applied across Terminal A and Terminal B,

divided by the 256/1024 positions of the potentiometer divider.

The general equations defining the output voltage at V_Wwith

respect to ground for any valid input voltage applied to Terminal A

and Terminal B are

AD5291:

D

256

R_WB(D) =

×R_AB

(1)

(2)

AD5292:

D

1024

R_WB(D) =

× R_AB

where:

D is the decimal equivalent of the binary code loaded in the

8-/10-bit RDAC register.

AD5291:

D

256

256 − D

256

R

_ABis the end-to-end resistance.

V_W(D) =

×V_A+

×V_B

(5)

(6)

Similar to the mechanical potentiometer, the resistance of the

AD5292:

V_W(D) =

RDAC between the W terminal and the A terminal also produces a

digitally controlled complementary resistance, R_WA. R_WAis also

calibrated to give a maximum of 1% absolute resistance error.

R_WAstarts at the maximum resistance value and decreases as the

data loaded into the latch increases. The general equations for

this operation are

1024− D

D

1024

×V_A+

×V_B

1024

If using the AD5291 and AD5292 in voltage divider mode as

shown in Figure 67, then the 1% resistor tolerance calibration

feature reduces the error when matching with discrete resistors.

However, it is recommended to disable the internal 1% resistor

tolerance calibration feature by programming Bit C2 of the

control register (see Table 13 and Table 14) to optimize wiper

position update rate. In this configuration, the RDAC is ratiome-

tric and resistor tolerance error does not affect performance.

AD5291:

256 − D

256

R

_WA(D) =

AD5292:

_WA(D) =

× R_AB

(3)

(4)

1024 − D

1024

R

×R_AB

Rev. D | Page 26 of 32

AD5291/AD5292

Operation of the digital potentiometer in the voltage divider

mode results in a more accurate operation over temperature.

Unlike the rheostat mode, the output voltage is dependent

mainly on the ratio of the internal resistors, R_WAand R_WB, and

not the absolute values. Therefore, the temperature drift reduces

to 5 ppm/°C.

The ground pins of the AD5291 and AD5292 devices are

primarily used as a digital ground reference. To minimize the

digital ground bounce, the AD5291 and AD5292 ground

terminals should be joined remotely to the common ground.

The digital input control signals to the AD5291 and AD5292

must be referenced to the device ground pin (GND), and satisfy

the logic level defined in the Specifications section.

EXT_CAP CAPACITOR

Power-Up Sequence

A 1 μF capacitor to GND must be connected to the EXT_CAP

pin (see Figure 68) on power-up and throughout the operation

of the AD5291 and AD5292.

To ensure that the AD5291 and AD5292 power up correctly, a

1 μF capacitor must be connected to the EXT_CAP pin. Because

there are diodes to limit the voltage compliance at Terminal A,

Terminal B, and Terminal W (see Figure 69), it is important to

power V_DDand V_SSfirst before applying any voltage to Terminal A,

Terminal B, and Terminal W. Otherwise, the diode is forward-

biased such that V_DDand V_SSare powered up unintentionally.

The ideal power-up sequence is GND, V_SS, V_LOGICand V_DD, the

digital inputs, and then V_A, V_B, and V_W. The order of powering

up V_A, V_B, V_W, and the digital inputs is not important as long as

AD5291/

AD5292

EXT_CAP

OTP

MEMORY

BLOCK

C1

1µF

GND

Figure 68. Hardware Setup for EXT_CAP Pin

they are powered after V_DD, V_SS, and V_LOGIC

.

TERMINAL VOLTAGE OPERATING RANGE

Regardless of the power-up sequence and the ramp rates of the

power supplies, after V_LOGICis powered, the power-on preset

activates, restoring the 20-TP memory value to the RDAC register.

The positive V_DDand negative V_SSpower supplies of the

AD5291 and AD5292 define the boundary conditions for

proper 3-terminal digital potentiometer operation. Supply

signals present on Terminal A, Terminal B, and Terminal W

that exceed V_DDor V_SSare clamped by the internal forward-

biased diodes (see Figure 69).

V

DD

A

W

B

V

SS

Figure 69. Maximum Terminal Voltages Set by V_DDand V _SS

Rev. D | Page 2ꢀ of 32

AD5291/AD5292

APPLICAꢂIONS INFOꢁMAꢂION

HIGH VOLTAGE DAC

HIGH ACCURACY DAC

The AD5292 can be configured as a high voltage DAC, with

output voltage as high as 33 V. The circuit is shown in Figure 70.

The output is

It is possible to configure the AD5292 as a high accuracy DAC

by optimizing the resolution of the device over a specific

reduced voltage range. This is achieved by placing external

resistors on either side of the RDAC, as shown in Figure 72.

The improved 1% R-Tolerance specification greatly reduces

error associated with matching to discrete resistors.

⎡

⎤

⎥

⎛

⎞

⎟

⎠

D

R₂

R₁

(7)

⎜

× 1.2 V × 1+

⎢

V_OUT(D) =

⎜

1024

⎢

⎣

⎥

⎦

⎝

R₃+ (^D₁₀₂₄× R_AB) ×V _DD

R₁+ (^(1024−D)₁₀₂₄) × R_AB+ R₃

where D is the decimal code from 0 to 1023.

V_OUT(D) =

(8)

V

DD

V

DD

V

DD

R

BIAS

U2

U1A

R

1

U1

V+

AD5292

D1

AD8512

V–

AD5292

V

DD

U1B

20kꢀ

ADR512

U2

V+

OP1177

V–

R

20kꢀ

2

V

OUT

B

V

AD8512

±1%

OUT

B

R

2

R

3

R

1

Figure 72. Optimizing Resolution

Figure 70. High Voltage DAC

VARIABLE GAIN INSTRUMENTATION AMPLIFIER

PROGRAMMABLE VOLTAGE SOURCE WITH

BOOSTED OUTPUT

The AD8221 in conjunction with the AD5291 and AD5292 and

the ADG1207, as shown in Figure 73, make an excellent

instrumentation amplifier for use in data acquisition systems.

The data acquisition system’s low distortion and low noise

enable it to condition signals in front of a variety of ADCs.

For applications that require high current adjustments such as a

laser diode or tunable laser, a boosted voltage source can be

considered; see Figure 71.

U3 2N7002

V

OUT

IN

ADG1207

V

DD

U1

AD5292

R

+V

BIAS

C

IN1

C

A

U2

OP184

I

W

L

V

+V

–V

OUT

AD5292

IN4

IN1

SIGNAL

LD

AD8221

B

–V

IN4

V

SS

Figure 71. Programmable Boosted Voltage Source

Figure 73. Data Acquisition System

In this circuit, the inverting input of the op amp forces V_OUTto

be equal to the wiper voltage set by the digital potentiometer.

The load current is then delivered by the supply via the N-channel

FET (U3). The N-Channel FET power handling must be adequate

to dissipate (V_IN− V_OUT) × I_Lpower. This circuit can source a

maximum of 100 mA with a 33 V supply.

The gain can be calculated by using Equation 9.

49.4 kꢀ

(9)

G(D) =1+

(

D 1024 × R_AB

)

Rev. D | Page 28 of 32

AD5291/AD5292

The configuration to reduce zipper noise is shown in Figure 74,

and the results of using this configuration is shown in Figure 75.

The input is ac-coupled by C1 and attenuated down before feeding

into the window comparator formed by U2, U3, and U4B. U6 is

used to establish the signal zero reference. The upper limit of

the comparator is set above its offset and, therefore, the output

pulses high whenever the input falls between 2.502 V and 2.497 V

(or 0.005 V window) in this example. This output is AND’ed

AUDIO VOLUME CONTROL

The excellent THD performance and high voltage capability

make the AD5291 and AD5292 ideal for a digital volume

control as an audio attenuator or gain amplifier. A typical

problem in these systems is that a large step change in the

volume level at any arbitrary time can lead to an abrupt

discontinuity of the audio signal causing an audible zipper

noise. To prevent this, a zero-crossing window detector can be

SYNC

with the

updates whenever the signal crosses the window. To avoid a

SYNC

signal such that the AD5291 and AD5292

SYNC

inserted to the

line to delay the device update until the

audio signal crosses the window. Because the input signal can

operate on top of any dc level rather than absolute zero volt

level, zero-crossing in this case means the signal is ac-coupled,

and the dc offset level is the signal zero reference point.

constant update of the device, the

signal should be

programmed as two pulses, rather than as one.

In Figure 75, the lower trace shows that the volume level changes

from a quarter-scale to full-scale when a signal change occurs

near the zero-crossing window.

C1

1µF

V

IN

5V

AD5292

U1

+15V

R

1

+5V

V

DD

100kꢀ

C3

0.1µF

A

U2

CC

ADCMP371

GND

V

C2

0.1µF

R

2

+15V

U5

200ꢀ

R

90kꢀ

V

4

SS

W

–15V

U4B

V+

V

OUT

4

5

U4A

20kꢀ

6

1

2

+5V

U3

7408

SYNC

7408

R

5

V–

10kꢀ

V

CC

5V

SCLK

SDIN

SCLK

SDIN

ADCMP371

GND

B

–15V

U6

V+

AD8541

V–

SYNC

GND

R

3

100kꢀ

Figure 74. Audio Volume Control with Zipper Noise Reduction

1

2

CHANNEL 1

FREQ = 20.25kHz

1.03V p-p

Figure 75. Zipper Noise Detector

Rev. D | Page 29 of 32

AD5291/AD5292

OUꢂLINꢄ DIMꢄNSIONS

5.10

5.00

4.90

14

8

7

4.50

4.40

4.30

6.40

BSC

1

PIN 1

0.65 BSC

1.05

1.00

0.80

1.20

MAX

0.20

0.09

0.75

0.60

0.45

8°

0°

0.15

0.05

COPLANARITY

0.10

SEATING

PLANE

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 76. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

AD5291BRUZ-2±

AD5291BRUZ-2±-RLꢀ

AD5291BRUZ-5±

AD5291BRUZ-5±-RLꢀ

AD5291BRUZ-1±±

AD5291BRUZ-1±±-RLꢀ

AD5292BRUZ-2±

AD5292BRUZ-2±-RLꢀ

AD5292BRUZ-5±

AD5292BRUZ-5±-RLꢀ

AD5292BRUZ-1±±

AD5292BRUZ-1±±-RLꢀ

EVAL-AD5292EBZ

R_AB(kΩ)

2±

5±

1±±

2±

5±

Resolution

256

Memory

2±-TP

Temperature Range

−4±°C to +1±5°C

Package Description

14-Lead TSSOP

Evaluation Board

Package Option

RU-14

256

1,±24

5±

1±±

¹Z = RoHS Compliant Part.

Rev. D | Page 3± of 32

AD5291/AD5292

NOꢂꢄS

Rev. D | Page 31 of 32

AD5291/AD5292

NOꢂꢄS

registered trademarks are the property of their respective owners.

D07674-0-9/10(D)

Rev. D | Page 32 of 32


型号：	AD5291BRUZ-100-RL7
厂家：	ADI
描述：	256-/1024-Position, Digital Potentiometers 256 / 1024的位置，数字电位器转换器电位器数字电位计电阻器光电二极管
文件：	总32页 (文件大小：1051K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5291BRUZ-100-RL7 [ADI]

相关型号：

AD5291BRUZ-20

AD5291BRUZ-20-RL7

AD5291BRUZ-21

AD5291BRUZ-50

AD5291BRUZ-50-RL7

AD5292

AD5292/AD5291

AD5292ABRUZ100

AD5292ABRUZ20

AD5292ABRUZ50

AD5292BRUZ-100

AD5292BRUZ-100-RL7