HMC1099LP5DE [ADI]
HMC1099LP5DE;
ADI 
>10 W, GaN Power Amplifier,
0.01 GHz to 1.1 GHz
Data Sheet
HMC1099
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High saturated output power (PSAT): 40.5 dBm typical
High small signal gain: 18.5 dB typical
High power added efficiency (PAE): 69% typical
Instantaneous bandwidth: 0.01 GHz to 1.1 GHz
Supply voltage: VDD = 28 V at 100 mA
Internal prematching
Simple and compact external tuning for optimal
performance
32-lead, 5 mm × 5 mm, LFCSP package: 25 mm2
GND
NIC
NIC
1
2
3
4
5
6
7
8
24 GND
23 NIC
HMC1099
22
NIC
21 RFOUT/V
RFIN/V
RFIN/V
DD
DD
GG
GG
20
19
RFOUT/V
NIC
NIC
NIC
GND
18 NIC
17 GND
PACKAGE
BASE
APPLICATIONS
Extended battery operation for public mobile radios
Power amplifier stage for wireless infrastructures
Test and measurement equipment
NIC = NO INTERNAL CONNECTION. THESE PINS
ARE NOT CONNECTED INTERNALLY.
Figure 1.
Commercial and military radars
General-purpose transmitter amplification
GENERAL DESCRIPTION
The HMC1099 is a gallium nitride (GaN), broadband power
amplifier delivering >10 W with up to 69% PAE across an
instantaneous bandwidth of 0.01 GHz to 1.1 GHz, and with a
0.5 dB typical gain flatness.
The HMC1099 is ideal for pulsed or continuous wave (CW)
applications, such as wireless infrastructure, radars, public
mobile radios, and general-purpose amplification.
The HMC1099 amplifier is externally tuned using low cost,
surface-mount components and is available in a compact
LFCSP package.
Multifunction pin names may be referenced by their relevant
function only.
Rev. A
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Technical Support
©2016 Analog Devices, Inc. All rights reserved.
www.analog.com
HMC1099
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 13
Applications Information .............................................................. 14
Typical Application Circuit....................................................... 14
Evaluation PCB........................................................................... 15
Bill of Materials........................................................................... 15
Outline Dimensions....................................................................... 16
Ordering Guide .......................................................................... 16
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Total Supply Current by VDD....................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
REVISION HISTORY
12/2016—Rev. 0 to Rev. A
Changed HCP-32-2 to CG-32-1.................................. Throughout
Updated Outline Dimensions....................................................... 16
Changes to Ordering Guide .......................................................... 16
1/2016—Revision 0: Initial Version
Rev. A | Page 2 of 16
Data Sheet
HMC1099
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
TA = 25°C, VDD = 28 V, IDD = 100 mA, frequency range = 0.01 GHz to 0.4 GHz.
Table 1.
Parameter
Symbol Min Typ
Max Unit Test Conditions/Comments
FREQUENCY RANGE
GAIN
0.01
0.4
GHz
Small Signal Gain
Gain Flatness
18
20
1
dB
dB
RETURN LOSS
Input
Output
12
15
dB
dB
POWER
Output Power for 4 dB Compression
Power Gain for P4dB Compression
Saturated Output Power
Power Gain for PSAT
Power Added Efficiency
OUTPUT THIRD-ORDER INTERCEPT
NOISE FIGURE
P4dB
PSAT
40
15
40.5
13
73
49
8
dBm
dB
dBm >10 W saturated output power
dB
%
PAE
IP3
dBm Measurement taken at POUT/tone = 30 dBm
dB
TOTAL SUPPLY CURRENT
IDD
100
mA
Adjust the gate bias control voltage (VGG) between
−8 V to 0 V to achieve an IDD = 100 mA typical
TA = 25°C, VDD = 28 V, IDD = 100 mA, frequency range = 0.4 GHz to 0.7 GHz.
Table 2.
Parameter
Symbol Min Typ
Max Unit Test Conditions/Comments
FREQUENCY RANGE
GAIN
0.4
0.7
GHz
Small Signal Gain
Gain Flatness
16.5 18.5
dB
dB
0.25
RETURN LOSS
Input
Output
9.5
14
dB
dB
POWER
Output Power for 4 dB Compression
Power Gain for P4dB Compression
Saturated Output Power
Power Gain for PSAT
Power Added Efficiency
OUTPUT THIRD-ORDER INTERCEPT
NOISE FIGURE
P4dB
PSAT
40.5
14
40.5
13
dBm
dB
dBm >10 W saturated output power
dB
%
PAE
IP3
69
48
dBm Measurement taken at POUT/tone = 30 dBm
dB
5.5
100
TOTAL SUPPLY CURRENT
IDD
mA
Adjust the gate bias control voltage (VGG) between
−8 V to 0 V to achieve an IDD = 100 mA typical
Rev. A | Page 3 of 16
HMC1099
Data Sheet
TA = 25°C, VDD = 28 V, IDD = 100 mA, frequency range = 0.7 GHz to 1.1 GHz.
Table 3.
Parameter
Symbol Min Typ
Max Unit Test Conditions/Comments
FREQUENCY RANGE
GAIN
0.7
1.1
GHz
Small Signal Gain
Gain Flatness
16.5 18.5
0.5
dB
dB
RETURN LOSS
Input
Output
12
17
dB
dB
POWER
Output Power for 4 dB Compression
Power Gain for P4dB Compression
Saturated Output Power
Power Gain for PSAT
Power Added Efficiency
OUTPUT THIRD-ORDER INTERCEPT
NOISE FIGURE
P4dB
PSAT
41.5
14
41.5
13.5
69
dBm
dB
dBm >10 W saturated output power
dB
%
PAE
IP3
47
dBm Measurement taken at POUT/tone = 30 dBm
dB
5
TOTAL SUPPLY CURRENT
IDD
100
mA
Adjust the gate bias control voltage (VGG) between
−8 V to 0 V to achieve an IDD = 100 mA typical
TOTAL SUPPLY CURRENT BY VDD
Table 4.
Parameter
Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT IDD
Adjust the gate bias control voltage (VGG) between −8 V to 0 V to achieve an
DD = 100 mA typical
I
VDD = 24 V
VDD = 28 V
100
100
mA
mA
Rev. A | Page 4 of 16
Data Sheet
HMC1099
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses at or above those listed under Absolute Maximum
Parameter1
Rating
32 V dc
−8 V to 0 V dc
33 dBm
4 mA
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Drain Bias Voltage (VDD)
Gate Bias Voltage (VGG)
Radio Frequency (RF) Input Power (RFIN)
Maximum Forward Gate Current
Maximum Voltage Standing Wave Ratio
(VSWR)2
6:1
Channel Temperature
225°C
260°C
12.5 W
Maximum Peak Reflow Temperature (MSL3)3
ESD CAUTION
Continuous Power Dissipation, PDISS (TA = 85°C,
Derate 89 mW/°C Above 85°C)
Thermal Resistance (Junction to Back of
Paddle)
11.2°C/W
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity (Human Body Model)
−55°C to +150°C
−40°C to +85°C
Class 1B,
passed 500 V
1 When referring to a single function of a multifunction pin in the parameters,
only the portion of the pin name that is relevant to the Absolute Maximum
Rating is listed. For full pin names of multifunction pins, refer to the Pin
Configuration and Function Descriptions section.
2 Restricted by maximum power dissipation.
3 See the Ordering Guide for additional information.
Rev. A | Page 5 of 16
HMC1099
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
NIC
NIC
1
2
3
4
5
6
7
8
24 GND
23 NIC
22
NIC
HMC1099
21 RFOUT/V
20
RFOUT/V
19 NIC
18 NIC
17 GND
RFIN/V
DD
DD
GG
TOP VIEW
RFIN/V
GG
(Not to Scale)
NIC
NIC
GND
NOTES
1. EXPOSED PAD. EXPOSED PAD MUST
BE CONNECTED TO RF/DC GROUND.
2. NO INTERNAL CONNECTION. THESE PINS
ARE NOT CONNECTED INTERNALLY.
Figure 2. Pin Configuration
Table 6. Pad Function Descriptions
Pin No.
Mnemonic Description
1, 8, 9, 16, 17, 24, 25, 32
2, 3, 6, 7, 10 to 15, 18,
19, 22, 23, 26 to 31
GND
NIC
Ground. These pins must be connected to RF/dc ground. See Figure 3 for the GND interface schematic.
No Internal Connection. These pins are not connected internally. However, all data was measured
with these pins connected to RF/dc ground externally.
4, 5
RFIN/VGG
RF Input (RFIN)/Gate Bias Control Voltage (VGG). This pin is a multifunction pin. The RFIN/VGG pin is
dc-coupled with internal prematching and requires external matching to 50 Ω, as shown in Figure 38.
See Figure 4 for the RFIN/VGG interface schematic.
20, 21
RFOUT/VDD RF Output (RFOUT)/Drain Bias Voltage (VDD). This is a multifunction pin. The RFOUT/VDD pin is dc-coupled
and requires external matching to 50 Ω, as shown in Figure 38. See Figure 4 for the RFOUT/VDD interface
schematic.
EPAD
Exposed Pad. The exposed pad must be connected to RF/dc ground.
INTERFACE SCHEMATICS
RFOUT/V
DD
GND
RFIN/V
GG
Figure 3. GND Interface
Figure 4. RFIN/VGG and RFOUT/VDD Interface
Rev. A | Page 6 of 16
Data Sheet
HMC1099
TYPICAL PERFORMANCE CHARACTERISTICS
30
25
21
17
13
9
20
10
0
–10
–20
+85°C
+25°C
–40°C
S11
–30
S21
S22
–40
5
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
0.2
0.4
0.6
0.8
1.0
1.2
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 5. Response (Gain and Return Loss) vs. Frequency
Figure 8. Gain vs. Frequency at Various Temperatures
0
0
–5
+85°C
+25°C
–40°C
–5
–10
–15
–20
–25
–10
–15
–20
–25
–30
–35
–40
+85°C
+25°C
–40°C
0
0.2
0.4
0.6
0.8
1.0
1.2
0
0.2
0.4
0.6
0.8
1.0
1.2
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 6. Input Return Loss vs. Frequency at Various Temperatures
Figure 9. Output Return Loss vs. Frequency at Various Temperatures
25
25
21
17
13
21
17
13
9
9
150mA
100mA
50mA
24V
28V
5
5
0
0.2
0.4
0.6
0.8
1.0
1.2
0
0.2
0.4
0.6
0.8
1.0
1.2
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 7. Gain vs. Frequency at Various Supply Voltages
Figure 10. Gain vs. Frequency at Various Supply Currents
Rev. A | Page 7 of 16
HMC1099
Data Sheet
44
43
42
41
40
39
38
37
36
45
40
35
30
25
P4dB
IN
SAT
+85°C
+25°C
–40°C
P
P
= 27dBm
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
FREQUENCY (GHz)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
FREQUENCY (GHz)
Figure 11. Power Output (POUT ) vs. Frequency
Figure 14. Output Power for 4 dB Compression (P4dB) vs. Frequency at
Various Temperatures
45
40
35
30
25
45
40
35
30
+85°C
+25°C
–40°C
24V
28V
25
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
FREQUENCY (GHz)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
FREQUENCY (GHz)
Figure 12. Output Power for 4 dB Compression (P4dB) vs. Frequency at
Various Supply Voltages
Figure 15. Saturated Output Power (PSAT) vs. Frequency at
Various Temperatures
45
40
35
30
45
40
35
30
25
150mA
100mA
50mA
24V
28V
25
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
FREQUENCY (GHz)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
FREQUENCY (GHz)
Figure 13. Saturated Output Power (PSAT) vs. Frequency at
Various Supply Voltages
Figure 16. Output Power for 4 dB Compression (P4dB) vs. Frequency at
Various Supply Currents
Rev. A | Page 8 of 16
Data Sheet
HMC1099
45
20
16
12
8
40
35
30
25
4
P4dB
150mA
100mA
50mA
P
P
= 27dBm
IN
SAT
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
FREQUENCY (GHz)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
FREQUENCY (GHz)
Figure 17. Saturated Output Power (PSAT) vs. Frequency at
Various Supply Currents
Figure 20. Power Gain vs. Frequency
55
55
52
49
46
43
40
52
49
46
43
40
+85°C
+25°C
–40°C
24V
28V
0
0.2
0.4
0.6
0.8
1.0
0
0.2
0.4
0.6
0.8
1.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 18. Output Third-Order Intercept (IP3) vs. Frequency at
Various Temperatures, POUT/Tone = 30 dBm
Figure 21. Output Third-Order Intercept (IP3) vs. Frequency at
Various Supply Voltages, POUT/Tone = 30 dBm
55
52
49
46
65
1GHz
0.5GHz
0.1GHz
60
55
50
45
40
35
30
25
43
150mA
100mA
50mA
40
0
0.2
0.4
0.6
0.8
1.0
10
12
14
16
18
20
22
24
26
28
30
32
FREQUENCY (GHz)
P
/TONE (dBm)
OUT
Figure 19. Output Third-Order Intercept (IP3) vs. Frequency at
Various Supply Currents, POUT/Tone = 30 dB
Figure 22. Output Third-Order Intermodulation (IM3) vs.
OUT/TONE at VDD = 24 V
P
Rev. A | Page 9 of 16
HMC1099
Data Sheet
65
60
55
50
45
40
35
30
25
90
80
70
60
50
40
30
20
10
0
900
800
700
600
500
400
300
200
100
0
P
1GHz
OUT
0.5GHz
0.1GHz
GAIN
PAE
I
DD
10
12
14
16
18
20
22
24
26
28
30
32
0
4
8
12
16
20
24
28
P
/TONE (dBm)
INPUT POWER (dBm)
OUT
Figure 26. Power Output (POUT), GAIN, Power Added Efficiency (PAE), and
Total Supply Current (IDD) vs. Input Power at 0.1 GHz
Figure 23. Output Third-Order Intermodulation (IM3) vs.
OUT/TONE at VDD = 28 V
P
80
70
60
50
40
30
20
10
0
850
750
650
550
450
350
250
150
50
80
70
60
50
40
30
20
10
0
800
700
600
500
400
300
200
100
0
P
P
OUT
OUT
GAIN
GAIN
PAE
PAE
I
I
DD
DD
0
4
8
12
16
20
24
28
0
4
8
12
16
20
24
28
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 24. Power Output (POUT), GAIN, Power Added Efficiency (PAE), and
Total Supply Current (IDD) vs. Input Power at 0.5 GHz
Figure 27. Power Output (POUT), GAIN, Power Added Efficiency (PAE), and
Total Supply Current (IDD) vs. Input Power at 1 GHz
90
80
70
60
50
40
30
0
–10
–20
–30
–40
–50
20
+85°C
+25°C
–40°C
+85°C
–60
–70
+25°C
–40°C
10
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
FREQUENCY (GHz)
0
0.2
0.4
0.6
0.8
1.0
1.2
FREQUENCY (GHz)
Figure 25. Power Added Efficiency (PAE) vs. Frequency at
Various Temperatures
Figure 28. Reverse Isolation vs. Frequency at Various Temperatures
Rev. A | Page 10 of 16
Data Sheet
HMC1099
45
40
35
30
25
20
15
45
40
35
30
25
20
15
10
GAIN
GAIN
P4dB (dBm)
P4dB (dBm)
P
(dBm)
P
(dBm)
SAT
SAT
10
24
25
26
(V)
27
28
50
70
90
110
130
150
V
I
(mA)
DD
DD
Figure 29. Gain, Output Power for 4 dB Compression (P4dB), and Saturated
Output Power (PSAT) vs. Supply Voltage (VDD) at 0.5 GHz
Figure 32. Gain, Output Power for 4 dB Compression (P4dB), and Saturated
Output Power (PSAT) vs. Supply Current (IDD) at 0.5 GHz
30
30
+85°C
+25°C
–40°C
24V
28V
25
25
20
15
10
5
20
15
10
5
0
0
0
0.2
0.4
0.6
0.8
1.0
0
0.2
0.4
0.6
0.8
1.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 30. Second Harmonic vs. Frequency at Various Temperatures
Figure 33. Second Harmonic vs. Frequency at Various Supply Voltages
30
25
20
15
10
10
1GHz
9
8
7
6
5
4
3
2
1
0
0.5GHz
0.1GHz
5dBm
10dBm
5
0
15dBm
20dBm
25dBm
0
0.2
0.4
0.6
0.8
1.0
0
4
8
12
16
20
24
28
FREQUENCY (GHz)
INPUT POWER (dBm)
Figure 31. Second Harmonic vs. Frequency at Various Input Power Levels
Figure 34. Power Dissipation vs. Input Power at Various Frequencies
Rev. A | Page 11 of 16
HMC1099
Data Sheet
12
10
8
12
10
8
6
6
4
4
+85°C
+25°C
–40°C
150mA
100mA
50mA
2
2
0
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
FREQUENCY (GHz)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
FREQUENCY (GHz)
Figure 35. Noise Figure vs. Frequency at Various Temperatures
Figure 37. Noise Figure vs. Frequency at Various Supply Currents
12
10
8
6
4
24V
28V
32V
2
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
FREQUENCY (GHz)
Figure 36. Noise Figure vs. Frequency at Various Supply Voltages
Rev. A | Page 12 of 16
Data Sheet
HMC1099
THEORY OF OPERATION
The HMC1099 is a >1 0 W, gallium nitride (GaN), power amplifier
that consists of a single gain stage that effectively operates like a
single field effect transistor (FET). The device is internally
prematched so that a simple, external matching network
optimizes the performance across the entire operating
frequency range. The recommended dc bias conditions put the
device in deep Class AB operation, resulting in high saturated
output power (40.5 dBm typical) at improved levels of power
efficiency (69% typical).
Rev. A | Page 13 of 16
HMC1099
Data Sheet
APPLICATIONS INFORMATION
The drain bias voltage is applied through the RFOUT/VDD pin,
and the gate bias voltage is applied through the RFIN/VGG pin.
For operation of a single application circuit across the entire
frequency range, it is recommended to use the external matching
components specified in the typical application circuit (L1, C1, L3,
and C8) shown in Figure 38. If operation is only required across
a narrower frequency range, performance may be optimized
additionally through the implementation of alternate matching
networks. Capacitive bypassing of VDD and VGG is recommended.
The recommended power-down bias sequence follows:
1. Turn off the RF signal.
2. Set VGG to −8 V to pinch off the drain current.
3. Set VDD to 0 V.
4. Set VGG to 0 V.
All measurements for this device were taken using the typical
application circuit, configured as shown in the assembly diagram
(see Figure 38). The bias conditions shown in the electrical
specifications table (see Table 1 to Table 3) are the operating
points recommended to optimize the overall performance.
Unless otherwise noted, the data shown was taken using the
recommended bias conditions. Operation of the HMC1099
under other bias conditions may provide performance that
differs from what is shown in the Typical Performance
Characteristics section.
The recommended power-up bias sequence follows:
1. Connect to the GND pin.
2. Set VGG to −8 V to pinch off the drain current.
3. Set VDD to 28 V (drain current is pinched off).
4. Adjust VGG more positive (approximately −2.5 V to −3.0 V)
until a quiescent of IDD = 100 mA is obtained.
5. Apply the RF signal.
The evaluation printed circuit board (PCB) provides the HMC1099
in its typical application circuit, allowing easy operation using
standard dc power supplies and 50 Ω RF test equipment.
TYPICAL APPLICATION CIRCUIT
V
DD
V
GG
C6
10µF
C9
10µF
C7
10µF
C10
10µF
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
C4
C5
2200pF
2200pF
R1
L2
0.9µH
C2
68.1Ω
C3
2200pF
2200pF
RFIN
RFOUT
L3
5.6nH
L1
5.4nH
C8
3.3pF
C1
3.3pF
9
10 11 12 13 14 15 16
Figure 38. Typical Application Circuit
Rev. A | Page 14 of 16
Data Sheet
HMC1099
sufficient number of via holes to connect the top and bottom
ground planes. The evaluation circuit board shown in Figure 39
is available from Analog Devices, Inc., upon request.
EVALUATION PCB
Use RF circuit design techniques for the circuit board used in
the application. Provide 50 Ω impedance for the signal lines and
directly connect the package ground leads and exposed paddle
to the ground plane, similar to that shown in Figure 39. Use a
Figure 39. Evaluation Printed Circuit Board
BILL OF MATERIALS
Table 7. Bill of Materials for Evaluation PCB EV1HMC1099LP5D
Item
Description
SMA connectors
DC pin
J2, J3
J1
J4
Preform jumper
C1, C8
C2 to C5
C6, C7, C9, C10
3.3 pF capacitors, 0603 package
2200 pF capacitors, 0603 package
10 μF capacitors, 1210 package
L1
5.4 nH inductor, 0906 package
L2
0.9 μH inductor, 1008 package
L3
5.6 nH inductor, 0402 package
R1
U1
PCB
68.1 Ω resistor, 0603 package
HMC1099LP5DE
600-00625-00-2 evaluation PCB, circuit board material: Rogers 4350 or Arlon 25FR
Rev. A | Page 15 of 16
HMC1099
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
32
24
1
0.50
BSC
3.15
3.00 SQ
2.85
EXPOSED
PAD
4.81 REF
SQ
8
17
16
9
0.55
0.50
0.35
0.50 MIN
TOP VIEW
SIDE VIEW
BOTTOM VIEW
3.50 REF
1.53
1.35
1.15
6° BSC
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
Figure 40. 32-Lead Lead Frame Chip Scale Package, Premolded Cavity [LFCSP_CAV]
5 mm × 5 mm Body and 1.34 mm Package Height
(CG-32-1)
Dimensions shown in millimeters
ORDERING GUIDE
MSL
Model1, 2
Temperature
Rating3
Description4
Package Option Branding5
HMC1099LP5DE
−40°C to +85°C MSL3
32-Lead LFCSP_CAV
CG-32-1
H1099
XXXX
H1099
XXXX
HMC1099LP5DETR
−40°C to +85°C MSL3
32-Lead LFCSP_CAV
CG-32-1
EV1HMC1099LP5D
Evaluation PCB
1 The HMC1099LP5DE and the HMC1099LP5DETR are LFCSP premolded copper alloy lead frame and RoHS Compliant.
2 When ordering the evaluation board only, reference the model number, EV1HMC1099LP5D.
3 See the Absolute Maximum Ratings section for additional information.
4 The lead finish of the HMC1099LP5DE and the HMC1099LP5DETR are nickel palladium gold (NiPdAu).
5 The 4-digit lot number for the HMC1099LP5DE and the HMC1099LP5DETR are represented by XXXX.
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registered trademarks are the property of their respective owners.
D13525-0-12/16(A)
Rev. A | Page 16 of 16
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