EVAL-AD7719-EB [ADI]
Evaluation Board for the AD7719, 16&24-Bit, Dual Sigma Delta ADC; 评估板为AD7719 ， 16 ＆ 24位，双通道Σ-Δ ADC
| 型号： | EVAL-AD7719-EB |
| 厂家： | 
ADI |
| 描述： | Evaluation Board for the AD7719, 16&24-Bit, Dual Sigma Delta ADC |
| 文件： | 总21页 (文件大小：1125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Evaluation Board for the AD7719,
16&24-Bit, Dua l Sigma Delta ADC
a
EVAL-AD7719-EB
ation board wh ich allows th e u ser to easily program th e
FEATURES
AD7719.
Full-Fe a ture d Eva lua tio n Bo a rd fo r the AD7719
O n-Bo a rd Re fe re nc e a nd Dig ita l Buffe rs
Va rio u s Lin kin g O p tio n s
Oth er com pon en ts on th e AD7719 Evalu ation Board
in clu de two AD780s (precision 2.5V referen ces), a
32.7680 kHz crystal an d digital bu ffers to bu ffer
sign als to an d from th e PC.
PC So ftw a re fo r C o n tro l o f AD7719
INTRO D U C TIO N
Th is Tech n ical Note describes th e evalu ation board
for th e AD7719, Low Voltage, Low Power, 16&24-
Bit, Du al Sigm a Delta ADC. Th e AD7719 is a
com plete an alog fron t en d for low frequ en cy m easu re-
m en t application s. Th e AD7719 is factory calibrated
an d th erefore does n ot requ ire field calibration . Th e
device can accept low level in pu t sign als directly from
a tran sdu cer an d produ ce a serial digital ou tpu t. It
em ploys a sigm a-delta con version tech n iqu e to realize
u p to 24 bits (Main ADC) or 16 bits (Au xiliary ADC)
of n o m issin g codes perform an ce. Th e selected in pu t
sign al is applied to a proprietary program m able gain
(Main ADC on ly) fron t en d based arou n d an an alog
m odu lator. Th e m odu lator ou tpu t is processed by an
on -ch ip digital filter. Th e first n otch of th is digital
filter can be program m ed via an on -ch ip con trol
register allowin g adju stm en t of th e filter cu toff an d
ou tpu t u pdate rate. Fu ll data on th e AD7719 is
available in th e AD7719 datash eet available from
An alog Devices an d sh ou ld be con su lted in con ju n c-
tion with th is Tech n ical Note wh en u sin g th e evalu a-
tion board.
OPERATING THE AD7 7 1 9 EVAL BOARD
Power Su pplies
Th is evalu ation board h as two an alog power su pply
in pu ts: AVDD an d AGND. An extern al +5V m u st be
applied between th ese in pu ts wh ich is u sed to provide
th e VDD for th e AD7719 an d th e referen ce. Digital
Power con n ection s are also requ ired th rou gh DGND
& DVDD
. Th e DVDD is u sed to provide th e DVDD for
th e digital circu itry. DGND an d AGND are con -
n ected togeth er at th e AD7719 GND pin . Th erefore,
it is recom m en ded n ot to con n ect AGND an d DGND
elsewh ere in th e system .
All power su pplies are decou pled to th eir respective
grou n ds. DVDD is decou pled u sin g a 10µF tan talu m
capacitor an d 0.1µF ceram ic capacitor at th e in pu t to
th e evalu ation board. It is again decou pled u sin g
0.1µF capacitors as close as possible to each logic
device. AVDD is decou pled u sin g a 10µF tan talu m
capacitor an d 0.1µF ceram ic capacitor as close as
possible to th e AD7719 an d also at th e referen ce.
The evalu ation board interfaces to the parallel port ofan
IBM compatible PC. Software is available with the evalu -
Fig. 1. Evaluation Board
Set-up
REV. B
Informa tion furnishe d b yAna log De vic e sisb e lie ve d to b e a c c ura te
a nd re lia b le . Howe ve r, no re sp onsib ility is a ssum e d b y Ana log
De vic e sforitsuse ,norfora nyinfring e me ntsofp a te ntsorothe rrig hts
of third p a rtie s whic h m a y re sult from its use . No lic e nse is g ra nte d
b y im p lic a tion or othe rwise und e r a ny p a te nt or p a te nt rig hts of
Ana log De vic e s.
One Te c hno lo g y Wa y, P.O. Bo x 9106, No rwo o d . MA 02062-9106,
U.S.A.
Te l: 617/ 329-4700
Fa x: 617/ 326-8703
EVAL-AD7719-EB
LINK AND S WITCH OP TIONS
Th ere are fou rteen lin k option s wh ich m u st be set for th e requ ired operatin g setu p before u sin g th e evalu ation
board. Th e fu n ction s of th ese lin k option s are ou tlin ed below.
Lin k No.
F u n c t io n
LK1-LK6 Th ese lin ks are in series with th e AIN1 th rou gh AIN6 an alog in pu ts respectively.
With th ese lin ks in place, th e an alog in pu ts on th e relevan t SKT in pu t is con n ected directly to th e
respective AIN in pu t on th e part. For exam ple, with LK1 in place, th e an alog in pu t applied to SKT1
is con n ected directly to AIN1 of th e AD7719.
LK7 &8
Th is option selects th e m aster clock sou rce for th e AD7719. Th e m aster clock is gen erated by th e
on -board crystal or from an extern al sou rce via SKT7. Th is is a dou ble lin k an d both lin ks m u st
be m oved togeth er for th e correct operation of th e evalu ation board.
With both lin ks in position "A", th e extern al clock option is selected an d an extern al clock applied
to SKT7 is rou ted to th e XTAL1 pin of th e AD7719.
With both lin ks in position "B", th e on -board crystal is selected to provide th e m aster clock to th e
AD7 7 1 9 .
LK9
Th is lin k is u sed to select th e referen ce sou rce for th e REFIN(-) in pu t of th e AD7719.
With th is lin k in position "A", REFIN1(-) is con n ected directly to AGND.
With th is lin k in position "B", th e voltage gen erated across R10 (IOUT1*R10) is selected as th e on -
board referen ce for REFIN(+). LK10 sh ou ld also be con n ected for th is set-u p to con n ect R10 an d
REFIN(-) to AGND. LK11 & LK12 sh ou ld also be con n ected for th is set-u p to con n ect IOUT1 to
R10.
With th is lin k in position "C", th e REFIN(-) pin is con n ected to SKT14. An extern al voltage applied
to SKT14 can n ow be u sed as th e REFIN(-) for th e AD7719.
LK1 0
Th is lin k is u sed to select th e referen ce sou rce for th e REFIN(+) in pu t of th e AD7719.
With th is lin k in position "A", REFIN1(+) is con n ected to th e ou tpu t of th e on -board referen ce
(AD780 - U6).
With th is lin k in position "B", th e REFIN1(+) pin is con n ected to SKT15. An extern al voltage
applied to SKT15 can n ow be u sed as th e REFIN(+) for th e AD7719.
With th is lin k in position "C", th e REFIN(+) pin is con n ected to AVDD.
Th is lin k sh ou ld be discon n ected if u sin g th e voltage gen erated across R10, du e to IOUT1.
Th is lin k is u sed for selectin g IOUT1*R10 as a referen ce voltage.
LK1 1
LK1 2
LK1 3
LK1 4
Th is lin k is u sed for selectin g IOUT1*R10 as a referen ce voltage.
Th is lin k is u sed for selectin g IOUT1*R10 as a referen ce voltage.
Th is lin k selects th e referen ce sou rce for th e REFIN2 in pu t of th e AD7719.
With th is lin k in positon "A", REFIN2 is con n ected to th e ou tpu t of th e on -board referen ce (AD780
- U2).
With th is lin k in position "B", th e REFIN2 pin is con n ected to SKT16. An extern al voltage applied
to SKT16 can n ow be u sed as th e REFIN2 for th e AD7719.
S E T -UP C O ND I T I O NS
Care sh ou ld be taken before applyin g power an d sign als to th e evalu ation board to en su re th at all lin k position s
are as per th e requ ired operatin g m ode. Table 1 sh ows th e position in wh ich all th e lin ks are set wh en th e
evalu ation board is sen t ou t.
Table 1 : In it ial Lin k an d Swit ch Posit ion s
Lin k No.
Po s it io n
F u n c t io n
LK1 -LK6 IN
AD7 7 1 9 .
Con n ects an alog in pu ts from SKT1-SKT6 to th e in pu t pin s AIN1-AIN6 of th e
LK7 &LK8 B+B
AD7 7 1 9 .
Both lin ks in position B to select th e on -board crystal as th e m aster clock for th e
Th is con n ects th e REFIN1(-) in pu t of th e AD7719 to AGND.
LK9
A
-2-
Rev. B
EVAL-AD7719-EB
LK10
A
Th e on -board referen ce (U6) provides th e referen ce voltage for th e REFIN1(+) in pu t
ofthe AD7719.
LK11
LK12
LK13
LK14
OUT
OUT
OUT
A
IOUT1*R10 n ot u sed as REFIN1 voltage referen ce.
IOUT1*R10 n ot u sed as REFIN1 voltage referen ce.
IOUT1*R10 n ot u sed as REFIN1 voltage referen ce.
Th e on -board referen ce (U2) provides th e referen ce voltage for th e REFIN2 in pu t of th e
AD7719.
E VALUAT IO N BO AR D INT E R F AC ING
Interfacing to the evalu ation board is via either a 9-way d-type connector, J 4 or a 36-way centronics connector, J 1. The
pin -ou t for th e J 4 con n ector is sh own in Fig. 2 an d its pin design ation s are given in Table 2. Th e pin -ou t for th e J 1
con n ector is sh own in Fig. 3 an d its pin design ation s are given in Table 3.
J 1 is u sed to connect the evalu ation board to the parallel(printer)port ofa PC. Connection is via a standard printer cable.
J 4 is u sed to con n ect th e evalu ation to an y oth er system . Th e evalu ation board sh ou ld be powered u p before a cable
is con n ected to eith er of th ese con n ectors.
1
2
3
4
5
6
7
8
9
Fig. 2: Pin Configuration for the 9-Way D-Type Connector, J4.
1
Table 2 .:
J 4 Pin Descript ion
1
S C LK
Serial Clock. Th e sign al on th is pin is bu ffered before bein g applied to th e SCLK pin of th e
AD7 7 1 9 .
2
3
4
5
6
7
8
RDY
CS
Logic ou tpu t. Th is is a bu ffered version of th e sign al on th e AD7719 RDY pin
Ch ip Select. Th e sign al on th is pin is bu ffered before bein g applied to th e CS pin on th e AD7719.
RESET Reset In pu t. Data applied to th is pin is bu ffered before bein g applied to th e AD7719 RESETpin .
DIN
Serial Data In pu t. Data applied to th is pin is bu ffered before bein g applied to th e AD7719 DIN pin .
Grou nd reference point for the digital circu itry. Connects to the DGND plane on the Evalu ation board.
Serial Data Ou tpu t. Th is is a bu ffered version of th e sign al on th e AD7719 DOUT pin .
DGND
DOUT
DVDD
DigitalSu pply Voltage. Ifno voltage is applied to the board's DVDD inpu t terminalthen the voltage applied
to th is pin will su pply th e DVDD for th e digital bu ffers.
9
NC
Not Connected.
Note
1 An explanation ofthe AD7719 fu nctions m entioned here is given in Table 3 below as part of the J 1 pin descriptions.
Table 3 : 3 6 -Way Con n ect or Pin Descript ion
1
2
N C
No Con n ect. Th is pin is n ot con n ected on th e evalu ation board.
D I N
Serial Data In pu t. Data applied to th is pin is bu ffered before bein g applied to th e
AD7719 DIN pin . Serial Data In pu t with serial data bein g written to th e in pu t sh ift
register on th e part. Data from th is in pu t sh ift register is tran sferred to th e calibration
or con trol registers, depen din g on th e register selection bits of th e Com m u n ication s
Register.
3
RESET
Reset In pu t. Th e sign al on th is pin is bu ffered before bein g applied to th e RESETpin of th e
AD7719. RESET is an a ctive low in pu t wh ich resets th e con trol logic, in terface logic,
calibration coefficien ts, digital filter an d analog m odu lator of th e part to power-on statu s.
-3-
Rev. B
EVAL-AD7719-EB
1
18
19
36
Fig. 3: 36-w a y Centronics (SKT2) Pin Configura tion
4
CS
Ch ip Select. Th e sign al on th is pin is bu ffered before bein g applied to th e CS pin of th e
AD7719. CS is an active low Logic In pu t u sed to select th e AD7719. With th is in pu t h ard-
wired low, the AD7719 can operate in its three-wire interface mode with SCLK, DINand DOUT
u sed to interface to the device. CS can be u sed to select the device in systems with more than
one device on the serialbu s or as a frame synchronization signalin commu nicating with the
AD7719.
5
6
SCLK
Serial Clock. Th e sign al on th is pin is bu ffered before bein g applied to th e SCLK pin of th e
AD7719. An externalserialclock is applied to this inpu t to read/ write serialdata from/ to the
AD7719. This serialclock can be continu ou s with alldata transmitted in a continu ou s train
ofpu lses. Alternatively, it can be non-continu ou s with the information being transmitted to
the AD7719 in smaller batches ofdata.
SYNC
Logic In pu t. Th e sign al on th is pin is bu ffered before bein g applied to th e SYNCpin of th e
AD7719. Th e SYNCin pu t allows for syn ch ron isation of th e digital filters an d m odu lators
across a n u m ber of AD7719s. Wh ile SYNC is low, th e n odes of th e digital filter, th e filter
con trol logic an d th e calibration con trol logic are h eld in a reset state.
7-8
9
N C
No Con n ect. Th ese pin s are n ot con n ected on th e evalu ation board.
DVDD
Digital Su pply Voltage. Th is provides th e su pply voltage for th e bu ffer ch ips, U3-U5,
wh ich bu ffer th e sign als between th e AD7719 an d J 1/ J 4.
10
RDY
Logic ou tpu t. Th is is a bu ffered version of th e sign al on th e AD7719 RDY pin . A logic low
on th is ou tpu t in dicates th at eith er th e Main ADC or Au xiliary ADC h as valid data in th eir
data register. The RDYpin willreturn high upon completion ofa read operation ofa fulloutput
word. Ifdata is not read RDY will retu rn high prior to the next u pdate indicating to the u ser
th at a read operation sh ou ld n ot be in itiated. Th e RDY pin also retu rn s low after th e
completion ofa calibration cycle. The RDYpin is effectively the NOR ofthe RDY0 and RDY1
bits in the Statu s register. Ifone ofthe ADCs is disabled the RDYpin reflects the active ADC.
RDYdoes not retu rn high aftera calibration u ntilthe mode bits are written to enabling a new
conversion or calibration.
11-12
13
NC
No Con n ect. Th ese pin s are n ot con n ected on th e evalu ation board.
DOUT
Serial Data Ou tpu t. This is a bu ffered version ofthe signal on the AD7719 DOUTpin. Serial
Data Output with serialdata obtained from the output shift register on the AD7719. The output
shift register can contain information from ofthe on-chip registers depending on the register
selection bits ofthe Commu nications Register.
14-18
19-30
NC
No Con n ect. Th ese pin s are n ot con n ected on th e evalu ation board.
DGND
Grou nd reference point for digital circu itry. Connects to the DGND plane on the evalu ation
board.
31-36
NC
No Con n ect. Th ese pin s are n ot con n ected on th e evalu ation board.
S O C K E T S
Th ere are eigh teen sockets relevan t to th e operation of th e AD7719 on th is evalu ation board. Th e fu n ction s of
th ese sockets are ou tlin ed in Table 4.
Table 4. Socket Funct ions
Socket
Function
J4
9-way D-Type con n ector u sed to in terface to oth er system s.
-4-
Rev. B
EVAL-AD7719-EB
Su b-Min iatu re BNC (SMB) Con n ector. Th e
AD7719 current sourcepin IOUT2 is connected
to th is socket.
J1
36-waycentronics connector used to interface
to PC via parallel printer port.
SKT13
SKT14
SKT1
Su b-Min iatu re BNC (SMB) Con n ector. Th e
an alog in pu t sign al for th e AIN1 in pu t of th e
AD7719 is applied to th is socket.
Su b-Min iatu re BNC (SMB) Con n ector. Th e
referen ce voltage for th e REFIN1(-) in pu t of
the AD7719 is applied to this socket when the
board is con figu red for an extern ally applied
referen ce voltage.
SKT2
SKT3
SKT4
SKT5
SKT6
SKT7
Su b-Min iatu re BNC (SMB) Con n ector. Th e
an alog in pu t sign al for th e AIN2 in pu t of th e
AD7719 is applied to th is socket.
Su b-Min iatu re BNC (SMB) Con n ector. Th e
an alog in pu t sign al for th e AIN3 in pu t of th e
AD7719 is applied to th is socket.
SKT15
SKT16
Su b-Min iatu re BNC (SMB) Con n ector. Th e
referen ce voltage for th e REFIN1(+) in pu t of
the AD7719 is applied to this socket when the
board is con figu red for an extern ally applied
referen ce voltage.
Su b-Min iatu re BNC (SMB) Con n ector. Th e
an alog in pu t sign al for th e AIN4 in pu t of th e
AD7719 is applied to th is socket.
Su b-Min iatu re BNC (SMB) Con n ector. Th e
referen ce voltage for th e REFIN2 in pu t of th e
AD7719 is applied to th is socket wh en th e
board is con figu red for an extern ally applied
referen ce voltage.
Su b-Min iatu re BNC (SMB) Con n ector. Th e
an alog in pu t sign al for th e AIN5 in pu t of th e
AD7719 is applied to th is socket.
Su b-Min iatu re BNC (SMB) Con n ector. Th e
an alog in pu t sign al for th e AIN6 in pu t of th e
AD7719 is applied to th is socket.
C O N N E C T O R S
Th ere are two con n ectors on th e AD7719 evalu ation
board as ou tlin ed in Table 5.
Su b-Min iatu re BNC (SMB) Con n ector. Th e
master clock signalfor the XTAL1 inpu t ofthe
AD7719 is applied to th is socket wh en th e
board is con figu red for an extern ally applied
m aster clock.Th e AD7719 can be operated
with in tern al clock frequ en cies in th e ran ge
32.768 kHz+/ -10%.
Table 5 . Con n ect or Fu n ct ion s
Co n n e c t o r
Fu n c t ion s
J3
PCB Mou n tin g Term in al Block. Th e
Digital Power Su pply to th e Evalu a-
tion Board is provided via th is Con -
n ector if it is n ot bein g su pplied via
SKT1 or SKT2.
SKT8
SKT9
SKT10
Su b-Min iatu re BNC (SMB) Con n ector. Th e
output value from AD7719 output pin P1/ SW1
is available from this socket.
Su b-Min iatu re BNC (SMB) Con n ector. Th e
output value from AD7719 output pin P2/ SW2
is available from this socket.
J2
PCB Mou n tin g Term in al Block. Th e
An alog Power Su pply to th e Evalu a-
tion Board m u st be provided via th is
Con n ector.
Su b-Min iatu re BNC (SMB) Con n ector. Th e
ou tpu t valu e from th e AD7719 I/ O pin P3 is
available from th is socket wh en P3 is
configu red as an ou tpu t. The inpu t signal for
AD7719 I/ O pin P3 is applied to th is in pu t
when P3 is configu red as an inpu t.
SWITCHES
There is one switch on the AD7719 Evaluation board. SW1
is a pu sh -bu tton reset switch . Pu sh in g th is switch acti-
vates th e active low RESET in pu t on th e AD7719 wh ich
resets the control logic, interface logic, calibration coeffi-
cien ts, digital filter an d an alog m odu lator of th e part to
power-on statu s.
SKT11
SKT12
Su b-Min iatu re BNC (SMB) Con n ector. Th e
ou tpu t valu e from th e AD7719 I/ O pin P4 is
available from th is socket wh en P4 is
configu red as an ou tpu t. The inpu t signal for
AD7719 I/ O pin P4 is applied to th is in pu t
when P4 is configu red as an inpu t.
Su b-Min iatu re BNC (SMB) Con n ector. Th e
AD7719 current sourcepin IOUT1 is connected
to th is socket.
-5-
Rev. B
EVAL-AD7719-EB
AD7 7 1 9 SOFTWARE DESCRIPTION
The AD7719 evalu ation board is shipped with a CD-ROM containing software that can be installed onto a standard PC
to control the AD7719.
The software u ses the printer port ofthe PC to commu nicate with the AD7719, so a Centronics printer cable is u sed to
con n ect th e PC to th e evalu ation board.
Soft ware Requirem en t s an d In st allat ion
Th e software ru n s u n der Win dows ME 2000 NT™ an d typically requ ires 8Mb of RAM.
To install the software the u ser shou ld start Windows and insert the CD-ROM disc. The installation software shou ld
lau nch au tom atically. Ifnot, u se Windows Explorer to locate the file 'setu p.exe' on the CD-ROM. Dou ble clicking on
th is file will start th e in stallation procedu re. Th e u ser is prom pted for a destin ation directory wh ich is "C:\ Program
Files\ ANALOG DEVICES\ AD7719"bydefau lt. Once the directoryhas been selected the installation procedu re willcopy
th e files in to th e relevan t directories on th e h ard drive. Th e in stallation program will create a Program Grou p called
"Analog Devices"with su b-grou p 'AD7719' in the "Start"taskbar. Once the installation procedu re is complete the u ser
can dou ble click on th e AD7719 icon to start th e program .
Feat ures of t h e Soft ware
1. Th e software will allow th e u ser to write to an d read from all th e registers of th e AD7719.
2. Data can be read from th e AD7719 an d displayed or stored for later an alysis.
3. Th e data th at h as been read can be exported to oth er packages su ch as Math cad or Excel for fu rth er an alysis.
-6-
Rev. B
EVAL-AD7719-EB
Wh at follows is a description of th e variou s win dows th at appear wh ile th e software is bein g u sed. Fig. 4. sh ows th e
main screen that appears once the program has started. The printer port that willbe u sed by the software is determined
au tomatically. There are three possible printer ports that can be handled by the software, LPT1 (standard), LPT2 and
PRN. The u ser can change to another printer port by clicking on the "Printer Port"dropdown menu . Abriefdescription
of each of th e bu tton s on th e m ain screen follows:
Program AD7719
Allows the u ser to program or read the on-chip registers ofthe AD7719.
Read Data from Main ADC
Allows the u ser to read a nu mber ofsamples from the AD7719 Main ADC.
These samples can be stored for fu rther analysis or ju st displayed for reference.
Read Data from AuxADC
Main ADC Noise Analysis
Aux ADC Noise An alysis
Allows the u ser to read a nu mber ofsamples from the AD7719 Au x ADC. These
samples can be stored for fu rther analysis or ju st displayed for reference.
Allows the u ser to perform noise analysis on the data that has been read in from the
Main ADC.
Allows the u ser to perform noise analysis on the data that has been read in from the
Au x ADC.
ResetAD7719
Allows the u ser to perform a software or hardware reset on the AD7719.
Read From File
Allows the u ser to read in previou sly stored data for display or analysis - u ser needs
to specify Au x or Main ADC data.
Write To File
Allows the u ser to write the cu rrent set of data to a file for later u se - u ser needs to
specify Au x or Main ADC data.
About
Provides information abou t the version of software being u sed.
Read Dual ADC
Allows the u ser to display samples from the Main and Au x ADCs
simu ltaneou sly. These samples can be stored for fu rther analysis or ju st displayed
for reference.
Quit
Ends the program
Fig. 4 . Th e Ma in Screen
-7-
Rev. B
EVAL-AD7719-EB
Th e Program AD7719 Screen
Fig. 5. shows the screen that appears when the Program AD7719 bu tton is selected. This screen allows the u ser to select
which register is to be programmed.
Fig. 5 . Th e Progra m AD7 7 1 9 Screen
-8-
Rev. B
EVAL-AD7719-EB
Fig. 6 . Th e Filter Regis ter Screen
Th e Filt er Regist er Screen
Fig. 6. shows the Filter Register screen. When the screen is loaded the software will read the cu rrent contents from the
Filter Register ofthe AD7719 and change the display accordingly. The Filter register is u sed to change the u pdate rate
ofthe AD7719, the allowable range for the word written to the Filter Register is 13(dec)to 255(dec)or 0D(Hex)to FF(Hex).
Th e u ser can en ter th e filter word in Hex valu es in th e text box provided. Th e u ser sh ou ld con su lt th e datash eets for
m ore inform ation on th e u se of the Filter Register.
-9-
Rev. B
EVAL-AD7719-EB
Th e Main ADC Calibrat ion Regist ers Screen
Fig. 7. sh ows th e Main ADC Calibration Registers screen . Wh en th is screen is displayed th e valu es of th e Gain an d
Offset Registers are read from the Main ADC ofthe AD7719 and displayed. The u ser has the ability to change the valu es
ofeither register ifrequ ired. the defau lt valu e for the Fu llscale Main CalRegister is 535xx5 hex and the defau lt valu e for
the Zero Scale Main CalRegister is 800000 hex. The Au x ADC Calibration Registers screen has the same fu nction with
the defau lt valu es being 555Xhex for the Fu llScale Au x CalRegister and 8000 hex for the Zero Scale Au x CalRegister.
Fig. 7. The Calibration Registers Screen
-10-
Rev. B
EVAL-AD7719-EB
Th e Main ADC Con t rol Regist er Screen
Fig. 8. sh ows th e Main ADC Con trol Register Screen . Th is register con trols th e Word-len gth , Bipolar/ Un ipolar
operation , Ch an n el selection an d Ran ge selection for th e Main ADC. Wh en th e screen is loaded th e software reads
th e cu rren t con ten ts from th e Main ADC Con trol Register of th e AD7719 an d sets th e bu tton s accordin gly. Note
ifthe Channel Configu re bit is set in the Mode Register the channels the Main and Au x ADCs can u se is changed - see
AD7719 datasheets for m ore inform ation. Everytim e a change is m ade, the software writes the new conditions to the
AD7719 an d th en reads back from th e Main ADC Con trol Register for con form ation . Th e Au x ADC Con trol Register
Screen performs a similar operation for the Au x ADC Control Register - see AD7719 datasheets for more information.
Fig. 8 . Th e Ma in ADC Con trol Regis ter Screen
-11-
Rev. B
EVAL-AD7719-EB
Fig. 9 . Th e I/ O a n d Cu rren t Sou rce Con trol Regis terScreen
Th e I/ O an d Curren t Source Con t rol Regist er Screen
Fig.9. shows th e I/ O an d Cu rren t Sou rce Con trol Register Screen. Th is screen allows th e u ser to con trol th e on -ch ip
200u A cu rren t sou rces an d also th e two I/ O ports P3 & P4 an d th e ou tpu t ports P1 & P2. Wh en th e screen is loaded,
th e software reads th e cu rren t con ten ts of th e I/ O an d Cu rren t Sou rce Con trol Register of th e AD7719 an d sets th e
bu ttons accordingly. The cu rrent sou rces IEXC1 &IEXC2 can be enabled and directed to the two AD7719 ou tpu t pins
IOUT1 & IOUT2 by th e u ser. Th e on -ch ip bu rn ou t cu rren t can be tu rn ed on / off by th e u ser.
Th e two I/ 0 ports P3 & P4 can be selected as in pu ts or ou tpu ts, th e u ser can set th e ou tpu ts as requ ired - n ote 'h igh '
represents a 5V ou tpu t on th e pin , 'low' represen ts AGND. Th e u ser can also read in th e valu e at th e in pu ts P3 & P4 if
configu red as inpu ts. Note pressingUpdate Displaybu tton willread the cu rrent contents ofthe I/ O and Cu rrent Sou rce
Control Register and u pdate the screen.
The two ou tpu ts P1 &P2 can be configu red as a standard Ou tpu t pin or as a Power Switch to PWRGND. When selected
as an Ou tpu t pin P1 or P2 can be enabled as a regu lar digitalou tpu t or as a tri-state ou tpu t. Everytime a change is made,
the software writes the new conditions to the AD7719 and then reads back from the I/ O and Cu rrent Sou rce Control
Register for con form ation - ign orin g databits P1DAT - P4DAT. Refer to AD7719 datash eets for m ore in form ation .
Th e Mode Regist er Screen
The Mode Register Screen is shown in Fig. 10. When the screen is loaded the software reads the cu rrent contents from
the Mode Register ofthe AD7719 and sets the bu ttons accordingly. This screen allows the u ser to change the operating
mode ofthe AD7719, change the channel configu ration and power down the crystal oscillator. When the u ser selects
a calibration the software will start a calibration by writing to the AD7719 (prompt u ser for inpu t ifsystem calibration)
and then monitor the RDYpin. Afalling edge ofthe RDYpin willindicate that the calibration has been completed. After
a calibration th e AD7719 is placed in th e idle m ode an d th e screen is u pdated to in dicate th is. Everytim e a ch an ge is
m ade, th e software writes th e n ew con dition s to th e AD7719 an d th en reads back from th e Mode Register for
con form ation . Th e AD7719 sh ou ld be powered-down or placed in Idle Mode before writin g to Filter, ADC Con trol or
Calibration registers. The defau lt statu s for the Mode register is 0 hex - refer to AD7719 datasheets for more information.
-12-
Rev. B
EVAL-AD7719-EB
Fig. 1 0 . Th e Mod e Regis ter Screen
Th e St at us Regist er Screen
Fig. 11. sh ows th e Statu s Register Screen . Wh en th e screen is loaded th e software reads th e cu rren t con ten ts from
th e Statu s Register of th e AD7719 an d sets th e bu tton s accordin gly. Th is is a read-on ly register an d flags th e
operatin g con dition s of th e AD7719 su ch as data ready or Main ADC Error. Refer to AD7719 datash eets for m ore
information.
Fig. 1 1 . Th e Sta tu s Regis ter Screen
-13-
Rev. B
EVAL-AD7719-EB
Fig. 1 2 . Th e Rea d Da ta from Ma in ADC Screen
Th e Read Dat a from Main ADC Screen
Fig. 12. shows the Main ADC Read Data screen. This is where the u ser can read a nu mber ofsamples from the AD7719
Main ADC. Th e u ser h as th e option of eith er readin g data for an alysis or display.
When the Read For Analysis bu tton is selected the software willread the requ ired nu mber ofsamples from the AD7719
Main ADC an d store th em in an array so th at th ey can be graph ed or an alysed later. It is possible to read an d graph
u p to 5000 sam ples at any one tim e. The read can be interru pted with a u ser key press.
When the Read for Display bu tton is selected the software will read one sample from the AD7719 and display its valu e
in the Cu rrent Code text box. The software will continu e to read and display the samples u ntil a key has been pressed.
It is possible to add a delay to the read cycle by entering the requ ired nu mber ofmilliseconds between reading samples.
It sh ou ld be n oted h owever th at th e accu racy of th e tim e delay can be affected by oth er program s ru n n in g u n der
Windows, therefore this method is not su itable where equ idistant sampling is requ ired. Note the Read Data from Au x
ADC Screen has a similar fu nction to the Read Data from Main ADC Screen, only reading from the Au x ADC and storing
in a seperate array.
-14-
Rev. B
EVAL-AD7719-EB
Fig. 1 3 . Th e Rea d Da ta from Du a l ADC Screen
Th e Read Dat a from Du al ADC Screen
Fig. 13 shows th e Read Data from Du al ADC display. Th is is wh ere th e u ser can read a n u m ber of sam ples from both
ADCs sim u ltan eou sly. Th e resu lts are stored in two arrays so th at th e resu lts can be graph ed or an alysed later by
selectin g th e Au x or Main ADC Noise An alysis Bu tton s on th e Main Men u Screen . It is possible to read an d graph u p
to 5000 samples at any one time. The read can be interru pted with a u ser key press. Note both ADCs mu st be enabled
for this screen to operate. The u ser is informed ifboth ADCs aren't enabled. This will also overwrite resu lts from single
Main or Au x ADC an alysis u n less th e data h as been saved.
When the Read for Display bu tton is selected the software will read one sample from the AD7719 and display its valu e
in the Cu rrent Code text box. The software will continu e to read and display the samples u ntil a key has been pressed.
It is possible to add a delay to the read cycle by entering the requ ired nu mber ofmilliseconds between reading samples.
It sh ou ld be n oted h owever th at th e accu racy of th e tim e delay can be affected by oth er program s ru n n in g u n der
Windows, therefore this m ethod is not su itable where equ idistant sam pling is requ ired.
-15-
Rev. B
EVAL-AD7719-EB
Fig. 1 4 . Th e Ma in ADC Nois e An a lys is Screen
Th e Main ADC Noise An alysis Screen
On ce data h as been read from th e AD7719 Main ADC, it is possible to perform som e an alysis on it. Fig. 14 sh ows th e
Main ADC Noise Analysis Screen. This screen displays the maximu m and minimu m codes read from the AD7719 Main
ADC (in decim al an d h exadecim al), as well as th e average code, th e average valu e an d th e RMS an d Peak-Peak n oise
valu es. From this screen it is possible to display the data on a graph or as a histogram of codes. Figu res 15 & 16 show
the Graph and Histogram screens. The Au x ADC Noise Analysis Screen performs the same fu nction on data from the
Au x ADC.
Th e Main ADC Graph Screen
Fig. 15 sh ows th e Main ADC Graph Screen . Th is screen displays th e data in a graph form at. A grid can be placed
on th e graph by pressin g th e Grid on / off bu tton . Th e graph screen also h as zoom an d scroll fu n ction s u sin g th e
two wh ite h an dles at eith er en d of th e x-axis.
Fig. 1 5 . Th e Ma in ADC Gra ph Screen
-16-
Rev. B
EVAL-AD7719-EB
Fig. 1 6 . Th e Ma in ADC His togra m Screen
-17-
Rev. B
EVAL-AD7719-EB
Fig. 1 7 . Th e Eva lu a tion Boa rd Sch ema tic
-18-
Rev. B
EVAL-AD7719-EB
Table 6 . Com pon en t List in g an d Man u fact u rers
I NT E GR AT E D C I R C UI T S
Co m p o n e n t
AD7 7 1 9
Lo c a t io n
U 1
Ve n d o r
An alog Devices
An alog Devices
Ph ilips
AD 7 8 0 AN
7 4 HC4 0 5 0 N
7 4 C0 8 S MD
7 4 ACT2 4 4
S D1 0 3 C
U2/ U6
U 3
U 4
Texas In stru m en ts
Fairch ild Sem icon du ctor
I T T
U 5
D1/ D2
C AP AC I T O R S
Co m p o n e n t
Lo c a t io n
Ve n d o r
10µF ± 20% Tan talu m (16 V) C12 C13 C17 C19 C20 C22 C23 C24 AVX-Kyocera
Mftrs No. TAG106MO16
FEC No. 499-768
0.1µF Ceram ic (0805 SMD)
0.1u F Ceram ic (X7R ±20%)
C1-C6 C8 C15 C18 C21
C7 C9 C10 C11 C14 C16
Ph ilips
Mftrs No. CW20C104M
R E S I S T O R S
Co m p o n e n t
Sh ort Circu its
Lo c a t io n
Ve n d o r
R1-R6
Bou rns
10kΩ±5% 0.25W Carbon Film R7-R9
12kΩ±5% 0.25W Carbon Film R10
Bou rns
Bou rns
Bou rns
3kΩ±5% 0.25W Carbon Film
R12
LINK O P T IO NS
Co m p o n e n t
Lo c a t io n
Ve n d o r
Pin Headers
Lk1-Lk6 Lk11-Lk13 (1x2 way)
Lk7 Lk8 (2x2 way)
Ha rwin
Mftrs No. M20-9983606
Lk9 Lk10 Lk14 (3x2 way)
Sh ortin g Plu gs
Pin Headers
Ha rwin
(14 requ ired)
Mftrs No. M7571-05
S W I T C H
Co m p o n e n t
Lo c a t io n
Ve n d o r
Sealed Pu sh Bu tton Switch
S W1
Om ron Mftrs No. B3W1000
S O C K E T S
Co m p o n e n t
Lo c a t io n
Ve n d o r
Min iatu re BNC Con n ectors
S KT1 - S KT1 6
M/ A - Com Green par
Mftrs No. B65N07G999X99
9-Way D-Type Con n ector
J4
McMu rdo Mftrs No. SDE9PNTD
-19-
Rev. B
EVAL-AD7719-EB
36 Way Cen tron ics Con n ector
2 Way Term in al Block
Low profile socket
J1
Fu jitsu Mftrs No. FCN785J 036G0
Bu lgin RIA
J 1 J 2
U2 , U3 , U6
Harwin (32 pin s n eeded)
Farn ell No. 519-959
CR YS TAL
OS CILLATOR
Co m p o n e n t
Lo c a t io n
Ve n d o r
32.768 kHz Oscillator
Xtal 1
I Q D
FEC No. 221-533
Fig. 1 8 . Th e Eva lu a tion Boa rd Compon en t La you t Dia gra m
-20-
Rev. B
EVAL-AD7719-EB
Fig. 1 9 . Th e Eva lu a tion Boa rd Compon en t Sid e Artw ork
Fig. 2 0 . Th e Eva lu a tion Boa rd Sold er Sid e Artw ork
-21-
Rev. B
相关型号：
©2020 ICPDF网 联系我们和版权申明