EVAL-AD7678CBZ [ADI]
18-Bit, 2.5 LSB INL, 100 kSPS SAR ADC;
| 型号： | EVAL-AD7678CBZ |
| 厂家： | 
ADI |
| 描述： | 18-Bit, 2.5 LSB INL, 100 kSPS SAR ADC |
| 文件： | 总29页 (文件大小：437K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
18-Bit, 2.5 LSB INL, 100 kSPS SAR ADC
AD7678
FUNCTIONAL BLOCK DIAGRAM
FEATURES
PDBUF
REF
REFGND
DVDD DGND
18-bit resolution with no missing codes
No pipeline delay (SAR architecture)
Differential input range: ±±REF (±REF up to 5 ±)
Throughput: 100 kSPS
AGND
AVDD
OVDD
OGND
AD7678
SERIAL
PORT
REFBUFIN
INL: ±2.5 LSB max (±9.5 ppm of full scale)
Dynamic range: 103 dB typ (±REF = 5 ±)
S/(N+D): 100 dB typ @ 2 kHz (±REF = 5 ±)
Parallel (18-,16-, or 8-bit bus) and serial 5 ±/3 ± interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
On-board reference buffer
18
IN+
IN–
SWITCHED
CAP DAC
D[17:0]
BUSY
PARALLEL
INTERFACE
RD
CS
CLOCK
PD
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
MODE0
MODE1
RESET
Single 5 ± supply operation
Power dissipation:18 mW @ 100 kSPS
180 μW @ 1 kSPS
CNVST
03084–0–001
48-lead LQFP or 48-lead LFCSP package
Pin-to-pin compatible upgrade of AD7674/AD7676/AD7679
Figure 1. Functional Block Diagram
Table 1. PulSAR Selection
APPLICATIONS
800–
1000
CT scanners
Type/kSPS
100–250
500–570
High dynamic data acquisition
Geophone and hydrophone sensors
- replacement (low power, multichannel)
Instrumentation
Spectrum analysis
Medical instruments
Pseudo-
Differential
AD7651
AD7650/AD7652 AD7653
AD7660/AD7661 AD7664/AD7666 AD7667
True Bipolar
AD7663
AD7675
AD7665
AD7676
AD7671
AD7677
True
Differential
18-Bit
AD7678
AD7679
AD7674
Multichannel/
Simultaneous
AD7654
AD7655
GENERAL DESCRIPTION
The AD7678 is an 18-bit, 100 kSPS, charge redistribution SAR,
fully differential analog-to-digital converter that operates on a
single 5 V power supply. The part contains a high speed 18-bit
sampling ADC, an internal conversion clock, an internal
reference buffer, error correction circuits, and both serial and
parallel system interface ports.
PRODUCT HIGHLIGHTS
1. High Resolution, Fast Throughput.
The AD7678 is a 100 kSPS, charge redistribution, 18-bit
SAR ADC (no latency).
2. Excellent Accuracy.
The part is available in 48-lead LQFP or 48-lead LFCSP
packages with operation specified from –40°C to +85°C.
The AD7678 has a maximum integral nonlinearity of
2.5 LSB with no missing 18-bit codes.
3. Serial or Parallel Interface.
Versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial
interface arrangement compatible with both 3 V and
5 V logic.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights ofthird parties that may result fromits use. Specifications subject to change without notice. No
licenseis granted byimplication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved.
AD7678* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DESIGN RESOURCES
• AD7678 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
EVALUATION KITS
• AD7678 Evaluation Kit
DOCUMENTATION
Application Notes
DISCUSSIONS
View all AD7678 EngineerZone Discussions.
• AN-931: Understanding PulSAR ADC Support Circuitry
• AN-932: Power Supply Sequencing
Data Sheet
SAMPLE AND BUY
Visit the product page to see pricing options.
• AD7678: 18-Bit, 2.5 LSB INL, 100 kSPS SAR ADC Data Sheet
Product Highlight
TECHNICAL SUPPORT
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number.
• 8- to 18-Bit SAR ADCs ... From the Leader in High
Performance Analog
DOCUMENT FEEDBACK
REFERENCE MATERIALS
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Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
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AD7678
TABLE OF CONTENTS
Specifications..................................................................................... 3
Digital Interface.......................................................................... 20
Parallel Interface......................................................................... 20
Serial Interface............................................................................ 20
Master Serial Interface............................................................... 21
Slave Serial Interface .................................................................. 22
Microprocessor Interfacing....................................................... 24
Application Hints ........................................................................... 25
Layout .......................................................................................... 25
Evaluating the AD7678’s Performance.................................... 25
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Definition of Specifications........................................................... 11
Typical Performance Characteristics ........................................... 12
Circuit Information........................................................................ 15
Converter Operation.................................................................. 15
Typical Connection Diagram ................................................... 17
Power Dissipation versus Throughput .................................... 19
Conversion Control.................................................................... 19
REVISION HISTORY
6/09—Rev. 0 to Rev. A
Removed Endnote 3 from DC Accuracy; Zero Error, TMIN to
TMAX Parameter; Table 2................................................................... 3
Changes to Endnote 3, Table 2........................................................ 4
Moved ESD Caution......................................................................... 7
Changes to Figure 4 and Table 6..................................................... 8
Changes to Evaluating the AD7678’s Performance Section...... 25
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide .......................................................... 26
8/03—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD7678
SPECIFICATIONS
Table 2. –40°C to +85°C, VREF = 4.096 V, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
18
Bits
ANALOG INPUT
Voltage Range
VIN+ – VIN–
VIN+, VIN– to AGND
fIN = 100 kHz
–VREF
–0.1
+VREF
AVDD + 0.1
V
V
dB
μA
Operating Input Voltage
Analog Input CMRR
Input Current
65
4
100 kSPS Throughput
Input Impedance1
THROUGHPUT SPEED
Complete Cycle
10
μs
Throughput Rate
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise
0
100
kSPS
–2.5
–1
18
+2.5
+1.75
LSB2
LSB
Bits
LSB
VREF = 5 V
0.7
Zero Error, TMIN to TMAX
Zero Error Temperature Drift
Gain Error, TMIN to TMAX
Gain Error Temperature Drift
Power Supply Sensitivity
AC ACCURACY
–40
40
LSB
0.5
See Note 3
1.6
4
ppm/°C
% of FSR
ppm/°C
LSB
3
–0.048
+0.048
AVDD = 5 V 5%
Signal-to-Noise
fIN = 2 kHz, VREF = 5 V
VREF = 4.096 V
101
100
99.5
98
103
120
117
110
–118
–115
–110
100
41
dB4
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
kHz
98
fIN = 10 kHz, VREF = 4.096 V
fIN = 45 kHz, VREF = 4.096 V
VIN+ = VIN– = VREF/2 = 2.5 V
fIN = 2 kHz
Dynamic Range
Spurious-Free Dynamic Range
fIN = 10 kHz
fIN = 45 kHz
fIN = 2 kHz
Total Harmonic Distortion
fIN = 10 kHz
fIN = 45 kHz
fIN = 2 kHz
Signal-to-(Noise + Distortion)
fIN = 2 kHz, –60 dB Input
–3 dB Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
900
2
5
ns
ps rms
μs
Full-Scale Step
8.5
8.5
Overvoltage Recovery
REFERENCE
μs
External Reference Voltage Range
REF Voltage with Reference Buffer
Reference Buffer Input Voltage Range
REFBUFIN Input Current
REF Current Drain
REF
3
4.096
4.096
2.5
AVDD + 0.1
4.15
2.6
V
V
V
μA
μA
REFBUFIN = 2.5 V
REFBUFIN
4.05
1.8
–1
+1
100 kSPS Throughput
42
Rev. A | Page 3 of 28
AD7678
Parameter
Conditions
Min
Typ
Max
Unit
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
–0.3
2.0
–1
+0.8
DVDD + 0.3
+1
+1
V
V
μA
μA
–1
DIGITAL OUTPUTS
Data Format5
Pipeline Delay6
VOL
ISINK = 1.6 mA
ISOURCE = –500 μA
0.4
V
V
VOH
OVDD – 0.6
POWER SUPPLIES
Specified Performance
AVDD
4.75
4.75
2.7
5
5
5.25
5.25
DVDD + 0.37
V
V
V
DVDD
OVDD
Operating Current
AVDD
100 kSPS Throughput
PDBUF High
2.6
1
40
18
180
31
mA
mA
μA
mW
μW
mW
DVDD8
OVDD8
PDBUF High @ 100 kSPS
PDBUF High @ 1 kSPS
PDBUF Low @ 100 kSPS
26
TEMPERATURE RANGE9
Specified Performance
TMIN to TMAX
–40
+85
°C
1 See the Analog Inputs section.
2 LSB means Least Significant Bit. With the 4.096 V input range, 1 LSB is 31.25 μV.
3 See the Definition of Specifications section. The nominal gain error is not centered at zero and is −0.029% of FSR. This specification is the deviation from this nominal
value. These specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used.
4 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
5 Data format parallel or serial 18-bit.
6 Conversion results are available immediately after completed conversion.
7 The maximum should be the minimum of 5.25 V and DVDD + 0.3 V.
8 Tested in Parallel Reading mode.
9 Contact factory for extended temperature range.
Rev. A | Page 4 of 28
AD7678
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figure 27 and Figure 28
Convert Pulse Width
Time between Conversions
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except Master Serial Read after Convert
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
t1
t2
t3
t4
t5
t6
t7
t8
t9
10
10
ns
μs
ns
μs
ns
ns
μs
μs
ns
35
1.5
2
10
1.5
8.5
10
RESET Pulsewidth
Refer to Figure 29, Figure 30, and Figure 31 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay
Data Valid to BUSY LOW Delay
Bus Access Request to Data Valid
Bus Relinquish Time
t10
t11
t12
t13
1.5
μs
ns
ns
ns
20
5
45
15
Refer to Figure 33 and Figure 34 (Master Serial Interface Modes)1
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CNVST LOW to SYNC Delay
525
SYNC Asserted to SCLK First Edge Delay2
3
Internal SCLK Period2
25
12
7
4
2
40
Internal SCLK HIGH2
Internal SCLK LOW2
SDOUT Valid Setup Time2
SDOUT Valid Hold Time2
SCLK Last Edge to SYNC Delay2
3
CS HIGH to SYNC HI-Z
10
10
10
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert2
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
Refer to Figure 35 and Figure 36 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
See Table 4
1.5
25
μs
ns
t31
t32
t33
t34
t35
t36
t37
5
3
5
5
25
10
10
ns
ns
ns
ns
ns
ns
ns
18
External SCLK Period
External SCLK HIGH
External SCLK LOW
1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2In Serial Master Read during Convert mode. See Table 4 for Serial Master Read after Convert mode.
Rev. A | Page 5 of 28
AD7678
Table 4. Serial Clock Timings in Master Read after Convert
DI±SCLK[1]
0
0
1
1
DI±SCLK[0]
Symbol
t18
t19
t19
t20
t21
t22
t23
t24
0
1
0
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum
3
17
60
80
22
21
18
4
17
120
160
50
49
18
30
140
4.5
17
25
40
12
7
4
2
240
320
100
99
18
89
3
2.25
60
3
300
7.5
t28
μs
Rev. A | Page 6 of 28
AD7678
ABSOLUTE MAXIMUM RATINGS
Table 5. AD7678 Absolute Maximum Ratings1
Parameter
Rating
I
1.6mA
OL
Analog Inputs
IN+2, IN–2, REF, REFBUFIN, REFGND
to AGND
AVDD + 0.3 V to
AGND – 0.3 V
TO OUTPUT
PIN
1.4V
C
L
1
Ground Voltage Differences
AGND, DGND, OGND
Supply Voltages
60pF
0.3 V
I
500A
OH
AVDD, DVDD, OVDD
AVDD to DVDD, AVDD to OVDD
DVDD to OVDD
–0.3 V to +7 V
7 V
–0.3 V to +7 V
–0.3 V to DVDD + 0.3 V
700 mW
1
IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD
C
OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
L
03084–0–002
Digital Inputs
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, CL = 10 pF
Internal Power Dissipation3
Internal Power Dissipation4
Junction Temperature
Storage Temperature Range
Lead Temperature Range
(Soldering 10 sec)
2.5 W
150°C
2V
–65°C to +150°C
0.8V
tDELAY
tDELAY
300°C
2V
2V
0.8V
0.8V
03084–0–003
1Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Figure 3. Voltage Reference Levels for Timing
ESD CAUTION
2See Analog Inputs section.
3Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W,
θ
JC = 30°C/W.
4 Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W.
Rev. A | Page 7 of 28
AD7678
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
1
AGND
36
35
34
33
32
31
30
29
28
27
26
25
AGND
PIN 1
IDENTIFIER
2
AV D D
MODE0
MODE1
CNVST
PD
3
4
RESET
5
D0/OB/2C
NC
CS
AD7678
6
RD
TOP VIEW
7
NC
DGND
BUSY
D17
(Not to Scale)
D1/A0
8
9
D2/A1
D3
10
11
12
D16
D4/DIVSCLK[0]
D5/DIVSCLK[1]
D15
D14
13 14 15 16 17 18 19 20 21 22 23 24
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND. THIS
CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL
PERFORMANCES; HOWEVER, FOR INCREASED RELIABILITY OF
THE SOLDER JOINTS, IT IS RECOMMENDED THAT THE PAD BE
SOLDERED TO THE ANALOG GROUND OF THE SYSTEM.
Figure 4. 48-Lead LQFP and 48-Lead LFCSP (ST-48 and CP-48) Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic
Type1 Description
1, 44
2, 47
3
AGND
AVDD
MODE0
MODE1
P
P
DI
DI
Analog Power Ground Pin.
Input Analog Power Pins. Nominally 5 V.
Data Output Interface Mode Selection.
Data Output Interface Mode Selection:
Interface MODE # MODE1 MODE0 Description
4
0
1
2
3
0
0
1
1
0
1
0
1
18-Bit Interface
16-Bit Interface
Byte Interface
Serial Interface
5
D0/OB/2C
NC
DI/O
When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the
data coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos
complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is
inverted, resulting in a twos complement output from its internal shift register.
6, 7,
40–42,
45
No Connect.
8
D1/A0
D2/A1
D3
DI/O
DI/O
DO
When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all
other modes, this input pin controls the form in which data is output, as shown in Table 7.
When MODE = 0 or 1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data output
bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7.
In all modes except MODE = 3, this output is used as Bit 3 of the parallel port data output bus. This pin
is always an output, regardless of the interface mode.
9
10
11, 12
D[4:5]or
DI/O
In all modes except MODE = 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus.
DIVSCLK[0:1]
When MODE = 3 (serial mode), EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after
convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock
that clocks the data output. In other serial modes, these pins are not used.
Rev. A | Page 8 of 28
AD7678
Pin No. Mnemonic
Type1 Description
13
D6
or EXT/INT
DI/O
In all modes except MODE = 3, this output is used as Bit 6 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used as a digital select input for
choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is
selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an
external clock signal connected to the SCLK input.
14
15
16
D7
DI/O
DI/O
DI/O
In all modes except MODE = 3, this output is used as Bit 7 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used to select the active state of the
SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
In all modes except MODE = 3, this output is used as Bit 8 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used to invert the SCLK signal. It is
active in both master and slave modes.
or INVSYNC
D8
or INVSCLK
D9
In all modes except MODE = 3, this output is used as Bit 9 of the parallel port data output bus.
or RDC/SDIN
When MODE = 3 (serial mode), this input, part of the serial port, is used as either an external data
input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH,
RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs
onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK
periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the
read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When
RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete.
17
18
OGND
OVDD
P
P
Input/Output Interface Digital Power Ground.
Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Should
not exceed DVDD by more than 0.3 V.
19
20
21
DVDD
DGND
D10
P
P
DO
Digital Power. Nominally at 5 V.
Digital Power Ground.
In all modes except MODE = 3, this output is used as Bit 10 of the parallel port data output bus.
or SDOUT
When MODE = 3 (serial mode), this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7678 provides the
conversion result, MSB first, from its internal shift register. The data format is determined by the logic
level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial
mode when EXT/INT is HIGH and INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and is
valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and is
valid on the next rising edge.
22
23
D11
or SCLK
DI/O
DO
In all modes except MODE = 3, this output is used as Bit 11 of the parallel port data output bus.
When MODE = 3 (serial mode), this pin, part of the serial port, is used as a serial data clock input or
output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is
updated depends upon the logic state of the INVSCLK pin.
D12
In all modes except MODE = 3, this output is used as Bit 12 of the parallel port data output bus.
or SYNC
When MODE = 3 (serial mode), this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is
valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW
while SDOUT output is valid.
24
D13
DO
In all modes except MODE = 3, this output is used as Bit 13 of the parallel port data output bus.
or RDERROR
In MODE = 3 (serial mode) and when EXT/INT is HIGH, this output, part of the serial port, is used as an
incomplete read error flag. In slave mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed high.
25–28
29
D[14:17]
BUSY
DO
DO
Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the
interface mode.
Busy Output. Transitions HIGH when a conversion is started. Remains HIGH until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.
30
31
32
DGND
RD
P
DI
DI
Must Be Tied to Digital Ground.
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
CS
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock.
33
RESET
DI
Reset Input. When set to a logic HIGH, reset the AD7678. Current conversion, if any, is aborted. If not
used, this pin could be tied to DGND.
Rev. A | Page 9 of 28
AD7678
Pin No. Mnemonic
Type1 Description
34
PD
DI
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
inhibited after the current one is completed.
35
CNVST
DI
Start Conversion. If CNVST is held HIGH when the acquisition phase (t8) is complete, the next falling
edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. If CNVST
is held LOW when the acquisition phase is complete, the internal sample/hold is put into the hold
state and a conversion is started immediately.
36
37
AGND
REF
P
AI
Must Be Tied to Analog Ground.
Reference Input Voltage and Internal Reference Buffer Output. Apply an external reference on this pin
if the internal reference buffer is not used. Should be decoupled effectively with or without the
internal buffer.
38
39
43
46
REFGND
IN–
IN+
AI
AI
AI
AI
Reference Input Analog Ground.
Differential Negative Analog Input.
Differential Positive Analog Input.
Reference Buffer Input Voltage. The internal reference buffer has a fixed gain. It outputs 4.096 V
typically when 2.5 V is applied on this pin.
REFBUFIN
48
PDBUF
DI
Allows Choice of Buffering Reference. When LOW, buffer is selected. When HIGH, buffer is switched
off.
49
(EPAD)
Exposed Pad
(EPAD)
The exposed pad is internally connected to AGND. This connection is not required to meet the
electrical performances; however, for increased reliability of the solder joints, it is recommended that
the pad be soldered to the analog ground of the system.
1AI = Analog Input; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.
Table 7. Data Bus Interface Definitions
MODE MODE1 MODE0 D0/OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description
0
1
1
2
2
2
2
3
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
1
R[0]
R[1]
R[2]
R[2]
R[3] R[4:9]
R[3] R[4:9]
R[1]
R[10:11]
R[10:11]
R[12:15]
R[12:15]
R[16:17]
R[16:17]
18-Bit Parallel
OB/2C
OB/2C
OB/2C
OB/2C
OB/2C
OB/2C
OB/2C
A0:0
A0:1
A0:0
A0:0
A0:1
A0:1
16-Bit High Word
16-Bit Low Word
8-Bit HIGH Byte
8-Bit MID Byte
8-Bit LOW Byte
8-Bit LOW Byte
Serial Interface
R[0]
All Zeros
A1:0
A1:1
A1:0
A1:1
All Hi-Z
All Hi-Z
R[10:11]
R[2:3]
R[12:15]
R[4:7]
R[16:17]
R[8:9]
All Hi-Z
All Hi-Z
R[0:1]
All Zeros
R[0:1]
All Hi-Z
All Zeros
Serial Interface
R[0:17] is the 18-bit ADC value stored in its output register.
Rev. A | Page 10 of 28
AD7678
DEFINITION OF SPECIFICATIONS
Integral Nonlinearity Error (INL)
Total Harmonic Distortion (THD)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured with the inputs shorted together. The
value for dynamic range is expressed in decibels.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Gain Error
The first transition (from 000…00 to 000…01) should occur for
an analog voltage ½ LSB above the nominal –full scale
(–4.095991 V for the 4.096 V range). The last transition (from
111…10 to 111…11) should occur for an analog voltage
1½ LSB below the nominal full scale (4.095977 V for the
4.096 V range). The gain error is the deviation of the differ-
ence between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the
input to when
CNVST
Zero Error
the input signal is held for a conversion.
The zero error is the difference between the ideal midscale
input voltage (0 V) from the actual voltage producing the
midscale output code.
Transient Response
Transient response is the time required for the AD7678 to
achieve its rated accuracy after a full-scale step function is
applied to its input.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input, and is expressed in bits. It is related to S/(N+D) by the
following formula:
ENOB = (S/[N+D]dB – 1.76)/6.02
Rev. A | Page 11 of 28
AD7678
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–0.5
–1.0
0
65536
131072
CODE
196608
262144
0
65536
131072
CODE
196608
262144
03084-0-008
03084-0-005
Figure 5. Integral Nonlinearity vs. Code
Figure 8. Differential Nonlinearity vs. Code
70000
60000
50000
40000
30000
20000
10000
0
90000
80000
70000
60000
50000
40000
30000
20000
10000
0
83610
V
= 5V
REF
V
= 5V
REF
60158
59966
23000
21862
5919
3931
1053
1
0
0
522
0
0
0
32
42
0
0
20015 20016 20017 20018 20019 2001A2001B2001C2001D2001E
2001B 2001C 2001D 2001E 2001F 20020 20021 20022 20023
CODE IN HEX
CODE IN HEX
03084-0-009
03084-0-006
Figure 6. Histogram of 131,072 Conversions of a
DC Input at the Code Transition
Figure 9. Histogram of 131,072 Conversions of a
DC Input at the Code Center
16.6
16.4
0
–20
102
f
f
V
= 100kSPS
= 11kHz
S
IN
= 4.096V
REF
SNR = 99.6dB
–40
100
98
THD = –116dB
SFDR = 116.2dB
S/(N+D) = 99.5dB
–60
–80
SNR
16.2
S/(N+D)
–100
–120
–140
–160
–180
16.0
96
ENOB
15.8
50
94
0
5
10
15
20
25
30
35
40
45
50
0
10
20
30
40
FREQUENCY (kHz)
FREQUENCY (kHz)
03084-0-012
03084-0-015
Figure 7. FFT (11 kHz Tone)
Figure 10. SNR, S/(N+D), and ENOB vs. Frequency
Rev. A | Page 12 of 28
AD7678
–80
–90
–100
–110
–120
–130
–140
–100
–110
–120
–130
–140
–150
THD
THIRD
HARMONIC
THD
THIRD
SECOND
HARMONIC
HARMONIC
SECOND
HARMONIC
–55
–35
–15
5
25
45
65
85
105
125
0
10
20
30
40
50
FREQUENCY (kHz)
TEMPERATURE (C)
03084-0-016
03084-0-019
Figure 11. THD and Harmonics vs. Frequency
Figure 14. THD and Harmonics vs. Temperature
104
103
102
101
100
99
10000
1000
100
10
V
= 4.096V
REF
SNR
S/(N+D)
1
AVDD
DVDD
0.1
OVDD
0.01
0.001
98
–60
–50
–40
–30
–20
–10
0
1
100
1k
10k
100k
10
INPUT LEVEL (dB)
SAMPLING RATE (SPS)
03084-0-017
03084-0-020
Figure 12. SNR and S/(N+D) vs. Input Level
Figure 15. Operating Current vs. Sampling Rate
16.5
1000
800
600
400
200
0
101
100
99
SNR
16.0
15.5
15.0
14.5
S/(N+D)
DVDD
ENOB
AVDD
98
OVDD
97
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
C)
85
105
125
TEMPERATURE (
TEMPERATURE (C)
03084-0-021
03084-0-018
Figure 13. SNR, S/(N+D), and ENOB vs. Temperature
Figure 16. Power-Down Operating Currents vs. Temperature
Rev. A | Page 13 of 28
AD7678
50
40
50
40
30
20
10
0
OVDD = 2.7V @ 85°C
30
GAIN ERROR
20
10
0
ZERO ERROR
–10
–20
–30
–40
OVDD = 2.7V @ 25°C
OVDD = 5V @ 85°C
OVDD = 5V @ 25°C
–50
–55
–35
–15
5
25
45
65
C)
85
105
125
0
50
100
(pF)
150
200
TEMPERATURE (
C
L
03083-0-022
03084-0-024
Figure 17. Zero Error and Gain Error vs. Temperature
Figure 18. Typical Delay vs. Load Capacitance CL
Rev. A | Page 14 of 28
AD7678
CIRCUIT INFORMATION
IN+
SWITCHES
CONTROL
SW+
MSB
LSB
262,144C 131,072C
4C
2C
C
C
BUSY
REF
CONTROL
LOGIC
COMP
OUTPUT
CODE
REFGND
4C
2C
C
C
262,144C 131,072C
MSB
LSB
SW–
CNVST
03084–0–025
IN–
Figure 19. ADC Simplified Schematic
The AD7678 is a very fast, low power, single-supply, precise
18-bit analog-to-digital converter (ADC) using successive
approximation architecture.
CON±ERTER OPERATION
The AD7678 is a successive approximation ADC based on a
charge redistribution DAC. Figure 19 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary weighted capacitors, which are
connected to the two comparator inputs.
The AD7678’s linearity and dynamic range are similar or better
than many - ADCs. With the advantages of its successive
architecture, which ease multiplexing and reduce power with
throughput, it can be advantageous in applications that
normally use - ADCs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW–.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on IN+ and IN– inputs. When the
The AD7678 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
CNVST
acquisition phase is complete and the
input goes low, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW– are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the REFGND input. Therefore, the differential voltage between
the IN+ and IN– inputs captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each element
of the capacitor array between REFGND and REF, the
comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4...VREF/262144). The control logic toggles these
switches, starting with the MSB first, to bring the comparator
back into a balanced condition. After completing this process,
the control logic generates the ADC output code and brings the
BUSY output low.
The AD7678 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP, or a tiny 48-lead LFCSP package that offers space
savings and allows for flexible configurations as either a serial
or parallel interface. The AD7678 is pin-to-pin compatible with
the AD7674, AD7676, and AD7679.
Rev. A | Page 15 of 28
AD7678
Transfer Functions
Table 8. Output Codes and Ideal Input Voltages
Except in 18-bit interface mode, the AD7678 offers straight
binary and twos complement output coding when using OB/
See Figure 20 and Table 8 for the ideal transfer characteristic.
Straight Twos
.
2C
Analog Input
±REF = 4.096 ±
Binary
Complement
(Hex)
Description
FSR –1 LSB
FSR – 2 LSB
Midscale +
1 LSB
(Hex)
4.095962 V
4.095924 V
31.25 μV
3FFFF1
3FFFE
20001
1FFFF1
1FFFE
00001
111...111
111...110
111...101
Midscale
Midscale –
1 LSB
0 V
–31.25 μV
20000
1FFFF
00000
3FFFF
–FSR + 1 LSB
–FSR
-4.095962 V
-4.096 V
00001
000002
20001
200002
000...010
000...001
000...000
1 This is also the code for overrange analog input (VIN+ – VIN–
above VREF – VREFGND).
–FS
–FS + 1 LSB
+FS – 1 LSB
+FS – 1.5 LSB
–FS + 0.5 LSB
2 This is also the code for underrange analog input (VIN+ – VIN–
below –VREF + VREFGND).
ANALOG INPUT
03084-0-026
Figure 20. ADC Ideal Transfer Function
DVDD
ANALOG
SUPPLY
20
DIGITAL SUPPLY
(3.3V OR 5V)
+
NOTE 5
(5V)
+
+
100nF
10F
10F
100nF
100nF
10F
ADR421
AVDD
AGND
DGND
DVDD
OVDD
OGND
REFBUFIN
SERIAL PORT
2.5V REF
NOTE 1
SCLK
1M
50k
100nF
100nF
SDOUT
NOTE 3
REF
C
REF
BUSY
10F
NOTE 2
C/P/DSP
REFGND
CNVST
50
–
NOTE 4
MODE1
MODE0
OB/2C
IN+
U1
+
AD7678
ANALOG INPUT+
DVDD
C
C
AD8021
CLOCK
PDBUF
CS
50
RD
–
NOTE 4
IN–
U2
+
RESET
PD
ANALOG INPUT–
C
C
AD8021
NOTES
1. SEE VOLTAGE REFERENCE SECTION.
2. C is 10F CERAMIC CAPACITOR OR LOW ESR TANTALUM. CERAMIC SIZE
REF
1206 PANASONIC ECJ-3xB0J106 IS RECOMMENDED. SEE VOLTAGE REFERENCE SECTION.
3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.
4.THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
5. OPTION, SEE POWER SUPPLY SECTION.
03084-0-027
Figure 21. Typical Connection Diagram (Internal Reference Buffer, Serial Interface)
Rev. A | Page 16 of 28
AD7678
TYPICAL CONNECTION DIAGRAM
During the acquisition phase for ac signals, the AD7678 behaves
like a 1-pole RC filter consisting of the equivalent resistance,
R+, R–, and CS. Resistors R+ and R– are typically 3 k and are
lumped components made up of a serial resistor and the on
resistance of the switches. CS is typically 60 pF and mainly
consists of the ADC sampling capacitor. This 1-pole filter with a
–3 dB cutoff frequency of 900 kHz typ reduces any undesirable
aliasing effect and limits the noise coming from the inputs.
Figure 21 shows a typical connection diagram for the AD7678.
Different circuitry shown on this diagram is optional and is
discussed later in this data sheet.
Analog Inputs
Figure 22 shows a simplified analog input section of the
AD7678. The diodes shown in Figure 22 provide ESD protec-
tion for the inputs. Care must be taken to ensure that the analog
input signal never exceeds the absolute ratings on these inputs.
This will cause these diodes to become forward-biased and start
conducting current. These diodes can handle a forward-biased
current of 120 mA max. This condition could eventually occur
when the input buffer’s U1 or U2 supplies are different from
AVDD. In such a case, an input buffer with a short-circuit
current limitation can be used to protect the part.
Because the input impedance of the AD7678 is very high, the
part can be driven directly by a low impedance source without
gain error.
Driver Amplifier Choice
Although the AD7678 is easy to drive, the driver amplifier
needs to meet the following requirements:
AVDD
The driver amplifier and the AD7678 analog input circuit
have to be able to settle for a full-scale step of the capacitor
array at an 18-bit level (0.0004%). In the amplifier’s data
sheet, settling at 0.1% or 0.01% is more commonly
specified. This could differ significantly from the settling
time at an 18-bit level and, therefore, should be verified
prior to driver selection. The tiny op amp AD8021, which
combines ultralow noise and high gain-bandwidth, meets
this settling time requirement.
R+ = 3k
IN+
C
S
S
C
IN–
R– = 3k
AGND
03084-0-028
The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7678. The noise
coming from the driver is filtered by the AD7678 analog
input circuit 1-pole low-pass filter made by R+, R–, and CS.
Figure 22. Simplified Analog Input
This analog input structure is a true differential structure. By
using these differential inputs, signals common to both inputs
are rejected as shown in Figure 23, which represents typical
CMRR over frequency.
The SNR degradation due to the amplifier is
25
SNRLOSS 20 log
80
75
70
65
60
55
50
2
f
625 –3dB (NeN )
where:
–3dB is the –3 dB input bandwidth in MHz of the AD7678
(0.9 MHz).
N is the noise factor of the amplifiers (1 if in buffer
configuration).
eN is the equivalent input noise voltage of each op amp in
f
nV/Hz.
For instance, for a driver with an equivalent input noise of
6 nV/Hz (e.g., AD8610) configured as a buffer, thus with
a noise gain of +1, the SNR degrades by only 0.65 dB.
1
10
100
1000
10000
FREQUECY (kHz)
03084-0-029
The driver needs to have a THD performance suitable to
that of the AD7678.
Figure 23. Analog Input CMRR vs. Frequency
Rev. A | Page 17 of 28
AD7678
The AD8021 meets these requirements and is usually appropri-
ate for almost all applications. The AD8021 needs a 10 pF
external compensation capacitor, which should have good
linearity as an NPO ceramic or mica type.
To use the internal reference buffer, PDBUF should be LOW. A
2.5 V reference voltage applied on the REFBUFIN input will
result in a 4.096 V reference on the REF pin.
In both cases, the voltage reference input REF has a dynamic
input impedance and therefore requires an efficient decoupling
between REF and REFGND inputs. The decoupling consists of
a low ESR 47 μF tantalum capacitor connected to the REF and
REFGND inputs with minimum parasitic inductance.
The AD8022 could be used if a dual version is needed and gain
of 1 is present. The AD829 is an alternative in applications
where high frequency (above 100 kHz) performance is not
required. In gain of 1 applications, it requires an 82 pF
compensation capacitor. The AD8610 is another option when
low bias current is needed in low frequency applications.
Care should also be taken with the reference temperature
coefficient of the voltage reference, which directly affects the
full-scale accuracy if this parameter matters. For instance, a
4 ppm/°C temperature coefficient of the reference changes the
full scale by 1 LSB/°C.
Single-to-Differential Driver
For applications using unipolar analog signals, a single-ended-
to-differential driver will allow for a differential input into the
part. The schematic is shown in Figure 24. When provided an
input signal of 0 to VREF, this configuration will produce a
differential VREF with midscale at VREF/2.
Power Supply
The AD7678 uses three sets of power supply pins: an analog 5 V
supply (AVDD), a digital 5 V core supply (DVDD), and a digital
output interface supply (OVDD). The OVDD supply defines
the output logic level and allows direct interface with any logic
working between 2.7 V and DVDD + 0.3 V. To reduce the
number of supplies needed, the digital core (DVDD) can be
supplied through a simple RC filter from the analog supply, as
shown in Figure 21. The AD7678 is independent of power
supply sequencing once OVDD does not exceed DVDD by
more than 0.3 V, and is therefore free from supply voltage
induced latch-up. Additionally, it is very insensitive to power
supply variations over a wide frequency range, as shown in
Figure 25.
If the application can tolerate more noise, the AD8138
differential driver can be used.
U1
ANALOG INPUT
AD8021
10pF
(UNIPOLAR
0V TO 4.096V)
590
590
IN+
IN–
AD7678
U2
1.82k
REFBUFIN
REF
10
AD8021
10pF
F
100nF
8.25k
65
60
55
50
45
40
2.5V
03084-0-030
Figure 24. Single-Ended-to-Differential Driver Circuit
(Internal Reference Buffer Used)
Voltage Reference
The AD7678 allows the use of an external voltage reference with
or without the internal reference buffer.
Using the internal reference buffer is recommended when
sharing a common reference voltage between multiple ADCs is
desired.
1
10
100
1000
10000
FREQUECY (kHz)
However, the advantages of using the external reference voltage
directly are
03084-0-031
Figure 25. PSRR vs. Frequency
The SNR and dynamic range improvement (about 1.7 dB)
resulting from the use of a reference voltage very close to
the supply (5 V) instead of a typical 4.096 V reference
when the internal buffer is used.
The power saving when the internal reference buffer is
powered down (PDBUF HIGH).
Rev. A | Page 18 of 28
AD7678
POWER DISSIPATION ±ERSUS THROUGHPUT
t2
t1
The AD7678 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low, which allows for a signifi-
cant power savings when the conversion rate is reduced, as
shown in Figure 26. This feature makes the AD7678 ideal for
very low power battery applications.
CNVST
BUSY
t4
t3
t5
t6
MODE ACQUIRE
CONVERT
t7
ACQUIRE
t8
CONVERT
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be
driven close to the power rails (DVDD and DGND), and
OVDD should not exceed DVDD by more than 0.3 V.
03084-0-033
Figure 27. Basic Conversion Timing
Although
is a digital signal, it should be designed with
CNVST
100000
10000
1000
100
special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.
For other applications, conversions can be automatically
initiated. If
is held low when BUSY is low, the AD7678
CNVST
controls the acquisition phase and then automatically initiates a
new conversion. By keeping low, the AD7678 keeps the
CNVST
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
10
power-up,
should be brought low once to initiate the
CNVST
1
conversion process. In this mode, the AD7678 could sometimes
run slightly faster than the guaranteed limits of 100 kSPS.
PDBUF HIGH
10k 100k
0.1
1
100
1k
10
SAMPLING RATE (SPS)
03084-0-032
t9
Figure 26. Power Dissipation vs. Sample Rate
RESET
CON±ERSION CONTROL
Figure 27 shows the detailed timing diagrams of the conversion
process. The AD7678 is controlled by the signal, which
BUSY
CNVST
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the
DATA
BUS
conversion is complete. The
signal operates
CNVST
independently of the
and signals.
CS
RD
t8
CNVST
03084-0-034
Figure 28. RESET Timing
Rev. A | Page 19 of 28
AD7678
DIGITAL INTERFACE
CS
The AD7678 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7678 digital interface also accommodates both 3 V and 5 V
logic by simply connecting the AD7678’s OVDD supply pin to
the host system interface digital supply. Finally, by using the
RD
BUSY
DATA
BUS
CURRENT
CONVERSION
OB/ input pin in any mode except 18-bit interface mode,
both twos complement and straight binary coding can be used.
2C
t12
t13
03084-0-036
Figure 30. Slave Parallel Data Timing for Reading (Read after Convert)
The two signals,
and
, control the interface. When at least
RD
CS
one of these signals is high, the interface outputs are in high
impedance. Usually, allows the selection of each AD7678 in
CS
multicircuit applications, and is held low in a single AD7678
design. is generally used to enable the conversion result on
CS = 0
t1
CNVST,
RD
RD
the data bus.
BUSY
t4
CS = RD = 0
t1
t3
CNVST
BUSY
PREVIOUS
CONVERSION
DATA
BUS
t10
t12
t13
t4
03084-0-037
t3
Figure 31. Slave Parallel Data Timing for Reading (Read during Convert)
t11
DATA
BUS
PREVIOUS CONVERSION DATA
NEW DATA
03084-0-035
CS
RD
Figure 29. Master Parallel Data Timing for Reading (Continuous Read)
PARALLEL INTERFACE
A0, A1
The AD7678 is configured to use the parallel interface with an
18-bit, a 16-bit, or an 8-bit bus width, according to Table 7. The
data can be read either after each conversion, which is during
the next acquisition phase, or during the following conversion,
as shown in Figure 30 and Figure 31, respectively. When the
data is read during the conversion, however, it is recommended
that it is read only during the first half of the conversion phase.
This avoids any potential feedthrough between voltage
transients on the digital interface and the most critical analog
conversion circuitry. Refer to Table 7 for a detailed description
of the different options available.
HI-Z
HI-Z
HI-Z
PINS D[15:8]
PINS D[7:0]
HIGH BYTE
LOW BYTE
t12
t12
t13
HI-Z
LOW BYTE
HIGH BYTE
03084-0-038
Figure 32. 8-Bit and 16-Bit Parallel Interface
SERIAL INTERFACE
The AD7678 is configured to use the serial interface when
MODE0 and MODE1 are held high. The AD7678 outputs 18
bits of data, MSB first, on the SDOUT pin. This data is
synchronized with the 18 clock pulses provided on the SCLK
pin. The output data is valid on both the rising and falling edge
of the data clock.
Rev. A | Page 20 of 28
AD7678
MASTER SERIAL INTERFACE
Internal Clock
In Read during Conversion mode, the serial clock and data
toggle at appropriate instants, minimizing potential
feedthrough between digital activity and critical conversion
decisions.
The AD7678 is configured to generate and provide the serial
data clock SCLK when the EXT/
pin is held low. The
INT
AD7678 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. Figure 33 and Figure 34 show
the detailed timing diagrams of these two modes.
In Read after Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns low after the 18 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
Usually, because the AD7678 is used with a fast throughput, the
mode master read during conversion is the most recommended
serial mode.
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
EXT/INT = 0
CS, RD
t3
CNVST
t28
BUSY
t30
t29
t25
SYNC
t14
t18
t19
t24
t20
t21
2
t26
1
3
16
17
18
SCLK
t15
t27
X
D17
D16
t23
D2
D1
D0
SDOUT
t16
t22
03084-0-039
Figure 33. Master Serial Data Timing for Reading (Read after Convert)
Rev. A | Page 21 of 28
AD7678
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
CS, RD
t1
CNVST
BUSY
t3
t17
t25
SYNC
t14
t19
t20 t21
t24
t26
t15
SCLK
1
2
3
16
17
18
t18
t27
X
D17
D16
t23
D2
D1
D0
SDOUT
t16
t22
03084-0-040
Figure 34. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
SLA±E SERIAL INTERFACE
External Clock
External Discontinuous Clock Data Read after
Conversion
The AD7678 is configured to accept an externally supplied
This mode is the most recommended of the serial slave modes.
Figure 35 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
serial data clock on the SCLK pin when the EXT/
pin is
INT
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by . When and
CS
CS
low, the result of this conversion can be read while both
and
CS
are both low, the data can be read after each conversion or
RD
are low. Data is shifted out MSB first with 18 clock pulses,
RD
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 35 and Figure 36 show the detailed timing
diagrams of these methods.
and is valid on both the rising and falling edge of the clock.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients
on the digital interface during the conversion process. Also,
data can be read at speeds up to 40 MHz, accommodating both
slow digital host interface and the fastest serial reading.
While the AD7678 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7678 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is recom-
mended that when an external clock is being provided, it is a
discontinuous clock that only toggles when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.
Finally, in this mode only, the AD7678 provides a daisy-chain
feature using the RDC/SDIN input pin to cascade multiple
converters together. This feature is useful for reducing
component count and wiring connections when desired (for
instance, in isolated multiconverter applications).
An example of the concatenation of two devices is shown in
Figure 37. Simultaneous sampling is possible by using a
common
signal. It should be noted that the RDC/SDIN
CNVST
input is latched on the edge of SCLK opposite the one used to
shift out data on SDOUT. Thus, the MSB of the upstream
converter follows the LSB of the downstream converter on the
next SCLK cycle.
Rev. A | Page 22 of 28
AD7678
INVSCLK = 0
EXT/INT = 1
RD = 0
CS
BUSY
t35
t36
t37
SCLK
1
2
3
16
17
18
19
20
t31
t32
SDOUT
X
D17
D16
D15
X15
D1
X1
D0
X17
Y17
X16
Y16
t16
t34
SDIN
X17
X16
X0
t33
03084-0-041
Figure 35. Slave Serial Data Timing for Reading (Read after Convert)
INVSCLK = 0
EXT/INT = 1
RD = 0
CS
CNVST
BUSY
t3
t35
t36 t37
SCLK
1
2
3
16
17
18
t31
t32
SDOUT
X
D17
D16
D15
D1
D0
t16
03084-0-042
Figure 36. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
Rev. A | Page 23 of 28
AD7678
BUSY
OUT
MICROPROCESSOR INTERFACING
BUSY
BUSY
The AD7678 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7678 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7678 to prevent digital noise from coupling
into the ADC. The following section illustrates the use of the
AD7678 with an SPI equipped DSP, the ADSP-219x.
AD7678
AD7678
#2 (UPSTREAM)
#1 (DOWNSTREAM)
DATA
OUT
RDC/SDIN
SDOUT
RDC/SDIN
SDOUT
CNVST
CS
CNVST
CS
SCLK
SCLK
SCLK IN
CS IN
CNVST IN
03084-0-043
SPI Interface (ADSP-219x)
Figure 37. Two AD7678s in a Daisy-Chain Configuration
Figure 38 shows an interface diagram between the AD7678 and
the SPI equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7678 acts as a slave device, and data
must be read after conversion. This mode also allows the daisy-
chain feature. The convert command could be initiated in
response to an internal timer interrupt. The 18-bit output data
are read with 3-byte SPI access. The reading process could be
initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The serial
interface (SPI) on the ADSP-219x is configured for master
mode (MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase
bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00, by
writing to the SPI control register (SPICLTx). It should be noted
that to meet all timing requirements, the SPI clock should be
limited to 17 Mbits/s, which allow it to read an ADC result in
about 1.1 μs.
External Clock Data Read during Conversion
Figure 36 shows the detailed timing diagrams of this method.
During a conversion, while both and are low, the result
of the previous conversion can be read. The data is shifted out
MSB first with 18 clock pulses, and is valid on both the rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete. If that is not done,
RDERROR is pulsed high and can be used to interrupt the host
interface to prevent incomplete data reading. There is no daisy-
chain feature in this mode, and the RDC/SDIN input should
always be tied either high or low.
CS
RD
To reduce performance degradation due to digital activity, a fast
discontinuous clock is recommended to ensure that all bits are
read during the first half of the conversion phase. It is also
possible to begin to read the data after conversion and continue
to read the last bits even after a new conversion has been
initiated.
DVDD
ADSP-219x*
AD7678*
SER/PAR
EXT/INT
BUSY
CS
PFx
SPIxSEL (PFx)
MISOx
RD
SDOUT
SCLK
CNVST
INVSCLK
SCKx
PFx or TFSx
*ADDITIONAL PINS OMITTED FOR CLARITY
03084-0-044
Figure 38. Interfacing the AD7678 to an SPI Interface
Rev. A | Page 24 of 28
AD7678
APPLICATION HINTS
LAYOUT
interface digital supply OVDD and the remaining digital
circuitry. When DVDD is powered from the system supply, it is
The AD7678 has very good immunity to noise on the power
supplies. However, care should still be taken with regard to
grounding layout.
useful to insert a bead to further reduce high frequency spikes.
The AD7678 has four different ground pins: REFGND, AGND,
DGND, and OGND. REFGND senses the reference voltage and
should be a low impedance return to the reference because it
carries pulsed currents. AGND is the ground to which most
internal ADC analog signals are referenced. This ground must
be connected with the least resistance to the analog ground
plane. DGND must be tied to the analog or digital ground plane
depending on the configuration. OGND is connected to the
digital system ground.
The printed circuit board that houses the AD7678 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. Digital and
analog ground planes should be joined in only one place,
preferably underneath the AD7678, or at least as close to the
AD7678 as possible. If the AD7678 is in a system where
multiple devices require analog-to-digital ground connections,
the connection should still be made at one point only, a star
ground point that should be established as close to the AD7678
as possible.
The layout of the decoupling of the reference voltage is
important. The decoupling capacitor should be close to the
ADC and should be connected with short and large traces to
minimize parasitic inductances.
The user should avoid running digital lines under the device,
because these will couple noise onto the die. The analog ground
plane should be allowed to run under the AD7678 to avoid
E±ALUATING THE AD7678’S PERFORMANCE
The evaluation board for the AD7678 allows a quick means to
measure both dc (histograms and time domain) and ac (time
and frequency domain) performances of the converter. The
EVAL-AD7678CBZ is an evaluation board package that includes
a fully assembled and tested evaluation board, documentation,
and software. The accompanying software requires the use of a
capture board that must be ordered seperately from the evalua-
tion board (see the Ordering Guide for information). The
evaluation board can also be used in a standalone configuration
and does not use the software when in this mode. Refer to the
EVAL-AD76XXEDZ and EVAL-AD76XXCBZ data sheets
available from www.analog.com for evaluation board details.
noise coupling. Fast switching signals like
or clocks
CNVST
should be shielded with digital ground to avoid radiating noise
to other sections of the board, and should never run near
analog signal paths. Crossover of digital and analog signals
should be avoided. Traces on different but close layers of the
board should run at right angles to each other. This will reduce
the effect of feedthrough through the board. The power supply
lines to the AD7678 should use as large a trace as possible to
provide low impedance paths and reduce the effect of glitches
on the power supply lines. Good decoupling is also important
to lower the supply’s impedance presented to the AD7678 and
to reduce the magnitude of the supply spikes. Decoupling
ceramic capacitors, typically 100 nF, should be placed close to
and ideally right up against each power supply pin (AVDD,
DVDD, and OVDD) and their corresponding ground pins.
Additionally, low ESR 10 μF capacitors should be located near
the ADC to further reduce low frequency ripple.
Two types of data capture boards can be used with the EVAL-
AD7678CBZ:
USB based (EVAL-CED1Z recommended)
Parallel port based (EVAL-CONTROL BRD3Z not
recommended because many newer PCs do not include
parallel ports any longer)
The DVDD supply of the AD7678 can be a separate supply or
can come from the analog supply, AVDD, or the digital
interface supply, OVDD. When the system digital supply is
noisy or when fast switching digital signals are present, and if
no separate supply is available, the user should connect the
DVDD digital supply to the analog supply AVDD through an
RC filter (see Figure 21), and connect the system supply to the
The recommended board layout for the AD7678 is outlined in
the evaluation board data sheet.
Rev. A | Page 25 of 28
AD7678
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
0.75
0.60
0.45
1.60
MAX
37
48
36
1
PIN 1
7.20
TOP VIEW
(PINS DOWN)
7.00 SQ
6.80
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
25
12
0.15
0.05
13
24
SEATING
PLANE
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 39. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
SECTION OF THIS DATA SHEET.
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 40. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad (CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7678ASTZ1
AD7678ASTZRL1
AD7678ACPZ1
AD7678ACPZRL1
EVAL-AD7678CBZ2
EVAL-CONTROL BRD2Z1, 3
EVAL-CONTROL BRD3Z1, 3
EVAL-CED1Z1, 3
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
Package Option
ST-48
ST-48
CP-48-1
CP-48-1
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Parallel Port Capture Board, 32k RAM
Parallel Port Capture Board, 128k RAM
USB Data Capture Board
1 Z = RoHS Compliant Part.
2This board can be used as a standalone evaluation board or in conjunction with the a capture board for evaluation/demonstration purposes.
3These capture board allow the PC to control and communicate with all Analog Devices evaluation boards ending in ED for EVAL-CED1Z and CB for EVAL-CONTROL
BRDxZ (x = 2, 3).
Rev. A | Page 26 of 28
AD7678
NOTES
Rev. A | Page 27 of 28
AD7678
NOTES
©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
D03084-0-6/09(A)
Rev. A | Page 28 of 28
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