EVAL-AD7683CB [ADI]
16-Bit, 100 kSPS PulSAR ADC in MSOP/QFN; 16位100 kSPS时的PulSAR ADC ，采用MSOP / QFN
| 型号： | EVAL-AD7683CB |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 100 kSPS PulSAR ADC in MSOP/QFN |
| 文件： | 总16页 (文件大小：615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 100 kSPS PulSAR
ADC in MSOP/QFN
AD7683
FEATURES
APPLICATION DIAGRAM
16-bit resolution with no missing codes
Throughput: 100 kSPS
INL: 1 LSB typ, 3 LSB max
0.5V TO VDD 2.7V TO 5.5V
Pseudodifferential analog input range
0 V to VREF with VREF up to VDD
Single-supply operation: 2.7 V to 5.5 V
Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible
Power dissipation : 4 mW @ 5 V, 1.5 mW @ 2.7 V,
150 µW @ 2.7 V/10 kSPS
REF
VDD
0 TO V
REF
+IN
–IN
DCLOCK
3-WIRE SPI
INTERFACE
AD7683
D
OUT
CS
GND
Standby current: 1 nA
Figure 1.
8-lead package: MSOP package and
3 mm × 3 mm QFN1 (LFCSP) (SOT-23 size)
Improved 2nd source to ADS8320 and ADS8325
Table 1. MSOP, QFN (LFCSP)/SOT-23, 16-Bit PulSAR ADC
Type
100 kSPS
AD7684
AD7683
250 kSPS
500 kSPS
AD7688
AD7686
True Differential
Pseudo
Differential/Unipolar
AD7687
AD7685
AD7694
APPLICATIONS
Battery-powered equipment
Data acquisition
Unipolar
AD7680
Instrumentation
Medical instruments
Process control
GENERAL DESCRIPTION
The AD7683 is a 16-bit, charge redistribution, successive
approximation, PulSAR™ analog-to-digital converter (ADC)
that operates from a single power supply, VDD, between 2.7 V
to 5.5 V. It contains a low power, high speed, 16-bit sampling
ADC with no missing codes (B grade), an internal conversion
clock, and a serial, SPI-compatible interface port. The part also
contains a low noise, wide bandwidth, short aperture delay,
track-and-hold circuit. On the
falling edge, it samples an
CS
analog input, +IN, between 0 V to REF with respect to a ground
sense, –IN. The reference voltage, REF, is applied externally and
can be set up to the supply voltage. Its power scales linearly with
throughput.
The AD7683 is housed in an 8-lead MSOP or an 8-lead QFN
(LFCSP) package, with an operating temperature specified from
−40°C to +85°C.
1 QFN package in development. Contact factory for samples and availability.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD7683
TABLE OF CONTENTS
Specifications..................................................................................... 3
Typical Connection Diagram ................................................... 13
Analog Input ............................................................................... 13
Driver Amplifier Choice............................................................ 13
Voltage Reference Input ............................................................ 14
Power Supply............................................................................... 14
Digital Interface.......................................................................... 14
Layout .......................................................................................... 14
Evaluating the AD7683’s Performance.................................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Functional Descriptions.......................... 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Application Information................................................................ 12
Circuit Information.................................................................... 12
Converter Operation.................................................................. 12
Transfer Functions...................................................................... 12
REVISION HISTORY
9/04—Initial Version: Revision 0
Rev. 0 | Page 2 of 16
AD7683
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted.
Table 2.
AD7683 All Grades
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range
Absolute Input Voltage
+IN − (–IN)
+IN
−IN
0
−0.1
−0.1
VREF
VDD + 0.1
0.1
V
V
V
Analog Input CMRR
Leakage Current at 25°C
Input Impedance
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
DCLOCK Frequency
REFERENCE
Voltage Range
Load Current
DIGITAL INPUTS
Logic Levels
VIL
fIN = 100 kHz
Acquisition phase
65
1
dB
nA
See the Analog Input section.
10
100
2.9
µS
kSPS
MHz
0
0
0.5
VDD + 0.3
50
V
µA
100 kSPS, V+IN − V−IN = VREF/2 = 2.5 V
−0.3
0.3 × VDD
V
VIH
0.7 × VDD
VDD + 0.3
V
IIL
IIH
−1
−1
+1
+1
µA
µA
pF
Input Capacitance
DIGITAL OUTPUTS
Data Format
VOH
5
Serial, 16 bits straight binary.
0.4
ISOURCE = −500 µA
ISINK = +500 µA
VDD − 0.3
V
V
VOL
POWER SUPPLIES
VDD
VDD Range1
Operating Current
VDD
Specified performance
2.7
2.0
5.5
5.5
V
V
100 kSPS throughput
VDD = 5 V
VDD = 2.7 V
800
560
µA
µA
Standby Current2, 3
Power Dissipation
1
50
6
nA
VDD = 5 V, 25°C
VDD = 5 V
VDD = 2.7 V
4
1.5
150
mW
mW
µW
2
VDD = 2.7 V, 10 kSPS throughput
TEMPERATURE RANGE
Specified Performance
TMIN to TMAX
−40
+85
°C
1 See the Typical Performance Characteristics section for more information.
2 With all digital inputs forced to VDD or GND, as required.
3 During acquisition phase.
Rev. 0 | Page 3 of 16
AD7683
VDD = 5 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted.
Table 3.
A Grade
B Grade
Parameter
Conditions
Min Typ
Max
Min Typ
Max
Unit
ACCURACY
No Missing Codes
Integral Linearity Error
Transition Noise
15
−6
16
−3
Bits
LSB
LSB
LSB
ppm/°C
mV
3
0.5
2
0.3
0.7
+6
24
1.6
1
0.5
2
0.3
0.4
+3
15
1.6
Gain Error1, TMIN to TMAX
Gain Error Temperature Drift
Offset Error
1
, TMIN to TMAX
Offset Temperature Drift
Power Supply Sensitivity
0.3
0.05
0.3
0.05
ppm/°C
LSB
VDD = 5 V ±5%
AC ACCURACY
Signal-to-Noise
Spurious-Free Dynamic Range fIN = 1 kHz
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Effective Number of Bits
fIN = 1 kHz
90
88
88
91
dB2
dB
dB
dB
Bits
−100
−100
90
−108
−106
91
fIN = 1 kHz
fIN = 1 kHz
fIN = 1 kHz
14.7
14.8
1 See the Terminology section. These specifications include full temperature range variation, but do not include the error contribution from the external reference.
2All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
VDD = 2.7 V; VREF = 2.5V; TA = –40°C to +85°C, unless otherwise noted.
Table 4.
A Grade
B Grade
Parameter
Conditions
Min Typ
Max
Min Typ
Max
Unit
ACCURACY
No Missing Codes
Integral Linearity Error
Transition Noise
15
−6
16
−3
Bits
LSB
LSB
LSB
ppm/°C
mV
ppm/°C
LSB
3
0.85
2
0.3
0.7
0.3
+6
30
3.5
1
0.85
2
0.3
0.7
0.3
+3
15
3.5
Gain Error1, TMIN to TMAX
Gain Error Temperature Drift
Offset Error, TMIN to TMAX
1
Offset Temperature Drift
Power Supply Sensitivity
0.05
0.05
VDD = 2.7 V ±5%
AC ACCURACY
Signal-to-Noise
Spurious-Free Dynamic Range fIN = 1 kHz
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Effective Number of Bits
fIN = 1 kHz
85
86
dB2
dB
dB
dB
Bits
−96
−94
85
−100
−98
86
fIN = 1 kHz
fIN = 1 kHz
fIN = 1 kHz
13.8
14
1 See the Terminology section. These specifications do include full temperature range variation, but do not include the error contribution from the external reference.
2All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Rev. 0 | Page 4 of 16
AD7683
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; TA = −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter
Symbol
tCYC
tCSD
tSUCS
tHDO
tDIS
Min
Typ
Max
100
0
Unit
kHz
µs
Throughput Rate
CS Falling to DCLOCK Low
CS Falling to DCLOCK Rising
DCLOCK Falling to Data Remains Valid
CS Rising Edge to DOUT High Impedance
DCLOCK Falling to Data Valid
Acquisition Time
20
5
ns
16
14
16
ns
ns
100
50
tEN
tACQ
tF
ns
ns
ns
ns
400
DOUT Fall Time
DOUT Rise Time
11
11
25
25
tR
tCYC
COMPLETE CYCLE
CS
tSUCS
tACQ
POWER DOWN
1
4
5
DCLOCK
tDIS
Hi-Z
tCSD
tEN
tHDO
Hi-Z
0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(MSB) (LSB)
D
0
OUT
NOTE:
A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
D
GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
OUT
Figure 2. Serial Interface Timing
Rev. 0 | Page 5 of 16
AD7683
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Analog Inputs
+IN1, –IN1
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
GND − 0.3 V to VDD + 0.3 V
or 130 mA
GND − 0.3 V to VDD + 0.3 V
REF
Supply Voltages
VDD to GND
−0.3 V to +6 V
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature Range
Vapor Phase (60 sec)
Infrared (15 sec)
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−65°C to +150°C
150°C
200°C/W (MSOP-8)
44°C/W (MSOP-8)
1 See the Analog Input section.
215°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
500µA
I
OL
T
O D
OUT
1.4V
C
L
100pF
500µA
I
OH
Figure 3. Load Circuit for Digital Interface Timing
2V
0.8V
tDELAY
tDELAY
2V
2V
0.8V
0.8V
Figure 4. Voltage Reference Levels for Timing
90%
10%
D
OUT
tR
tF
Figure 5. DOUT Rise and Fall Timing
Rev. 0 | Page 6 of 16
AD7683
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
REF
+IN
1
2
3
4
8
7
6
5
VDD
DCLOCK
AD7683
TOP VIEW
–IN
D
OUT
(Not to Scale)
GND
CS
Figure 6. 8-Lead MSOP and QFN1 (LFCSP) Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type2 Function
1
REF
AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a ceramic capacitor of a few µF.
2
+IN
AI
Analog Input. It is referred to in –IN. The voltage range, i.e., the difference between +IN and –IN, is 0 V
to VREF
.
3
4
5
–IN
GND
CS
AI
P
DI
Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground.
Power Supply Ground.
Chip Select Input. On its falling edge, it initiates the conversions. The part returns in shutdown mode as
soon as the conversion is done. It also enables DOUT. When high, DOUT is high impedance.
6
7
8
DOUT
DCLOCK
VDD
DO
DI
P
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input.
Power Supply.
1 QFN package in development. Contact factory for samples and availability.
2 AI = Analog Input; DI = Digital Input; DO = Digital Output; and P = Power
Rev. 0 | Page 7 of 16
AD7683
TERMINOLOGY
Integral Nonlinearity Error (INL)
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line
(see Figure 21).
ENOB=
[
S / N + D
]
−1.76 /6.02
)
dB
and is expressed in bits.
Total Harmonic Distortion (THD)
Differential Nonlinearity Error (DNL)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Signal-to-Noise Ratio (SNR)
Offset Error
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
The first transition should occur at a level ½ LSB above analog
ground (38.1 µV for the 0 V to 5 V range). The offset error is the
deviation of the actual transition from that point.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
Gain Error
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in dB.
The last transition (from 111...10 to 111...11) should occur for
an analog voltage 1½ LSB below the nominal full scale
(4.999886 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset has been adjusted out.
Aperture Delay
Spurious-Free Dynamic Range (SFDR)
Aperture delay is a measure of the acquisition performance and
is the time between the falling edge of the
the input signal is held for a conversion.
input and when
CS
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.
Transient Response
The time required for the ADC to accurately acquire its input
after a full-scale step function was applied.
Rev. 0 | Page 8 of 16
AD7683
TYPICAL PERFORMANCE CHARACTERISTICS
3
3
2
POSITIVE INL = +0.43LSB
NEGATIVE INL = –0.97LSB
POSITIVE DNL = +0.43LSB
NEGATIVE DNL = –0.41LSB
2
1
1
0
0
–1
–2
–3
–1
–2
–3
0
16384
32768
CODE
49152
65536
0
16384
32768
CODE
49152
65536
Figure 7. Integral Nonlinearity vs. Code
Figure 10. Differential Nonlinearity vs. Code
7000
120000
100000
80000
60000
40000
20000
0
62564
VDD = REF = 2.5V
VDD = REF = 5V
102287
6000
5000
4000
3000
2000
1000
0
35528
25440
15152
13619
4604
8
2755
50
130
0
0
1
0
0
0
0
6
0
0
79FD 79FE 79FF 7A00 7A01 7A02 7A03 7A04 7A05 7A06 7A07 7A08
CODE IN HEX
7A0E 7A0F 7A10 7A11 7A12 7A13 7A14 7A15 7A16
CODE IN HEX
Figure 8. Histogram of a DC Input at the Code Center
Figure 11. Histogram of a DC Input at the Code Center
0
–20
0
–20
16384 POINT FFT
VDD = REF = 5V
fS = 100kSPS
16384 POINT FFT
VDD = REF = 2.5V
fS = 100kSPS
fIN = 20.43kHz
fIN = 20.43kHz
–40
–40
SNR = 92.7dB
SNR = 88.7dB
THD = –105.7dB
SFDR = –106.4dB
THD = –102.6dB
SFDR = –104.6dB
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
10
20
30
40
50
0
10
20
30
40
50
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 9. FFT Plot
Figure 12. FFT Plot
Rev. 0 | Page 9 of 16
AD7683
100
17
16
15
14
13
1200
1000
800
600
400
200
0
fS = 100kSPS
95
90
85
SNR
S/[N+D]
ENOB
80
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
REFERENCE VOLTAGE (V)
SUPPLY (V)
Figure 13. SNR, S/(N + D), and ENOB vs. Reference Voltage
Figure 16. Operating Current vs. Supply
100
900
800
700
600
500
400
300
200
100
0
VDD = 5V, fS = 100kSPS
95
90
85
80
75
70
V
= 5V, –10dB
REF
V
= 5V, –1dB
REF
VDD = 2.7V, fS = 100kSPS
V
= 2.5V, –1dB
REF
–55
–34
–15
5
25
45
65
85
105
125
0
50
100
FREQUENCY (kHz)
150
200
TEMPERATURE (°C)
Figure 14. S/[N + D] vs. Frequency
Figure 17. Operating Current vs. Temperature
1000
750
500
250
0
–80
–85
V
2.5V = –1dB
REF
–90
–95
V
5V = –1dB
REF
–100
–105
–110
–55
–35
–15
5
25
45
65
85
105
125
0
40
80
120
160
200
TEMPERATURE (°C)
FREQUENCY (kHz)
Figure 18. Power-Down Current vs. Temperature
Figure 15. THD, ENOB vs. Frequency
Rev. 0 | Page 10 of 16
AD7683
6
5
4
3
2
OFFSET ERROR
GAIN ERROR
1
0
–1
–2
–3
–4
–5
–6
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 19. Offset and Gain Error vs. Temperature
Rev. 0 | Page 11 of 16
AD7683
APPLICATION INFORMATION
+IN
SWITCHES CONTROL
CONTROL
MSB
LSB
LSB
SW+
SW–
32,768C 16,384C
4C
4C
2C
2C
C
C
C
C
BUSY
REF
COMP
LOGIC
GND
OUTPUT CODE
32,768C 16,384C
MSB
CNV
–IN
Figure 20. ADC Simplified Schematic
array between GND and REF, the comparator input varies by
binary-weighted voltage steps (VREF/2, VREF/4...VREF/65536). The
control logic toggles these switches, starting with the MSB, to
bring the comparator back into a balanced condition. After the
completion of this process, the part returns to the acquisition
phase and the control logic generates the ADC output code.
CIRCUIT INFORMATION
The AD7683 is a low power, single-supply, 16-bit ADC using a
successive approximation architecture.
The AD7683 is capable of converting 100,000 samples per sec-
ond (100 kSPS) and powers down between conversions. When
operating at 10 kSPS, for example, it consumes typically 150 µW
with a 2.7 V supply, ideal for battery-powered applications.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7683 is shown in
Figure 21 and Table 8.
The AD7683 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
111...111
111...110
111...101
The AD7683 is specified from 2.7 V to 5.5 V. It is housed in a
8-lead MSOP package or a tiny, 8-lead QFN (LFCSP)package.
The AD7683 is an improved second source to the ADS8320 and
ADS8325. For even better performance, consider the AD7685.
CONVERTER OPERATION
000...010
000...001
000...000
The AD7683 is a successive approximation ADC based on a
charge redistribution DAC. Figure 20 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors, which are
connected to the two comparator inputs.
–FS
–FS + 1 LSB
+FS – 1 LSB
–FS + 0.5 LSB
+FS – 1.5 LSB
ANALOG INPUT
Figure 21. ADC Ideal Transfer Function
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the +IN and −IN inputs. When the
Table 8. Output Codes and Ideal Input Voltages
Analog Input
VREF = 5 V
Digital Output Code
Hexadecimal
FFFF1
8001
8000
Description
FSR – 1 LSB
Midscale + 1 LSB
Midscale
4.999924 V
2.500076 V
2.5 V
acquisition phase is complete and the
input goes low, a con-
CS
version phase is initiated. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the GND
input. Therefore, the differential voltage between the inputs,
+IN and −IN, captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
2.499924 V
76.3 µV
0 V
7FFF
0001
00002
1 This is also the code for an overranged analog input (V+IN – V–IN above
VREF – VGND).
2 This is also the code for an underranged analog input (V+IN – V–IN below VGND).
Rev. 0 | Page 12 of 16
AD7683
(NOTE 1)
REF
2.7V TO 5.25V
2.2 TO 10µF
(NOTE 2)
100nF
REF
VDD
33Ω
+IN
–IN
0 TO V
REF
DCLOCK
2.7nF
AD7683
(NOTE 3)
D
3-WIRE INTERFACE
OUT
CS
(NOTE 4)
GND
NOTE 1: SEE REFERENCE SECTION FOR REFERENCE SELECTION.
NOTE 2: C
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
REF
NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION.
NOTE 4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
Figure 22. Typical Application Diagram
sampling capacitor. During the conversion phase, where the
switches are opened, the input impedance is limited to CPIN. RIN
and CIN make a 1-pole, low-pass filter that reduces undesirable
aliasing effects and limits the noise.
TYPICAL CONNECTION DIAGRAM
Figure 22 shows an example of the recommended application
diagram for the AD7683.
ANALOG INPUT
When the source impedance of the driving circuit is low, the
AD7683 can be driven directly. Large source impedances signi-
ficantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance.
Figure 23 shows an equivalent circuit of the input structure of
the AD7683.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, +IN and −IN. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V, because this will cause these diodes to become for-
ward-biased and start conducting current. However, these
diodes can handle a forward-biased current of 130 mA maxi-
mum. For instance, these conditions could eventually occur
when the input buffer’s (U1) supplies are different from VDD.
In such a case, an input buffer with a short-circuit current
limitation can be used to protect the part.
DRIVER AMPLIFIER CHOICE
Although the AD7683 is easy to drive, the driver amplifier
needs to meet the following requirements:
•
The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7683. Note that the
AD7683 has a noise much lower than most other 16-bit
ADCs and, therefore, can be driven by a noisier op amp
while preserving the same or better system performance.
The noise coming from the driver is filtered by the AD7683
analog input circuit 1-pole, low-pass filter made by RIN and
CIN or by the external filter, if one is used.
VDD
D1
D2
C
IN
R
IN
+IN
OR –IN
C
PIN
GND
•
•
For ac applications, the driver needs to have a THD
performance suitable to that of the AD7683. Figure 15
shows the THD versus frequency that the driver should
exceed.
Figure 23. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the
differential signal between +IN and −IN. By using this
For multichannel multiplexed applications, the driver
amplifier and the AD7683 analog input circuit must be able
to settle for a full-scale step of the capacitor array at a
16-bit level (0.0015%). In the amplifier’s data sheet, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
differential input, small signals common to both inputs are
rejected. For instance, by using −IN to sense a remote signal
ground, ground potential differences between the sensor and
the local ADC ground are eliminated. During the acquisition
phase, the impedance of the analog input +IN can be modeled
as a parallel combination of the capacitor CPIN and the network
formed by the series connection of RIN and CIN. CPIN is primarily
the pin capacitance. RIN is typically 600 Ω and is a lumped com-
ponent made up of some serial resistors and the on-resistance
of the switches. CIN is typically 30 pF and is mainly the ADC
Rev. 0 | Page 13 of 16
AD7683
Table 9. Recommended Driver Amplifiers
A falling edge on
initiates a conversion and the data transfer.
CS
Amplifier
Typical Application
After the fifth DCLOCK falling edge, DOUT is enabled and
forced low. The data bits are then clocked, MSB first, by subse-
quent DCLOCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate, provided it has an acceptable hold time.
AD8021
AD8022
OP184
AD8605, AD8615
AD8519
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single-supply, low power
Small, low power, and low frequency
High frequency and low power
AD8031
CONVERT
DIGITAL HOST
DATA IN
CS
VOLTAGE REFERENCE INPUT
AD7683
DCLOCK
The AD7683 voltage reference input, REF, has a dynamic input
impedance. It should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
D
OUT
CLK
Figure 25. Connection Diagram
When REF is driven by a very low impedance source (e.g., an
unbuffered reference voltage like the low temperature drift
ADR43x reference or a reference buffer using the AD8031 or
the AD8605), a 10 µF (X5R, 0805 size) ceramic chip capacitor is
appropriate for optimum performance.
LAYOUT
The printed circuit board housing the AD7683 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7683 with all its analog signals on the left side and all its
digital signals on the right side eases this task.
If desired, smaller reference decoupling capacitor values down
to 2.2 µF can be used with a minimal impact on performance,
especially DNL.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7683 is used as a shield. Fast switching signals, such as
or
CS
POWER SUPPLY
clocks, should never run near analog signal paths. Crossover of
digital and analog signals should be avoided.
The AD7683 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 24. This makes the part
ideal for low sampling rates (even of a few Hz) and low battery-
powered applications.
At least one ground plane should be used. It could be common
or split between the digital and analog section. In such a case, it
should be joined underneath the AD7683.
1000
The AD7683 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. That is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and by connecting these pins with wide, low
impedance traces.
VDD = 5V
100
VDD = 2.7V
10
1
0.1
Finally, the power supply, VDD, of the AD7683 should be
decoupled with a ceramic capacitor, typically 100 nF, and placed
close to the AD7683. It should be connected using short and
large traces to provide low impedance paths and reduce the
effect of glitches on the power supply lines.
0.01
10
100
1k
10k
100k
SAMPLING RATE (SPS)
EVALUATING THE AD7683’S PERFORMANCE
Other recommended layouts for the AD7683 are outlined in the
evaluation board for the AD7683 (EVAL-AD7683). The evalu-
ation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-CONTROL BRD2.
Figure 24. Operating Current vs. Sampling Rate
DIGITAL INTERFACE
The AD7683 is compatible with SPI, QSPI, digital hosts, and
DSPs (e.g., Blackfin® ADSP-BF53x or ADSP-219x). The con-
nection diagram is shown in Figure 25 and the corresponding
timing is given in Figure 2.
Rev. 0 | Page 14 of 16
AD7683
OUTLINE DIMENSIONS
3.00
BSC
8
5
4
4.90
BSC
3.00
BSC
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.80
0.60
0.40
8°
0°
0.38
0.22
0.23
0.08
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 26. 8-Lead Micro Small Outline Package [MSOP]
(RM-8)
Dimensions Shown in Millimeters
INDEX
AREA
PIN 1
INDICATOR
3.00
BSC SQ
8
5
1
4
1.50
BCS SQ
0.65
BSC
2.48
2.38
2.23
EXPOSED
PAD
(BOTTOM VIEW)
TOP VIEW
0.50
0.40
0.30
1.74
1.64
1.49
PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
0.80 MAX
0.55 TYP
0.80
0.75
0.70
ELECTRICAL PERFORMANCES
0.05 MAX
0.02 NOM
SIDE VIEW
0.30
0.23
0.18
0.20 REF
SEATING
PLANE
Figure 27. 8-Terminal Quad Flat No Lead Package[QFN1 (LFCSP)]
3 mm × 3 mm Body
(CP-8-9)
Dimensions Shown in Millimeters
ORDERING GUIDE
Transport Media,
Quantity
Models
Integral Nonlinearity Temperature Range Package (Option)
Branding
C1L
C1L
C1C
C1C
AD7683ARM
AD7683ARMRL7
AD7683BRM
AD7683BRMRL7
EVAL-AD7683CB2
EVAL-CONTROL BRD23
EVAL-CONTROL BRD33
6 LSB max
6 LSB max
3 LSB max
3 LSB max
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
MSOP (RM-8)
MSOP (RM-8)
MSOP (RM-8)
MSOP (RM-8)
Tube, 50
Reel, 1,000
Tube, 50
Reel, 1,000
Evaluation Board
Controller Board
Controller Board
1 QFN package in development. Contact factory for samples and availability.
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.
3 These boards allow a PC to control and communicate with all Analog Devices’ evaluation boards ending in the CB designators.
Rev. 0 | Page 15 of 16
AD7683
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered
trademarks are the property of
their respective owners.
D04301-0-9/04(0)
Rev. 0 | Page 16 of 16
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