ADV7623BSTZ [ADI]
HDMI Transceiver with Fast Port Switching; HDMI收发器，具有快速端口切换
| 型号： | ADV7623BSTZ |
| 厂家： | 
ADI |
| 描述： | HDMI Transceiver with Fast Port Switching |
| 文件： | 总16页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HDMI Transceiver with
Fast Port Switching
ADV7623
Data Sheet
FEATURES
APPLICATIONS
4-input, 1-output multiplexed HDMI transceiver
Xpressview fast switching on all HDMI input ports
Character- and icon-based on-screen display (OSD)
High-Bandwidth Digital Content Protection (HDCP 1.4)
HDCP repeater support
AVRs
HTiB
Sound bar with HDMI repeater support
HBR enabled TVs
Other repeater applications
225 MHz HDMI Rx and Tx support 36-/30-/24-bit Deep Color
Supports DVI RGB graphics up to 1600 × 1200 at 60 Hz
Ultralow jitter digital PLL (100% deskew)
Quad HDMI Rx input
Format details available on all unselected ports
Adaptive equalizer for cable lengths up to 30 meters
Internal extended display identification data (EDID) RAM
EDID replication (512 bytes per port)
EDID with HDMI cable 5 V power support
5 V detect inputs
Hot plug assertion control pins
Single HDMI Tx output
EDID data extraction
Hot plug detect (HPD) input
Audio support
HDMI-compatible audio interface
Dedicated flexible audio input/output port
S/PDIF (IEC 60958-compatible) digital audio input/output
Super audio CD (SACD) with DSD input/output interface
High bit rate (HBR) audio
GENERAL DESCRIPTION
The ADV7623 is a high performance, four-input, one-output,
High-Definition Multimedia Interface (HDMI®) transceiver
that integrates HDMI receiver and transmitter functions with
digital audio I/Os onto one chip. It supports all HDCP repeater
functions through fully tested Analog Devices, Inc., repeater
software libraries and drivers.
The ADV7623 incorporates Xpressview™ fast switching on all
input HDMI ports. Using an Analog Devices hardware-based
HDCP engine that minimizes software overhead, Xpressview
technology allows fast switching between any HDMI input
ports in less than 1 second.
The ADV7623 supports all mandatory HDMI 3D TV formats in
addition to all HDTV formats up to 1080p 36-bit Deep Color. The
ADV7623 also features an integrated HDMI CEC controller that
supports capability, discovery, and control (CDC).
The ADV7623 has an integrated on-screen display (OSD) feature
that allows generation and control of high quality character- and
icon-based system status and control displays. Customers interested
in using OSD are provided with Analog Devices OSD SDK.
Dolby® TrueHD
DTS-HD Master Audio™
Full audio input and output support
General
Interrupt controller with 3 interrupt outputs
STDI (standard identification circuit)
Software libraries, driver, and application available
2-layer PCB design supported
The ADV7623 offers a dedicated flexible audio output port and
a dedicated audio input port to allow for easy extraction and
insertion of audio data into and out of the HDMI stream. HDMI
audio formats, including SACD via DSD and compressed high
bit rate audio via HBR, are supported. The ADV7623 also features
an audio return channel (ARC) receiver. ARC simplifies cabling
by combining upstream audio capability in a conventional
HDMI cable.
Fabricated in an advanced CMOS process, the ADV7623 is
provided in a 144-lead, 20 mm × 20 mm, Pb-free LQFP and is
specified over the 0°C to 70°C temperature range.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third partiesthat may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADV7623
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Package Thermal Performance....................................................8
ESD Caution...................................................................................8
Pin Configuration and Function Descriptions..............................9
Functional Overview...................................................................... 13
HDMI Receiver........................................................................... 13
HDMI Transmitter..................................................................... 13
I2C Interface ................................................................................ 13
Other Features ............................................................................ 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Digital, HDMI, and AC Specifications...................................... 4
Data and I2C Timing Characteristics......................................... 5
Power Specifications .................................................................... 7
Absolute Maximum Ratings............................................................ 8
REVISION HISTORY
3/13—Revision D: Initial Version
Rev. D | Page 2 of 16
Data Sheet
ADV7623
FUNCTIONAL BLOCK DIAGRAM
TX
PLL
XTAL
XTAL1
VIDEO DATA
DE
VS
RXA_C
RX
PLL
RXB_C
RXC_C
RXD_C
HS
AUDIO DATA
VIDEO DATA
DE
VS
RXA_0
RXA_1
RXA_2
OSD
HS
EQUALIZER
EQUALIZER
EQUALIZER
EQUALIZER
SAMPLER
SAMPLER
SAMPLER
SAMPLER
AUDIO DATA
VIDEO DATA
RXB_0
RXB_1
RXB_2
VIDEO DATA
DE
VS
DE
VS
HS
CH0
CH1
CH2
TXC
TX0
TX1
TX2
HS
AUDIO DATA
RXC_0
RXC_1
RXC_2
AUDIO DATA
RXD_0
RXD_1
RXD_2
AUDIO
PROCESSOR
SYNC
PACKET
TXDDC_SDA
TXDDC_SCL
MEASUREMENT PROCESSOR
CEC
CONTROLLER
CEC
AUDIO
CAPTURE
INFOFRAME
PACKET
MEMORY
5V_DETA
5V_DETB
5V_DETC
5V_DETD
5V DETECT
INT1
INT2
INT_TX
HP_CTRLA
HP_CTRLB
HP_CTRLC
HP_CTRLD
RX HPD
CONTROLLER
AP0_IN
AP1_IN
AP2_IN
AP3_IN
AP4_IN
AP5_IN
EP_MISO
EP_MOSI
EP_CS
SPI MASTER/
SLAVE
EP_SCK
SCLK_IN
MCLK_IN
AP0_OUT
AP1_OUT
AP2_OUT
AP3_OUT
AP4_OUT
AP5_OUT
SCLK_OUT
MCLK_OUT
DDCA_SDA
DDCA_SCL
DDCB_SDA
DDCB_SCL
DDCC_SDA
DDCC_SCL
DDCD_SDA
DDCD_SCL
EDID
RAM
RX EDID/
REPEATER
CONTROLLER
PWRDN
RESET
GLOBAL
CONTROLS
HPD_ARC–
ARC+
ADV7623
ARC
RECEIVER
SCL
SDATA
ALSB
CS
I2C
CONTROLLER
Figure 1.
Rev. D | Page 3 of 16
ADV7623
Data Sheet
SPECIFICATIONS
CVDD = 1.8 V 5%, DVDD = 1.8 V 5%, DVDDIO = 3.3 V 5%, PVDD = 1.8 V 5%, TVDD = 3.3 V 5%, TXAVDD = 1.8 V 5%,
TXPVDD = 1.8 V 5%, TXPLVDD = 1.8 V 5%, TMIN to TMAX = 0°C to 70°C.
DIGITAL, HDMI, AND AC SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIGITAL INPUTS
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IIN)
2
V
V
µA
µA
pF
0.8
RESET, EP_MISO, ALSB and CS pins
Other digital inputs
−60
−10
+60
+10
10
Input Capacitance (CIN)
DIGITAL INPUTS (5 V TOLERANT)1
Input High Voltage (VIH)
Input Low Voltage (VIL)
2.6
V
V
0.8
Input Current (IIN)
−82
2.4
+82
µA
DIGITAL OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
High Impedance Leakage Current (ILEAK
Output Capacitance (COUT
HDMI
V
V
µA
pF
0.4
20
)
10
)
TMDS Differential Pin Capacitance
AC SPECIFICATIONS
0.3
pF
Input Specifications
Intrapair (+ to −) Differential Input Skew for
TMDS Clock Rates up to 222.75 MHz
Intrapair (+ to −) Differential Input Skew for
TMDS Clock Rates Above 222.75 MHz
0.4 tBIT
ps
ps
0.15 tBIT + 112
Channel-to-Channel Differential Input Skew
TMDS Input Clock Range
0.2 tPIXEL + 1.78 ns
25
225
MHz
TMDS Input Clock Jitter Tolerance
Output Specifications
0.5
0.25
tBIT
TMDS Output Clock Frequency
TMDS Output Clock Duty Cycle
TMDS Output Differential Swing
Differential Output Timing
20
48
900
225
52
1100 1200
MHz
%
mV
Low-to-High Transition Time
High-to-Low Transition Time
75
75
175
175
ps
ps
1 The following pins are 5 V tolerant: DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA, TXDDC_SDA, TXDDC_SCL,
PWRDN
HP_CTRLA, HP_CTRLB, HP_CTRLC, HP_CTRLD, HPD_ARC−, 5V_DETA, 5V_DETB, 5V_DETC, 5V_DETD,
, CEC, ARC+.
Rev. D | Page 4 of 16
Data Sheet
ADV7623
DATA AND I2C TIMING CHARACTERISTICS
Table 2.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
VIDEO SYSTEM CLOCK AND XTAL
Crystal Nominal Frequency
Crystal Frequency Stability
External Clock Source1
Input High Voltage
28.63636
MHz
ppm
50
External crystal must operate at 1.8 V
XTAL driven with external clock source
XTAL driven with external clock source
VIH
VIL
1.2
5
V
V
Input Low Voltage
0.4
RESET FEATURE
Reset Pulse Width
ms
I2C PORTS (FAST MODE)
xCL Frequency2
400
kHz
ns
µs
ns
ns
ns
ns
ns
µs
xCL Minimum Pulse Width High2
xCL Minimum Pulse Width Low2
Hold Time (Start Condition)
Setup Time (Start Condition)
xDA Setup Time2
t1
t2
t3
t4
t5
t6
t7
t8
600
1.3
600
600
100
xCL and xDA Rise Time2
xCL and xDA Fall Time2
Setup Time (Stop Condition)
I2C PORTS (NORMAL MODE)
xCL Frequency2
xCL Minimum Pulse Width High2
xCL Minimum Pulse Width Low2
Hold Time (Start Condition)
Setup Time (Start Condition)
xDA Setup Time2
xCL and xDA Rise Time2
xCL and xDA Fall Time2
Setup Time (Stop Condition)
AUDIO OUTPUT PORT (MASTER MODE)
SCLK Mark Space Ratio
300
300
0.6
100
kHz
µs
µs
µs
µs
t1
t2
t3
t4
t5
t6
t7
t8
4.0
4.7
4.0
4.7
250
ns
1000 ns
300
ns
µs
4.0
t13:t14
45:55
55:45 % duty
cycle
APx_OUT Data Transition Time (LRCLK)3
APx_OUT Data Transition Time (LRCLK)3
APx_OUT Data Transition Time (I2S Data)3
APx_OUT Data Transition Time (I2S Data)3
AUDIO INPUT PORT
t15
t16
t17
t18
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
10
10
5
ns
ns
ns
ns
5
APx_IN Setup Time (I2S Data)3
t19
t20
t19
t20
2
2
2
2
ns
ns
ns
ns
APx_IN Hold Time (I2S Data)3
APx_IN Setup Time (LRCLK)3
APx_IN Hold Time (LRCLK)3
1 This part must be configured for external oscillator operation. A 1.8 V oscillator must be used.
2 The prefix x refers to S, DDCA_S, DDCB_S, DDCC_S, and DDCD_S.
3 The suffix x refers to 0, 1, 2, 3, 4, and 5.
Rev. D | Page 5 of 16
ADV7623
Data Sheet
Timing Diagrams
t3
t5
t3
xDA
t6
t1
xCL
t2
t7
t4
t8
NOTES
1. x REFERS TO S, DDCA_S, DDCB_S, DDCC_S, DDCD_S.
Figure 2. I2C Timing
t13
SCLK
t14
t15
LRCLK
I2S[3:0]
t16
t17
LEFT-JUSTIFIED
MODE
MSB
MSB – 1
MSB
t18
t17
I2S[3:0]
2
I S MODE
MSB – 1
t18
t17
I2S[3:0]
RIGHT-JUSTIFIED
MODE
MSB
LSB
t18
Figure 3. I2S Output Timing
t19
SCLK
RISING EDGE
R0x0B[6] = 0
t20
I2S[3:0],
LRCLK
VALID DATA
t19
t20
SCLK
FALLING EDGE
R0x0B[6] = 1
I2S[3:0]
LRCLK
VALID DATA
Figure 4. I2S Input Timing
Rev. D | Page 6 of 16
Data Sheet
ADV7623
POWER SPECIFICATIONS
Table 3.
Parameter
Min Typ
Max
Unit Test Conditions/Comments
POWER SUPPLIES
Comparator Power Supply (CVDD)
Digital Core Power Supply (DVDD)
Digital I/O Power Supply (DVDDIO)
PLL Power Supply (PVDD)
Termination Power Supply (TVDD)
1.71 1.8
1.71 1.8
3.14 3.3
1.71 1.8
3.14 3.3
1.89
1.89
3.46
1.89
3.46
1.89
1.89
1.89
V
V
V
V
V
V
V
V
TX TMDS Output Power Supply (TXAVDD) 1.71 1.8
TX Power Supply (TXPVDD)
TX PLL Power Supply (TXPLVDD)
CURRENT CONSUMPTION1, 2, 3, 4
1.71 1.8
1.71 1.8
Comparator Power Supply (ICVDD
)
481
301
1.0
545
1.0
1.0
350
9.0
6.7
2.0
3.4
3.3
39.6
1.7
1.6
312
0.4
0.4
14.3
0.5
0.3
6.6
2.8
2.8
26.4
1.6
1.6
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Four ports with 1080p 12-bit, Xpressview and OSD enabled
Power-Down Mode 1
Power-Down Mode 0
Four ports with 1080p 12-bit, Xpressview and OSD enabled
Power-Down Mode 1
Power-Down Mode 0
Four ports with 1080p 12-bit, Xpressview and OSD enabled
Power-Down Mode 1
Power-Down Mode 0
Four ports with 1080p 12-bit, Xpressview and OSD enabled
Power-Down Mode 1
Power-Down Mode 0
Four ports with 1080p 12-bit, Xpressview and OSD enabled
Power-Down Mode 1
Power-Down Mode 0
Four ports with 1080p 12-bit, Xpressview and OSD enabled
Power-Down Mode 1
Power-Down Mode 0
Four ports with 1080p 12-bit, Xpressview and OSD enabled
Power-Down Mode 1
Power-Down Mode 0
Four ports with 1080p 12-bit, Xpressview and OSD enabled
Power-Down Mode 1
Power-Down Mode 0
Digital Core Power Supply (IDVDD
)
Digital I/O Power Supply (IDVDDIO
)
PLL Power Supply (IPVDD
)
34.0
283
13.0
5.0
Termination Power Supply (ITVDD
)
TX TMDS Output Power Supply (ITXAVDD
)
TX Power Supply (ITXPVDD
)
TX PLL Power Supply (ITXPLVDD
)
23.0
1 All maximum current values are guaranteed by characterization to assist in power supply design.
2 Typical current consumption values are recorded with nominal voltage supply levels and at room temperature.
3 Maximum current consumption values are recorded with maximum rated voltage supply levels and at room temperature.
4 Termination power supply includes TVDD current consumed off chip.
Rev. D | Page 7 of 16
ADV7623
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the ADV7623, turn
off the unused sections of the part.
Parameter
Rating
2.2 V
2.2 V
2.2 V
4.0 V
4.0 V
2.2 V
2.2 V
2.2 V
CVDD to GND
DVDD to GND
PVDD to GND
DVDDIO to GND
TVDD to GND
TXAVDD to GND
TXPVDD to GND
TXPLVDD to GND
Digital Inputs Voltage to GND
Due to printed circuit board (PCB) metal variation and, thus,
variation in PCB heat conductivity, the value of θJA may differ
for various PCBs.
The most efficient measurement solution is obtained using the
package surface temperature to estimate the die temperature
because this eliminates the variance associated with the θJA value.
The maximum junction temperature (TJ MAX) of 125°C must not
be exceeded. The following equation calculates the junction
temperature using the measured package surface temperature
and applies only when no heat sink is used on the DUT:
GND − 0.3 V to DVDDIO + 0.3 V
up to a maximum of 4.0 V
5 V Tolerant Digital Inputs to GND1 5.5 V
Digital Output Voltage to GND
GND − 0.3 V to DVDDIO + 0.3 V
up to a maximum of 4.0 V
−0.3 V to PVDD to +0.3 V
Maximum Junction Temperature 125°C
(TJ MAX
TJ = TS + (ΨJT × WTOTAL
where:
TS = the package surface temperature (°C).
JT = 0.6°C/W for a 144-lead LQFP.
)
XTAL, XTAL1 Pins
)
Ψ
Storage Temperature
Infrared Reflow, Soldering (20 sec)
150°C
260°C
W
TOTAL = ((CVDD × ICVDD) + (DVDD × IDVDD) +
(PVDD × IPVDD) + (DVDDIO × IDVDDIO) +
(0.7 × TVDD × ITVDD) + (TXAVDD × ITXAVDD) +
(TXPVDD × ITXPVDD) + (TXPLVDD × ITXPLVDD))
1 The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL,
DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL,
DDCD_SDA, TXDDC_SDA, TXDDC_SCL, HP_CTRLA, HP_CTRLB, HP_CTRLC,
PWRDN
HP_CTRLD, HPD_ARC−, 5V_DETA, 5V_DETB, 5V_DETC, 5V_DETD,
CEC, ARC+.
,
Note that for WTOTAL, 5% of TVDD power is dissipated on the
part itself.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. D | Page 8 of 16
Data Sheet
ADV7623
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
108
107
106
105
104
103
102
101
100
99
DDCC_SCL
CVDD
DDCA_SDA
RTERM
5V_DETA
HP_CTRLA
PGND
PVDD
XTAL1
XTAL
PVDD
PIN 1
2
3
CGND
4
RXC_C–
RXC_C+
TVDD
RXC_0–
RXC_0+
CGND
RXC_1–
RXC_1+
TVDD
RXC_2–
RXC_2+
HP_CTRLD
5V_DETD
DGND
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PGND
98
PWRDN
RESET
MCLK_OUT
SCLK_OUT
AP5_OUT
DVDD
97
96
95
94
93
92
DGND
ADV7623
TOP VIEW
91
DVDD
AP4_OUT
AP3_OUT
AP2_OUT
AP1_OUT
AP0_OUT
DVDDIO
DGNDIO
INT_TX
INT2
INT1
DVDD
DGND
SCL
90
DDCD_SDA
DDCD_SCL
CVDD
(Not to Scale)
89
88
87
CGND
86
RXD_C–
RXD_C+
TVDD
RXD_0–
RXD_0+
CGND
RXD_1–
RXD_1+
TVDD
RXD_2–
RXD_2+
CVDD
85
84
83
82
81
80
79
78
SDATA
77
AP0_IN
AP1_IN
AP2_IN
AP3_IN
DVDDIO
76
75
74
CGND
TXPVDD
73
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic
Type
Description
1
2
DDCC_SCL
CVDD
Digital input
Power
HDCP Slave Serial Clock Port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant.
Receiver Comparator Supply Voltage (1.8 V).
3
CGND
Ground
TVDD and CVDD Ground.
4
5
6
RXC_C−
RXC_C+
TVDD
HDMI input
HDMI input
Power
Digital Input Clock Complement of Port C in the HDMI Interface.
Digital Input Clock True of Port C in the HDMI Interface.
Receiver Terminator Supply Voltage (3.3 V).
7
8
9
RXC_0−
RXC_0+
CGND
HDMI input
HDMI input
Ground
Digital Input Channel 0 Complement of Port C in the HDMI Interface.
Digital Input Channel 0 True of Port C in the HDMI Interface.
TVDD and CVDD Ground.
10
11
12
RXC_1−
RXC_1+
TVDD
HDMI input
HDMI input
Power
Digital Input Channel 1 Complement of Port C in the HDMI Interface.
Digital Input Channel 1 True of Port C in the HDMI Interface.
Receiver Terminator Supply Voltage (3.3 V).
Rev. D | Page 9 of 16
ADV7623
Data Sheet
Pin No. Mnemonic
Type
Description
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
RXC_2−
RXC_2+
HP_CTRLD
5V_DETD
DGND
HDMI input
HDMI input
Digital output
Digital input
Ground
Digital Input Channel 2 Complement of Port C in the HDMI Interface.
Digital Input Channel 2 True of Port C in the HDMI Interface.
Hot Plug Detect for Port D.
5 V Detect Pin for Port D in the HDMI Interface.
DVDD Ground.
DVDD
Power
Digital Supply Voltage (1.8 V).
DDCD_SDA
DDCD_SCL
CVDD
Digital I/O
Digital input
Power
HDCP Slave Serial Data Port D. DDCD_SDA is a 3.3 V input/output that is 5 V tolerant.
HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant.
Receiver Comparator Supply Voltage (1.8 V).
CGND
Ground
TVDD and CVDD Ground.
RXD_C−
RXD_C+
TVDD
RXD_0−
RXD_0+
CGND
RXD_1−
RXD_1+
TVDD
RXD_2−
RXD_2+
CVDD
HDMI input
HDMI input
Power
HDMI input
HDMI input
Ground
HDMI input
HDMI input
Power
HDMI input
HDMI input
Power
Digital Input Clock Complement of Port D in the HDMI Interface.
Digital Input Clock True of Port D in the HDMI Interface.
Receiver Terminator Supply Voltage (3.3 V).
Digital Input Channel 0 Complement of Port D in the HDMI Interface.
Digital Input Channel 0 True of Port D in the HDMI Interface.
TVDD and CVDD Ground.
Digital Input Channel 1 Complement of Port D in the HDMI Interface.
Digital Input Channel 1 True of Port D in the HDMI Interface.
Receiver Terminator Supply Voltage (3.3 V).
Digital Input Channel 2 Complement of Port D in the HDMI Interface.
Digital Input Channel 2 True of Port D in the HDMI Interface.
Receiver Comparator Supply Voltage (1.8 V).
CGND
TXPVDD
Ground
Power
TVDD and CVDD Ground.
1.8 V Power Supply for Digital and I/O Power Supply. This pin supplies power to the
digital logic and I/Os. It should be filtered and as quiet as possible.
37
38
39
40
TXPLVDD
TXGND
TXPGND
EXT_SWING
Power
Ground
Ground
Analog input
1.8 V Power Supply.
TXPVDD Ground.
TXPLVDD Ground.
This pin sets the internal reference currents. Place an 887 Ω resistor (1% tolerance) between
this pin and ground.
41
HPD_ARC−
Analog input
Hot Plug Detect Signal and Audio Return Channel Inverted Input. This pin indicates to the
interface whether the receiver is connected.
42
43
ARC+
Analog input
Audio Return Channel (ARC) Input (5 V Tolerant).
Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. It supports a
5 V CMOS logic level.
TXDDC_SDA Digital I/O
44
TXDDC_SCL Digital output
Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus.
It supports a 5 V CMOS logic level.
45
46
47
TXAVDD
TXGND
TXC−
Power
Ground
HDMI output
1.8 V Power Supply for TMDS Outputs.
TXAVDD Ground.
Differential Clock Output. Differential clock output at the TMDS clock rate; supports
TMDS logic level.
48
TXC+
HDMI output
Differential Clock Output. Differential clock output at the TMDS clock rate; supports
TMDS logic level.
49
50
TXGND
TX0−
Ground
HDMI output
TXAVDD Ground.
Differential Output Channel 0 Complement. Differential output of the red data at 10×
the pixel clock rate; supports TMDS logic level.
51
TX0+
HDMI output
Differential Output Channel 0 True. Differential output of the red data at 10× the pixel clock
rate; supports TMDS logic level.
52
53
TXGND
TX1−
Ground
HDMI output
TXAVDD Ground.
Differential Output Channel 1 Complement. Differential output of the red data at 10×
the pixel clock rate; supports TMDS logic level.
54
55
TX1+
HDMI output
Power
Differential Output Channel 1 True. Differential output of the red data at 10× the pixel
clock rate; supports TMDS logic level.
1.8 V Power Supply for TMDS Outputs.
TXAVDD
Rev. D | Page 10 of 16
Data Sheet
ADV7623
Pin No. Mnemonic
Type
Description
56
TX2−
HDMI output
Differential Output Channel 2 Complement. Differential output of the red data at 10×
the pixel clock rate; supports TMDS logic level.
57
TX2+
HDMI output
Differential Output Channel 2 True. Differential output of the red data at 10× the pixel
clock rate; supports TMDS logic level.
58
59
60
61
62
63
TXGND
CEC
DGND
DVDD
ALSB
CS
Ground
Digital I/O
Ground
Power
Digital input
Digital input
TXAVDD Ground.
Consumer Electronics Control Channel (5 V Tolerant).
DVDD Ground.
Digital Supply Voltage (1.8 V).
This pin is used to set the I2C address of the Rx IO and the Tx main map.
Chip Select Pin. This pin must be set low or left floating for the chip to process I2C messages
that are destined for the ADV7623. The ADV7623 ignores I2C messages that it receives if
this pin is high.
64
65
66
67
68
EP_SCK
EP_CS
EP_MOSI
EP_MISO
MCLK_IN
Digital output
Digital output
Digital output
Digital input
Digital input
SPI Clock Interface for the EDID/OSD.
SPI Chip Selected Interface for the EDID/OSD.
SPI Master Out/Slave In for the EDID/OSD.
SPI Master In/Slave Out for the EDID/OSD.
Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (fS),
256 × fS, 384 × fS, or 512 × fS. It supports CMOS logic levels from 1.8 V to 3.3 V.
69
70
71
72
73
74
75
76
77
78
79
80
81
82
SCLK_IN
AP5_IN
AP4_IN
DGNDIO
DVDDIO
AP3_IN
AP2_IN
AP1_IN
AP0_IN
SDATA
SCL
Digital input
Digital input
Digital input
Ground
I2S Audio Clock. It supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Input Port 5. It supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Input Port 4. It supports CMOS logic levels from 1.8 V to 3.3 V.
DVDDIO Ground.
Power
Digital I/O Supply Voltage (3.3 V).
Digital input
Digital input
Digital input
Digital input
Digital I/O
Digital input
Ground
Audio Input Port 3. It supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Input Port 2. It supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Input Port 1. It supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Input Port 0. It supports CMOS logic levels from 1.8 V to 3.3 V.
I2C Port Serial Data Input/Output Pin. SDATA is the data line for the control port.
I2C Port Serial Clock Input. SCL is the clock line for the control port.
DVDD Ground.
DGND
DVDD
INT1
(AMUTE1)
Power
Digital output
Digital Supply Voltage (1.8 V).
Interrupt Pin. This pin can be active low or active high. When status bits change, this pin is
triggered. The events that trigger an interrupt are under user control. This pin can also output
an audio mute signal.
83
INT2
(AMUTE2)
Digital output
Interrupt Pin. This pin can be active low or active high. When status bits change, this pin is
triggered. The events that trigger an interrupt are under user control. This pin can also output
an audio mute signal.
84
85
86
87
88
89
90
91
92
93
94
95
96
97
INT_TX
Digital output
Ground
Power
Digital output
Digital output
Digital output
Digital output
Digital output
Ground
Interrupt; Open Drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply is recommended.
DVDDIO Ground.
DGNDIO
DVDDIO
AP0_OUT
AP1_OUT
AP2_OUT
AP3_OUT
AP4_OUT
DGND
Digital I/O Supply Voltage (3.3 V).
Audio Output Port 0.
Audio Output Port 1.
Audio Output Port 2.
Audio Output Port 3.
Audio Output Port 4.
DVDD Ground.
Digital Supply Voltage (1.8 V).
Audio Output Port 5.
Audio Serial Clock Output.
Audio Master Clock Output.
DVDD
Power
AP5_OUT
SCLK_OUT
MCLK_OUT
RESET
Digital output
Digital output
Digital output
Digital input
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7623 circuitry.
98
PWRDN
Digital input
Active Low Power-Down Pin. If used, this pin should be pulled high to power up the
ADV7623. This pin can also be used as an in system power detect where internal EDID can
be powered from a 5 V signal of the HDMI port when it is connected to active equipment.
Rev. D | Page 11 of 16
ADV7623
Data Sheet
Pin No. Mnemonic
Type
Description
99
100
101
PGND
PVDD
XTAL
Ground
Power
Miscellaneous
analog
PVDD Ground.
PLL Supply Voltage (1.8 V).
Input pin for 28.63636 MHz crystal or an external 1.8 V 28.63636 MHz clock oscillator source to
clock the ADV7623.
102
XTAL1
Miscellaneous
analog
Crystal Output Pin. This pin should be left floating if a clock oscillator is used.
103
104
105
106
107
PVDD
PGND
HP_CTRLA
5V_DETA
RTERM
Power
Ground
Digital output
Digital input
Miscellaneous
analog
PLL Supply Voltage (1.8 V).
PVDD Ground.
Hot Plug Detect for Port A.
5 V Detect Pin for Port A in the HDMI Interface.
This pin sets the internal termination resistance. A 500 Ω resistor between this pin and
ground should be used.
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
DDCA_SDA
DDCA_SCL
CVDD
Digital I/O
Digital input
Power
HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input/output that is 5 V tolerant.
HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
Receiver Comparator Supply Voltage (1.8 V).
CGND
Ground
TVDD and CVDD Ground.
RXA_C−
RXA_C+
TVDD
RXA_0−
RXA_0+
CGND
RXA_1−
RXA_1+
TVDD
RXA_2−
RXA_2+
HP_CTRLB
5V_DETB
DGND
HDMI input
HDMI input
Power
HDMI input
HDMI input
Ground
HDMI input
HDMI input
Power
HDMI input
HDMI input
Digital output
Digital input
Ground
Digital Input Clock Complement of Port A in the HDMI Interface.
Digital Input Clock True of Port A in the HDMI Interface.
Receiver Terminator Supply Voltage (3.3 V).
Digital Input Channel 0 Complement of Port A in the HDMI Interface.
Digital Input Channel 0 True of Port A in the HDMI Interface.
TVDD and CVDD Ground.
Digital Input Channel 1 Complement of Port A in the HDMI Interface.
Digital Input Channel 1 True of Port A in the HDMI Interface.
Receiver Terminator Supply Voltage (3.3 V).
Digital Input Channel 2 Complement of Port A in the HDMI Interface.
Digital Input Channel 2 True of Port A in the HDMI Interface.
Hot Plug Detect for Port B.
5 V Detect Pin for Port B in the HDMI Interface.
DVDD Ground.
Digital Supply Voltage (1.8 V).
HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input/output that is 5 V tolerant.
HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.
Receiver Comparator Supply Voltage (1.8 V).
DVDD
Power
DDCB_SDA
DDCB_SCL
CVDD
Digital I/O
Digital input
Power
CGND
Ground
TVDD and CVDD Ground.
RXB_C−
RXB_C+
TVDD
RXB_0−
RXB_0+
CGND
RXB_1−
RXB_1+
TVDD
RXB_2−
RXB_2+
HP_CTRLC
5V_DETC
DDCC_SDA
HDMI input
HDMI input
Power
HDMI input
HDMI input
Ground
HDMI input
HDMI input
Power
HDMI input
HDMI input
Digital output
Digital input
Digital I/O
Digital Input Clock Complement of Port B in the HDMI Interface.
Digital Input Clock True of Port B in the HDMI Interface.
Receiver Terminator Supply Voltage (3.3 V).
Digital Input Channel 0 Complement of Port B in the HDMI Interface.
Digital Input Channel 0 True of Port B in the HDMI Interface.
TVDD and CVDD Ground.
Digital Input Channel 1 Complement of Port B in the HDMI Interface.
Digital Input Channel 1 True of Port B in the HDMI Interface.
Receiver Terminator Supply Voltage (3.3 V).
Digital Input Channel 2 Complement of Port B in the HDMI Interface.
Digital Input Channel 2 True of Port B in the HDMI Interface.
Hot Plug Detect for Port C.
5 V Detect Pin for Port C in the HDMI Interface.
HDCP Slave Serial Data Port C. DDCC_SDA is a 3.3 V input/output that is 5 V tolerant.
Rev. D | Page 12 of 16
Data Sheet
ADV7623
FUNCTIONAL OVERVIEW
high frequency losses inherent in HDMI and DVI cabling, especially
at longer lengths and higher frequencies. The receiver also contains
a programmable data island packet interrupt generator.
HDMI RECEIVER
The ADV7623 front end incorporates a 4:1 multiplexed HDMI
receiver boasting Xpressview fast switching technology and
support for HDMI features including 3D TV, content type bits,
and advanced features, such as capability discovery and control.
Building on the feature set of existing Analog Devices HDMI
devices, the ADV7623 also offers support for all HDTV formats
up to 36-bit, 1080p Deep Color and all display resolutions up to
UXGA (1600 × 1200 at 60 Hz).
HDMI TRANSMITTER
The ADV7623 features a single HDMI transmitter supporting
ARC, 3D TV formats as well as all HDTV formats up to 1080p,
36-bit Deep Color.
Supporting both single-ended and differential modes, the ARC
feature simplifies cabling by combining an upstream audio capability
in a conventional HDMI cable.
The transmitter features an on-chip MPU with an I2C master to
perform HDCP operations and EDID reading operations.
Xpressview fast switching technology, using Analog Devices
hardware-based HDCP engine that minimizes software overhead,
allows switching between any two input ports in less than 1 second.
A key feature of the ADV7623 is the on-chip character-based
OSD generator. The OSD generated can be converted to match
the input format 4:2:2 or 4:4:4 in RGB or YCrCb color space. The
OSD is overlaid at the output resolution for best performance. The
OSD portion of the image is optionally semitransparent using a
5-bit alpha blend between the input video and the OSD. The OSD
font characters are stored in either an external SPI flash or read
directly into the RAM when instructed or can be loaded in to
the on-chip RAM via the SPI or I2C.
I2C INTERFACE
The ADV7623 supports a 2-wire serial (I2C-compatible) micro-
processor bus driving multiple peripherals. The ADV7623 is
controlled by an external I2C master device, such as a micro-
controller.
OTHER FEATURES
Other features include the following:
•
Fully qualified software low level libraries, driver, and
application
Complete input and output audio support
Programmable interrupt request output pins: INT1, INT2,
and INT_TX
With the inclusion of HDCP 1.4, displays can receive encrypted
video content. The HDMI interface of the ADV7623 allows for
authentication of a video receiver, decryption of encoded data
at the receiver, and renewability of that authentication during
transmission as specified by the HDCP 1.4 protocol. Repeater
support is also offered by the ADV7623.
•
•
•
•
Chip select
Non-HDCP professional variant available
(ADV7623BSTZ-P). No evaluation board is available
for this variant.
Low power consumption: 1.8 V digital core, 1.8 V analog,
and 3.3 V digital input/output, low power power-down
mode, and green PC mode
The HDMI receiver offers advanced audio functionality. It supports
multichannel I2S audio for up to eight channels. It also supports
a 6-DSD channel interface with each channel carrying an over-
sampled 1-bit representation of the audio signal as delivered on
SACD. The ADV7623 can also receive HBR audio packet streams
and output them through the HBR interface in an S/PDIF format
conforming to the IEC 60958 standard. S/PDIF is supported via
the HPD back channel. The receiver also contains an audio mute
controller that can detect a variety of conditions that may result
in audible extraneous noise in the audio output. On detection of
these conditions, the audio data can be ramped to prevent audio
clicks or pops.
•
•
•
Temperature range: 0°C to 70°C
20 mm × 20 mm, Pb-free, 144-lead LQFP
For more detailed product information about the ADV7623,
contact your local Analog Devices sales office.
The ADV7623HDMI receiver incorporates active, programmable
equalization of the HDMI data signals that compensates for the
Rev. D | Page 13 of 16
ADV7623
Data Sheet
OUTLINE DIMENSIONS
22.20
22.00 SQ
21.80
0.75
0.60
0.45
1.60
MAX
109
144
1
108
PIN 1
20.20
20.00 SQ
19.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
0.15
0.05
73
36
SEATING
PLANE
72
37
0.27
0.22
0.17
VIEW A
0.50
BSC
VIEW A
LEAD PITCH
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BFB
Figure 6. 144-Lead Low Profile Quad Flat Package [LQFP]
(ST-144)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Model1
Model Description
HDCP Transceiver
HDCP Transceiver (Reel)
Non-HDCP Transceiver
Package Description
ADV7623BSTZ
ADV7623BSTZ-RL
ADV7623BSTZ-P
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
144-Lead Low Profile Quad Flat Package [LQFP]
144-Lead Low Profile Quad Flat Package [LQFP]
144-Lead Low Profile Quad Flat Package [LQFP]
144-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
ST-144
ST-144
ST-144
ST-144
ADV7623BSTZ-P-RL Non-HDCP Transceiver (Reel)
EVAL-ADV7623EB1Z HDCP Transceiver Evaluation Board
1 Z = RoHS Compliant Part.
Rev. D | Page 14 of 16
Data Sheet
NOTES
ADV7623
Rev. D | Page 15 of 16
ADV7623
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Phillips Semiconductors (now NXP Semiconductors).
HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other
countries.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08302-0-3/13(D)
Rev. D | Page 16 of 16
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