ADSP-21369_技术文档

SHARC^®Processors

a

ADSP-21367/ADSP-21368/ADSP-21369

Code compatible with all other members of the SHARC family

The ADSP-21367/ADSP-21368/ADSP-21369 are available

with a 333 MHz core instruction rate with unique audiocen-

tric peripherals such as the digital audio interface, S/PDIF

transceiver, serial ports, 8-channel asynchronous sample

rate converter, precision clock generators, and more. For

SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—2M bit of on-chip SRAM and 6M bit of on-

chip mask programmable ROM

complete ordering information, see Ordering Guide on

Page 56.

JTAG TEST & EMULATION

CORE PROCESSOR

INSTRUCTION

4 BLOCK OF

ON-CHIP MEMORY

CACHE

TIMER

FLAGS4-15

PWM

32 × 48-BIT

2M BIT RAM

6M BIT ROM

32

DAG2

8 × 4 × 32

DAG1

8 × 4 × 32

PROGRAM

SEQUENCER

ADDR

DATA

EXTERNAL PORT

DATA

7

SDRAM

CONTROLLER

18

3

PM ADDRESS BUS

DM ADDRESS BUS

32

ASYNCHRONOUS

MEMORY INTERFACE

CONTROL

8

64

PM DATA BUS

SHARED MEMORY

24

INTERFACE

ADDRESS

DM DATA BUS

IOA(24)

IOD(32)

DMA

CONTROLLER

PX REGISTER

IOP REGISTER (MEMORY MAPPED)

CONTROL, STATUS, & DATA BUFFERS

PROCESSING

ELEMENT

(PEY)

PROCESSING

ELEMENT

(PEX)

34 CHANNELS

MEMORY-TO-

MEMORY DMA (2)

PRECISION CLOCK

GENERATORS (4)

SERIAL PORTS (8)

SPI PORT (2)

4

UART (2)

GPIO FLAGS/

IRQ/TIMEXP

INPUT DATA PORT/

PDAP

TWO WIRE

INTERFACE

SRC (8 CHANNELS)

SPDIF (Rx/Tx)

TIMERS (3)

DAI PINS

DPI PINS

S

DIGITAL PERIPHERAL INTERFACE

I/O PROCESSOR

DIGITAL AUDIO INTERFACE

20

14

Figure 1. Functional Block Diagram

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Rev. A

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Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADSP-21367/ADSP-21368/ADSP-21369

Digital audio interface (DAI) includes eight serial ports, four

precision clock generators, an input data port, an S/PDIF

transceiver, an 8-channel asynchronous sample rate con-

verter, and a signal routing unit

Digital peripheral interface (DPI) includes three timers, two

UARTs, two SPI ports, and a two wire interface port

Outputs of PCG's C and D can be driven on to DPI pins

Eight dual data line serial ports that operate at up to

50M bits/s on each data line—each has a clock, frame sync,

and two data lines that can be configured as either a

receiver or transmitter pair

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony interfaces

such as H.100/H.110

Up to 16 TDM stream support, each with 128 channels per

frame

Companding selection on a per channel basis in TDM mode

Input data port, configurable as eight channels of serial data

or seven channels of serial data and up to a 20-bit wide

parallel data channel

Signal routing unit provides configurable and flexible con-

nections between all DAI/DPI components

2 muxed flag/IRQ lines

KEY FEATURES—PROCESSOR CORE

At 333 MHz (3 ns) core instruction rate, the processors per-

form 2 GFLOPS/666 MMACS

2M bit on-chip, SRAM (0.75M bit in blocks 0 and 1, and

0.25M bit in blocks 2 and 3) for simultaneous access by the

core processor and DMA

6M bit on-chip, mask-programmable ROM (3M bit in block 0

and 3M bit in block 1)

Dual data address generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single-instruction, multiple-data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution

Code compatibility with other SHARC family members at

the assembly level

Parallelism in buses and computational units allows: single

cycle executions (with or without SIMD) of a multiply

operation, an ALU operation, a dual memory read or

write, and an instruction fetch

Transfers between memory and core at a sustained

6.4G bytes/s bandwidth at 333 MHz core instruction rate

1 muxed flag/timer expired line /MS pin

1 muxed flag/IRQ /MS pin

INPUT/OUTPUT FEATURES

DEDICATED AUDIO COMPONENTS

DMA controller supports:

S/PDIF-compatible digital audio receiver/transmitter sup-

ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards

Left-justified, I²S, or right-justified serial data input with

16-, 18-, 20- or 24-bit word widths (transmitter)

Four independent asynchronous sample rate converters

(SRC). Each converter has separate serial input and output

ports, a de-emphasis filter providing up to –140 dB SNR

performance, stereo sample rate converter (SRC) and sup-

ports left-justified, I²S, TDM, and right-justified modes and

24, 20, 18, and 16 audio data word lengths

34 zero-overhead DMA channels for transfers between

internal memory and a variety of peripherals

32-bit DMA transfers at peripheral clock speed, in parallel

with full-speed processor execution

32-bit wide external port provides glueless connection to

both synchronous (SDRAM) and asynchronous memory

devices

Programmable wait state options: 2 SCLK to 31 SCLK cycles

Delay-line DMA engine maintains circular buffers in exter-

nal memory with tap/offset-based reads

SDRAM accesses at 133 MHz and asynchronous accesses at

66 MHz

Shared-memory support allows multiple DSPs to automat-

ically arbitrate for the bus and gluelessly access a

common memory device

Shared memory interface (ADSP-21368 only) support

provides:

Glueless connection for scalable DSP multiprocessing

architecture

Distributed on-chip bus arbitration for parallel bus

Connect of up to four ADSP-21368 processors and global

memory

Pulse-width modulation provides:

16 PWM outputs configured as four groups of four outputs

supports center-aligned or edge-aligned PWM waveforms

ROM-based security features include:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Dual voltage: 3.3 V I/O, 1.2 V or 1.3 V core

Available in 256-ball SBGA and 208-lead MQFP packages (see

Ordering Guide on Page 56)

Four memory select lines allow multiple external memory

devices

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ADSP-21367/ADSP-21368/ADSP-21369

TABLE OF CONTENTS

Summary ................................................................1

Key Features—Processor Core ..................................2

Input/Output Features ............................................2

Dedicated Audio Components ..................................2

General Description ..................................................4

Core Architecture ..................................................4

Memory Architecture .............................................5

External Memory ...................................................5

Input/Output Features ............................................7

System Design .......................................................9

Development Tools .............................................. 10

Additional Information ......................................... 11

Pin Function Descriptions ........................................ 12

Data Modes ........................................................ 15

Boot Modes ........................................................ 15

Core Instruction Rate to CLKIN Ratio Modes ............. 15

Specifications ......................................................... 16

Operating Conditions ........................................... 16

Electrical Characteristics ........................................ 17

Package Information ............................................ 18

Maximum Power Dissipation ................................. 18

Absolute Maximum Ratings ................................... 18

ESD Sensitivity .................................................... 18

Timing Specifications ........................................... 19

Output Drive Currents .......................................... 47

Test Conditions ................................................... 47

Capacitive Loading ............................................... 47

Thermal Characteristics ........................................ 48

256-Ball SBGA Pinout .............................................. 49

208-Lead MQFP Pinout ............................................ 52

Package Dimensions ................................................ 54

Surface-Mount Design .......................................... 55

Ordering Guide ...................................................... 56

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ADSP-21367/ADSP-21368/ADSP-21369

GENERAL DESCRIPTION

The ADSP-21367/ADSP-21368/ADSP-21369 SHARC proces-

sors are members of the SIMD SHARC family of DSPs that

feature Analog Devices’ Super Harvard Architecture. These pro-

cessors are source code-compatible with the ADSP-2126x and

ADSP-2116x DSPs as well as with first generation ADSP-2106x

SHARC processors in SISD (single-instruction, single-data)

mode. The processors are 32-bit/40-bit floating point processors

optimized for high performance automotive audio applications

with its large on-chip SRAM, and mask-programmable ROM,

multiple internal buses to eliminate I/O bottlenecks, and an

innovative digital audio interface (DAI).

• On-chip mask-programmable ROM (6M bit)

• JTAG test access port

The block diagram of the ADSP-21368 on Page 1 also illustrates

the following architectural features:

• DMA controller

• Eight full-duplex serial ports

• Digital audio interface that includes four precision clock

generators (PCG), an input data port (IDP), an S/PDIF

receiver/transmitter, eight channels asynchronous sample

rate converters, eight serial ports, eight serial interfaces, a

16-bit parallel input port (PDAP), a flexible signal routing

unit (DAI SRU).

As shown in the functional block diagram on Page 1, the

processors use two computational units to deliver a significant

performance increase over the previous SHARC processors on a

range of DSP algorithms. Fabricated in a state-of-the-art, high

speed, CMOS process, the ADSP-21367/ADSP-21368/

ADSP-21369 processors achieve an instruction cycle time of up

to 3.0 ns at 333 MHz. With its SIMD computational hardware,

the processors can perform two GFLOPS running at 333 MHz.

• Digital peripheral interface that includes three timers, an

I²C® interface, two UARTs, two serial peripheral interfaces

(SPI), and a flexible signal routing unit (DPI SRU).

CORE ARCHITECTURE

The ADSP-21367/ADSP-21368/ADSP-21369 are code compati-

ble at the assembly level with the ADSP-2126x, ADSP-21160,

and ADSP-21161, and with the first generation ADSP-2106x

SHARC processors. The ADSP-21367/ADSP-21368/

ADSP-21369 share architectural features with the ADSP-2126x

and ADSP-2116x SIMD SHARC processors, as detailed in the

following sections.

Table 1 shows performance benchmarks for these devices.

Table 1. Processor Benchmarks (at 333 MHz)

Speed

Benchmark Algorithm

(at 333 MHz)

1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs

FIR Filter (per tap)¹

IIR Filter (per biquad)¹

1.5 ns

6.0 ns

SIMD Computational Engine

The processors contain two computational processing elements

that operate as a single-instruction, multiple-data (SIMD)

engine. The processing elements are referred to as PEX and PEY

and each contains an ALU, multiplier, shifter, and register file.

PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. When this mode is

enabled, the same instruction is executed in both processing ele-

ments, but each processing element operates on different data.

This architecture is efficient at executing math intensive DSP

algorithms.

Matrix Multiply (pipelined)

[3×3] × [3×1]

[4×4] × [4×1]

13.5 ns

23.9 ns

Divide (y/×)

10.5 ns

16.3 ns

Inverse Square Root

¹Assumes two files in multichannel SIMD mode.

The ADSP-21367/ADSP-21368/ADSP-21369 continues

SHARC’s industry-leading standards of integration for DSPs,

combining a high performance 32-bit DSP core with integrated,

on-chip system features.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the band-

width between memory and the processing elements. When

using the DAGs to transfer data in SIMD mode, two data values

are transferred with each access of memory or the register file.

The block diagram of the ADSP-21368 on Page 1, illustrates the

following architectural features:

• Two processing elements, each of which comprises an

ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

• Three programmable interval timers with PWM genera-

tion, PWM capture/pulse width measurement, and

external event counter capabilities

• On-chip SRAM (2M bit)

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ADSP-21367/ADSP-21368/ADSP-21369

ALU and multiplier operations occur in both processing ele-

ments. These computation units support IEEE 32-bit single-

precision floating-point, 40-bit extended precision floating-

point, and 32-bit fixed-point data formats.

MEMORY ARCHITECTURE

The ADSP-21367/ADSP-21368/ADSP-21369 processors add

the following architectural features to the SIMD SHARC

family core.

Data Register File

On-Chip Memory

A general-purpose data register file is contained in each pro-

cessing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

register files, combined with the ADSP-2136x enhanced Har-

vard architecture, allow unconstrained data flow between

computation units and internal memory. The registers in PEX

are referred to as R0–R15 and in PEY as S0–S15.

The processors contain two megabits of internal RAM and six

megabits of internal mask-programmable ROM. Each block can

be configured for different combinations of code and data stor-

age (see Table 2 on Page 6). Each memory block supports

single-cycle, independent accesses by the core processor and I/O

processor. The memory architecture, in combination with its

separate on-chip buses, allow two data transfers from the core

and one from the I/O processor, in a single cycle.

Single-Cycle Fetch of Instruction and Four Operands

The SRAM can be configured as a maximum of 64K words of

32-bit data, 128K words of 16-bit data, 42K words of 48-bit

instructions (or 40-bit data), or combinations of different word

sizes up to two megabits. All of the memory can be accessed as

16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point

storage format is supported that effectively doubles the amount

of data that may be stored on-chip. Conversion between the

32-bit floating-point and 16-bit floating-point formats is per-

formed in a single instruction. While each memory block can

store combinations of code and data, accesses are most efficient

when one block stores data using the DM bus for transfers, and

the other block stores instructions and data using the PM bus

for transfers.

The ADSP-21367/ADSP-21368/ADSP-21369 feature an

enhanced Harvard architecture in which the data memory

(DM) bus transfers data and the program memory (PM) bus

transfers both instructions and data (see Figure 1 on Page 1).

With separate program and data memory buses and on-chip

instruction cache, the processors can simultaneously fetch four

operands (two over each data bus) and one instruction (from

the cache), all in a single cycle.

Instruction Cache

The processors include an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full-speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Using the DM bus and PM buses, with one bus dedicated to

each memory block, assures single-cycle execution with two

data transfers. In this case, the instruction must be available in

the cache.

EXTERNAL MEMORY

Data Address Generators with Zero-Overhead Hardware

Circular Buffer Support

The external port provides a high performance, glueless inter-

face to a wide variety of industry-standard memory devices. The

32-bit wide bus may be used to interface to synchronous and/or

asynchronous memory devices through the use of its separate

internal memory controllers. The first is an SDRAM controller

for connection of industry-standard synchronous DRAM

devices and DIMMs (Dual Inline Memory Module), while the

second is an asynchronous memory controller intended to

interface to a variety of memory devices. Four memory select

pins enable up to four separate devices to coexist, supporting

any desired combination of synchronous and asynchronous

device types. NonSDRAM external memory address space is

shown in Table 3.

The ADSP-21367/ADSP-21368/ADSP-21369 have two data

address generators (DAGs). The DAGs are used for indirect

addressing and implementing circular data buffers in hardware.

Circular buffers allow efficient programming of delay lines and

other data structures required in digital signal processing, and

are commonly used in digital filters and Fourier transforms.

The two DAGs contain sufficient registers to allow the creation

of up to 32 circular buffers (16 primary register sets, 16 second-

ary). The DAGs automatically handle address pointer

wraparound, reduce overhead, increase performance, and sim-

plify implementation. Circular buffers can start and end at any

memory location.

SDRAM Controller

Flexible Instruction Set

The SDRAM controller provides an interface of up to four sepa-

rate banks of industry-standard SDRAM devices or DIMMs, at

speeds up to f_SCLK. Fully compliant with the SDRAM standard,

each bank has its own memory select line (MS0–MS3), and can

be configured to contain between 16M bytes and 128M bytes of

memory. SDRAM external memory address space is shown in

Table 4.

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

ADSP-21367/ADSP-21368/ADSP-21369 can conditionally exe-

cute a multiply, an add, and a subtract in both processing

elements while branching and fetching up to four 32-bit values

from memory—all in a single instruction.

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Table 2. Internal Memory Space ¹

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 Bits)

Instruction Word (48 Bits)

Normal Word (32 Bits)

Short Word (16 Bits)

BLOCK 0 ROM (Reserved)

0x0004 0000–0x0004 BFFF

BLOCK 0 ROM (Reserved)

0x0008 0000–0x0008 FFFF

BLOCK 0 ROM (Reserved)

0x0008 0000–0x0009 7FFF

BLOCK 0 ROM (Reserved)

0x0010 0000–0x0012 FFFF

Reserved

0x0004 F000–0x0004 FFFF

0x0009 4000–0x0009 FFFF

0x0009 E000–0x0009 FFFF

0x0013 C000–0x0013 FFFF

BLOCK 0 SRAM

0x0004 C000–0x0004 EFFF

0x0009 0000–0x0009 3FFF

0x0009 8000–0x0009 DFFF

0x0013 0000–0x0013 BFFF

BLOCK 1 ROM (Reserved)

0x0005 0000–0x0005 BFFF

BLOCK 1 ROM (Reserved)

0x000A 0000–0x000A FFFF

BLOCK 1 ROM (Reserved)

0x000A 0000–0x000B 7FFF

BLOCK 1 ROM (Reserved)

0x0014 0000–0x0016 FFFF

Reserved

0x0005 F000–0x0005 FFFF

0x000B 4000–0x000B FFFF

0x000B E000–0x000B FFFF

0x0017 C000–0x0017 FFFF

BLOCK 1 SRAM

0x0005 C000–0x0005 EFFF

0x000B 0000–0x000B 3FFF

0x000B 8000–0x000B DFFF

0x0017 0000–0x0017 BFFF

BLOCK 2 SRAM

0x0006 0000–0x0006 0FFF

0x000C 0000–0x000C 1554

0x000C 0000–0x000C 1FFF

0x0018 0000–0x0018 3FFF

Reserved

0x0006 1000– 0x0006 FFFF

0x000C 1555–0x000C 3FFF

0x000C 2000–0x000D FFFF

0x0018 4000–0x001B FFFF

BLOCK 3 SRAM

0x0007 0000–0x0007 0FFF

0x000E 0000–0x000E 1554

0x000E 0000–0x000E 1FFF

0x001C 0000–0x001C 3FFF

Reserved

0x0007 1000–0x0007 FFFF

0x000E 1555–0x000F FFFF

0x000E 2000–0x000F FFFF

0x001C 4000–0x001F FFFF

¹The ADSP-21368 and ADSP-21369 processors include a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details.

The controller maintains all of the memory banks as a contigu-

ous address space so that the processor sees this as a single

address space, even if different size devices are used in the

different banks.

Table 4. External Memory for SDRAM Addresses

Size in

Bank

Words

Address Range

A set of programmable timing parameters is available to config-

ure the SDRAM banks to support slower memory devices. The

memory banks can be configured as either 32 bits wide for max-

imum performance and bandwidth or 16 bits wide for

minimum device count and lower system cost.

Bank 0

Bank 1

Bank 2

Bank 3

62M

0x0020 0000 – 0x03FF FFFF

0x0400 0000 – 0x07FF FFFF

0x0800 0000 – 0x0BFF FFFF

0x0C00 0000 – 0x0FFF FFFF

64M

The SDRAM controller address, data, clock, and control pins

can drive loads up to 30 pF. For larger memory systems, the

SDRAM controller external buffer timing should be selected

and external buffering should be provided so that the load on

the SDRAM controller pins does not exceed 30 pF.

Asynchronous Controller

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O

devices. Each bank can be independently programmed with dif-

ferent timing parameters, enabling connection to a wide variety

of memory devices including SRAM, ROM, flash, and EPROM,

as well as I/O devices that interface with standard memory con-

trol lines. Bank 0 occupies a 14M word window and banks 1, 2,

and 3 occupy a 16M word window in the processor’s address

space but, if not fully populated, these windows are not made

contiguous by the memory controller logic. The banks can also

be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of

interfacing to a range of memories and I/O devices tailored

either to high performance or to low cost and power.

Table 3. External Memory for NonSDRAM Addresses

Size in

Bank

Words

Address Range

Bank 0

Bank 1

Bank 2

Bank 3

14M

0x0020 0000 – 0x00FF FFFF

0x0400 0000 – 0x04FF FFFF

0x0800 0000 – 0x08FF FFFF

0x0C00 0000 – 0x0CFF FFFF

16M

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The asynchronous memory controller is capable of a maximum

throughput of 264M bytes/s using a 66 MHz external bus speed.

Other features include 8-bit to 32-bit and 16-bit to 32-bit pack-

ing and unpacking, booting from bank select 1, and support for

delay line DMA.

the SPI interface, two for the external port, and two for

memory-to-memory transfers. Programs can be downloaded to

the processors using DMA transfers. Other DMA features

include interrupt generation upon completion of DMA trans-

fers, and DMA chaining for automatic linked DMA transfers.

Delay Line DMA

Shared External Memory

The ADSP-21367/ADSP-21368/ADSP-21369 processors pro-

vide delay line DMA functionality. This allows processor reads

and writes to external delay line buffers (in external memory,

SRAM, or SDRAM) with limited core interaction.

The ADSP-21368 processor supports connecting to common

shared external memory with other ADSP-21368 processors to

create shared external bus processor systems. This support

includes:

• Distributed, on-chip arbitration for the shared external bus

• Fixed and rotating priority bus arbitration

• Bus time-out logic

Digital Audio and Digital Peripheral Interfaces (DAI/DPI)

The digital audio and digital periphal interfaces (DAI and DPI)

provide the ability to connect various peripherals to any of the

DSP’s DAI or DPI pins (DAI_P20–1 and DPI_P14–1).

• Bus lock

Programs make these connections using the signal routing units

(SRU1 and SRU2), shown in Figure 1.

Multiple processors can share the external bus with no addi-

tional arbitration logic. Arbitration logic is included on-chip to

allow the connection of up to four processors.

The SRUs are matrix routing units (or group of multiplexers)

that enable the peripherals provided by the DAI and DPI to be

interconnected under software control. This allows easy use of

the associated peripherals for a much wider variety of applica-

tions by using a larger set of algorithms than is possible with

nonconfigurable signal paths.

Bus arbitration is accomplished through the BR1-4 signals and

the priority scheme for bus arbitration is determined by the set-

ting of the RPBA pin. Table 5 on Page 12 provides descriptions

of the pins used in multiprocessor systems.

INPUT/OUTPUT FEATURES

The DAI and DPI also include eight serial ports, an S/PDIF

receiver/transmitter, four precision clock generators (PCG),

eight channels of synchronous sample rate converters, and an

input data port (IDP). The IDP provides an additional input

path to the processor core, configurable as either eight channels

of I²S serial data or as seven channels plus a single 20-bit wide

synchronous parallel data acquisition port. Each data channel

has its own DMA channel that is independent from the proces-

sor’s serial ports.

The I/O processor provides 34 channels of DMA, as well as an

extensive set of peripherals. These include a 20-pin digital audio

interface which controls:

• Eight serial ports

• S/PDIF receiver/transmitter

• Four precision clock generators

• Four stereo sample rate converters

• Internal data port/parallel data acquisition port

For complete information on using the DAI and DPI, see the

ADSP-21368 SHARC Processor Hardware Reference.

The processors also contain a 14-pin digital peripheral interface

which controls:

Serial Ports

The processors feature eight synchronous serial ports (SPORTs)

that provide an inexpensive interface to a wide variety of digital

and mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and frame sync. The

data lines can be programmed to either transmit or receive and

each data line has a dedicated DMA channel.

• Three general-purpose timers

• Two serial peripheral interfaces

• Two universal asynchronous receiver/transmitters

(UARTs)

• A two-wire interface (I²C-compatible)

DMA Controller

Serial ports are enabled via 16 programmable and simultaneous

receive or transmit pins that support up to 32 transmit or 32

receive channels of audio data when all eight SPORTS are

enabled, or eight full duplex TDM streams of 128 channels

per frame.

The processor’s on-chip DMA controller allows data transfers

without processor intervention. The DMA controller operates

independently and invisibly to the processor core, allowing

DMA operations to occur while the core is simultaneously exe-

cuting its program instructions. DMA transfers can occur

between the processor’s internal memory and its serial ports, the

SPI-compatible (serial peripheral interface) ports, the IDP

(input data port), the parallel data acquisition port (PDAP), or

the UART. Thirty-four channels of DMA are available on the

ADSP-21367/ADSP-21368/ADSP-21369—16 via the serial

ports, eight via the input data port, four for the UARTs, two for

The serial ports operate at a maximum data rate of 50M bits/s.

Serial port data can be automatically transferred to and from

on-chip memory via dedicated DMA channels. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides the two receive signals.

The frame sync and clock are shared.

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ADSP-21367/ADSP-21368/ADSP-21369

Serial ports operate in five modes:

• Standard DSP serial mode

• Multichannel (TDM) mode with support for packed I²S

mode

• I²S mode

• Packed I²S mode

Digital Peripheral Interface (DPI)

The digital peripheral interface provides connections to two

serial peripheral interface ports (SPI), two universal asynchro-

nous receiver-transmitters (UARTs), a two-wire interface

(TWI), 12 flags, and three general-purpose timers.

Serial Peripheral (Compatible) Interface

The processors contain two serial peripheral interface ports

(SPIs). The SPI is an industry-standard synchronous serial link,

enabling the SPI-compatible port to communicate with other

SPI-compatible devices. The SPI consists of two data pins, one

device select pin, and one clock pin. It is a full-duplex synchro-

nous serial interface, supporting both master and slave modes.

The SPI port can operate in a multimaster environment by

interfacing with up to four other SPI-compatible devices, either

acting as a master or slave device. The ADSP-21367/

ADSP-21368/ADSP-21369 SPI-compatible peripheral imple-

mentation also features programmable baud rate and clock

phase and polarities. The SPI-compatible port uses open drain

drivers to support a multimaster configuration and to avoid

data contention.

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Each of the serial ports supports the left-justified sample pair

and I²S protocols (I²S is an industry-standard interface com-

monly used by audio codecs, ADCs, and DACs such as the

Analog Devices AD183x family), with two data pins, allowing

four left-justified sample pair or I²S channels (using two stereo

devices) per serial port, with a maximum of up to 32 I²S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For the left-justified sample pair and I²S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial

ports offer selectable synchronization and transmit modes as

well as optional μ-law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-

nally or externally generated.

UART Port

The processors provide a full-duplex universal asynchronous

receiver/transmitter (UART) port, which is fully compatible

with PC-standard UARTs. The UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. The UART also has multiprocessor communication capa-

bility using 9-bit address detection. This allows it to be used in

multidrop networks through the RS-485 data interface stan-

dard. The UART port also includes support for five data bits to

eight data bits, one stop bit or two stop bits, and none, even, or

odd parity. The UART port supports two modes of operation:

The serial ports also contain frame sync error detection logic

where the serial ports detect frame syncs that arrive early (for

example, frame syncs that arrive while the transmission/recep-

tion of the previous word is occurring). All the serial ports also

share one dedicated error interrupt.

S/PDIF-Compatible Digital Audio Receiver/Transmitter

and Synchronous/Asynchronous Sample Rate Converter

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

The S/PDIF receiver/transmitter has no separate DMA chan-

nels. It receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

receiver/transmitter can be formatted as left-justified, I²S, or

right-justified with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

receiver/transmitter are routed through the signal routing unit

(SRU). They can come from a variety of sources such as the

SPORTs, external pins, the precision clock generators (PCGs),

or the sample rate converters (SRC) and are controlled by the

SRU control registers.

The UART port’s baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f_SCLK/ 1,048,576) to

(f_SCLK/16) bits per second.

The sample rate converter (SRC) contains four SRC blocks and

is the same core as that used in the AD1896 192 kHz stereo

asynchronous sample rate converter and provides up to 128 dB

SNR. The SRC block is used to perform synchronous or asyn-

chronous sample rate conversion across independent stereo

channels, without using internal processor resources. The four

SRC blocks can also be configured to operate together to con-

vert multichannel audio data without phase mismatches.

Finally, the SRC can be used to clean up audio data from jittery

clock sources such as the S/PDIF receiver.

• Supporting data formats from 7 bits to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

Where the 16-bit UART_Divisor comes from the DLH register

(most significant eight bits) and DLL register (least significant

eight bits).

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ADSP-21367/ADSP-21368/ADSP-21369

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

midpoint of the PWM period. In this mode, it is possible to pro-

duce asymmetrical PWM patterns that produce lower harmonic

distortion in three-phase PWM inverters.

Timers

ROM-Based Security

The ADSP-21367/ADSP-21368/ADSP-21369 have a total of

four timers: a core timer that can generate periodic software

interrupts and three general-purpose timers that can generate

periodic interrupts and be independently set to operate in one

of three modes:

The ADSP-21367/ADSP-21368/ADSP-21369 have a ROM secu-

rity feature that provides hardware support for securing user

software code by preventing unauthorized reading from the

internal code when enabled. When using this feature, the pro-

cessor does not boot-load any external code, executing

exclusively from internal SRAM/ROM. Additionally, the pro-

cessor is not freely accessible via the JTAG port. Instead, a

unique 64-bit key, which must be scanned in through the JTAG

or test access port will be assigned to each customer. The device

will ignore a wrong key. Emulation features and external boot

modes are only available after the correct key is scanned.

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

The core timer can be configured to use FLAG3 as a timer

expired signal, and each general purpose timer has one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables all three

general-purpose timers independently.

SYSTEM DESIGN

The following sections provide an introduction to system design

options and power supply issues.

Program Booting

Two-Wire Interface Port (TWI)

The internal memory of the processors can be booted up at sys-

tem power-up from an 8-bit EPROM via the external port, an

SPI master or slave, or an internal boot. Booting is determined

by the boot configuration (BOOT_CFG1–0) pins (see Table 7

on Page 15). Selection of the boot source is controlled via the

SPI as either a master or slave device, or it can immediately

begin executing from ROM.

The TWI is a bidirectional 2-wire, serial bus used to move 8-bit

data while maintaining compliance with the I²C bus protocol.

The TWI master incorporates the following features:

• Simultaneous master and slave operation on multiple

device systems with support for multimaster data

arbitration

• Digital filtering and timed event processing

• 7-bit and 10-bit addressing

Power Supplies

The processors have separate power supply connections for the

• 100K bits/s and 400K bits/s data rates

• Low interrupt rate

internal (V_DDINT), external (V_DDEXT), and analog (A_VDD/A_VSS

)

power supplies. The internal and analog supplies must meet the

1.3 V requirement for the 333 MHz device and 1.2 V for the

266 MHz device. The external supply must meet the 3.3 V

requirement. All external supply pins must be connected to the

same power supply.

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

Note that the analog supply pin (A_VDD) powers the processor’s

internal clock generator PLL. To produce a stable clock, it is rec-

ommended that PCB designs use an external filter circuit for the

A_VDDpin. Place the filter components as close as possible to the

A_VDD/A_VSSpins. For an example circuit, see Figure 2. (A recom-

mended ferrite chip is the muRata BLM18AG102SN1D). To

reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for V_DDINTand GND. Use wide traces

to connect the bypass capacitors to the analog power (A_VDD) and

ground (A_VSS) pins. Note that the A_VDDand A_VSSpins specified in

Figure 2 are inputs to the processor and not the analog ground

plane on the board—the A_VSSpin should connect directly to dig-

ital ground (GND) at the chip.

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period.

This results in PWM patterns that are symmetrical about the

midpoint of the PWM period. In double update mode, a second

updating of the PWM registers is implemented at the

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ADSP-21367/ADSP-21368/ADSP-21369

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

ADSP-213xx

100nF

10nF

1nF

A

V

VDD

DDINT

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

HI-Z FERRITE

BEAD CHIP

A

VSS

• View mixed C/C++ and assembly code (interleaved source

and object information)

LOCATE ALL COMPONENTS

CLOSE TO A AND A PINS

VDD

VSS

• Insert breakpoints

• Set conditional breakpoints on registers, memory,

and stacks

Figure 2. Analog Power (A_VDD) Filter Circuit

• Trace instruction execution

Target Board JTAG Emulator Connector

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the ADSP-21367/

ADSP-21368/ADSP-21369 processors to monitor and control

the target board processor during emulation. Analog Devices

DSP Tools product line of JTAG emulators provides emulation

at full processor speed, allowing inspection and modification of

memory, registers, and processor stacks. The processor’s JTAG

interface ensures that the emulator will not affect target system

loading or timing.

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the SHARC devel-

opment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate “Emulator Hardware User’s Guide.”

• Control how the development tools process inputs and

generate outputs

• Maintain a one-to-one correspondence with the tool’s

command line switches

DEVELOPMENT TOOLS

The processors are supported with a complete set of CROSS-

®

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning, when

developing new application code. The VDK features include

threads, critical and unscheduled regions, semaphores, events,

and device flags. The VDK also supports priority-based, pre-

emptive, cooperative, and time-sliced scheduling approaches. In

addition, the VDK was designed to be scalable. If the application

does not use a specific feature, the support code for that feature

is excluded from the target system.

CORE software and hardware development tools, including

®

Analog Devices emulators and VisualDSP++ development

environment. The same emulator hardware that supports other

SHARC processors also fully emulates the ADSP-21367/ADSP-

21368/ADSP-21369.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to DSP assembly. The SHARC has

architectural features that improve the efficiency of compiled

C/C++ code.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK-based objects, and visualizing the

system state, when debugging an application that uses the VDK.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to nonintrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

VisualDSP++ Component Software Engineering (VCSE) is

Analog Devices’ technology for creating, using, and reusing

software components (independent modules of substantial

functionality) to quickly and reliably assemble software

applications. The user can download components from the

Web, drop them into the application, and publish component

archives from within VisualDSP++. VCSE supports component

implementation in C/C++ or assembly language.

Rev. A

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ADSP-21367/ADSP-21368/ADSP-21369

Use the Expert Linker to visually manipulate the placement of

code and data on the embedded system. View memory utiliza-

tion in a color-coded graphical form, easily move code and data

to different areas of the processor or external memory with a

drag of the mouse and examine runtime stack and heap usage.

The expert linker is fully compatible with the existing linker def-

inition file (LDF), allowing the developer to move between the

graphical and textual environments.

in-circuit programming of the on-board flash device to store

user-specific boot code, enabling the board to run as a stand-

alone unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),

engineers can develop software for the EZ-KIT Lite or any

custom-defined system. Connecting one of Analog Devices

JTAG emulators to the EZ-KIT Lite board enables high speed,

non-intrusive emulation.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the SHARC processor family. Hard-

ware tools include SHARC processor PC plug-in cards. Third-

party software tools include DSP libraries, real-time operating

systems, and block diagram design tools.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the

ADSP-21367/ADSP-21368/ADSP-21369 architecture and func-

tionality. For detailed information on the ADSP-2136x family

core architecture and instruction set, refer to the ADSP-21368

SHARC Processor Hardware Reference and the ADSP-

2136x/ADSP-2137x SHARC Processor Programming Reference.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every

DSP developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG test

access port (TAP) on each JTAG DSP. Nonintrusive in-circuit

emulation is assured by the use of the processor’s JTAG inter-

face—the emulator does not affect target system loading or

timing. The emulator uses the TAP to access the internal fea-

tures of the processor, allowing the developer to load code, set

breakpoints, observe variables, observe memory, and examine

registers. The processor must be halted to send data and com-

mands, but once an operation has been completed by the

emulator, the DSP system is set running at full speed with no

impact on system timing.

To use these emulators, the target board must include a header

that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, signal buffering, signal ter-

mination, and emulator pod logic, see the EE-68: Analog Devices

JTAG Emulation Technical Reference on the Analog Devices

website (www.analog.com)—use site search on “EE-68.” This

document is updated regularly to keep pace with improvements

to emulator support.

Evaluation Kit

®

Analog Devices offers a range of EZ-KIT Lite evaluation plat-

forms to use as a cost effective method to learn more about

developing or prototyping applications with Analog Devices

processors, platforms, and software tools. Each EZ-KIT Lite

includes an evaluation board along with an evaluation suite of

the VisualDSP++ development and debugging environment

with the C/C++ compiler, assembler, and linker. Also included

are sample application programs, power supply, and a USB

cable. All evaluation versions of the software tools are limited

for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the

board to the USB port of the user’s PC, enabling the

VisualDSP++ evaluation suite to emulate the on-board proces-

sor in-circuit. This permits the customer to download, execute,

and debug programs for the EZ-KIT Lite system. It also allows

Rev. A

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ADSP-21367/ADSP-21368/ADSP-21369

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 5:

A = asynchronous, G = ground, I = input, O = output,

O/T = output three-state, P = power supply, S = synchronous,

(A/D) = active drive, (O/D) = open drain, (pd) = pull-down

resistor, (pu) = pull-up resistor.

Table 5. Pin List

State During/

After Reset

Name

Type

(ID = 00x)

Description

ADDR_23–0

O/T (pu)¹

Pulled high/

driven low

External Address. The processors output addresses for external memory and periph-

erals on these pins.

DATA_31–0

I/O (pu)¹

Pulled high/

pulled high

External Data. Data pins can be multiplexed to support external memory interface

data (I/O), the PDAP (I), FLAGS (I/O), and PWM (O). After reset, all DATA pins are in EMIF

mode and FLAG(0-3) pins are in FLAGS mode (default). When configured using the

IDP_PDAP_CTL register, IDP Channel 0 scans the DATA_31–8pins for parallel input data.

DAI _P_20–1

I/O with pro-

Pulled high/

pulled high

Digital Audio Interface. These pins provide the physical interface to the DAI SRU. The

DAI SRU configuration registers define the combination of on-chip audiocentric periph-

eral inputs or outputs connected to the pin, and to the pin’s output enable. The

configuration registers then determines the exact behavior of the pin. Any input or

output signal present in the DAI SRU may be routed to any of these pins. The DAI SRU

provides the connection from the serial ports (8), the SRC module, the S/PDIF module,

input data ports (2), and the precision clock generators (4), to the DAI_P20–1 pins. Pull-

ups can be disabled via the DAI_PIN_PULLUP register.

grammable pu²

DPI _P_14–1

I/O with pro-

Pulled high/

pulled high

Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.

The DPI SRU configuration registers define the combination of on-chip peripheral

inputsoroutputsconnectedtothepinandtothepin’soutputenable.Theconfiguration

registers of these peripherals then determines the exact behavior of the pin. Any input

or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU

provides the connection from the timers (3), SPIs (2), UARTs (2), flags (12) TWI (1), and

general-purpose I/O (9) to the DPI_P14–1 pins. The TWI output is an open-drain

output—so the pins used for I²C data and clock should be connected to logic level 0.

Pull-ups can be disabled via the DPI_PIN_PULLUP register.

grammable pu²

ACK

I (pu)¹

Memory Acknowledge. External devices can deassert ACK (low) to add wait states to

an external memory access. ACK is used by I/O devices, memory controllers, or other

peripherals to hold off completion of an external memory access.

RD

O/T (pu)¹

Pulled high/

driven high

External Port Read Enable. RD is asserted whenever the processors read a word from

external memory.

WR

Pulled high/

driven high

External Port Write Enable. WR is asserted when the processors write a word to

external memory.

SDRAS

SDCAS

SDWE

Pulled high/

driven high

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with other

SDRAM command pins, defines the operation for the SDRAM to perform.

Pulled high/

driven high

SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with

other SDRAM command pins, defines the operation for the SDRAM to perform.

Pulled high/

driven high

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.

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ADSP-21367/ADSP-21368/ADSP-21369

Table 5. Pin List

State During/

After Reset

(ID = 00x)

Name

Type

Description

SDCKE

O/T (pu)¹

Pulled high/

driven high

SDRAM Clock Enable. Connect to SDRAM’s CKE pin. Enables and disables the CLK

signal. For details, see the data sheet supplied with the SDRAM device.

SDA10

O/T (pu)¹

Pulled high/

driven low

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with non-

SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.

SDCLK0

SDCLK1

O/T

High-Z/driving

SDRAM Clock Output 0.

SDRAMClockOutput1. Additional clock for SDRAM devices. For systems with multiple

SDRAM devices, handles the increased clock load requirements, eliminating need of

off-chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated.

MS_0–1

O/T (pu)¹

Pulled high/

driven high

Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the corre-

spondingbanksofexternalmemory.TheMS_3-0linesaredecodedmemoryaddresslines

that change at the same time as the other address lines. When no external memory

access is occurring, the MS_3-0lines are inactive; they are active, however, when a condi-

tional memory access instruction is executed, whether or not the condition is true.

The MS₁pin can be used in EPORT/FLASH boot mode. See the hardware reference for

more information.

FLAG[0]/IRQ0

FLAG[1]/IRQ1

I/O

High-Z/high-Z

FLAG0/Interrupt Request 0.

FLAG1/Interrupt Request 1.

FLAG[2]/IRQ2/

MS₂

I/O with pro-

grammable pu

(for MS mode)

FLAG2/Interrupt Request 2/Memory Select 2.

FLAG[3]/TIMEXP/

MS₃

I/O with pro-

grammable pu

(for MS mode)

High-Z/high-Z

FLAG3/Timer Expired/Memory Select 3.

TDI

I (pu)

O/T

I (pu)

I

Test Data Input (JTAG). Provides serial data for the boundary scan logic.

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Mode Select (JTAG). Used to control the test state machine.

TDO

TMS

TCK

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up, or held low for proper operation of the processor

TRST

I (pu)

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the processor.

EMU

O/T (pu)

I

Emulation Status. Must be connected to the ADSP-21367/ADSP-21368/ADSP-21369

Analog Devices DSP Tools product line of JTAG emulator target board connectors only.

CLK_CFG_1–0

Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See Table 8 for

a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL multiplier

and divider in the PMCTL register at any time after the core comes out of reset.

BOOT_CFG_1–0

I

Boot Configuration Select. These pins select the boot mode for the processor. The

BOOT_CFG pins must be valid before reset is asserted. See Table 7 for a description of

the boot modes.

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Table 5. Pin List

State During/

After Reset

Name

Type

(ID = 00x)

Description

RESET

I

Processor Reset. Resets the processor to a known state. Upon deassertion, there is a

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program

execution from the hardware reset vector address. The RESET input must be asserted

(low) at power-up.

XTAL

O

I

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

CLKIN

Local Clock In. Used with XTAL. CLKIN is the processor’s clock input. It configures the

processors to use either its internal clock generator or an external clock source. Con-

necting the necessary components to CLKIN and XTAL enables the internal clock

generator. Connecting the external clock to CLKIN while leaving XTAL unconnected

configures the processor to use an external clock such as an external clock oscillator.

CLKIN may not be halted, changed, or operated below the specified frequency.

RESETOUT/

CLKOUT

O/T

Driven low/

driven high

Reset Out/Local Clock Out. Reset out provide a 4096 cycle delay that allows the PLL

to lock. This pin can also be configured as a CLKOUT signal to clock synchronous periph-

erals and memory. Thefunctionality can be switchedbetween the PLLoutput clock and

reset out by setting Bit 12 of the PMCTL register. The default is reset out.

BR_4–1

ID_2–0

RPBA

I/O (pu)¹

Pulled high/

pulled high

External Bus Request. Used by the ADSP-21368 processor to arbitrate for bus master-

ship. A processor only drives its own BR_xline (corresponding to the value of its ID2-0

inputs) and monitors all others. In a system with less than four processors, the unused

BR_xpins should be tied high; the processor’s own BR_xline must not be tied high or low

because it is an output.

I (pd)

Processor ID. Determines which bus request (BR_4–1) is used by the ADSP-21368 pro-

cessor. ID = 001 corresponds to BR_1,ID = 010 corresponds to BR₂, and so on. Use

ID = 000 or 001 in single-processor systems. These lines are a system configuration

selection that should be hardwired or only changed at reset. ID = 101,110, and 111 are

reserved.

I (pu)¹

Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for the

ADSP-21368 external bus arbitration is selected. When RPBA is low, fixed priority is

selected. This signal is a system configuration selection which must be set to the same

value on every processor in the system.

¹The pull-up is always enabled on the ADSP-21367 and ADSP-21369 processors. The pull-up on the ADSP-21368 processor is only enabled on the processor with ID_2–0= 00x

²Pull-up can be enabled/disabled, value of pull-up cannot be programmed.

Rev. A

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Page 14 of 56

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

DATA MODES

The upper 32 data pins of the external memory interface are

muxed (using bits in the SYSCTL register) to support the exter-

nal memory interface data (input/output), the PDAP (input

only), the FLAGS (input/output), and the PWM channels (out-

put). Table 6 provides the pin settings.

Table 6. Function of Data Pins

DATA PIN MODE

DATA31–16

DATA15–8

DATA7–0

000

001

010

011

100

101

110

111

EPDATA32–0

FLAGS/PWM15–0¹

EPDATA15–0

FLAGS15–0

FLAGS15–8

EPDATA7–0

PDAP (DATA + CTRL)

EPDATA7–0

FLAGS7–0

Reserved

Three-state all pins

¹These signals can be FLAGS or PWM or a mix of both. However, they can be selected only in groups of four. Their function is determined by the control signals

FLAGS/PWM_SEL. For more information, see the ADSP-21368 SHARC Processor Hardware Reference.

BOOT MODES

Table 7. Boot Mode Selection

BOOT_CFG1–0

Booting Mode

SPI Slave Boot

00

01

10

SPI Master Boot

EPROM/FLASH Boot

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see Timing Specifications and

Figure 4 on Page 19.

Table 8. Core Instruction Rate/CLKIN Ratio Selection

CLK_CFG1–0

Core to CLKIN Ratio

00

01

10

6:1

32:1

16:1

Rev. A

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

SPECIFICATIONS

OPERATING CONDITIONS

333 MHz

Min

266 MHz

Min

Parameter¹Description

Max

Unit

V_DDINT

A_VDD

Internal (Core) Supply Voltage

1.235

3.13

2.0

1.365

1.14

3.13

2.0

1.26

V

Analog (PLL) Supply Voltage

1.365

1.26

V_DDEXT

External (I/O) Supply Voltage

3.47

2

V_IH

High Level Input Voltage @ V_DDEXT= max

Low Level Input Voltage @ V_DDEXT= min

High Level Input Voltage @ V_DDEXT= max

Low Level Input Voltage @ V_DDEXT= min

V_DDEXT+ 0.5

+0.8

V_DDEXT+ 0.5

+0.8

2

V_IL

–0.5

1.74

–0.5

1.74

–0.5

3

V_IH

_

V_DDEXT+ 0.5

+1.19

V_DDEXT+ 0.5

+1.19

CLKIN

3

V_IL

T_J

_CLKIN

Junction Temperature

208-Lead MQFP @ T_AMBIENT0°C to +70°C

256-Ball SBGA @ T_AMBIENT0°C to +70°C

256-Ball SBGA @ T_AMBIENT–40°C to +85°C

0

+120

°C

0

–40

+110

+125

¹Specifications subject to change without notice.

²Applies to input and bidirectional pins: DATAx, ACK, RPBA, BRx, IDx, FLAGx, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, TRST.

³Applies to input pin CLKIN.

Rev. A

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

ELECTRICAL CHARACTERISTICS

Parameter¹

Description

Test Conditions

Min

Typ

Max

Unit

2

V_OH

High Level Output Voltage

Low Level Output Voltage

@ V_DDEXT= min, I_OH= –1.0 mA³

@ V_DDEXT= min, I_OL= 1.0 mA³

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

2.4

V

2

V_OL

0.4

10

V

4, 5

I_IH

High Level Input Current

μA

4, 6, 7

I_IL

Low Level Input Current

10

6

I_IHPD

High Level Input Current Pull-down

Low Level Input Current Pull-up

Three-State Leakage Current

Three-State Leakage Current Pull-up

Supply Current (Internal)

@ V_DDEXT= max, V_IN= 0 V

250

200

10

5

I_ILPU

@ V_DDEXT= max, V_IN= 0 V

8, 9

I_OZH

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

8, 10

I_OZL

10

9

I_OZLPU

@ V_DDEXT= max, V_IN= 0 V

200

11

I_DD

-

t_CCLK= 3.75 ns, V_DDINT= 1.2 V, 25°C

t_CCLK= 3.00 ns, V_DDINT= 1.3 V, 25°C

700

900

mA

INTYP

12

AI_DD

Supply Current (Analog)

Input Capacitance

A_VDD= max

10

mA

pF

13, 14

C_IN

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 1.3 V

4.7

1

Specifications subject to change without notice.

²Applies to output and bidirectional pins: ADDRx, DATAx, RD, WR, MSx, BRx, FLAGx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDCLKx, EMU, TDO,

CLKOUT.

³See Output Drive Currents on Page 47 for typical drive current capabilities.

⁴Applies to input pins without internal pull-ups: BOOT_CFGx, CLK_CFGx, CLKIN, RESET, TCK.

⁵Applies to input pins with internal pull-ups: ACK, RPBA, TMS, TDI, TRST.

⁶Applies to input pins with internal pull-downs: IDx.

⁷Applies to input pins with internal pull-ups disabled: ACK, RPBA.

⁸Applies to three-statable pins without internal pull-ups: FLAGx, SDCLKx, TDO.

⁹Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU.

¹⁰Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10

¹¹See Engineer-to-Engineer Note 299 for further information.

¹²Characterized, but not tested.

¹³Applies to all signal pins.

¹⁴Guaranteed, but not tested.

Rev. A

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

PACKAGE INFORMATION

MAXIMUM POWER DISSIPATION

The information presented in Figure 3 provides details about

the package branding for the ADSP-21367/ADSP-21368/

ADSP-21369 processors. For a complete listing of product avail-

ability, see Ordering Guide on Page 56.

See Engineer-to-Engineer Note (EE-299) for detailed thermal

and power information regarding maximum power dissipation.

For information on package thermal specifications, see Thermal

Characteristics on Page 48.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 10 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

a

ADSP-2136x

tppZ-cc

vvvvvv.x n.n

yyww country_of_origin

S

Table 10. Absolute Maximum Ratings

Figure 3. Typical Package Brand

Parameter

Rating

Internal (Core) Supply Voltage (V_DDINT

)

–0.3 V to +1.5 V

–0.3 V to +4.6 V

–0.5 V to +3.8 V

–0.5 V to V_DDEXT+ 0.5 V

200 pF

Table 9. Package Brand Information

Analog (PLL) Supply Voltage (A_VDD

)

Brand Key

Field Description

Temperature Range

Package Type

External (I/O) Supply Voltage (V_DDEXT

Input Voltage

)

t

pp

Output Voltage Swing

Z

Lead Free Option (optional)

See Ordering Guide

Assembly Lot Code

Silicon Revision

Load Capacitance

cc

Storage Temperature Range

Junction Temperature Under Bias

–65°C to +150°C

125°C

vvvvvv.x

n.n

yyww

Date Code

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADSP-21367/ADSP-21368/ADSP-21369 feature proprietary ESD protection circuitry, permanent

damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Table 11. ADSP-21367/ADSP-21368/ADSP-21369

CLKOUT and CCLK Clock Generation Operation

TIMING SPECIFICATIONS

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, processor core, and

serial ports. During reset, program the ratio between the proces-

sor’s internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG1–0 pins (see Table 8 on Page 15).

To determine switching frequencies for the serial ports, divide

down the internal clock, using the programmable divider con-

trol of each port (DIVx for the serial ports).

Timing

Requirements

Description

Input Clock

Core Clock

Calculation

1/t_CK

CLKIN

CCLK

1/t_CCLK

Table 12. Clock Periods

Timing

Requirements

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL).

This PLL-based clocking minimizes the skew between the sys-

tem clock (CLKIN) signal and the processor’s internal clock.

Description¹

CLKIN Clock Period

t_CK

t_CCLK

(Processor) Core Clock Period

t_PCLK

(Peripheral) Clock Period = 2 × t_CCLK

Serial Port Clock Period = (t_PCLK) × SR

SDRAM Clock Period = (t_CCLK) × SDR

SPI Clock Period = (t_PCLK) × SPIR

Figure 4 shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with

external oscillator or crystal. Note that more ratios are possible

and can be set through software using the power management

control register (PMCTL). For more information, see the

ADSP-2136x/ADSP-2137x SHARC Processor Programming

Reference.

t_SCLK

t_SDCLK

t_SPICLK

¹where:

SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV

bits in DIVx register)

Note the definitions of various clock periods shown in Table 12

which are a function of CLKIN and the appropriate ratio con-

trol shown in Table 11.

SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register

setting)

SPICLK = SPI Clock

SDR = SDRAM-to-Core Clock Ratio (values determined by bits 20–18 of the

PMCTL register)

CCLK

PLLICLK

(CORE CLOCK)

CLKIN

XTAL

OSC

INDIV

÷1, 2

DIVEN

÷2, 4, 8, 16

PCLK

PLLM

÷ 2

XTAL

(PERIPHERAL CLOCK)

SDCLK

(SDRAM CLOCK)

÷ 2, 2.5,

3, 3.5, 4

CLK_CFG [1:0]

(6:1, 16:1, 32:1)

CLKOUT

OR

RSTOUT

RESET

DELAY

Figure 4. Core Clock and System Clock Relationship to CLKIN

Rev. A

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Page 19 of 56

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 39 on Page 47 under Test Conditions for voltage refer-

ence levels.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Rev. A

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Page 20 of 56

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 13.

Table 13. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

RESET Low Before V_DDINT/V_DDEXTOn

V_DDINTOn Before V_DDEXT

0

ns

t_IVDDEVDD

–50

0

10²

+200

ms

μs

1

t_CLKVDD

CLKIN Valid After V_DDINT/V_DDEXTValid

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted

t_CLKRST

t_PLLRST

20

μs

Switching Characteristic

3, 4

t_CORERST

Core Reset Deasserted After RESET Deasserted

4096t_CK+ 2 t_CCLK

¹Valid V_DDINT/V_DDEXTassumes that the supplies are fully ramped to their 1.2 volt rails and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time. Assume

a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate

default states at all I/O pins.

⁴The 4096 cycle count depends on t_srstspecification in Table 15. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles

maximum.

RESET

t_RSTVDD

V

DDINT

t_IVDDEVDD

V

t_CLKVDD

DDEXT

CLKIN

t_CLKRST

CLK_CFG1-0

t_CORERST

t_PLLRST

RSTOUT

Figure 5. Power-Up Sequencing

Rev. A

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Clock Input

Table 14. Clock Input

333 MHz

Max

Parameter

Min

Unit

Timing Requirements

t_CK

CLKIN Period

18¹

8¹

100²

45²

3

ns

ps

t_CKL

t_CKH

t_CKRF

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V to 2.0 V)

CCLK Period

3

t_CCLK

3.0¹

10

4, 5

t_CKJ

CLKIN Jitter Tolerance

–250

+250

¹Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.

²Applies only for CLK_CFG1–0 = 10 and default values for PLL control bits in PMCTL.

³Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t_CCLK

⁴Actual input jitter should be combined with ac specifications for accurate timing analysis.

⁵Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

.

t_CK

CLKIN

t_CKH

t_CKL

Figure 6. Clock Input

Clock Signals

The processors can use an external clock or a crystal. See the

CLKIN pin description in Table 5. Programs can configure the

processor to use its internal clock generator by connecting the

necessary components to CLKIN and XTAL. Figure 7 shows the

component connections used for a crystal operating in funda-

mental mode. Note that the clock rate is achieved using a

20.81 MHz crystal and a PLL multiplier ratio 16:1

(CCLK:CLKIN achieves a clock speed of 333 MHz). To achieve

the full core clock rate, programs need to configure the multi-

plier bits in the PMCTL register.

ADSP-2136x

R1

XTAL

CLKIN

1M⍀ (TYPICAL)

R2

47⍀ (TYPICAL)

C1

22pF

C2

22pF

Y1

24.576MHz

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER.

REFER TO CRYSTAL MANUFACTURER’S SPECIFICATIONS

Figure 7. 333 MHz Operation (Fundamental Mode Crystal)

Rev. A

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Reset

Table 15. Reset

Parameter

Min

Max

Unit

Timing Requirements

1

t_WRST

t_SRST

RESET Pulse Width Low

RESET Setup Before CLKIN Low

4t_CK

8

ns

¹Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable

V_DDand CLKIN (not including startup time of external clock oscillator).

CLKIN

t_SRST

t_WRST

RESET

Figure 8. Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts.

Table 16. Interrupts

Parameter

Min

2 × t_PCLK+2

Max

Unit

Timing Requirement

t_IPW

IRQx Pulse Width

ns

DAI_P20-1

DPI_14

FLAG2

(IRQ2-0)

-1

-0

t_IPW

Figure 9. Interrupts

Rev. A

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (CTIMER).

Table 17. Core Timer

Parameter

Min

Max

Unit

Switching Characteristic

t_WCTIM

CTIMER Pulse Width

4 × t_PCLK– 1

ns

t_WCTIM

FLAG3

(CTIMER)

Figure 10. Core Timer

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in PWM_OUT (pulse-width modulation) mode.

Timer signals are routed to the DPI_P14–1 pins through the

DPI SRU. Therefore, the timing specifications provided below

are valid at the DPI_P14–1 pins.

Table 18. Timer PWM_OUT Timing

Parameter

Min

2 × t_PCLK– 2

Max

2 × (2³¹– 1) × t_PCLK

Unit

Switching Characteristic

t_PWMO

Timer Pulse Width Output

ns

t_PWMO

DPI_P14

(TIMER2

-

1

-0)

Figure 11. Timer PWM_OUT Timing

Rev. A

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Timer WDTH_CAP Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in WDTH_CAP (pulse width count and capture)

mode. Timer signals are routed to the DPI_P14–1 pins through

the DPI SRU. Therefore, the timing specification provided

below are valid at the DPI_P14–1 pins.

Table 19. Timer Width Capture Timing

Parameter

Min

Max

Unit

Switching Characteristic

t_PW

Timer Pulse Width

2 × t_PCLK

2 × (2³¹– 1) × t_PCLK

ns

I

t_PWI

DPI_P14

(TIMER2

-1

-0)

Figure 12. Timer Width Capture Timing

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example, DAI_PB01_I to

DAI_PB02_O).

Table 20. DAI Pin to Pin Routing

Parameter

Min

Max

10

Unit

Timing Requirement

t_DPIO

Delay DAI Pin Input Valid to DAI Output Valid

1.5

ns

DAI_Pn

DPI_Pn

DAI_pm

DPI_Pm

t_DPIO

Figure 13. DAI Pin to Pin Direct Routing

Rev. A

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Page 25 of 56

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 – DAI_P20).

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

Table 21. Precision Clock Generator (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

t_PCGIP

t_STRIG

Input Clock Period

24

ns

PCG Trigger Setup Before Falling

Edge of PCG Input Clock

4.5

t_HTRIG

PCG Trigger Hold After Falling

Edge of PCG Input Clock

3

ns

Switching Characteristics

t_DPCGIO

PCG Output Clock and Frame Sync Active Edge

Delay After PCG Input Clock

2.5

10

ns

t_DTRIGCLK

PCG Output Clock Delay After PCG Trigger

PCG Frame Sync Delay After PCG Trigger

Output Clock Period

2.5 + ((2.5 + D) × t_PCGIP

)

10 + ((2.5 + D) × t_PCGIP)

t_DTRIGFS

2.5 + ((2.5 + D – PH) × t_PCGIP

2 × t_PCGIP– 1

)

10 + ((2.5 + D – PH) × t_PCGIP)

1

t_PCGOW

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21368 Processor,

“Precision Clock Generators” chapter.

¹In normal mode.

t_STRIG

t_HTRIG

DAI_Pn

DPI_Pn

PCG_TRIGx_I

t_PCGIP

DAI_Pm

DPI_Pm

PCG_EXTx_I

(CLKIN)

t_DPCGIO

DAI_Py

DPI_Py

PCG_CLKx_O

t_DTRIGCLK

t_DPCGIO

t_PCGOW

DAI_Pz

DPI_Pz

PCG_FSx_O

t_DTRIGFS

Figure 14. Precision Clock Generator (Direct Pin Routing)

Rev. A

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Flags

The timing specifications provided below apply to the FLAG3–0

and DPI_P14–1 pins, and the serial peripheral interface (SPI).

See Table 5 on Page 12 for more information on flag use.

Table 22. Flags

Parameter

Min

Max

Unit

ns

Timing Requirement

t_FIPW

Switching Characteristic

t_FOPWFLAG3–0 OUT Pulse Width

FLAG3–0 IN Pulse Width

2 × t_PCLK+ 3

2 × t_PCLK– 1.5

ns

DPI_P14

(FLAG3

(DATA31

-1

-0_IN

)

-0)

t_FIPW

DPI_P14

(FLAG3

(DATA31

-

0_OUT

1

-

)

-

0)

t_FOPW

Figure 15. Flags

Rev. A

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

SDRAM Interface Timing (133 MHz SDCLK)

The 133 MHz access speed is for a single processor. When mul-

tiple ADSP-21368 processors are connected in a shared memory

system, the access speed is 100 MHz.

Table 23. SDRAM Interface Timing¹

Parameter

Min

Max

Unit

Timing Requirements

t_SSDAT

t_HSDAT

DATA Setup Before SDCLK

DATA Hold After SDCLK

0.58

1.23

ns

Switching Characteristics

t_SDCLK

t_SDCLKH

t_SDCLKL

t_DCAD

SDCLK Period

7.5

ns

SDCLK Width High

3.65

SDCLK Width Low

Command, ADDR, Data Delay After SDCLK²

Command, ADDR, Data Hold After SDCLK²

Data Disable After SDCLK

4.8

5.3

t_HCAD

1.5

1.6

t_DSDAT

t_ENSDAT

Data Enable After SDCLK

¹For F_CCLK= 333 MHz (SDCLK ratio = 1:2.5).

²Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.

t_SDCLK

t_SDCLKH

SDCLK

t_SSDAT

t_SDCLKL

t_HSDAT

DATA (IN)

t_DCAD

t_DSDAT

t_HCAD

t_ENSDAT

DATA(OUT)

t_DCAD

CMND ADDR

(OUT)

t_HCAD

Figure 16. SDRAM Interface Timing

Rev. A

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

SDRAM Interface Enable/Disable Timing (133 MHz SDCLK)

Table 24. SDRAM Interface Enable/Disable Timing¹

Parameter

Min

Max

Unit

Switching Characteristics

t_DSDC

Command Disable After CLKIN Rise

Command Enable After CLKIN Rise

SDCLK Disable After CLKIN Rise

SDCLK Enable After CLKIN Rise

Address Disable After CLKIN Rise

Address Enable After CLKIN Rise

2 × t_PCLK+ 1

8.5

ns

t_ENSDC

t_DSDCC

t_ENSDCC

t_DSDCA

t_ENSDCA

4.0

3.8

9.2

2 × t_PCLK– 4

4 × t_PCLK

¹For F_CCLK= 333 MHz (SDCLK ratio = 1:2.5).

CLKIN

t_DSDC

t_DSDCC

t_DSDCA

COMMAND

SDCLK

ADDR

t_ENSDC

t_ENSDCC

t_ENSDCA

COMMAND

SDCLK

ADDR

Figure 17. SDRAM Interface Enable/Disable Timing

Rev. A

|

Page 29 of 56

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to memo-

ries. These specifications apply when the processors are the bus

master accessing external memory space in asynchronous access

mode. Note that timing for ACK, DATA, RD, WR, and strobe

timing parameters only apply to asynchronous access mode.

Table 25. Memory Read—Bus Master

Parameter

Min

Max

Unit

Timing Requirements

t_DAD

Address, Selects Delay to Data Valid^{1, 2}

RD Low to Data Valid¹

W+t_SDCLK–5.12

W– 2.9

ns

t_DRLD

t_SDS

Data Setup to RD High

2.2

0

t_HDRH

t_DAAK

t_DSAK

Data Hold from RD High^{3, 4}

ACK Delay from Address, Selects^{2, 5}

ACK Delay from RD Low⁴

t_SDCLK–9.5+ W

W – 7.0

Switching Characteristics

t_DRHA

t_DARL

t_RW

Address Selects Hold After RD High

Address Selects to RD Low²

RH + 0.38

t_SDCLK–3.3

W – 1.2

ns

RD Pulse Width

t_RWR

RD High to WR, RD Low

HI +t_SDCLK– 0.8

W = (number of wait states specified in AMICTLx register) × t_SDCLK

HI =RHC + IC (RHC = number of read hold cycles specified in AMICTLx register) × t_SDCLK

IC = (number of idle cycles specified in AMICTLx register) × t_SDCLK

.

H = (number of hold cycles specified in AMICTLx register) × t_SDCLK

.

¹Data delay/setup: system must meet t_DAD, t_DRLD, or t_SDS.

²The falling edge of MSx is referenced.

³Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.

⁴Data hold: User must meet t_HDAor t_HDRHin asynchronous access mode. See Test Conditions on Page 47 for the calculation of hold times given capacitive and dc loads.

⁵ACK Delay/Setup: User must meet t_DAAK, or t_DSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t_DAAKor t_DSAK

.

ADDRESS

MSx

t_DRHA

t_DARL

t_RW

RD

t_DRLD

t_SDS

t_DAD

t_HDRH

DATA

t_DSAK

t_DAAK

t_RWR

ACK

WR

Figure 18. Memory Read—Bus Master

Rev. A

|

Page 30 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Memory Write—Bus Master

Use these specifications for asynchronous interfacing to memo-

ries. These specifications apply when the processors are the bus

master accessing external memory space in asynchronous access

mode. Note that timing for ACK, DATA, RD, WR, and strobe

timing parameters only apply to asynchronous access mode.

Table 26. Memory Write—Bus Master

Parameter

Min

Max

Unit

Timing Requirements

t_DAAK

t_DSAK

ACK Delay from Address, Selects^{1, 2}

ACK Delay from WR Low ^{1, 3}

t_SDCLK– 9.7 + W

W – 4.9

ns

Switching Characteristics

t_DAWH

t_DAWL

t_WW

Address, Selects to WR Deasserted²

Address, Selects to WR Low²

t_SDCLK– 3.1+ W

t_SDCLK– 2.7

ns

WR Pulse Width

W – 1.3

t_DDWH

t_DWHA

t_DWHD

t_WWR

t_DDWR

t_WDE

Data Setup Before WR High

Address Hold After WR Deasserted

Data Hold After WR Deasserted

WR High to WR, RD Low

t_SDCLK– 3.0+ W

H + 0.15

H + 0.02

t_SDCLK– 1.5+ H

2t_SDCLK– 4.11

t_SDCLK– 3.5

Data Disable Before RD Low

WR Low to Data Enabled

W = (number of wait states specified in AMICTLx register) × t_SDCLK

H = (number of hold cycles specified in AMICTLx register) x t_SDCLK

.

¹ACK Delay/Setup: System must meet t_DAAK, or t_DSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t_DAAKor t_DSAK

²The falling edge of MSx is referenced.

.

³Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.

ADDRESS

MSx

t_DAWH

t_DWHA

t_DAWL

t_WW

WR

t_WWR

t_WDE

t_DDWR

t_DDWH

DATA

t_DSAK

t_DWHD

t_DAAK

ACK

RD

Figure 19. Memory Write—Bus Master

Rev. A

|

Page 31 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Asynchronous Memory Interface (AMI) Enable/Disable

Use these specifications for passing bus mastership between

ADSP-21368 processors (BRx).

Table 27. AMI Enable/Disable

Parameter

Min

Max

Unit

Switching Characteristics

t_ENAMIAC

t_ENAMID

t_DISAMIAC

t_DISAMID

Address/Control Enable After Clock Rise

Data Enable After Clock Rise

4

ns

t_SCLK+ 4

Address/Control Disable After Clock Rise

Data Disable After Clock Rise

8.7

0

t_DISAMIAC

t_DISAMID

CLKIN

ADDR, WR, RD,

MS1-0, DATA

t_ENAMIAC

t_ENAMID

ADDR, WR, RD,

MS1 0, DATA

-

Figure 20. AMI Enable/Disable

Rev. A

|

Page 32 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Shared Memory Bus Request

Use these specifications for passing bus mastership between

ADSP-21368 processors (BRx).

Table 28. Multiprocessor Bus Request

Parameter

Min

Max

Unit

Timing Requirements

t_SBRI

t_HBRI

BRx, Setup Before CLKIN High

BRx, Hold After CLKIN High

9

ns

0.5

Switching Characteristics

t_DBROBRx Delay After CLKIN High

t_HBROBRx Hold After CLKIN High

9

ns

1.0

CLKIN

t_DBRO

t_HBRO

BR_X(OUT)

t_SBRI

t_HBRI

BR_X(IN)

Figure 21. Shared Memory Bus Request

Rev. A

|

Page 33 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Serial Ports

To determine whether communication is possible between two

devices at clock speed n, the following specifications must be

confirmed: 1) frame sync delay and frame sync setup and hold,

2) data delay and data setup and hold, and 3) SCLK width.

Serial port signals (SCLK, FS, data channel A, data channel B)

are routed to the DAI_P20–1 pins using the SRU. Therefore, the

timing specifications provided below are valid at the

DAI_P20–1 pins.

Table 29. Serial Ports—External Clock

Parameter

Min

Max

Unit

Timing Requirements

1

t_SFSE

FS Setup Before SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

2.5

ns

1

t_HFSE

FS Hold After SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

2.5

10

ns

1

t_SDRE

Receive Data Setup Before Receive SCLK

Receive Data Hold After SCLK

SCLK Width

1

t_HDRE

t_SCLKW

t_SCLK

SCLK Period

20

Switching Characteristics

2

t_DFSE

FS Delay After SCLK

(Internally Generated FS in Either Transmit or Receive Mode)

9.5

9.6

ns

2

t_HOFSE

FS Hold After SCLK

(Internally Generated FS in Either Transmit or Receive Mode)

2

ns

2

t_DDTE

t_HDTE

Transmit Data Delay After Transmit SCLK

Transmit Data Hold After Transmit SCLK

¹Referenced to sample edge.

²Referenced to drive edge.

Table 30. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

1

t_SFSI

FS Setup Before SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

7

ns

1

t_HFSI

FS Hold After SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

2.5

7

ns

1

t_SDRI

Receive Data Setup Before SCLK

Receive Data Hold After SCLK

1

t_HDRI

2.5

Switching Characteristics

2

t_DFSI

FS Delay After SCLK (Internally Generated FS in Transmit Mode)

4

ns

2

t_HOFSI

FS Hold After SCLK (Internally Generated FS in Transmit Mode)

FS Delay After SCLK (Internally Generated FS in Receive Mode)

FS Hold After SCLK (Internally Generated FS in Receive Mode)

Transmit Data Delay After SCLK

–1.0

2

t_DFSIR

9

2

t_HOFSIR

2

t_DDTI

3

2

t_HDTI

Transmit Data Hold After SCLK

–1.0

3

t_SCLKIW

Transmit or Receive SCLK Width

2 × t_PCLK– 1.5

2 × t_PCLK

¹Referenced to the sample edge.

²Referenced to drive edge.

³Minimum SPORT divisor register value.

Rev. A

|

Page 34 of 56

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Table 31. Serial Ports—Enable and Three-State

Parameter

Min

2

Max

Unit

Switching Characteristics

1

t_DDTEN

Data Enable from External Transmit SCLK

Data Disable from External Transmit SCLK

Data Enable from Internal Transmit SCLK

ns

1

t_DDTTE

10

1

t_DDTIN

–1

¹Referenced to drive edge.

Table 32. Serial Ports—External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

1

t_DDTLFSE

Data Delay from Late External Transmit FS or External Receive

FS with MCE = 1, MFD = 0

7.75

ns

1

t_DDTENFS

Data Enable for MCE = 1, MFD = 0

0.5

¹The t_DDTLFSEand t_DDTENFSparameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

DAI_P20-1

(SCLK)

t_SFSE/I

t_HFSE/I

DAI_P20

-

1

(FS)

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DAI_P20-1

(DATA CHANNEL A/B)

2ND BIT

t_DDTLFSE

LATE EXTERNAL TRANSMIT FS

DRIVE

SAMPLE

DRIVE

t_HFSE/I

DAI_P20

(SCLK)

-1

t_SFSE/I

DAI_P20

(FS)

-1

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

DAI_P20

(DATA CHANNEL A/B)

-1

2ND BIT

t_DDTLFSE

NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20

-

1 PINS

USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20

-1 PINS.

Figure 22. External Late Frame Sync¹

¹This figure reflects changes made to support left-justified sample pair mode.

Rev. A

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Page 35 of 56

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

DATA RECEIVE—INTERNAL CLOCK

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20

-

1

DAI_P20-1

(SCLK)

t_DFSIR

t_DFSE

t_HFSE

t_HFSI

t_SFSI

t_SFSE

t_HOFSIR

t_HOFSE

DAI_P20

-

1

DAI_P20-1

(FS)

t_HDRE

t_SDRI

t_HDRI

t_SDRE

DAI_P20

(DATA CHANNEL A/B)

-

1

DAI_P20

(DATA CHANNEL A/B)

-1

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

t_SCLKIW

t_SCLKW

DAI_P20

-

1

DAI_P20-1

(SCLK)

t_DFSI

t_DFSE

t_HFSI

t_HOFSI

t_SFSI

t_HOFSE

t_SFSE

t_HFSE

DAI_P20

-

1

DAI_P20-1

(FS)

t_DDTE

t_DDTI

t_HDTE

t_HDTI

DAI_P20-1

(DATA CHANNEL A/B)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

SCLK

DAI_P20-1

SCLK (EXT)

t_DDTEN

t_DDTTE

DAI_P20-1

(DATA CHANNEL A/B)

DRIVE EDGE

DAI_P20-1

SCLK (INT)

t_DDTIN

DAI_P20-1

(DATA CHANNEL A/B)

Figure 23. Serial Ports

Rev. A

|

Page 36 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Input Data Port

The timing requirements for the IDP are given in Table 33. IDP

signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Table 33. IDP

Parameter

Min

Max

Unit

Timing Requirements

1

t_SISFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SDATA Setup Before SCLK Rising Edge

SDATA Hold After SCLK Rising Edge

Clock Width

3.8

2.5

9

ns

1

t_SIHFS

1

t_SISD

1

t_SIHD

t_IDPCLKW

t_IDPCLK

Clock Period

24

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t

IDPCLK

t_IDPCLKW

DAI_P20-1

(SCLK)

t_SISFS

t_SIHFS

DAI_P20-1

(FS)

t_SISD

t_SIHD

DAI_P20

-

1

(SDATA)

Figure 24. IDP Master Timing

Rev. A

|

Page 37 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Reference. Note that the most significant 16 bits of external

PDAP data can be provided through the DATA31–16 pins. The

remaining four bits can only be sourced through DAI_P4–1.

The timing below is valid at the DATA31–16 pins.

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 34. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the IDP, see the IDP

chapter of the ADSP-21368 SHARC Processor Hardware

Table 34. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

1

t_SPCLKEN

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge

PDAP_CLKEN Hold After PDAP_CLK Sample Edge

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge

Clock Width

2.5

3.85

2.5

7.0

24

ns

1

t_HPCLKEN

1

t_PDSD

1

t_PDHD

t_PDCLKW

t_PDCLK

Clock Period

Switching Characteristics

t_PDHLDDDelay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

t_PDSTRBPDAP Strobe Pulse Width

2 × t_PCLK+ 3

2 × t_PCLK– 1

ns

1

Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

SAMPLE EDGE

t_PDCLK

t_PDCLKW

DAI_P20

-1

(PDAP_CLK)

t_SPCLKEN

t_HPCLKEN

DAI_P20-1

(PDAP_CLKEN)

t_PDSD

t_PDHD

DATA

DAI_P20

(PDAP_STROBE)

-1

t_PDSTRB

t_PDHLDD

Figure 25. PDAP Timing

Rev. A

|

Page 38 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Pulse-Width Modulation Generators

Table 35. PWM Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_PWMW

t_PWMP

PWM Output Pulse Width

PWM Output Period

t_PCLK– 2

(2¹⁶– 2) × t_PCLK– 2

(2¹⁶– 1) × t_PCLK– 1.5

ns

2 × t_PCLK– 1.5

t_PWMW

PWM

OUTPUTS

t_PWMP

Figure 26. PWM Timing

Sample Rate Converter—Serial Input Port

The SRC input signals (SCLK, FS, and SDATA) are routed from

the DAI_P20–1 pins using the SRU. Therefore, the timing spec-

ifications provided in Table 36 are valid at the DAI_P20–1 pins.

Table 36. SRC, Serial Input Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SDATA Setup Before SCLK Rising Edge

SDATA Hold After SCLK Rising Edge

Clock Width

4

ns

1

t_SRCHFS

5.5

4

1

t_SRCSD

1

t_SRCHD

t_SRCCLKW

t_SRCCLK

5.5

9

Clock Period

24

1

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

t_SRCCLKW

DAI_P20-1

(SCLK)

t_SRCSFS

t_SRCHFS

DAI_P20-1

(FS)

t_SRCSD

t_SRCHD

DAI_P20

-

1

(SDATA)

Figure 27. SRC Serial Input Port Timing

Rev. A

|

Page 39 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

and delay specification with regard to SCLK. Note that SCLK

rising edge is the sampling edge and the falling edge is the

drive edge.

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and it

should meet setup and hold times with regard to SCLK on the

output port. The serial data output, SDATA, has a hold time

Table 37. SRC, Serial Output Port

Parameter

Min

Max

Unit

Timing Requirements

1

t_SRCSFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

Clock Width

4

ns

1

t_SRCHFS

t_SRCCLKW

t_SRCCLK

5.5

9

Clock Period

24

Switching Characteristics

1

t_SRCTDD

Transmit Data Delay After SCLK Falling Edge

Transmit Data Hold After SCLK Falling Edge

8.9

ns

1

t_SRCTDH

1

DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SRCCLK

t_SRCCLKW

DAI_P20

(SCLK)

-

1

t_SRCSFS

t_SRCHFS

DAI_P20

-

(FS)

t_SRCTDD

DAI_P20

(SDATA)

-

1

t_SRCTDH

Figure 28. SRC Serial Output Port Timing

Rev. A

|

Page 40 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

SPDIF Transmitter—Serial Input Waveforms

SPDIF Transmitter

Figure 29 shows the right-justified mode. LRCLK is HI for the

left channel and LO for the right channel. Data is valid on the

rising edge of SCLK. The MSB is delayed 12-bit clock periods

(in 20-bit output mode) or 16-bit clock periods (in 16-bit output

mode) from an LRCLK transition, so that when there are 64

SCLK periods per LRCLK period, the LSB of the data is right-

justified to the next LRCLK transition.

Serial data input to the SPDIF transmitter can be formatted as

left justified, I²S, or right justified with word widths of 16, 18, 20,

or 24 bits. The following sections provide timing for the

transmitter.

DAI_P20

LRCLK

-

1

RIGHT CHANNEL

LEFT CHANNEL

DAI_P20

SCLK

-

LSB

MSB-1 MSB-2

LSB+2 LSB+1

LSB

MSB MSB-1 MSB-2

LSB+2 LSB+1

LSB

MSB

DAI_P20

SDATA

-

Figure 29. Right-Justified Mode

Figure 30 shows the default I²S-justified mode. LRCLK is LO for

the left channel and HI for the right channel. Data is valid on the

rising edge of SCLK. The MSB is left-justified to an LRCLK

transition but with a single SCLK period delay.

RIGHT CHANNEL

DAI_P20

LRCLK

-

1

LEFT CHANNEL

DAI_P20

SCLK

-

DAI_P20

SDATA

-

MSB

MSB-1 MSB-2

LSB+2 LSB+1 LSB

MSB

MSB-1 MSB-2

LSB+2 LSB+1

LSB

MSB

Figure 30. I²S-Justified Mode

Figure 31 shows the left-justified mode. LRCLK is HI for the left

channel and LO for the right channel. Data is valid on the rising

edge of SCLK. The MSB is left-justified to an LRCLK transition

with no MSB delay.

DAI_P20

LRCLK

-

1

RIGHT CHANNEL

LEFT CHANNEL

DAI_P20

SCLK

-

LSB+2 LSB+1 LSB

MSB

MSB-1 MSB-2

LSB+2

LSB+1

LSB

MSB

MSB-1 MSB-2

MSB MSB+1

DAI_P20

-

SDATA

Figure 31. Left-Justified Mode

Rev. A

|

Page 41 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

SPDIF Transmitter Input Data Timing

The timing requirements for the input port are given in

Table 38. Input signals (SCLK, FS, SDATA) are routed to the

DAI_P20–1 pins using the SRU. Therefore, the timing specifica-

tions provided below are valid at the DAI_P20–1 pins.

Table 38. SPDIF Transmitter Input Data Timing

Parameter

Min

Max

Unit

Timing Requirements

1

t_SISFS

FS Setup Before SCLK Rising Edge

FS Hold After SCLK Rising Edge

SData Setup Before SCLK Rising Edge

SData Hold After SCLK Rising Edge

Clock Width

3

ns

1

t_SIHFS

3

1

t_SISD

3

1

t_SIHD

t_SISCLKW

t_SISCLK

t_SITXCLKW

t_SITXCLK

3

36

80

9

Clock Period

Transmit Clock Width

Transmit Clock Period

20

1

DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

t_SITXCLKW

t_SITXCLK

DAI_P20

-1

(TXCLK)

t_SISCLKW

DAI_P20

-1

(SCLK)

t_SIHFS

t_SISFS

DAI_P20

(FS)

-

1

t_SISD

t_SIHD

DAI_P20

-

(SDATA)

Figure 32. SPDIF Transmitter Input Timing

Oversampling Clock (TxCLK) Switching Characteristics

The SPDIF transmitter has an oversampling clock. This TxCLK

input is divided down to generate the biphase clock.

Table 39. Oversampling Clock (TxCLK) Switching Characteristics

Parameter

Min

Max

147.5

98.4

Unit

MHz

kHz

TxCLK Frequency for TxCLK = 768 × FS

TxCLK Frequency for TxCLK = 512 × FS

TxCLK Frequency for TxCLK = 384 × FS

TxCLK Frequency for TxCLK = 256 × FS

Frame Rate

73.8

49.2

192.0

Rev. A

|

Page 42 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

SPDIF Receiver

The following section describes timing as it relates to the SPDIF

receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 40. SPDIF Receiver Internal Digital PLL Mode Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSI

LRCLK Delay After SCLK

LRCLK Hold After SCLK

5

ns

t_HOFSI

t_DDTI

–2

Transmit Data Delay After SCLK

Transmit Data Hold After SCLK

Transmit SCLK Width

t_HDTI

–2

40

1

t_SCLKIW

¹SCLK frequency is 64 × FS where FS = the frequency of LRCLK.

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

DAI_P20-1

(SCLK)

t_DFSI

t_HOFSI

DAI_P20-1

(FS)

t_DDTI

t_HDTI

DAI_P20-1

(DATA CHANNEL A/B)

Figure 33. SPDIF Receiver Internal Digital PLL Mode Timing

Rev. A

|

Page 43 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

SPI Interface—Master

The processors contain two SPI ports. The primary has dedi-

cated pins and the secondary is available through the DPI. The

timing provided in Table 41 and Table 42 on Page 45 applies

to both.

Table 41. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

t_SSPIDM

t_HSPIDM

Switching Characteristics

Data Input Valid to SPICLK Edge (Data Input Setup Time)

8.2

2

ns

SPICLK Last Sampling Edge to Data Input Not Valid

t_SPICLKM

t_SPICHM

t_SPICLM

t_DDSPIDM

t_HDSPIDM

t_SDSCIM

t_HDSM

Serial Clock Cycle

8 × _TPCLK– 2

4 × t_PCLK– 2

ns

Serial Clock High Period

Serial Clock Low Period

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge

Last SPICLK Edge to FLAG3–0IN High

Sequential Transfer Delay

2.5

2

4 × t_PCLK– 2

4 × t_PCLK– 1

t_SPITDM

FLAG3-0

(OUTPUT)

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICHM

t_DDSPIDM

t_SPICLKM

t_HDSM

t_SPITDM

SPICLK

(CP = 0)

(OUTPUT)

t_SPICLM

SPICLK

(CP = 1)

(OUTPUT)

t_HDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

CPHASE = 1

t_HSPIDM

MISO

MSB

LSB

(INPUT)

VALID

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

MSB

LSB

t_SSPIDM

t_HSPIDM

CPHASE = 0

MSB

VALID

LSB

VALID

MISO

(INPUT)

Figure 34. SPI Master Timing

Rev. A

|

Page 44 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

SPI Interface—Slave

Table 42. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

t_SPICLKS

t_SPICHS

t_SPICLS

t_SDSCO

Serial Clock Cycle

4 × t_PCLK– 2

2 × t_PCLK– 2

ns

Serial Clock High Period

Serial Clock Low Period

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

2 × t_PCLK

ns

t_HDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0

Data Input Valid to SPICLK Edge (Data Input Setup Time)

SPICLK Last Sampling Edge to Data Input Not Valid

SPIDS Deassertion Pulse Width (CPHASE = 0)

2 × t_PCLK

ns

t_SSPIDS

t_HSPIDS

t_SDPPW

2

2 × t_PCLK

Switching Characteristics

t_DSOE

SPIDS Assertion to Data Out Active

0

6.8

9.5

ns

t_DSDHI

t_DDSPIDS

t_HDSPIDS

t_DSOV

SPIDS Deassertion to Data High Impedance

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

SPIDS Assertion to Data Out Valid (CPHASE = 0)

2 × t_PCLK

5 × t_PCLK

SPIDS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLKS

t_HDS

t_SDPPW

SPICLK

(CP = 0)

(INPUT)

t_SPICLS

t_{SDSC O}

t_SPICHS

SPICLK

(CP = 1)

(INPUT)

t_{DSD HI}

t_{HD SPID S}

t_DDSPIDS

t_DSOE

t_{D DSPIDS}

MISO

(OUTPUT)

MSB

LSB

t_{HSPID S}

CPHASE = 1

t_SSPIDS

MOSI

(INPUT)

MSB VALID

LSB VALID

t_DSOV

t_DSOE

t_{HD SPID S}

t_DDSPIDS

t_DSDHI

MISO

(OUTPUT)

LSB

MSB

t_{H SPID S}

CPHASE = 0

t_SSPIDS

MOSI

MSB VALID

LSB VALID

(INPUT)

Figure 35. SPI Slave Timing

Rev. A

|

Page 45 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

JTAG Test Access Port and Emulation

Table 43. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

t_CK

5

ns

t_STAP

t_HTAP

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High

System Inputs Hold After TCK High

TRST Pulse Width

6

1

t_SSYS

7

1

t_HSYS

t_TRSTW

Switching Characteristics

t_DTDOTDO Delay from TCK Low

System Outputs Delay After TCK Low

18

4t_CK

7

ns

2

t_DSYS

t_CK÷ 2 + 7

¹System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.

²System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 36. IEEE 1149.1 JTAG Test Access Port

Rev. A

|

Page 46 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

OUTPUT DRIVE CURRENTS

Figure 37 shows typical I-V characteristics for the output driv-

ers of the ADSP-21367/ADSP-21368/ADSP-21369. The curves

represent the current drive capability of the output drivers as a

function of output voltage.

INPUT

OR

OUTPUT

1.5V

Figure 39. Voltage Reference Levels for AC Measurements

40

CAPACITIVE LOADING

V_OH

30

3.3V, 25°C

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 38). Figure 42 shows graphically

how output delays and holds vary with load capacitance. The

graphs of Figure 40, Figure 41, and Figure 42 may not be linear

outside the ranges shown for Typical Output Delay vs. Load

Capacitance and Typical Output Rise Time (20% to 80%,

V = Min) vs. Load Capacitance.

20

3.47V, -45°C

10

3.11V, 125°C

0

-

10

20

30

40

3.11V, 125°C

-

3.3V, 25°C

12

10

V_OL

-

3.47V,

1.0

-

45°C

-

0

0.5

1.5

2.0

2.5

3.0

3.5

RISE

y = 0.0467x + 1.6323

SWEEP (V_DDEXT) VOLTAGE (V)

FALL

8

Figure 37. Typical Drive at Junction temperature

6

TEST CONDITIONS

4

y = 0.045x + 1.524

The ac signal specifications (timing parameters) appear in

Table 15 on Page 23 through Table 43 on Page 46. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 39.

2

0

50

100

150

200

250

0

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 39. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

LOAD CAPACITANCE (pF)

Figure 40. Typical Output Rise/Fall Time (20% to 80%,

_DDEXT= Max)

V

12

10

I_OL

RISE

y = 0.049x + 1.5105

FALL

8

6

50⍀

TO

OUTPUT

1.5V

+

y = 0.0482x + 1.4604

30pF

4

I_OH

2

0

50

100

150

200

250

Figure 38. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

LOAD CAPACITANCE (pF)

Figure 41. Typical Output Rise/Fall Time (20% to 80%,

V_DDEXT= Min)

Rev. A

|

Page 47 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Values of θ_JBare provided for package comparison and PCB

design considerations. Note that the thermal characteristics val-

ues provided in Table 44 and Table 45 are modeled values.

10

8

Table 44. Thermal Characteristics for 256-Ball SBGA

Y = 0.0488x

-1.5923

6

4

Parameter

θ_JA

Condition

Typical

12.5

10.6

9.9

Unit

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

°C/W

θ_JMA

θ_JC

2

0

0.7

θ_JB

5.3

-

2

4

Ψ_JT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.3

-

Ψ_JMT

0.3

0

50

100

150

200

0.3

LOAD CAPACITANCE (pF)

Table 45. Thermal Characteristics for 208-Lead MQFP

Figure 42. Typical Output Delay or Hold vs. Load Capacitance

(at Junction Temperature)

Parameter

θ_JA

Condition

Typical

25.0

22.5

21.6

9.6

Unit

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

°C/W

THERMAL CHARACTERISTICS

θ_JMA

The ADSP-21367/ADSP-21368/ADSP-21369 processors are

rated for performance over the temperature range specified in

Operating Conditions on Page 16.

θ_JMA

θ_JC

Ψ_JT

Airflow = 0 m/s

Airflow = 1 m/s

Airflow = 2 m/s

0.7

Table 44 and Table 45 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-to-

board measurement complies with JESD51-8. Test board design

complies with JEDEC standard JESD51-9 (SBGA) and

JESD51-7 (MQFP). The junction-to-case measurement com-

plies with MIL-STD-883. All measurements use a 2S2P JEDEC

test board.

Ψ_JMT

0.8

0.9

To determine the junction temperature of the device while on

the application PCB, use:

T_J= T_TOP+ (Ψ_JT× P_D)

where:

T_J= junction temperature (°C)

T

_TOP= case temperature (°C) measured at the top center of the

package

Ψ_JT= junction-to-top (of package) characterization parameter

is the typical value from Table 44 and Table 45.

P_D= power dissipation (see EE Note EE-299)

Values of θ_JAare provided for package comparison and PCB

design considerations. θ_JAcan be used for a first-order approxi-

mation of T_Jby the equation:

T_J= T_A+ (θ_JA× P_D)

where:

T_A= ambient temperature (°C)

Values of θ_JCare provided for package comparison and PCB

design considerations when an external heat sink is required.

This is only applicable when a heat sink is used.

Rev. A

|

Page 48 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

256-BALL SBGA PINOUT

Table 46. 256-Ball SBGA Pin Assignment (Numerically by Ball Number)

Ball No. Signal

Ball No.

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

F01

F02

F03

F04

F17

F18

F19

F20

K01

K02

K03

K04

Signal

DAI5

Ball No.

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

G01

G02

G03

G04

G17

G18

G19

G20

L01

Signal

DAI9

Ball No.

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

H01

H02

H03

H04

H17

H18

H19

H20

M01

M02

M03

M04

Signal

DAI10

DAI6

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

E01

E02

E03

E04

E17

E18

E19

E20

J01

NC

TDI

SDCLK1

TRST

DAI7

TMS

GND

CLK_CFG0

CLK_CFG1

EMU

TCK

V_DDEXT

GND

V_DDEXT

GND

BOOT_CFG_0

BOOT_CFG_1

TDO

GND

V_DDEXT

V_DDINT

GND

DAI4

V_DDINT

DAI1

DAI3

GND

DPI14

DPI12

DPI10

DPI9

DAI2

GND

V_DDEXT

V_DDINT

GND

DPI13

DPI11

DPI8

V_DDINT

GND

V_DDEXT

V_DDINT

GND

DPI7

DPI5

V_DDINT

DPI6

DPI4

GND

DPI3

DPI1

GND

V_DDEXT

GND

DPI2

RESET

DATA30

DATA29

DATA28

NC

V_DDINT

CLKOUT

DATA31

NC

V_DDINT

V_DDEXT

GND

V_DDINT

DATA27

NC/RPBA¹

DAI15

DAI13

GND

DATA26

DATA24

DAI17

DAI16

V_DDINT

NC

DAI11

DAI8

DAI14

DAI12

GND

V_DDINT

GND

V_DDEXT

V_DDINT

GND

V_DDEXT

GND

V_DDINT

DATA25

DATA23

DAI19

DAI18

GND

GND/ID2¹

DATA21

FLAG0

DAI20

GND

DATA22

DATA20

FLAG2

FLAG1

V_DDINT

DATA19

DATA18

ACK

J02

L02

FLAG3

GND

J03

L03

J04

GND

V_DDEXT

L04

V_DDINT

GND

Rev. A

|

Page 49 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Table 46. 256-Ball SBGA Pin Assignment (Numerically by Ball Number) (Continued)

Ball No. Signal

Ball No.

K17

K18

K19

K20

P01

P02

P03

P04

P17

P18

P19

P20

V01

V02

V03

V04

V05

V06

V07

V08

V09

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

Signal

V_DDINT

Ball No.

L17

Signal

V_DDINT

Ball No.

M17

M18

M19

M20

T01

T02

T03

T04

T17

T18

T19

T20

Y01

Y02

Y03

Y04

Y05

Y06

Y07

Y08

Y09

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Signal

V_DDEXT

J17

GND

J18

GND

V_DDINT

L18

V_DDINT

GND

J19

GND/ID1¹

DATA17

RD

GND/ID0¹

DATA16

SDA10

WR

L19

DATA15

DATA14

SDWE

DATA12

DATA13

SDCKE

SDCAS

GND

J20

L20

N01

N02

N03

N04

N17

N18

N19

N20

U01

U02

U03

U04

U05

U06

U07

U08

U09

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

R01

SDCLK0

GND

R02

SDRAS

GND

V_DDINT

R03

V_DDEXT

GND

V_DDINT

R04

GND

V_DDEXT

V_DDINT

R17

V_DDEXT

GND

V_DDINT

R18

GND

DATA11

DATA10

MS0

DATA8

DATA9

ADDR22

ADDR23

V_DDINT

R19

DATA6

DATA7

GND

DATA5

DATA4

GND

R20

W01

W02

W03

W04

W05

W06

W07

W08

W09

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

MS1

ADDR21

ADDR19

ADDR20

ADDR17

ADDR16

ADDR15

ADDR14

A_VDD

NC

V_DDINT

NC

GND

ADDR18

NC/BR1¹

NC/BR2¹

XTAL2

CLKIN

NC

V_DDEXT

GND

V_DDEXT

V_DDINT

GND

V_DDINT

V_DDEXT

GND

A_VSS

NC

V_DDEXT

V_DDINT

GND

ADDR13

ADDR12

ADDR10

ADDR8

ADDR5

ADDR4

ADDR1

ADDR2

ADDR0

NC

NC/BR3¹

NC/BR4¹

ADDR11

ADDR9

ADDR7

ADDR6

ADDR3

GND

V_DDINT

V_DDEXT

V_DDINT

V_DDEXT

GND

V_DDINT

V_DDEXT

V_DDINT

GND

V_DDINT

GND

DATA0

DATA2

DATA1

DATA3

GND

NC

¹Applies to ADSP-21368 models only.

Rev. A

|

Page 50 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Figure 43 shows the bottom view of the SBGA ball configura-

tion. Figure 44 shows the top view of the SBGA ball

configuration.

2

4

6

8

10

12

14

16

18

20

1

3

5

7

9

11

13

15

17

19

A

B

C

D

E

F

20

18

16

14

12

10

8

6

4

2

5

3

1

19

17

15

13

11

9

7

A

B

C

D

E

F

G

H

J

TOP

VIEW

K

L

M

N

P

R

T

G

H

J

BOTTOM

VIEW

K

L

U

V

W

Y

M

N

P

R

T

U

V

W

Y

KEY

A

VSS

V

VDD

DDINT

DDEXT

GND

I/O SIGNALS

NO CONNECT

KEY

A_VDD

A_VSS

V_DDINT

I/O SIGNALS

V_DDEXT

GND

Figure 44. 256-Ball SBGA Ball Configuration (Top View)

NO CONNECT

Figure 43. 256-Ball SBGA Ball Configuration (Bottom View)

Rev. A

|

Page 51 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

208-LEAD MQFP PINOUT

Table 47. 208-Lead MQFP Pin Assignment (Numerically by Lead Number)

Pin No.

1

Signal

V_DD

Pin No.

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

Signal

V_DD

Pin No.

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

Signal

V_DD

Pin No.

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

Signal

V_DD

2

DATA28

DATA27

GND

V_DD

3

V_DDEXT

SDCAS

SDRAS

SDCKE

SDWE

WR

GND

V_DD

4

ADDR0

ADDR2

ADDR1

ADDR4

ADDR3

ADDR5

GND

5

V_DDEXT

V_DD

6

DATA26

DATA25

DATA24

DATA23

GND

V_DD

7

TDI

8

TRST

TCK

9

SDA10

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

GND

V_DD

V_DDEXT

SDCLK0

GND

DATA22

DATA21

DATA20

V_DDEXT

GND

TMS

V_DDEXT

CLK_CFG0

BOOT_CFG0

CLK_CFG1

EMU

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

GND

V_DD

RD

GND

ACK

DATA19

DATA18

V_DD

FLAG3

FLAG2

FLAG1

FLAG0

DAI20

GND

BOOT_CFG1

TDO

DAI4

DAI2

DAI3

DAI1

V_DDEXT

GND

V_DD

GND

V_DD

DATA17

V_DD

GND

V_DDEXT

GND

ADDR11

ADDR12

ADDR13

GND

V_DD

GND

V_DDEXT

DAI19

DAI18

DAI17

DAI16

DAI15

DAI14

DAI13

DAI12

V_DD

DATA16

DATA15

DATA14

DATA13

DATA12

V_DDEXT

GND

DPI14

DPI13

DPI12

DPI11

DPI10

DPI9

V_DD

AVSS

AVDD

GND

CLKIN

XTAL2

V_DDEXT

GND

V_DD

DPI8

GND

DPI7

DATA11

DATA10

DATA9

DATA8

DATA7

DATA6

V_DDEXT

V_DD

V_DDEXT

GND

V_DDEXT

GND

V_DD

ADDR14

GND

V_DD

V_DDEXT

GND

DPI6

ADDR15

ADDR16

ADDR17

ADDR18

GND

DAI11

DAI10

DAI8

DPI5

DPI4

GND

DAI9

DPI3

V_DD

DAI6

DPI1

DATA4

V_DDEXT

DAI7

DPI2

Rev. A

|

Page 52 of 56

|

August 2006

ADSP-21367/ADSP-21368/ADSP-21369

Table 47. 208-Lead MQFP Pin Assignment (Numerically by Lead Number) (Continued)

Pin No.

45

Signal

DATA5

DATA2

DATA3

DATA0

DATA1

V_DDEXT

Pin No.

97

Signal

ADDR19

ADDR20

ADDR21

ADDR23

ADDR22

MS1

Pin No.

149

Signal

DAI5

V_DDEXT

GND

V_DD

Pin No.

201

Signal

CLKOUT

RESET

V_DDEXT

46

98

150

202

47

99

151

203

48

100

101

102

103

104

152

204

GND

49

153

GND

V_DD

205

DATA30

DATA31

DATA29

V_DD

50

154

206

51

GND

MS0

155

GND

V_DD

207

52

V_DD

156

208

Rev. A

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

PACKAGE DIMENSIONS

The ADSP-21367/ADSP-21368/ADSP-21369 processors are

available in 256-ball lead-free and leaded SBGA, and 208-lead

lead-free MQFP packages.

30.85

30.60 SQ

30.35

0.75

4.10

0.60

MAX

0.45

208

157

156

1

SEATING

PLANE

PIN 1 INDICATOR

28.20

28.00 SQ

27.80

TOP VIEW

(PINS DOWN)

3.60

3.40

3.20

VIEW A

105

104

52

0.20

0.09

53

0.50

BSC

(LEAD PITCH)

0.27

0.17

0.50

0.25

0.08 MAX (LEAD

COPLANARITY)

(LEAD WIDTH)

VIEW A

ROTATED 90° CCW

NOTES:

1. THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL

POSITION WHEN MEASURED IN THE LATERAL DIRECTION.

2. CENTER DIMENSIONS ARE NOMINAL.

3. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD

MS-029, FA-1.

Figure 45. 208-Lead MQFP (S-208-2)

Rev. A

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

A1 CORNER

INDEX AREA

20 18 16 14 12 10

19 17 15 13 11

8

6

4

2

9

7

5

3

1

A

B

C

D

E

F

A1 BALL

INDICATOR

G

H

J

K

L

BOTTOM

VIEW

27.00

BSC SQ

TOP VIEW

M

N

P

R

T

U

V

W

Y

24.13

REF SQ

DETAIL A

1.00

0.80

0.60

1.27

NOM

1.70 MAX

DETAIL A

0.70

0.60

0.50

0.10

MIN

0.20

COPLANARITY

SEATING

PLANE

0.90

0.75

0.60

BALL

DIAMETER

0.25 MIN 4ϫ

DIMENSIONS ARE IN MILLIMETERS AND COMPLY

WITH JEDEC STANDARDS MO-192-BAL-2.

Figure 46. 256-Ball SBGA, Thermally Enhanced (BP-256)

SURFACE-MOUNT DESIGN

Table 48 is provided as an aide to PCB design. For industry-

standard design recommendations, refer to IPC-7351, Generic

Requirements for Surface-Mount Design and Land Pattern

Standard.

Table 48. SBGA Data for Use with Surface-Mount Design

Package

Ball Attach Type

Solder Mask Opening

Ball Pad Size

256-Lead Ball Grid Array SBGA

(BP-256)

Solder Mask Defined (SMD)

0.63

0.73

Rev. A

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August 2006

ADSP-21367/ADSP-21368/ADSP-21369

ORDERING GUIDE

Operating

Voltage

Internal/External Description

Temperature

Range ¹

Instruction On-Chip

Rate

Package

Option

Part Number

SRAM

2M bit

ROM

ADSP-21367KSZ-1A^{2, 3}

ADSP-21367KBP-2A³

ADSP-21367KBPZ-2A^{2, 3}

ADSP-21367BBP-2A

ADSP-21367BBPZ-2A²

ADSP-21368KBP-2A

ADSP-21368KBPZ-2A²

ADSP-21368BBP-2A

ADSP-21368BBPZ-2A²

ADSP-21369KSZ-1A²

ADSP-21369KBP-2A

ADSP-21369KBPZ-2A²

ADSP-21369BBP-2A

ADSP-21369BBPZ-2A²

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

266 MHz

333 MHz

266 MHz

333 MHz

6M bit

1.2 V/3.3 V

1.3 V/3.3 V

1.2 V/3.3 V

1.3 V/3.3 V

208-Lead MQFP S-208-2

256-Ball SBGA

BP-256

208-Lead MQFP S-208-2

256-Ball SBGA

BP-256

¹Referenced temperature is ambient temperature.

²Z = Pb-free part.

³Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at

www.analog.com/SHARC.

registered trademarks are the property of their respective owners.

D05267-0-8/06(A)

Rev. A

|

Page 56 of 56

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August 2006


型号：	ADSP-21369
厂家：	ADI
描述：	SHARC Processors SHARC处理器
文件：	总56页 (文件大小：1696K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21369 [ADI]

相关型号：

ADSP-21369BBP-2A

ADSP-21369BBPZ-2A

ADSP-21369BSWZ-1A

ADSP-21369BSWZ-2A

ADSP-21369KBP-2A

ADSP-21369KBP-3A

ADSP-21369KBP-ENG

ADSP-21369KBPZ-2A

ADSP-21369KBPZ-3A

ADSP-21369KBPZ-ENG

ADSP-21369KBPZ-X

ADSP-21369KSWZ-1A