ADSP-21369KBP-3A_技术文档

SHARC^®Processor

Data Sheet Addendum

a

Preliminary Technical Data

SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

ADSP-21367/ADSP-21368/ADSP-21369

sample rate converter, precision clock generators, and

more. For complete ordering information, see Ordering

Guide on Page 11.

At 400 MHz (2.5 ns) core instruction rate, the processors per-

form 2.4 GFLOPS/800 MMACS

Transfers between memory and core at a sustained

6.4G bytes/s bandwidth at 400 MHz core instruction rate

On-chip memory—2M bit of on-chip SRAM and 6M bit of on-

chip mask programmable ROM

400 MHz maximum core clock frequency

1.3 V core V_DD/3.3 V I/O

Code compatible with all other members of the SHARC

family

The ADSP-21367/ADSP-21368/ADSP-21369 are available

with a 400 MHz core instruction rate with unique audio-

centric peripherals such as the digital audio interface,

S/PDIF transceiver, serial ports, 8-channel asynchronous

GENERAL DESCRIPTION

This data sheet addendum introduces the 400 MHz ADSP-21367/ADSP-21368/ADSP-21369 SHARC processors. This addendum pro-

vides the frequency benchmark, as well as ac and dc specifications that differ from the 333 MHz ADSP-21367/ADSP-21368/ADSP-21369

SHARC processors. All other specifications and timing data as well as package information for these devices can be found in the

ADSP-21367/ADSP-21368/ADSP-21369 SHARC Processor Data Sheet, Rev A. The products listed in the addendum are engineering

grade and have not been fully characterized. For complete ordering information, see the Ordering Guide on Page 11.

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum

Preliminary Technical Data

Table 1 shows performance benchmarks for these devices.

TABLE OF CONTENTS

Summary ................................................................1

General Description ..................................................1

Specifications ...........................................................3

Operating Conditions .............................................3

Electrical Characteristics ..........................................3

Timing Specifications .............................................4

Output Drive Currents .......................................... 10

Capacitive Loading ............................................... 10

Ordering Guide ...................................................... 11

Table 1. Processor Benchmarks (at 400 MHz)

Benchmark Algorithm

Speed (at 400 MHz)

1024 Point Complex FFT (Radix 4, with 23.2 μs

reversal)

FIR Filter (per tap)¹

IIR Filter (per biquad)¹

1.25 ns

5.0 ns

Matrix Multiply (pipelined)

[3×3] × [3×1]

[4×4] × [4×1]

11.25 ns

20.0 ns

PERFORMANCE BENCHMARKS

Divide (y/×)

8.75 ns

13.5 ns

The processors use two computational units to deliver a signifi-

cant performance increase over the previous SHARC processors

on a range of DSP algorithms. Fabricated in a state-of-the-art,

high speed, CMOS process, the ADSP-21367/ADSP-

21368/ADSP-21369 processors achieve an instruction cycle

time of up to 2.5 ns at 400 MHz. With its SIMD computational

hardware, the processors can perform 2.4 GFLOPS running at

400 MHz.

Inverse Square Root

¹Assumes two files in multichannel SIMD mode.

POWER SUPPLIES

The processors have separate power supply connections for the

internal (V_DDINT), external (V_DDEXT), and analog (A_VDD/A_VSS

power supplies. The internal and analog supplies must meet the

1.3 V requirement for the 400 MHz device. The external supply

must meet the 3.3 V requirement. All external supply pins must

be connected to the same power supply.

)

Rev. PrA

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Page 2 of 12 | March 2007

Preliminary Technical Data

ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum

SPECIFICATIONS

OPERATING CONDITIONS

Parameter¹

Description

Min

Max

Unit

V_DDINT

A_VDD

Internal (Core) Supply Voltage

1.25

3.13

2.0

1.35

V

°C

Analog (PLL) Supply Voltage

1.35

V_DDEXT

External (I/O) Supply Voltage

3.47

2

V_IH

High Level Input Voltage @ V_DDEXT= max

Low Level Input Voltage @ V_DDEXT= min

High Level Input Voltage @ V_DDEXT= max

Low Level Input Voltage @ V_DDEXT= min

Junction Temperature, 256-Ball SBGA @ T_AMBIENT0°C to +70°C

V_DDEXT+ 0.5

+0.8

2

V_IL

–0.5

1.74

–0.5

0

3

V_IH

_

V_DDEXT+ 0.5

+1.1

CLKIN

3

V_IL

T_J

_CLKIN

+105

¹Specifications subject to change without notice.

²Applies to input and bidirectional pins: DATAx, ACK, RPBA, BRx, IDx, FLAGx, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RESET, TCK, TMS, TDI, TRST.

³Applies to input pin CLKIN.

ELECTRICAL CHARACTERISTICS

Parameter¹

Description

Test Conditions

Min

Typ

Max

Unit

2

V_OH

High Level Output Voltage

Low Level Output Voltage

High Level Input Current

@ V_DDEXT= min, I_OH= –1.0 mA³

@ V_DDEXT= min, I_OL= 1.0 mA³

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

2.4

V

2

V_OL

0.4

10

V

4, 5

I_IH

μA

A

4, 6, 7

I_IL

Low Level Input Current

10

6

I_IHPD

High Level Input Current Pull-down

Low Level Input Current Pull-up

Three-State Leakage Current

Three-State Leakage Current Pull-up

Supply Current (Internal)

@ V_DDEXT= max, V_IN= 0 V

250

200

10

5

I_ILPU

@ V_DDEXT= max, V_IN= 0 V

8, 9

I_OZH

@ V_DDEXT= max, V_IN= V_DDEXTmax

@ V_DDEXT= max, V_IN= 0 V

8, 10

I_OZL

10

9

I_OZLPU

@ V_DDEXT= max, V_IN= 0 V

200

11

I_DD

-

t_CCLK= 2.5 ns, V_DDINT= 1.3 V, 25°C

A_VDD= max

1.4

INTYP

12

AI_DD

Supply Current (Analog)

10

mA

pF

13, 14

C_IN

Input Capacitance

f_IN= 1 MHz, T_CASE= 25°C, V_IN= 1.3 V

4.7

1

Specifications subject to change without notice.

²Applies to output and bidirectional pins: ADDRx, DATAx, RD, WR, MSx, BRx, FLAGx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDCLKx, EMU, TDO,

CLKOUT.

³See Output Drive Currents on Page 10 for typical drive current capabilities.

⁴Applies to input pins without internal pull-ups: BOOT_CFGx, CLK_CFGx, CLKIN, RESET, TCK.

⁵Applies to input pins with internal pull-ups: ACK, RPBA, TMS, TDI, TRST.

⁶Applies to input pins with internal pull-downs: IDx.

⁷Applies to input pins with internal pull-ups disabled: ACK, RPBA.

⁸Applies to three-statable pins without internal pull-ups: FLAGx, SDCLKx, TDO.

⁹Applies to three-statable pins with internal pull-ups: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10, EMU.

¹⁰Applies to three-statable pins with internal pull-ups disabled: ADDRx, DATAx, RD, WR, MSx, BRx, DAI_Px, DPI_Px, SDRAS, SDCAS, SDWE, SDCKE, SDA10

¹¹See Engineer-to-Engineer Note 299 for further information.

¹²Characterized, but not tested.

¹³Applies to all signal pins.

¹⁴Guaranteed, but not tested.

Rev. PrA

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Page 3 of 12 | March 2007

ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum

Preliminary Technical Data

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

TIMING SPECIFICATIONS

The processor’s internal clock (a multiple of CLKIN) provides

the clock signal for timing internal memory, processor core, and

serial ports. During reset, program the ratio between the proces-

sor’s internal clock frequency and external (CLKIN) clock

frequency with the CLK_CFG1–0 pins. To determine switching

frequencies for the serial ports, divide down the internal clock,

using the programmable divider control of each port (DIVx for

the serial ports).

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL).

This PLL-based clocking minimizes the skew between the sys-

tem clock (CLKIN) signal and the processor’s internal clock.

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times.

Rev. PrA

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Page 4 of 12 | March 2007

Preliminary Technical Data

ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 2.

Table 2. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Max

Unit

Timing Requirements

t_RSTVDD

RESET Low Before V_DDINT/V_DDEXTOn

V_DDINTOn Before V_DDEXT

0

ns

t_IVDDEVDD

–50

0

10²

+200

ms

μs

1

t_CLKVDD

CLKIN Valid After V_DDINT/V_DDEXTValid

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted

t_CLKRST

t_PLLRST

20

μs

Switching Characteristic

3, 4

t_CORERST

Core Reset Deasserted After RESET Deasserted

4096t_CK+ 2 t_CCLK

¹Valid V_DDINT/V_DDEXTassumes that the supplies are fully ramped to their 1.3 volt rails and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

²Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time. Assume

a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

³Applies after the power-up sequence is complete. Subsequent resets require RESET to be held low a minimum of four CLKIN cycles in order to properly initialize and propagate

default states at all I/O pins.

⁴The 4096 cycle count depends on t_srstspecification. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum.

RESET

t_RSTVDD

V

DDINT

t_IVDDEVDD

V

t_CLKVDD

DDEXT

CLKIN

t_CLKRST

CLK_CFG1-0

t_CORERST

t_PLLRST

RESETOUT

Figure 1. Power-Up Sequencing

Rev. PrA

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Page 5 of 12 | March 2007

ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Adddendum

Preliminary Technical Data

Clock Input

Clock Signals

The processors can use an external clock or a crystal. See the

CLKIN pin description. Programs can configure the processor

to use its internal clock generator by connecting the necessary

components to CLKIN and XTAL. Figure 3 shows the compo-

nent connections used for a crystal operating in fundamental

mode. Note that the clock rate is achieved using a 25 MHz crys-

tal and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a

clock speed of 400 MHz). To achieve the full core clock rate,

programs need to configure the multiplier bits in the PMCTL

register.

Table 3. Clock Input

400 MHz

Min

Parameter

Max

Unit

Timing Requirements

t_CK

CLKIN Period

18¹

8¹

100²

45²

3

ns

t_CKL

t_CKH

t_CKRF

CLKIN Width Low

CLKIN Width High

CLKIN Rise/Fall (0.4 V to

2.0 V)

3

t_CCLK

CCLK Period

2.5¹

10

ns

ps

4, 5

t_CKJ

CLKIN Jitter Tolerance

–250

+250

ADSP-2136x

¹Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in

PMCTL.

R1

XTAL

CLKIN

²Applies only for CLK_CFG1–0 = 10 and default values for PLL control bits in

PMCTL.

1M⍀ (TYPICAL)

R2

³Any changes to PLL control bits in the PMCTL register must meet core clock

47⍀ (TYPICAL)

timing specification t_CCLK

.

C1

22pF

C2

22pF

⁴Actualinputjittershouldbecombinedwithacspecificationsforaccuratetiming

analysis.

Y1

⁵Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

24.576MHz

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER.

REFER TO CRYSTAL MANUFACTURER’S SPECIFICATIONS

t_CK

CLKIN

Figure 3. 400 MHz Operation (Fundamental Mode Crystal)

t_CKH

t_CKL

Figure 2. Clock Input

Rev. PrA

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Page 6 of 12

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March 2007

Preliminary Technical Data

ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum

SDRAM Interface Timing (133 MHz SDCLK)

The 133 MHz access speed is for a single processor. When mul-

tiple ADSP-21368 processors are connected in a shared memory

system, the access speed is 100 MHz.

Table 4. SDRAM Interface Timing¹

Parameter

Min

Max

Unit

Timing Requirements

t_SSDAT

t_HSDAT

DATA Setup Before SDCLK

DATA Hold After SDCLK

0.78

1.23

ns

Switching Characteristics

t_SDCLK

t_SDCLKH

t_SDCLKL

t_DCAD

SDCLK Period

7.5

ns

SDCLK Width High

3.65

SDCLK Width Low

Command, ADDR, Data Delay After SDCLK²

Command, ADDR, Data Hold After SDCLK²

Data Disable After SDCLK

4.8

5.3

t_HCAD

1.2

t_DSDAT

t_ENSDAT

Data Enable After SDCLK

¹For F_CCLK= 400 MHz (SDCLK ratio = 1:2.5).

²Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, SDCKE.

t_SDCLK

t_SDCLKH

SDCLK

t_SSDAT

t_SDCLKL

t_HSDAT

DATA (IN)

t_DCAD

t_DSDAT

t_HCAD

t_ENSDAT

DATA(OUT)

t_DCAD

CMND ADDR

(OUT)

t_HCAD

Figure 4. SDRAM Interface Timing

Rev. PrA

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Page 7 of 12 | March 2007

ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Adddendum

Preliminary Technical Data

SDRAM Interface Enable/Disable Timing (133 MHz SDCLK)

Table 5. SDRAM Interface Enable/Disable Timing¹

Parameter

Min

Max

Unit

Switching Characteristics

t_DSDC

Command Disable After CLKIN Rise

Command Enable After CLKIN Rise

SDCLK Disable After CLKIN Rise

SDCLK Enable After CLKIN Rise

Address Disable After CLKIN Rise

Address Enable After CLKIN Rise

2 × t_PCLK+ 1

8.5

ns

t_ENSDC

t_DSDCC

t_ENSDCC

t_DSDCA

t_ENSDCA

4.0

3.8

9.2

2 × t_PCLK– 4

4 × t_PCLK

¹For F_CCLK= 400 MHz (SDCLK ratio = 1:2.5).

CLKIN

t_DSDC

t_DSDCC

t_DSDCA

COMMAND

SDCLK

ADDR

t_ENSDC

t_ENSDCC

t_ENSDCA

COMMAND

SDCLK

ADDR

Figure 5. SDRAM Interface Enable/Disable Timing

Pin to Pin Direct Routing (DAI and DPI)

For direct pin connections only (for example, DAI_PB01_I to

DAI_PB02_O).

Table 6. DAI Pin to Pin Routing

Parameter

Min

Max

Unit

Timing Requirement

t_DPIO

Delay DAI Pin Input Valid to DAI Output Valid

1.5

12

ns

DAI_Pn

DPI_Pn

DAI_pm

DPI_Pm

t_DPIO

Figure 6. DAI Pin to Pin Direct Routing

Rev. PrA

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Page 8 of 12 | March 2007

Preliminary Technical Data

ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum

Memory Read – Bus Master to Memory Read

Use these specifications for asynchronous interfacing to memo-

ries. These specifications apply when the processors are the bus

master accessing external memory space in asynchronous access

mode. Note that timing for ACK, DATA, RD, WR, and strobe

timing parameters only apply to asynchronous access mode.

Table 7. Memory Read—Bus Master

Parameter

Min

Max

Unit

Timing Requirements

t_DAD

Address, Selects Delay to Data Valid^{1, 2}

RD Low to Data Valid¹

W+t_SDCLK–5.12

W– 2.9

ns

t_DRLD

t_SDS

Data Setup to RD High

2.2

0

t_HDRH

t_DAAK

t_DSAK

Data Hold from RD High^{3, 4}

ACK Delay from Address, Selects^{2, 5}

ACK Delay from RD Low⁴

t_SDCLK–9.5+ W

W – 7.0

Switching Characteristics

t_DRHA

t_DARL

t_RW

Address Selects Hold After RD High

Address Selects to RD Low²

RH + 0.18

t_SDCLK–3.3

W – 1.2

ns

RD Pulse Width

t_RWR

RD High to WR, RD Low

HI +t_SDCLK– 0.8

W = (number of wait states specified in AMICTLx register) × t_SDCLK

HI =RHC + IC (RHC = number of read hold cycles specified in AMICTLx register) × t_SDCLK

IC = (number of idle cycles specified in AMICTLx register) × t_SDCLK

.

H = (number of hold cycles specified in AMICTLx register) × t_SDCLK

.

¹Data delay/setup: system must meet t_DAD, t_DRLD, or t_SDS.

²The falling edge of MSx is referenced.

³Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode.

⁴Data hold: User must meet t_HDAor t_HDRHin asynchronous access mode.

⁵ACK Delay/Setup: User must meet t_DAAK, or t_DSAK, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t_DAAKor t_DSAK

.

ADDRESS

MSx

t_DRHA

t_DARL

t_RW

RD

t_DRLD

t_SDS

t_DAD

t_HDRH

DATA

t_DSAK

t_DAAK

t_RWR

ACK

WR

Figure 7. Memory Read—Bus Master

Rev. PrA

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Page 9 of 12 | March 2007

ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Adddendum

Preliminary Technical Data

OUTPUT DRIVE CURRENTS

CLKOUT (CLKOUT DRIVER), V

(MAX) = 3.65V,TEMPERATURE = 85°C

Figure 8 shows typical I-V characteristics for the output drivers

DDEXT

10

of the ADSP-21367/ADSP-21368/ADSP-21369. The curves rep-

9

resent the current drive capability of the output drivers as a

function of output voltage.

8

7

6

CLKOUT (CLKOUT DRIVER), V

(MAX) = 3.65V,TEMPERATURE = 85°C

DDEXT

10

5

4

3

2

1

0

9

8

7

6

5

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

4

3

2

1

0

Figure 10. Typical Output Rise/Fall Time (20% to 80%,

V_DDEXT= Min)

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

CLKOUT (CLKOUT DRIVER), V

(MAX) = 3.65V,TEMPERATURE = 85°C

DDEXT

10

9

8

7

Figure 8. Typical Drive at Junction temperature

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:

30 pF on all pins. Figure 11 shows graphically how output delays

and holds vary with load capacitance. The graphs of Figure 9,

Figure 10, and Figure 11 may not be linear outside the ranges

shown for Typical Output Delay vs. Load Capacitance and

Typical Output Rise Time (20% to 80%, V = Min) vs. Load

Capacitance.

6

5

4

3

2

1

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

CLKOUT (CLKOUT DRIVER), V

(MAX) = 3.65V,TEMPERATURE = 85°C

DDEXT

10

9

8

7

Figure 11. Typical Output Delay or Hold vs. Load Capacitance

(at Junction Temperature)

6

5

4

3

2

1

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 9. Typical Output Rise/Fall Time (20% to 80%,

_DDEXT= Max)

V

Rev. PrA

|

Page 10 of 12 | March 2007

Preliminary Technical Data

ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum

ORDERING GUIDE

Operating

Temperature

Range

Instruction On-Chip

Voltage

Internal/External Description

Package

Option

Part Number

Rate

SRAM

2M bit

ROM

ADSP-21367KBP-3A¹

ADSP-21367KBPZ-3A²

ADSP-21368KBP-3A

ADSP-21368KBPZ-3A²

ADSP-21369KBP-3A

ADSP-21369KBPZ-3A²

0°C to +70°C

400 MHz

6M bit

1.3 V/3.3 V

256-Ball SBGA

BP-256

¹Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at

www.analog.com/SHARC.

²Z = RoHS Compliant Part.

Rev. PrA

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Page 11 of 12 | March 2007

ADSP-21367/ADSP-21368/ADSP-21369 Data Sheet Addendum

Preliminary Technical Data

registered trademarks are the property of their respective owners.

PR06770-0-4/07(PrA)

Rev. PrA

|

Page 12 of 12 | March 2007


型号：	ADSP-21369KBP-3A
厂家：	ADI
描述：	IC 0-BIT, 25 MHz, OTHER DSP, PBGA256, SBGA-256, Digital Signal Processor
文件：	总12页 (文件大小：821K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21369KBP-3A [ADI]

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